@@ -0,0 +1,41 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | -----------------------------------------------------------------------------*/ | |||
|
22 | #ifndef ADC_DRIVER_H | |||
|
23 | #define ADC_DRIVER_H | |||
|
24 | ||||
|
25 | #include "apb_fifo_Driver.h" | |||
|
26 | #include "apb_uart_Driver.h" | |||
|
27 | #include "apb_gpio_Driver.h" | |||
|
28 | ||||
|
29 | #define samplecnt 4096 | |||
|
30 | #define Mask 0x0000FFFF | |||
|
31 | ||||
|
32 | /*=================================================== | |||
|
33 | F U N C T I O N S | |||
|
34 | ====================================================*/ | |||
|
35 | ||||
|
36 | void flushFIFO(FIFO_Device*,GPIO_Device*); | |||
|
37 | void getPacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); | |||
|
38 | void mkfakePacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); | |||
|
39 | void sendPacket(UART_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); | |||
|
40 | ||||
|
41 | #endif |
@@ -0,0 +1,93 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | -----------------------------------------------------------------------------*/ | |||
|
22 | #include "ADC_Driver.h" | |||
|
23 | #include <stdio.h> | |||
|
24 | ||||
|
25 | unsigned char packetNumber = 0; | |||
|
26 | ||||
|
27 | void flushFIFO(FIFO_Device*fifo,GPIO_Device* adcResetPin) | |||
|
28 | { | |||
|
29 | adcResetPin->Dout = 0x0; | |||
|
30 | int trash; | |||
|
31 | while((fifo->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) != FIFO_Empty){ // TANT QUE empty a 0 ALORS | |||
|
32 | trash = fifo->FIFOreg[(2*0)+FIFO_RWdata]; | |||
|
33 | trash = fifo->FIFOreg[(2*1)+FIFO_RWdata]; | |||
|
34 | trash = fifo->FIFOreg[(2*2)+FIFO_RWdata]; | |||
|
35 | trash = fifo->FIFOreg[(2*3)+FIFO_RWdata]; | |||
|
36 | trash = fifo->FIFOreg[(2*4)+FIFO_RWdata]; | |||
|
37 | } | |||
|
38 | ||||
|
39 | adcResetPin->Dout = 0x1; | |||
|
40 | } | |||
|
41 | ||||
|
42 | void getPacket(FIFO_Device*fifo,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize) | |||
|
43 | { | |||
|
44 | int i=0; | |||
|
45 | for(i=0;i<packetSize;i++) | |||
|
46 | { | |||
|
47 | while((fifo->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); | |||
|
48 | CH1[i] = (fifo->FIFOreg[(2*0)+FIFO_RWdata] & Mask); | |||
|
49 | CH2[i] = (fifo->FIFOreg[(2*1)+FIFO_RWdata] & Mask); | |||
|
50 | CH3[i] = (fifo->FIFOreg[(2*2)+FIFO_RWdata] & Mask); | |||
|
51 | CH4[i] = (fifo->FIFOreg[(2*3)+FIFO_RWdata] & Mask); | |||
|
52 | CH5[i] = (fifo->FIFOreg[(2*4)+FIFO_RWdata] & Mask); | |||
|
53 | } | |||
|
54 | } | |||
|
55 | ||||
|
56 | void mkfakePacket(FIFO_Device*fifo,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize) | |||
|
57 | { | |||
|
58 | int i=0; | |||
|
59 | for(i=0;i<packetSize;i++) | |||
|
60 | { | |||
|
61 | CH1[i] = (unsigned short)(i); | |||
|
62 | CH2[i] = (unsigned short)(i+10); | |||
|
63 | CH3[i] = (unsigned short)(i+20); | |||
|
64 | CH4[i] = (unsigned short)(i+30); | |||
|
65 | CH5[i] = (unsigned short)(i+40); | |||
|
66 | } | |||
|
67 | } | |||
|
68 | ||||
|
69 | ||||
|
70 | void sendPacket(UART_Device* uart0,unsigned short*CH1,unsigned short*CH2,unsigned short*CH3,unsigned short*CH4,unsigned short*CH5,int packetSize) | |||
|
71 | { | |||
|
72 | int i=0; | |||
|
73 | ||||
|
74 | for(i=0;i<packetSize;i++) | |||
|
75 | { | |||
|
76 | uartputc(uart0,0xa5); | |||
|
77 | uartputc(uart0,0x0f); | |||
|
78 | uartputc(uart0,packetNumber++); | |||
|
79 | uartputc(uart0,(char)(CH1[i]>>8)); | |||
|
80 | uartputc(uart0,(char)CH1[i]); | |||
|
81 | uartputc(uart0,(char)(CH2[i]>>8)); | |||
|
82 | uartputc(uart0,(char)CH2[i]); | |||
|
83 | uartputc(uart0,(char)(CH3[i]>>8)); | |||
|
84 | uartputc(uart0,(char)CH3[i]); | |||
|
85 | uartputc(uart0,(char)(CH4[i]>>8)); | |||
|
86 | uartputc(uart0,(char)CH4[i]); | |||
|
87 | uartputc(uart0,(char)(CH5[i]>>8)); | |||
|
88 | uartputc(uart0,(char)CH5[i]); | |||
|
89 | uartputc(uart0,0xf0); | |||
|
90 | uartputc(uart0,0x5a); | |||
|
91 | } | |||
|
92 | ||||
|
93 | } |
@@ -0,0 +1,41 | |||||
|
1 | /*------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Martin Morlot | |||
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |||
|
21 | -----------------------------------------------------------------------------*/ | |||
|
22 | #ifndef ADC_DRIVER_H | |||
|
23 | #define ADC_DRIVER_H | |||
|
24 | ||||
|
25 | #include "apb_fifo_Driver.h" | |||
|
26 | #include "apb_uart_Driver.h" | |||
|
27 | #include "apb_gpio_Driver.h" | |||
|
28 | ||||
|
29 | #define samplecnt 4096 | |||
|
30 | #define Mask 0x0000FFFF | |||
|
31 | ||||
|
32 | /*=================================================== | |||
|
33 | F U N C T I O N S | |||
|
34 | ====================================================*/ | |||
|
35 | ||||
|
36 | void flushFIFO(FIFO_Device*,GPIO_Device*); | |||
|
37 | void getPacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); | |||
|
38 | void mkfakePacket(FIFO_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); | |||
|
39 | void sendPacket(UART_Device*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,unsigned short*,int); | |||
|
40 | ||||
|
41 | #endif |
@@ -0,0 +1,25 | |||||
|
1 | #------------------------------------------------------------------------------ | |||
|
2 | #-- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | #-- | |||
|
5 | #-- This program is free software; you can redistribute it and/or modify | |||
|
6 | #-- it under the terms of the GNU General Public License as published by | |||
|
7 | #-- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | #-- (at your option) any later version. | |||
|
9 | #-- | |||
|
10 | #-- This program is distributed in the hope that it will be useful, | |||
|
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | #-- GNU General Public License for more details. | |||
|
14 | #-- | |||
|
15 | #-- You should have received a copy of the GNU General Public License | |||
|
16 | #-- along with this program; if not, write to the Free Software | |||
|
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | #------------------------------------------------------------------------------ | |||
|
19 | FILE = adc_Driver | |||
|
20 | LIB = liblpp_adc_Driver.a | |||
|
21 | ||||
|
22 | include ../../rules.mk | |||
|
23 | ||||
|
24 | all: $(FILE).a | |||
|
25 | @echo $(FILE)".a created" |
@@ -1,19 +1,14 | |||||
1 | #include <stdio.h> |
|
1 | #include <stdio.h> | |
2 | #include "lpp_apb_functions.h" |
|
2 | #include "lpp_apb_functions.h" | |
3 | #include "apb_uart_Driver.h" |
|
3 | #include "apb_uart_Driver.h" | |
4 |
|
4 | |||
5 |
|
5 | |||
6 | int main() |
|
6 | int main() | |
7 | { |
|
7 | { | |
8 | printf("Debut Main\n\n"); |
|
8 | printf("Debut Main\n\n"); | |
9 | UART_Device* dev = openUART(0); |
|
9 | UART_Device* dev = openUART(0); | |
10 | printf("addr: %x\n",(unsigned int)dev); |
|
10 | while(1){ | |
11 | printf("cfg: %x\n",dev->ConfigReg); |
|
11 | uartputc(dev,uartgetc(dev)); | |
12 | char* a = "hello world\n"; |
|
12 | } | |
13 | uartputs(dev,a); |
|
|||
14 | printf("Try #1 done\n"); |
|
|||
15 | uartputs(dev,"salut monde\n"); |
|
|||
16 | printf("Try #2 done\n"); |
|
|||
17 | return 0; |
|
13 | return 0; | |
18 | } |
|
14 | } | |
19 |
|
@@ -1,46 +1,48 | |||||
1 | #------------------------------------------------------------------------------ |
|
1 | #------------------------------------------------------------------------------ | |
2 | #-- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | #-- This file is a part of the LPP VHDL IP LIBRARY | |
3 | #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS | |
4 | #-- |
|
4 | #-- | |
5 | #-- This program is free software; you can redistribute it and/or modify |
|
5 | #-- This program is free software; you can redistribute it and/or modify | |
6 | #-- it under the terms of the GNU General Public License as published by |
|
6 | #-- it under the terms of the GNU General Public License as published by | |
7 | #-- the Free Software Foundation; either version 3 of the License, or |
|
7 | #-- the Free Software Foundation; either version 3 of the License, or | |
8 | #-- (at your option) any later version. |
|
8 | #-- (at your option) any later version. | |
9 | #-- |
|
9 | #-- | |
10 | #-- This program is distributed in the hope that it will be useful, |
|
10 | #-- This program is distributed in the hope that it will be useful, | |
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | #-- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | #-- GNU General Public License for more details. |
|
13 | #-- GNU General Public License for more details. | |
14 | #-- |
|
14 | #-- | |
15 | #-- You should have received a copy of the GNU General Public License |
|
15 | #-- You should have received a copy of the GNU General Public License | |
16 | #-- along with this program; if not, write to the Free Software |
|
16 | #-- along with this program; if not, write to the Free Software | |
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | #------------------------------------------------------------------------------ |
|
18 | #------------------------------------------------------------------------------ | |
19 |
|
19 | |||
20 | include ../rules.mk |
|
20 | include ../rules.mk | |
21 |
|
21 | |||
22 |
|
22 | |||
23 |
|
23 | |||
24 | all: |
|
24 | all: | |
25 | make all -C AMBA |
|
25 | make all -C AMBA | |
26 | make all -C LCD |
|
26 | make all -C LCD | |
27 | make all -C DAC |
|
27 | make all -C DAC | |
28 | make all -C FIFO |
|
28 | make all -C FIFO | |
29 | make all -C UART |
|
29 | make all -C UART | |
30 | make all -C FFT |
|
30 | make all -C FFT | |
31 | make all -C DELAY |
|
31 | make all -C DELAY | |
32 | make all -C GPIO |
|
32 | make all -C GPIO | |
|
33 | make all -C ADC | |||
33 | make all -C MATRIX |
|
34 | make all -C MATRIX | |
34 |
|
35 | |||
35 |
|
36 | |||
36 | cleanall: |
|
37 | cleanall: | |
37 | make clean -C AMBA |
|
38 | make clean -C AMBA | |
38 | make clean -C LCD |
|
39 | make clean -C LCD | |
39 | make clean -C DAC |
|
40 | make clean -C DAC | |
40 | make clean -C FIFO |
|
41 | make clean -C FIFO | |
41 | make clean -C UART |
|
42 | make clean -C UART | |
42 | make clean -C FFT |
|
43 | make clean -C FFT | |
43 | make clean -C DELAY |
|
44 | make clean -C DELAY | |
44 | make clean -C GPIO |
|
45 | make clean -C GPIO | |
|
46 | make clean -C ADC | |||
45 | make clean -C MATRIX |
|
47 | make clean -C MATRIX | |
46 |
|
48 |
@@ -1,60 +1,59 | |||||
1 | /*------------------------------------------------------------------------------ |
|
1 | /*------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | -----------------------------------------------------------------------------*/ |
|
21 | -----------------------------------------------------------------------------*/ | |
22 | #include "apb_uart_Driver.h" |
|
22 | #include "apb_uart_Driver.h" | |
23 | #include "lpp_apb_functions.h" |
|
23 | #include "lpp_apb_functions.h" | |
24 | #include <stdio.h> |
|
24 | #include <stdio.h> | |
25 |
|
25 | |||
26 |
|
26 | |||
27 | UART_Device* openUART(int count) |
|
27 | UART_Device* openUART(int count) | |
28 | { |
|
28 | { | |
29 | UART_Device* uart0; |
|
29 | UART_Device* uart0; | |
30 | uart0 = (UART_Device*) apbgetdevice(LPP_UART,VENDOR_LPP,count); |
|
30 | uart0 = (UART_Device*) apbgetdevice(LPP_UART,VENDOR_LPP,count); | |
31 | uart0->ConfigReg = BaudGenOnDuty; |
|
31 | uart0->ConfigReg = BaudGenOnDuty; | |
32 | return uart0; |
|
32 | return uart0; | |
33 | } |
|
33 | } | |
34 |
|
34 | |||
35 |
|
35 | |||
36 | void uartputc(UART_Device* dev,char c) |
|
36 | void uartputc(UART_Device* dev,char c) | |
37 | { |
|
37 | { | |
38 | //while (!(dev->ConfigReg & (1<<5))); |
|
38 | //while (!(dev->ConfigReg & (1<<5))); | |
39 | while (!((dev->ConfigReg & DataSended) == DataSended)); |
|
39 | while (!((dev->ConfigReg & DataSended) == DataSended)); | |
40 | dev->DataWReg = c; |
|
40 | dev->DataWReg = c; | |
41 | printf(" "); |
|
|||
42 | } |
|
41 | } | |
43 |
|
42 | |||
44 | void uartputs(UART_Device* dev,char* s) |
|
43 | void uartputs(UART_Device* dev,char* s) | |
45 | { |
|
44 | { | |
46 | while (*s) uartputc(dev,*(s++)); |
|
45 | while (*s) uartputc(dev,*(s++)); | |
47 | } |
|
46 | } | |
48 |
|
47 | |||
49 | char uartgetc(UART_Device* dev) |
|
48 | char uartgetc(UART_Device* dev) | |
50 | { |
|
49 | { | |
51 | //while (!((dev->ConfigReg & (1<<2)))); |
|
50 | //while (!((dev->ConfigReg & (1<<2)))); | |
52 | while (!((dev->ConfigReg & NewData) == NewData)); |
|
51 | while (!((dev->ConfigReg & NewData) == NewData)); | |
53 | return dev->DataRReg; |
|
52 | return dev->DataRReg; | |
54 | } |
|
53 | } | |
55 |
|
54 | |||
56 | void uartgets(UART_Device* dev,char* s) |
|
55 | void uartgets(UART_Device* dev,char* s) | |
57 | { |
|
56 | { | |
58 | while (*s && (*s!=0xd)) *s++ = uartgetc(dev); |
|
57 | while (*s && (*s!=0xd)) *s++ = uartgetc(dev); | |
59 | } |
|
58 | } | |
60 |
|
59 |
@@ -1,147 +1,144 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------ |
|
18 | ------------------------------------------------------------------------------ | |
19 | -- Author : Martin Morlot |
|
19 | -- Author : Martin Morlot | |
20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
|
20 | -- Mail : martin.morlot@lpp.polytechnique.fr | |
21 | ------------------------------------------------------------------------------ |
|
21 | ------------------------------------------------------------------------------ | |
22 | library ieee; |
|
22 | library ieee; | |
23 | use ieee.std_logic_1164.all; |
|
23 | use ieee.std_logic_1164.all; | |
24 | library grlib; |
|
24 | library grlib; | |
25 | use grlib.amba.all; |
|
25 | use grlib.amba.all; | |
26 | use grlib.stdlib.all; |
|
26 | use grlib.stdlib.all; | |
27 | use grlib.devices.all; |
|
27 | use grlib.devices.all; | |
28 | library lpp; |
|
28 | library lpp; | |
29 | use lpp.lpp_amba.all; |
|
29 | use lpp.lpp_amba.all; | |
30 | use lpp.apb_devices_list.all; |
|
30 | use lpp.apb_devices_list.all; | |
31 | use lpp.lpp_uart.all; |
|
31 | use lpp.lpp_uart.all; | |
32 |
|
32 | |||
33 | --! This is an APB UART you should use it with a processor as UART and drive it with its register over AMBA bus. |
|
33 | --! This is an APB UART you should use it with a processor as UART and drive it with its register over AMBA bus. | |
34 | --! \author Martin Morlot martin.morlot@lpp.polytechnique.fr |
|
34 | --! \author Martin Morlot martin.morlot@lpp.polytechnique.fr | |
35 |
|
35 | |||
36 | entity APB_UART is |
|
36 | entity APB_UART is | |
37 | generic ( |
|
37 | generic ( | |
38 | pindex : integer := 0; |
|
38 | pindex : integer := 0; | |
39 | paddr : integer := 0; |
|
39 | paddr : integer := 0; | |
40 | pmask : integer := 16#fff#; |
|
40 | pmask : integer := 16#fff#; | |
41 | pirq : integer := 0; |
|
41 | pirq : integer := 0; | |
42 | abits : integer := 8; |
|
42 | abits : integer := 8; | |
43 | Data_sz : integer := 8); |
|
43 | Data_sz : integer := 8); | |
44 | port ( |
|
44 | port ( | |
45 | clk : in std_logic; --! System clock |
|
45 | clk : in std_logic; --! System clock | |
46 | rst : in std_logic; --! System reset |
|
46 | rst : in std_logic; --! System reset | |
47 | apbi : in apb_slv_in_type; --! APB input signals see grlib.amba package |
|
47 | apbi : in apb_slv_in_type; --! APB input signals see grlib.amba package | |
48 | apbo : out apb_slv_out_type; --! APB input signals see grlib.amba package |
|
48 | apbo : out apb_slv_out_type; --! APB input signals see grlib.amba package | |
49 | TXD : out std_logic; --! UART Transmission pin |
|
49 | TXD : out std_logic; --! UART Transmission pin | |
50 | RXD : in std_logic --! UART Reception pin |
|
50 | RXD : in std_logic --! UART Reception pin | |
51 | ); |
|
51 | ); | |
52 | end APB_UART; |
|
52 | end APB_UART; | |
53 |
|
53 | |||
54 |
|
54 | |||
55 | architecture ar_APB_UART of APB_UART is |
|
55 | architecture ar_APB_UART of APB_UART is | |
56 |
|
56 | |||
57 | constant REVISION : integer := 1; |
|
57 | constant REVISION : integer := 1; | |
58 |
|
58 | |||
59 | constant pconfig : apb_config_type := ( |
|
59 | constant pconfig : apb_config_type := ( | |
60 | 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), |
|
60 | 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), | |
61 | 1 => apb_iobar(paddr, pmask)); |
|
61 | 1 => apb_iobar(paddr, pmask)); | |
62 |
|
62 | |||
63 | signal NwData : std_logic; |
|
63 | signal NwData : std_logic; | |
64 | signal ACK : std_logic; |
|
64 | signal ACK : std_logic; | |
65 | signal Capture : std_logic; |
|
65 | signal Capture : std_logic; | |
66 | signal Send : std_logic; |
|
66 | signal Send : std_logic; | |
67 | signal Sended : std_logic; |
|
67 | signal Sended : std_logic; | |
68 |
|
68 | |||
69 | type UART_ctrlr_Reg is record |
|
69 | type UART_ctrlr_Reg is record | |
70 | UART_Cfg : std_logic_vector(2 downto 0); |
|
70 | UART_Cfg : std_logic_vector(2 downto 0); | |
71 | UART_Wdata : std_logic_vector(7 downto 0); |
|
71 | UART_Wdata : std_logic_vector(7 downto 0); | |
72 | UART_Rdata : std_logic_vector(7 downto 0); |
|
72 | UART_Rdata : std_logic_vector(7 downto 0); | |
73 | UART_BTrig : std_logic_vector(11 downto 0); |
|
73 | UART_BTrig : std_logic_vector(11 downto 0); | |
74 | end record; |
|
74 | end record; | |
75 |
|
75 | |||
76 | signal Rec : UART_ctrlr_Reg; |
|
76 | signal Rec : UART_ctrlr_Reg; | |
77 | signal Rdata : std_logic_vector(31 downto 0); |
|
77 | signal Rdata : std_logic_vector(31 downto 0); | |
78 | signal temp_ND : std_logic; |
|
78 | signal temp_ND : std_logic; | |
79 |
|
79 | |||
80 | begin |
|
80 | begin | |
81 |
|
81 | |||
82 | Capture <= Rec.UART_Cfg(0); |
|
82 | Capture <= Rec.UART_Cfg(0); | |
83 | Rec.UART_Cfg(1) <= Sended; |
|
83 | Rec.UART_Cfg(1) <= Sended; | |
84 | Rec.UART_Cfg(2) <= NwData; |
|
84 | Rec.UART_Cfg(2) <= NwData; | |
85 |
|
85 | |||
86 |
|
86 | |||
87 | COM0 : UART |
|
87 | COM0 : UART | |
88 | generic map (Data_sz) |
|
88 | generic map (Data_sz) | |
89 | port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); |
|
89 | port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); | |
90 |
|
90 | |||
91 |
|
91 | |||
92 | process(rst,clk) |
|
92 | process(rst,clk) | |
93 | begin |
|
93 | begin | |
94 | if(rst='0')then |
|
94 | if(rst='0')then | |
95 | Rec.UART_Wdata <= (others => '0'); |
|
95 | Rec.UART_Wdata <= (others => '0'); | |
96 |
|
96 | Send <= '0'; | ||
97 |
|
97 | |||
98 | elsif(clk'event and clk='1')then |
|
98 | elsif(clk'event and clk='1')then | |
99 | temp_ND <= NwData; |
|
|||
100 | if(NwData='1' and temp_ND='1')then |
|
|||
101 | ACK <= '1'; |
|
|||
102 | else |
|
|||
103 | ACK <= '0'; |
|
|||
104 | end if; |
|
|||
105 |
|
99 | |||
106 | --APB Write OP |
|
100 | --APB Write OP | |
107 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
|
101 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then | |
108 | case apbi.paddr(7 downto 2) is |
|
102 | case apbi.paddr(7 downto 2) is | |
109 | when "000000" => |
|
103 | when "000000" => | |
110 | Rec.UART_Cfg(0) <= apbi.pwdata(0); |
|
104 | Rec.UART_Cfg(0) <= apbi.pwdata(0); | |
111 | when "000001" => |
|
105 | when "000001" => | |
112 | Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); |
|
106 | Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); | |
113 | Send <= '1'; |
|
107 | Send <= '1'; | |
114 | when others => |
|
108 | when others => | |
115 | null; |
|
109 | null; | |
116 | end case; |
|
110 | end case; | |
117 | else |
|
111 | elsif(Sended = '0')then | |
118 |
|
|
112 | Send <= '0'; | |
119 | end if; |
|
113 | end if; | |
120 |
|
114 | |||
121 | --APB READ OP |
|
115 | --APB READ OP | |
122 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
|
116 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then | |
123 | case apbi.paddr(7 downto 2) is |
|
117 | case apbi.paddr(7 downto 2) is | |
124 | when "000000" => |
|
118 | when "000000" => | |
125 | Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0); |
|
119 | Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0); | |
126 | Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1); |
|
120 | Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1); | |
127 | Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2); |
|
121 | Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2); | |
128 | Rdata(19 downto 12) <= X"EE"; |
|
122 | Rdata(19 downto 12) <= X"EE"; | |
129 | Rdata(31 downto 20) <= Rec.UART_BTrig; |
|
123 | Rdata(31 downto 20) <= Rec.UART_BTrig; | |
130 | when "000001" => |
|
124 | when "000001" => | |
131 | Rdata(31 downto 8) <= X"EEEEEE"; |
|
125 | Rdata(31 downto 8) <= X"EEEEEE"; | |
132 | Rdata(7 downto 0) <= Rec.UART_Wdata; |
|
126 | Rdata(7 downto 0) <= Rec.UART_Wdata; | |
133 | when "000010" => |
|
127 | when "000010" => | |
134 | Rdata(31 downto 8) <= X"EEEEEE"; |
|
128 | Rdata(31 downto 8) <= X"EEEEEE"; | |
135 | Rdata(7 downto 0) <= Rec.UART_Rdata; |
|
129 | Rdata(7 downto 0) <= Rec.UART_Rdata; | |
|
130 | ACK <= '1'; | |||
136 | when others => |
|
131 | when others => | |
137 | Rdata <= (others => '0'); |
|
132 | Rdata <= (others => '0'); | |
138 | end case; |
|
133 | end case; | |
|
134 | else | |||
|
135 | ACK <= '0'; | |||
139 | end if; |
|
136 | end if; | |
140 |
|
137 | |||
141 | end if; |
|
138 | end if; | |
142 | apbo.pconfig <= pconfig; |
|
139 | apbo.pconfig <= pconfig; | |
143 | end process; |
|
140 | end process; | |
144 |
|
141 | |||
145 | apbo.prdata <= Rdata when apbi.penable = '1'; |
|
142 | apbo.prdata <= Rdata when apbi.penable = '1'; | |
146 |
|
143 | |||
147 | end ar_APB_UART; |
|
144 | end ar_APB_UART; |
@@ -1,117 +1,92 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 |
|
25 | |||
26 | --! \brief Universal shift register can be used to serialize or deserialize data. |
|
26 | --! \brief Universal shift register can be used to serialize or deserialize data. | |
27 | --! |
|
27 | --! | |
28 | --! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr |
|
28 | --! \Author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr | |
29 | --! \todo move to general purpose library, explain more in detail the code and add some schematic in doc. |
|
29 | --! \todo move to general purpose library, explain more in detail the code and add some schematic in doc. | |
30 |
|
30 | |||
31 |
entity Shift_R |
|
31 | entity Shift_Reg is | |
32 | generic( |
|
32 | generic( | |
33 | Data_sz : integer := 10 --! Width of the shift register |
|
33 | Data_sz : integer := 10 --! Width of the shift register | |
34 | ); |
|
34 | ); | |
35 | port( |
|
35 | port( | |
36 | clk : in std_logic; --! System clock |
|
|||
37 | Sclk : in std_logic; --! Serial clock |
|
36 | Sclk : in std_logic; --! Serial clock | |
38 | reset : in std_logic; --! System reset |
|
|||
39 | SIN : in std_logic; --! Serial data in |
|
37 | SIN : in std_logic; --! Serial data in | |
40 | SOUT : out std_logic; --! Serial data out |
|
38 | SOUT : out std_logic; --! Serial data out | |
41 | Serialize : in std_logic; --! Launch serialization |
|
39 | Serialize : in std_logic; --! Launch serialization | |
42 | Serialized : out std_logic; --! Serialization complete |
|
40 | Serialized : out std_logic; --! Serialization complete | |
43 | D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out |
|
41 | D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out | |
44 | Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data |
|
42 | Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data | |
45 | ); |
|
43 | ); | |
46 | end entity; |
|
44 | end entity; | |
47 |
|
45 | |||
48 |
|
46 | |||
49 |
architecture ar_Shift_R |
|
47 | architecture ar_Shift_Reg of Shift_Reg is | |
50 |
|
48 | |||
51 | signal REG : std_logic_vector(Data_sz-1 downto 0); |
|
49 | signal REG : std_logic_vector(Data_sz-1 downto 0); | |
52 | signal Serialized_int : std_logic; |
|
50 | signal CptBits : std_logic_vector(Data_sz-1 downto 0) := (others => '0'); | |
53 | signal Serialize_reg : std_logic; |
|
|||
54 | signal Serial_reg : std_logic; |
|
|||
55 | signal CptBits : std_logic_vector(Data_sz-1 downto 0); |
|
|||
56 | constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); |
|
51 | constant CptBits_trig : std_logic_vector(Data_sz-1 downto 0) := (others => '1'); | |
57 | signal CptBits_flag : std_logic; |
|
52 | signal CptBits_flag : std_logic :='0'; | |
58 |
signal |
|
53 | signal Serialized_int : std_logic :='1'; | |
59 |
|
54 | |||
60 | begin |
|
55 | begin | |
61 |
|
56 | |||
|
57 | CptBits_flag <= '1' when CptBits=CptBits_trig else '0'; | |||
62 |
Serialized |
|
58 | Serialized <= Serialized_int; | |
63 | CptBits_flag <= '1' when CptBits = CptBits_trig else '0'; |
|
59 | process(Serialize,Sclk,D) | |
64 |
|
||||
65 | process(reset,clk) |
|
|||
66 | begin |
|
60 | begin | |
67 |
if |
|
61 | if(Serialize = '1') then | |
68 | Serialized_int <= '1'; |
|
62 | REG <= D; | |
69 |
CptBits |
|
63 | CptBits <= (others => '0'); | |
70 |
Serial |
|
64 | Serialized_int <= '0'; | |
71 |
Q |
|
65 | Q <= REG; | |
72 | elsif clk'event and clk = '1' then |
|
66 | SOUT <= '1'; | |
73 | CptBits_flag_reg <= CptBits_flag; |
|
67 | elsif Sclk'event and Sclk = '1' then | |
74 | Serial_reg <= Serialize; |
|
68 | if(Serialized_int='0') then | |
75 |
|
69 | REG <= SIN & REG(Data_sz-1 downto 1); | ||
76 | if CptBits_flag = '1' and CptBits_flag_reg = '0' then |
|
70 | CptBits <= '1' & CptBits(Data_sz-1 downto 1); | |
|
71 | SOUT <= REG(0); | |||
|
72 | if(CptBits_flag = '1') then | |||
77 |
Serialized_int |
|
73 | Serialized_int <= '1'; | |
78 |
Q |
|
74 | Q <= REG; | |
79 | elsif(Serial_reg='0' and Serialize='1')then |
|
75 | end if; | |
80 | Serialized_int <= '0'; |
|
76 | else | |
|
77 | SOUT <= '1'; | |||
|
78 | Serialized_int <= '1'; | |||
|
79 | -- Q <= REG; | |||
81 | end if; |
|
80 | end if; | |
82 | end if; |
|
81 | end if; | |
83 | end process; |
|
82 | end process; | |
84 |
|
83 | |||
|
84 | end architecture; | |||
85 |
|
85 | |||
86 | process(reset,Sclk) |
|
86 | ||
87 | begin |
|
87 | ||
88 | if reset = '0' then |
|
88 | ||
89 | CptBits <= (others => '0'); |
|
|||
90 | REG <= (others => '0'); |
|
|||
91 | SOUT <= '1'; |
|
|||
92 | Serialize_reg <= '0'; |
|
|||
93 | elsif Sclk'event and Sclk = '1' then |
|
|||
94 | Serialize_reg <= Serialized_int; |
|
|||
95 | if (Serialized_int = '0' and Serialize_reg ='1') then |
|
|||
96 | REG <= SIN & D(Data_sz-1 downto 1); |
|
|||
97 | SOUT <= D(0); |
|
|||
98 | elsif Serialized_int = '0' then |
|
|||
99 | REG <= SIN & REG(Data_sz-1 downto 1); |
|
|||
100 | SOUT <= REG(0); |
|
|||
101 | else |
|
|||
102 | SOUT <= '1'; |
|
|||
103 | end if; |
|
|||
104 | if Serialized_int = '0' then |
|
|||
105 | if CptBits_flag = '1' then |
|
|||
106 | CptBits <= (others => '0'); |
|
|||
107 | else |
|
|||
108 | CptBits <= '1' & CptBits(Data_sz-1 downto 1); |
|
|||
109 | end if; |
|
|||
110 | else |
|
|||
111 | CptBits <= (others => '0'); |
|
|||
112 | end if; |
|
|||
113 |
|
89 | |||
114 | end if; |
|
90 | ||
115 | end process; |
|
|||
116 |
|
91 | |||
117 | end ar_Shift_REG; |
|
92 |
@@ -1,106 +1,102 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | -- Author : Alexis Jeandet |
|
19 | -- Author : Alexis Jeandet | |
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr |
|
20 | -- Mail : alexis.jeandet@lpp.polytechnique.fr | |
21 | ---------------------------------------------------------------------------- |
|
21 | ---------------------------------------------------------------------------- | |
22 | library IEEE; |
|
22 | library IEEE; | |
23 | use IEEE.numeric_std.all; |
|
23 | use IEEE.numeric_std.all; | |
24 | use IEEE.std_logic_1164.all; |
|
24 | use IEEE.std_logic_1164.all; | |
25 | library lpp; |
|
25 | library lpp; | |
26 | use lpp.lpp_uart.all; |
|
26 | use lpp.lpp_uart.all; | |
27 |
|
27 | |||
28 | --! \brief A general purpose UART with automatic baudrate |
|
28 | --! \brief A general purpose UART with automatic baudrate | |
29 | --! |
|
29 | --! | |
30 | --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr |
|
30 | --! \author Alexis Jeandet alexis.jeandet@lpp.polytechnique.fr | |
31 |
|
31 | |||
32 | entity UART is |
|
32 | entity UART is | |
33 | generic(Data_sz : integer := 8); --! Data width |
|
33 | generic(Data_sz : integer := 8); --! Data width | |
34 | port( |
|
34 | port( | |
35 | clk : in std_logic; --! System clock |
|
35 | clk : in std_logic; --! System clock | |
36 | reset : in std_logic; --! System reset |
|
36 | reset : in std_logic; --! System reset | |
37 | TXD : out std_logic; --! UART Transmission pin |
|
37 | TXD : out std_logic; --! UART Transmission pin | |
38 | RXD : in std_logic; --! UART Reception pin |
|
38 | RXD : in std_logic; --! UART Reception pin | |
39 | Capture : in std_logic; --! Automatic baudrate module reset |
|
39 | Capture : in std_logic; --! Automatic baudrate module reset | |
40 | NwDat : out std_logic; --! New data flag, means that a new data have been received by the UART |
|
40 | NwDat : out std_logic; --! New data flag, means that a new data have been received by the UART | |
41 | ACK : in std_logic; --! Acknowledge flag to clear NwDat flag |
|
41 | ACK : in std_logic; --! Acknowledge flag to clear NwDat flag | |
42 | Send : in std_logic; --! To send a data you have to set this flag |
|
42 | Send : in std_logic; --! To send a data you have to set this flag | |
43 | Sended : out std_logic; --! When this flag is set you can sed a new data |
|
43 | Sended : out std_logic; --! When this flag is set you can sed a new data | |
44 | BTrigger : out std_logic_vector(11 downto 0); --! Baudrate generator current value, could be usefull if you whant to know the current value of the baudrate or of the oscillator (it suppose that you know baudrate) |
|
44 | BTrigger : out std_logic_vector(11 downto 0); --! Baudrate generator current value, could be usefull if you whant to know the current value of the baudrate or of the oscillator (it suppose that you know baudrate) | |
45 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word |
|
45 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word | |
46 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Put here the word you whant to send |
|
46 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Put here the word you whant to send | |
47 | ); |
|
47 | ); | |
48 | end entity; |
|
48 | end entity; | |
49 |
|
49 | |||
50 |
|
50 | |||
51 | architecture ar_UART of UART is |
|
51 | architecture ar_UART of UART is | |
52 | signal Bclk : std_logic; |
|
52 | signal Bclk : std_logic; | |
53 |
|
53 | |||
54 |
signal RDATA_int |
|
54 | signal RDATA_int : std_logic_vector(Data_sz+1 downto 0); | |
55 |
signal WDATA_int |
|
55 | signal WDATA_int : std_logic_vector(Data_sz+1 downto 0); | |
56 |
|
56 | |||
57 |
signal T |
|
57 | signal Take : std_logic; | |
58 |
signal |
|
58 | signal Taken : std_logic; | |
59 |
signal |
|
59 | signal Taken_reg : std_logic; | |
60 | signal receive : std_logic; |
|
60 | ||
61 |
constant |
|
61 | constant Dummy : std_logic_vector(Data_sz+1 downto 0) := (others => '1'); | |
62 |
|
62 | |||
63 | begin |
|
63 | begin | |
64 |
|
64 | |||
65 |
|
65 | NwDat <= '0' when (ack = '1') else '1' when (Taken_reg='0' and Taken='1'); | ||
66 |
|
||||
67 |
WDATA_int <= |
|
66 | WDATA_int <= '1' & WDATA & '0'; | |
68 |
|
67 | |||
69 |
BaudGenerator : |
|
68 | BaudGenerator : BaudGen | |
70 | port map(clk,reset,Capture,Bclk,RXD,BTrigger); |
|
69 | port map(clk,reset,Capture,Bclk,RXD,BTrigger); | |
71 |
|
70 | |||
72 |
|
71 | RX_REG : Shift_Reg | ||
73 | RX_REG : entity work.Shift_REG |
|
|||
74 | generic map(Data_sz+2) |
|
72 | generic map(Data_sz+2) | |
75 | port map(clk,Bclk,reset,RXD,TXD_Dummy,receive,NwDat_int,zeroVect,RDATA_int); |
|
73 | port map(Bclk,RXD,open,Take,Taken,Dummy,RDATA_int); | |
76 |
|
74 | |||
77 |
TX_REG : |
|
75 | TX_REG : Shift_Reg | |
78 | generic map(Data_sz+2) |
|
76 | generic map(Data_sz+2) | |
79 |
port map( |
|
77 | port map(Bclk,Dummy(0),TXD,Send,Sended,WDATA_int,open); | |
80 |
|
||||
81 |
|
||||
82 |
|
78 | |||
83 | process(clk,reset) |
|
79 | process(clk,reset) | |
84 | begin |
|
80 | begin | |
85 |
if |
|
81 | if(reset ='0')then | |
86 |
|
|
82 | Take <= '0'; | |
87 | elsif clk'event and clk = '1' then |
|
83 | ||
88 | NwDat_int_reg <= NwDat_int; |
|
84 | elsif(clk'event and clk ='1')then | |
89 | if RXD = '1' and NwDat_int = '1' then |
|
85 | Taken_reg <= Taken; | |
90 | receive <= '0'; |
|
86 | ||
91 |
|
|
87 | if(RXD ='0' and Taken ='1')then | |
92 |
|
|
88 | Take <= '1'; | |
|
89 | elsif(Taken ='0')then | |||
|
90 | Take <= '0'; | |||
93 | end if; |
|
91 | end if; | |
94 | if NwDat_int_reg = '0' and NwDat_int = '1' then |
|
92 | ||
95 | NwDat <= '1'; |
|
93 | if (Taken_reg ='0' and Taken ='1') then | |
96 |
|
|
94 | RDATA <= RDATA_int(8 downto 1); | |
97 | elsif ack = '1' then |
|
|||
98 | NwDat <= '0'; |
|
|||
99 | end if; |
|
95 | end if; | |
|
96 | ||||
100 | end if; |
|
97 | end if; | |
101 | end process; |
|
98 | end process; | |
102 |
|
99 | |||
103 | end ar_UART; |
|
100 | end architecture; | |
104 |
|
101 | |||
105 |
|
102 | |||
106 |
|
@@ -1,97 +1,96 | |||||
1 | ------------------------------------------------------------------------------ |
|
1 | ------------------------------------------------------------------------------ | |
2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |
4 | -- |
|
4 | -- | |
5 | -- This program is free software; you can redistribute it and/or modify |
|
5 | -- This program is free software; you can redistribute it and/or modify | |
6 | -- it under the terms of the GNU General Public License as published by |
|
6 | -- it under the terms of the GNU General Public License as published by | |
7 | -- the Free Software Foundation; either version 3 of the License, or |
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |
8 | -- (at your option) any later version. |
|
8 | -- (at your option) any later version. | |
9 | -- |
|
9 | -- | |
10 | -- This program is distributed in the hope that it will be useful, |
|
10 | -- This program is distributed in the hope that it will be useful, | |
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | -- GNU General Public License for more details. |
|
13 | -- GNU General Public License for more details. | |
14 | -- |
|
14 | -- | |
15 | -- You should have received a copy of the GNU General Public License |
|
15 | -- You should have received a copy of the GNU General Public License | |
16 | -- along with this program; if not, write to the Free Software |
|
16 | -- along with this program; if not, write to the Free Software | |
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
18 | ------------------------------------------------------------------------------- |
|
18 | ------------------------------------------------------------------------------- | |
19 | library ieee; |
|
19 | library ieee; | |
20 | use ieee.std_logic_1164.all; |
|
20 | use ieee.std_logic_1164.all; | |
21 | library grlib; |
|
21 | library grlib; | |
22 | use grlib.amba.all; |
|
22 | use grlib.amba.all; | |
23 | -- pragma translate_off |
|
23 | -- pragma translate_off | |
24 | use std.textio.all; |
|
24 | use std.textio.all; | |
25 | -- pragma translate_on |
|
25 | -- pragma translate_on | |
26 | library lpp; |
|
26 | library lpp; | |
27 | use lpp.lpp_amba.all; |
|
27 | use lpp.lpp_amba.all; | |
28 |
|
28 | |||
29 | package lpp_uart is |
|
29 | package lpp_uart is | |
30 |
|
30 | |||
31 | component UART is |
|
31 | component UART is | |
32 | generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee |
|
32 | generic(Data_sz : integer := 8); --! Constante de taille pour un mot de donnee | |
33 | port( |
|
33 | port( | |
34 | clk : in std_logic; --! Horloge a 25Mhz du systeme |
|
34 | clk : in std_logic; --! Horloge a 25Mhz du systeme | |
35 | reset : in std_logic; --! Reset du systeme |
|
35 | reset : in std_logic; --! Reset du systeme | |
36 | TXD : out std_logic; --! Transmission, cote PC |
|
36 | TXD : out std_logic; --! Transmission, cote PC | |
37 | RXD : in std_logic; --! Reception, cote PC |
|
37 | RXD : in std_logic; --! Reception, cote PC | |
38 | Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global |
|
38 | Capture : in std_logic; --! "Reset" cible pour le generateur de bauds, ici indissocie du reset global | |
39 | NwDat : out std_logic; --! Flag, Nouvelle donnee presente |
|
39 | NwDat : out std_logic; --! Flag, Nouvelle donnee presente | |
40 | ACK : in std_logic; --! Flag, Reponse au flag precedent |
|
40 | ACK : in std_logic; --! Flag, Reponse au flag precedent | |
41 | Send : in std_logic; --! Flag, Demande d'envoi sur le bus |
|
41 | Send : in std_logic; --! Flag, Demande d'envoi sur le bus | |
42 | Sended : out std_logic; --! Flag, Envoi termine |
|
42 | Sended : out std_logic; --! Flag, Envoi termine | |
43 | BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission |
|
43 | BTrigger : out std_logic_vector(11 downto 0); --! Registre contenant la valeur du diviseur de frequence pour la transmission | |
44 |
RDATA : out std_logic_vector(Data_sz-1 downto 0); --! |
|
44 | RDATA : out std_logic_vector(Data_sz-1 downto 0); --! Current read word | |
45 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur |
|
45 | WDATA : in std_logic_vector(Data_sz-1 downto 0) --! Mot de donnee a transmettre a l'utilisateur | |
46 | ); |
|
46 | ); | |
47 | end component; |
|
47 | end component; | |
48 |
|
48 | |||
49 |
|
49 | |||
50 |
component Shift_R |
|
50 | component Shift_Reg is | |
51 | generic(Data_sz : integer := 10); |
|
51 | generic( | |
|
52 | Data_sz : integer := 10 --! Width of the shift register | |||
|
53 | ); | |||
52 | port( |
|
54 | port( | |
53 |
clk |
|
55 | Sclk : in std_logic; --! Serial clock | |
54 |
S |
|
56 | SIN : in std_logic; --! Serial data in | |
55 | reset : in std_logic; |
|
57 | SOUT : out std_logic; --! Serial data out | |
56 | SIN : in std_logic; |
|
58 | Serialize : in std_logic; --! Launch serialization | |
57 | SOUT : out std_logic; |
|
59 | Serialized : out std_logic; --! Serialization complete | |
58 | Serialize : in std_logic; |
|
60 | D : in std_logic_vector(Data_sz-1 downto 0); --! Parallel data to be shifted out | |
59 | Serialized : out std_logic; |
|
61 | Q : out std_logic_vector(Data_sz-1 downto 0) --! Unserialized data | |
60 | D : in std_logic_vector(Data_sz-1 downto 0); |
|
|||
61 | Q : out std_logic_vector(Data_sz-1 downto 0) |
|
|||
62 |
|
||||
63 | ); |
|
62 | ); | |
64 | end component; |
|
63 | end component; | |
65 |
|
64 | |||
66 |
|
65 | |||
67 | component BaudGen is |
|
66 | component BaudGen is | |
68 | port( |
|
67 | port( | |
69 | clk : in std_logic; |
|
68 | clk : in std_logic; | |
70 | reset : in std_logic; |
|
69 | reset : in std_logic; | |
71 | Capture : in std_logic; |
|
70 | Capture : in std_logic; | |
72 | Bclk : out std_logic; |
|
71 | Bclk : out std_logic; | |
73 | RXD : in std_logic; |
|
72 | RXD : in std_logic; | |
74 | BTrigger : out std_logic_vector(11 downto 0) |
|
73 | BTrigger : out std_logic_vector(11 downto 0) | |
75 | ); |
|
74 | ); | |
76 | end component; |
|
75 | end component; | |
77 |
|
76 | |||
78 | component APB_UART is |
|
77 | component APB_UART is | |
79 | generic ( |
|
78 | generic ( | |
80 | pindex : integer := 0; |
|
79 | pindex : integer := 0; | |
81 | paddr : integer := 0; |
|
80 | paddr : integer := 0; | |
82 | pmask : integer := 16#fff#; |
|
81 | pmask : integer := 16#fff#; | |
83 | pirq : integer := 0; |
|
82 | pirq : integer := 0; | |
84 | abits : integer := 8; |
|
83 | abits : integer := 8; | |
85 | Data_sz : integer := 8); |
|
84 | Data_sz : integer := 8); | |
86 | port ( |
|
85 | port ( | |
87 | clk : in std_logic; |
|
86 | clk : in std_logic; | |
88 | rst : in std_logic; |
|
87 | rst : in std_logic; | |
89 | apbi : in apb_slv_in_type; |
|
88 | apbi : in apb_slv_in_type; | |
90 | apbo : out apb_slv_out_type; |
|
89 | apbo : out apb_slv_out_type; | |
91 | TXD : out std_logic; |
|
90 | TXD : out std_logic; | |
92 | RXD : in std_logic |
|
91 | RXD : in std_logic | |
93 | ); |
|
92 | ); | |
94 | end component; |
|
93 | end component; | |
95 |
|
94 | |||
96 |
|
95 | |||
97 | end lpp_uart; |
|
96 | end lpp_uart; |
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