HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r561:fafb37280653

EQM 2.1.67

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r561:fafb37280653

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boards/em-LeonLPP-A3PE3kL-v3-core1/LFR_EM_synthesis.sdc +5 -6

             # Clocks
             #
+            define_clock  -name {clk100MHz}    -freq 100    -clockgroup default_clkgroup_50 -route 5
-            define_clock  {clk100MHz} -name {clk100MHz}  -freq 100    -clockgroup default_clkgroup -route 5
+            define_clock  -name {clk49_152MHz} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
-            define_clock  {clk49_152MHz} -name {clk49_152MHz}  -freq 49.152 -clockgroup default_clkgroup -route 5
             #
             # Clock to Clock
             #
             # Inputs/Outputs
             #
-            define_output_delay -disable     -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
-            define_input_delay -disable      -default  5.00 -improve 0.00 -route 0.00 -ref {clk:r}
             #
             # False Path
             #
+            set_false_path -from reset
             #
             # Path Delay
             #
             #
             # Attributes
             #
             define_global_attribute          syn_useioff {1}
             define_global_attribute -disable syn_netlist_hierarchy {0}
-            define_attribute          {etx_clk} syn_noclockbuf {1}
             #
             # I/O standards

designs/LFR-EQM-WFP_MS/LFR-EQM.vhd +15 -11

               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
-              SIGNAL rstn : STD_LOGIC;
+              SIGNAL rstn_25 : STD_LOGIC;
+              SIGNAL rstn_24 : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
-              rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
+              rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
+              rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
               PROCESS(clk50MHz)
               BEGIN
                   USES_IAP_MEMCTRLR => 1)
                 PORT MAP (
                   clk    => clk_25,
-                  reset  => rstn,
+                  reset  => rstn_25,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
-                  clk25MHz      => clk_25,
+                  clk25MHz          => clk_25,
-                  clk24_576MHz  => clk_24,          -- 49.152MHz/2
+                  resetn_25MHz      => rstn_25,      --      TODO
-                  resetn        => rstn,
+                  clk24_576MHz      => clk_24,          -- 49.152MHz/2
+                  resetn_24_576MHz  => rstn_24,      --      TODO
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
-                PORT MAP(rstn, clk_25, spw_rxclk(0),
+                PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
-              LFR_rstn <= LFR_soft_rstn AND rstn;
+              LFR_rstn <= LFR_soft_rstn AND rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"02013F")  -- aa.bb.cc version
+                  top_lfr_version        => X"020144")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
-                  cnv_rstn   => rstn,
+                  cnv_rstn   => rstn_24,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
-                  rstn       => rstn,
+                  rstn       => rstn_25,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,

designs/LFR-em-WFP_MS/LFR-em.vhd +18 -14

               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
-              SIGNAL rstn : STD_LOGIC;
+              SIGNAL rstn_25 : STD_LOGIC;
+              SIGNAL rstn_24 : STD_LOGIC;
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn      : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
-              -----------------------------------------------------------------------------
+              ----------------------------------------------------------------------------
               SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
-              rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
+              rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
+              rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
               PROCESS(clk100MHz)
               BEGIN
               -----------------------------------------------------------------------------
-              PROCESS (clk_25, rstn)
+              PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
-                IF rstn = '0' THEN                  -- asynchronous reset (active low)
+                IF rstn_25 = '0' THEN                  -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                   USES_IAP_MEMCTRLR => 0)
                 PORT MAP (
                   clk    => clk_25,
-                  reset  => rstn,
+                  reset  => rstn_25,
                   errorn => OPEN,
                   ahbrxd => TAG1,
                   FIRST_DIVISION   => 374,  -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
-                  clk25MHz      => clk_25,
+                  clk25MHz          => clk_25,
-                  clk24_576MHz  => clk_24,          -- 49.152MHz/2
+                  resetn_25MHz      => rstn_25,      --      TODO
-                  resetn        => rstn,
+                  clk24_576MHz      => clk_24,          -- 49.152MHz/2
+                  resetn_24_576MHz  => rstn_24,      --      TODO
                   grspw_tick    => swno.tickout,
                   apbi          => apbi_ext,
                   apbo          => apbo_ext(6),
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
-                PORT MAP(rstn, clk_25, spw_rxclk(0),
+                PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
-              LFR_rstn <= LFR_soft_rstn AND rstn;
+              LFR_rstn <= LFR_soft_rstn AND rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010143")  -- aa.bb.cc version
+                  top_lfr_version        => X"010144")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                   FILTER_ENABLED  => 16#FF#)
                 PORT MAP (
                   cnv_clk    => clk_24,
-                  cnv_rstn   => rstn,
+                  cnv_rstn   => rstn_24,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
-                  rstn       => rstn,
+                  rstn       => rstn_25,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH_s,
                   sample     => sample,

designs/LFR-em-WFP_MS/Makefile +1 -1

             #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
             PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL_withHK-DAC.pdc
-            #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
+            SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
             SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +3 -14

               PROCESS (clk_50, reset)
               BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+                IF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
-                  clk_50_s   <= '0';
-                  rstn_50    <= '0';
-                  rstn_50_d1 <= '0';
-                  rstn_50_d2 <= '0';
-                  rstn_50_d3 <= '0';
-                ELSIF clk_50'EVENT AND clk_50 = '1' THEN  -- rising clock edge
                   clk_50_s   <= NOT clk_50_s;
-                  rstn_50_d1 <= '1';
-                  rstn_50_d2 <= rstn_50_d1;
-                  rstn_50_d3 <= rstn_50_d2;
-                  rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
-              PROCESS (clk_50_s, rstn_50)
+              PROCESS (clk_50_s, reset)
               BEGIN  -- PROCESS
-                IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
+                IF reset = '0' THEN               -- asynchronous reset (active low)
                   clk_25     <= '0';
                   rstn_25    <= '0';
                   rstn_25_d1 <= '0';

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