##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

add comments for clk_50 frequency in the code (ALTRAN request)
pellion -
r610:f9824a3b6ae2 simu_with_Leon3
parent child
Show More
Show file before | Show file after | Hide comments
@@ -48,7 +48,12 USE lpp.lpp_leon3_soc_pkg.ALL;
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 -----------------------------------------------------------------------------
52 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
53 -- clk_50 frequency is 100 Mhz !
51 54 clk_50 : IN STD_LOGIC;
55 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
56 -----------------------------------------------------------------------------
52 57 clk_49 : IN STD_LOGIC;
53 58 reset : IN STD_LOGIC;
54 59 --BPs
@@ -218,45 +223,18 ARCHITECTURE beh OF MINI_LFR_top IS
218 223 SIGNAL nSRAM_READY : STD_LOGIC;
219 224
220 225 BEGIN -- beh
221
222 -----------------------------------------------------------------------------
223 -- CLK
226
224 227 -----------------------------------------------------------------------------
225
226 --PROCESS(clk_50)
227 --BEGIN
228 -- IF clk_50'EVENT AND clk_50 = '1' THEN
229 -- clk_50_s <= NOT clk_50_s;
230 -- END IF;
231 --END PROCESS;
232
233 --PROCESS(clk_50_s)
234 --BEGIN
235 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
236 -- clk_25 <= NOT clk_25;
237 -- END IF;
238 --END PROCESS;
239
240 --PROCESS(clk_49)
241 --BEGIN
242 -- IF clk_49'EVENT AND clk_49 = '1' THEN
243 -- clk_24 <= NOT clk_24;
244 -- END IF;
245 --END PROCESS;
246
247 --PROCESS(clk_25)
248 --BEGIN
249 -- IF clk_25'EVENT AND clk_25 = '1' THEN
250 -- rstn_25 <= reset;
251 -- END IF;
252 --END PROCESS;
253
228 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
229 -- clk_50 frequency is 100 Mhz !
254 230 PROCESS (clk_50, reset)
255 231 BEGIN -- PROCESS
256 232 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
257 233 clk_50_s <= NOT clk_50_s;
258 234 END IF;
259 235 END PROCESS;
236 -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!
237 -----------------------------------------------------------------------------
260 238
261 239 PROCESS (clk_50_s, reset)
262 240 BEGIN -- PROCESS
@@ -300,32 +278,10 BEGIN -- beh
300 278 LED0 <= '0';
301 279 LED1 <= '0';
302 280 LED2 <= '0';
303 --IO1 <= '0';
304 --IO2 <= '1';
305 --IO3 <= '0';
306 --IO4 <= '0';
307 --IO5 <= '0';
308 --IO6 <= '0';
309 --IO7 <= '0';
310 --IO8 <= '0';
311 --IO9 <= '0';
312 --IO10 <= '0';
313 --IO11 <= '0';
314 281 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
315 282 LED0 <= '0';
316 283 LED1 <= '1';
317 284 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
318 --IO1 <= '1';
319 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
320 --IO3 <= ADC_SDO(0);
321 --IO4 <= ADC_SDO(1);
322 --IO5 <= ADC_SDO(2);
323 --IO6 <= ADC_SDO(3);
324 --IO7 <= ADC_SDO(4);
325 --IO8 <= ADC_SDO(5);
326 --IO9 <= ADC_SDO(6);
327 --IO10 <= ADC_SDO(7);
328 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
329 285 END IF;
330 286 END PROCESS;
331 287
@@ -337,7 +293,6 BEGIN -- beh
337 293 I00_s <= NOT I00_s;
338 294 END IF;
339 295 END PROCESS;
340 -- IO0 <= I00_s;
341 296
342 297 --UARTs
343 298 nCTS1 <= '1';
@@ -639,42 +594,9 BEGIN -- beh
639 594 gpioi.sig_en <= (OTHERS => '0');
640 595 gpioi.sig_in <= (OTHERS => '0');
641 596 gpioi.din <= (OTHERS => '0');
642 --pio_pad_0 : iopad
643 -- GENERIC MAP (tech => CFG_PADTECH)
644 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
645 --pio_pad_1 : iopad
646 -- GENERIC MAP (tech => CFG_PADTECH)
647 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
648 --pio_pad_2 : iopad
649 -- GENERIC MAP (tech => CFG_PADTECH)
650 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
651 --pio_pad_3 : iopad
652 -- GENERIC MAP (tech => CFG_PADTECH)
653 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
654 --pio_pad_4 : iopad
655 -- GENERIC MAP (tech => CFG_PADTECH)
656 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
657 --pio_pad_5 : iopad
658 -- GENERIC MAP (tech => CFG_PADTECH)
659 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
660 --pio_pad_6 : iopad
661 -- GENERIC MAP (tech => CFG_PADTECH)
662 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
663 --pio_pad_7 : iopad
664 -- GENERIC MAP (tech => CFG_PADTECH)
665 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
666
667 597 PROCESS (clk_25, rstn_25)
668 598 BEGIN -- PROCESS
669 599 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
670 -- --IO0 <= '0';
671 -- IO1 <= '0';
672 -- IO2 <= '0';
673 -- IO3 <= '0';
674 -- IO4 <= '0';
675 -- IO5 <= '0';
676 -- IO6 <= '0';
677 -- IO7 <= '0';
678 600 IO8 <= '0';
679 601 IO9 <= '0';
680 602 IO10 <= '0';
@@ -682,66 +604,26 BEGIN -- beh
682 604 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
683 605 CASE gpioo.dout(2 DOWNTO 0) IS
684 606 WHEN "011" =>
685 -- --IO0 <= observation_reg(0 );
686 -- IO1 <= observation_reg(1 );
687 -- IO2 <= observation_reg(2 );
688 -- IO3 <= observation_reg(3 );
689 -- IO4 <= observation_reg(4 );
690 -- IO5 <= observation_reg(5 );
691 -- IO6 <= observation_reg(6 );
692 -- IO7 <= observation_reg(7 );
693 607 IO8 <= observation_reg(8);
694 608 IO9 <= observation_reg(9);
695 609 IO10 <= observation_reg(10);
696 610 IO11 <= observation_reg(11);
697 611 WHEN "001" =>
698 -- --IO0 <= observation_reg(0 + 12);
699 -- IO1 <= observation_reg(1 + 12);
700 -- IO2 <= observation_reg(2 + 12);
701 -- IO3 <= observation_reg(3 + 12);
702 -- IO4 <= observation_reg(4 + 12);
703 -- IO5 <= observation_reg(5 + 12);
704 -- IO6 <= observation_reg(6 + 12);
705 -- IO7 <= observation_reg(7 + 12);
706 612 IO8 <= observation_reg(8 + 12);
707 613 IO9 <= observation_reg(9 + 12);
708 614 IO10 <= observation_reg(10 + 12);
709 615 IO11 <= observation_reg(11 + 12);
710 616 WHEN "010" =>
711 -- --IO0 <= observation_reg(0 + 12 + 12);
712 -- IO1 <= observation_reg(1 + 12 + 12);
713 -- IO2 <= observation_reg(2 + 12 + 12);
714 -- IO3 <= observation_reg(3 + 12 + 12);
715 -- IO4 <= observation_reg(4 + 12 + 12);
716 -- IO5 <= observation_reg(5 + 12 + 12);
717 -- IO6 <= observation_reg(6 + 12 + 12);
718 -- IO7 <= observation_reg(7 + 12 + 12);
719 617 IO8 <= '0';
720 618 IO9 <= '0';
721 619 IO10 <= '0';
722 620 IO11 <= '0';
723 621 WHEN "000" =>
724 -- --IO0 <= observation_vector_0(0 );
725 -- IO1 <= observation_vector_0(1 );
726 -- IO2 <= observation_vector_0(2 );
727 -- IO3 <= observation_vector_0(3 );
728 -- IO4 <= observation_vector_0(4 );
729 -- IO5 <= observation_vector_0(5 );
730 -- IO6 <= observation_vector_0(6 );
731 -- IO7 <= observation_vector_0(7 );
732 622 IO8 <= observation_vector_0(8);
733 623 IO9 <= observation_vector_0(9);
734 624 IO10 <= observation_vector_0(10);
735 625 IO11 <= observation_vector_0(11);
736 626 WHEN "100" =>
737 -- --IO0 <= observation_vector_1(0 );
738 -- IO1 <= observation_vector_1(1 );
739 -- IO2 <= observation_vector_1(2 );
740 -- IO3 <= observation_vector_1(3 );
741 -- IO4 <= observation_vector_1(4 );
742 -- IO5 <= observation_vector_1(5 );
743 -- IO6 <= observation_vector_1(6 );
744 -- IO7 <= observation_vector_1(7 );
745 627 IO8 <= observation_vector_1(8);
746 628 IO9 <= observation_vector_1(9);
747 629 IO10 <= observation_vector_1(10);
General Comments 0
You need to be logged in to leave comments. Login now