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HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

merge simu_with_leon3...
pellion -
r590:f6390d699855 JC
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@@ -165,14 +165,47 ARCHITECTURE beh OF LFR_EQM IS
165 SIGNAL clk_25_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
166
166
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168
168
169 SIGNAL rstn_50 : STD_LOGIC;
170 SIGNAL clk_lock : STD_LOGIC;
171 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
173
174 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
175 SIGNAL ahbrxd: STD_LOGIC;
176 SIGNAL ahbtxd: STD_LOGIC;
177 SIGNAL urxd1 : STD_LOGIC;
178 SIGNAL utxd1 : STD_LOGIC;
169 BEGIN -- beh
179 BEGIN -- beh
170
180
171 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182 -- CLK_LOCK
183 -----------------------------------------------------------------------------
184 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
185
186 PROCESS (clk50MHz_int, rstn_50)
187 BEGIN -- PROCESS
188 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
189 clk_lock <= '0';
190 clk_busy_counter <= (OTHERS => '0');
191 nSRAM_BUSY_reg <= '0';
192 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
193 nSRAM_BUSY_reg <= nSRAM_BUSY;
194 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
195 IF clk_busy_counter = "1111" THEN
196 clk_lock <= '1';
197 ELSE
198 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
199 END IF;
200 END IF;
201 END IF;
202 END PROCESS;
203
204 -----------------------------------------------------------------------------
172 -- CLK
205 -- CLK
173 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
207 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
208 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
176
209
177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
210 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 clk50MHz_int <= clk50MHz;
211 clk50MHz_int <= clk50MHz;
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@@ -74,7 +74,7 ARCHITECTURE Behavioral OF lpp_dma_SEND1
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
76
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -85,6 +85,13 ARCHITECTURE Behavioral OF lpp_dma_SEND1
85
85
86 SIGNAL bus_request : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
90
91 SIGNAL HREADY_pre : STD_LOGIC;
92 SIGNAL HREADY_falling : STD_LOGIC;
93
94 SIGNAL inhib_ren : STD_LOGIC;
88
95
89 BEGIN
96 BEGIN
90
97
@@ -111,23 +118,41 BEGIN
111
118
112 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
120 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
121 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
115
122
116 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
124 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 --ren <= NOT beat;
125 --ren <= NOT beat;
119 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
127
128 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
129
130
120 PROCESS (clk, rstn)
131 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
132 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
133 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
134 state <= IDLE;
124 done <= '0';
135 done <= '0';
136 ren <= '1';
125 address_counter_reg <= (OTHERS => '0');
137 address_counter_reg <= (OTHERS => '0');
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
138 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 AHB_Master_Out.HBUSREQ <= '0';
139 AHB_Master_Out.HBUSREQ <= '0';
128 AHB_Master_Out.HLOCK <= '0';
140 AHB_Master_Out.HLOCK <= '0';
141
142 data_reg <= (OTHERS => '0');
143
144 HREADY_pre <= '0';
145 inhib_ren <= '0';
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
146 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
147 HREADY_pre <= AHB_Master_In.HREADY;
148
149 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
150 data_reg <= data;
151 END IF;
152
130 done <= '0';
153 done <= '0';
154 ren <= '1';
155 inhib_ren <= '0';
131 CASE state IS
156 CASE state IS
132 WHEN IDLE =>
157 WHEN IDLE =>
133 AHB_Master_Out.HBUSREQ <= '0';
158 AHB_Master_Out.HBUSREQ <= '0';
@@ -135,30 +160,35 BEGIN
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
160 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 address_counter_reg <= (OTHERS => '0');
161 address_counter_reg <= (OTHERS => '0');
137 IF send = '1' THEN
162 IF send = '1' THEN
138 AHB_Master_Out.HBUSREQ <= '1';
163 state <= s_INIT_TRANS;
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
142 END IF;
164 END IF;
143
165
166 WHEN s_INIT_TRANS =>
167 AHB_Master_Out.HBUSREQ <= '1';
168 AHB_Master_Out.HLOCK <= '1';
169 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
170 state <= s_ARBITER;
171
144 WHEN s_ARBITER =>
172 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
173 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
174 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
176 address_counter_reg <= (OTHERS => '0');
149
177
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
178 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
179 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
180 state <= s_CTRL;
153 END IF;
181 END IF;
154
182
155 WHEN s_CTRL =>
183 WHEN s_CTRL =>
184 inhib_ren <= '1';
156 AHB_Master_Out.HBUSREQ <= '1';
185 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
186 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
187 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
188 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
189 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
190 state <= s_CTRL_DATA;
191 --ren <= '0';
162 END IF;
192 END IF;
163
193
164 WHEN s_CTRL_DATA =>
194 WHEN s_CTRL_DATA =>
@@ -176,11 +206,21 BEGIN
176 state <= s_DATA;
206 state <= s_DATA;
177 END IF;
207 END IF;
178
208
209 ren <= HREADY_falling;
210
211 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
212 -- ren <= '0';
213 --END IF;
214
215
179 WHEN s_DATA =>
216 WHEN s_DATA =>
217 ren <= HREADY_falling;
218
180 AHB_Master_Out.HBUSREQ <= '0';
219 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
220 --AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
221 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
222 IF AHB_Master_In.HREADY = '1' THEN
223 AHB_Master_Out.HLOCK <= '0';
184 state <= IDLE;
224 state <= IDLE;
185 done <= '1';
225 done <= '1';
186 END IF;
226 END IF;
@@ -193,7 +233,9 BEGIN
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
233 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
234 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
236
237
238 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197
239
198 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
199 --PROCESS (clk, rstn)
241 --PROCESS (clk, rstn)
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