@@ -169,14 +169,41 ARCHITECTURE beh OF LFR_EQM IS | |||||
169 | SIGNAL clk_25_int : STD_LOGIC := '0'; |
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169 | SIGNAL clk_25_int : STD_LOGIC := '0'; | |
170 |
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170 | |||
171 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; |
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171 | component clkint port(A : in std_ulogic; Y :out std_ulogic); end component; | |
172 |
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172 | |||
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173 | SIGNAL rstn_50 : STD_LOGIC; | |||
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174 | SIGNAL clk_lock : STD_LOGIC; | |||
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175 | SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0); | |||
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176 | SIGNAL nSRAM_BUSY_reg : STD_LOGIC; | |||
173 | BEGIN -- beh |
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177 | BEGIN -- beh | |
174 |
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178 | |||
175 | ----------------------------------------------------------------------------- |
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179 | ----------------------------------------------------------------------------- | |
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180 | -- CLK_LOCK | |||
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181 | ----------------------------------------------------------------------------- | |||
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182 | rst_gen_global : rstgen PORT MAP (reset, clk_50, '1', rstn_50, OPEN); | |||
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183 | ||||
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184 | PROCESS (clk50MHz_int, rstn_50) | |||
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185 | BEGIN -- PROCESS | |||
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186 | IF rstn_50 = '0' THEN -- asynchronous reset (active low) | |||
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187 | clk_lock <= '0'; | |||
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188 | clk_busy_counter <= (OTHERS => '0'); | |||
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189 | nSRAM_BUSY_reg <= '0'; | |||
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190 | ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge | |||
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191 | nSRAM_BUSY_reg <= nSRAM_BUSY; | |||
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192 | IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN | |||
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193 | IF clk_busy_counter = "1111" THEN | |||
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194 | clk_lock = '1'; | |||
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195 | ELSE | |||
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196 | clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4)); | |||
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197 | END IF; | |||
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198 | END IF; | |||
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199 | END IF; | |||
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200 | END PROCESS; | |||
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201 | ||||
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202 | ----------------------------------------------------------------------------- | |||
176 | -- CLK |
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203 | -- CLK | |
177 | ----------------------------------------------------------------------------- |
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204 | ----------------------------------------------------------------------------- | |
178 |
rst_domain25 : rstgen PORT MAP (reset, clk_25, |
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205 | rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN); | |
179 |
rst_domain24 : rstgen PORT MAP (reset, clk_24, |
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206 | rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN); | |
180 |
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207 | |||
181 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); |
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208 | --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int ); | |
182 | clk50MHz_int <= clk50MHz; |
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209 | clk50MHz_int <= clk50MHz; |
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