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LPP DMA v1.0.1...
pellion@stage-ps1.lab-lpp.local -
r102:ecadbe9f5050 JC
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@@ -27,7 +27,7 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 USE grlib.devices.ALL;
28 USE grlib.devices.ALL;
29 USE GRLIB.DMA2AHB_Package.ALL;
29 USE GRLIB.DMA2AHB_Package.ALL;
30 --USE GRLIB.DMA2AHB_TestPackage.ALL;
30
31 LIBRARY lpp;
31 LIBRARY lpp;
32 USE lpp.lpp_amba.ALL;
32 USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
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@@ -28,7 +28,7 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31 --USE GRLIB.DMA2AHB_TestPackage.ALL;
31
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
@@ -136,6 +136,8 ARCHITECTURE Behavioral OF lpp_dma IS
136 SIGNAL fifo_ren_trash : STD_LOGIC;
136 SIGNAL fifo_ren_trash : STD_LOGIC;
137 SIGNAL component_fifo_ren : STD_LOGIC;
137 SIGNAL component_fifo_ren : STD_LOGIC;
138
138
139 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
139 BEGIN
141 BEGIN
140
142
141 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
@@ -149,7 +151,7 BEGIN
149 deviceid => 0,
151 deviceid => 0,
150 version => 0,
152 version => 0,
151 syncrst => 1,
153 syncrst => 1,
152 boundary => 0)
154 boundary => 1) -- set TO TEST
153 PORT MAP (
155 PORT MAP (
154 HCLK => HCLK,
156 HCLK => HCLK,
155 HRESETn => HRESETn,
157 HRESETn => HRESETn,
@@ -158,6 +160,25 BEGIN
158 AHBIn => AHB_Master_In,
160 AHBIn => AHB_Master_In,
159 AHBOut => AHB_Master_Out);
161 AHBOut => AHB_Master_Out);
160
162
163
164 debug_info: PROCESS (HCLK, HRESETn)
165 BEGIN -- PROCESS debug_info
166 IF HRESETn = '0' THEN -- asynchronous reset (active low)
167 debug_reg <= (OTHERS => '0');
168 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
169 debug_reg(0) <= debug_reg(0) OR (DMAOut.Retry );
170 debug_reg(1) <= debug_reg(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
171 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
172 debug_reg(3) <= debug_reg(3) OR (header_send_ko);
173 debug_reg(4) <= debug_reg(4) OR (header_send_ok);
174 debug_reg(5) <= debug_reg(5) OR (component_send_ko);
175 debug_reg(6) <= debug_reg(6) OR (component_send_ok);
176
177 debug_reg(31 DOWNTO 7) <= (OTHERS => '1');
178 END IF;
179 END PROCESS debug_info;
180
181
161 matrix_type <= header(1 DOWNTO 0);
182 matrix_type <= header(1 DOWNTO 0);
162 component_type <= header(5 DOWNTO 2);
183 component_type <= header(5 DOWNTO 2);
163
184
@@ -312,7 +333,6 BEGIN
312 HRESETn => HRESETn,
333 HRESETn => HRESETn,
313 DMAIn => component_dmai,
334 DMAIn => component_dmai,
314 DMAOut => DMAOut,
335 DMAOut => DMAOut,
315
316 send => component_send,
336 send => component_send,
317 address => address,
337 address => address,
318 data => fifo_data,
338 data => fifo_data,
@@ -346,6 +366,8 BEGIN
346 ready_matrix_f2 => ready_matrix_f2,
366 ready_matrix_f2 => ready_matrix_f2,
347 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
367 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
348 error_bad_component_error => error_bad_component_error,
368 error_bad_component_error => error_bad_component_error,
369 --
370 debug_reg => debug_reg,
349 -- OUT
371 -- OUT
350 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
372 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
351 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
373 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
@@ -363,4 +385,3 BEGIN
363 -----------------------------------------------------------------------------
385 -----------------------------------------------------------------------------
364
386
365 END Behavioral;
387 END Behavioral;
366
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@@ -33,6 +33,7 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36 ENTITY lpp_dma_apbreg IS
37 ENTITY lpp_dma_apbreg IS
37 GENERIC (
38 GENERIC (
38 pindex : INTEGER := 4;
39 pindex : INTEGER := 4;
@@ -55,6 +56,7 ENTITY lpp_dma_apbreg IS
55 ready_matrix_f2 : IN STD_LOGIC;
56 ready_matrix_f2 : IN STD_LOGIC;
56 error_anticipating_empty_fifo : IN STD_LOGIC;
57 error_anticipating_empty_fifo : IN STD_LOGIC;
57 error_bad_component_error : IN STD_LOGIC;
58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58
60
59 -- OUT
61 -- OUT
60 status_ready_matrix_f0_0 : OUT STD_LOGIC;
62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
@@ -162,6 +164,7 BEGIN -- beh
162 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
163 WHEN "000100" => prdata <= reg.addr_matrix_f1;
165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
164 WHEN "000101" => prdata <= reg.addr_matrix_f2;
166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
165 WHEN OTHERS => NULL;
168 WHEN OTHERS => NULL;
166 END CASE;
169 END CASE;
167 IF (apbi.pwrite AND apbi.penable) = '1' THEN
170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
@@ -185,9 +188,11 BEGIN -- beh
185 END IF;
188 END IF;
186 END IF;
189 END IF;
187 END PROCESS lpp_dma_apbreg;
190 END PROCESS lpp_dma_apbreg;
191
188 apbo.pirq <= (OTHERS => '0');
192 apbo.pirq <= (OTHERS => '0');
189 apbo.pindex <= pindex;
193 apbo.pindex <= pindex;
190 apbo.pconfig <= pconfig;
194 apbo.pconfig <= pconfig;
191 apbo.prdata <= prdata;
195 apbo.prdata <= prdata;
192
196
197
193 END beh;
198 END beh;
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@@ -103,6 +103,7 PACKAGE lpp_dma_pkg IS
103 ready_matrix_f2 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106
107
107 -- OUT
108 -- OUT
108 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
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@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1
23
2 LIBRARY ieee;
24 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
@@ -57,7 +79,6 BEGIN -- beh
57
79
58 DMAIn.Reset <= '0';
80 DMAIn.Reset <= '0';
59 DMAIn.Address <= (OTHERS => '0');
81 DMAIn.Address <= (OTHERS => '0');
60 -- DMAIn.Data <= (others => '0');
61 DMAIn.Request <= '0';
82 DMAIn.Request <= '0';
62 DMAIn.Store <= '0';
83 DMAIn.Store <= '0';
63 DMAIn.Burst <= '1';
84 DMAIn.Burst <= '1';
@@ -67,7 +88,6 BEGIN -- beh
67
88
68 CASE state IS
89 CASE state IS
69 WHEN IDLE =>
90 WHEN IDLE =>
70 -- ren <= '1';
71 DMAIn.Store <= '1';
91 DMAIn.Store <= '1';
72 DMAIn.Request <= '0';
92 DMAIn.Request <= '0';
73 send_ok <= '0';
93 send_ok <= '0';
@@ -82,20 +102,16 BEGIN -- beh
82 DMAIn.Store <= '1';
102 DMAIn.Store <= '1';
83 END IF;
103 END IF;
84 WHEN REQUEST_BUS =>
104 WHEN REQUEST_BUS =>
85 -- ren <= '1';
86 IF DMAOut.Grant='1' THEN
105 IF DMAOut.Grant = '1' THEN
87 data_counter <= 1;
106 data_counter <= 1;
88 grant_counter <= 1;
107 grant_counter <= 1;
89 -- ren <= '0';
90 state <= SEND_DATA;
108 state <= SEND_DATA;
91 END IF;
109 END IF;
92 WHEN SEND_DATA =>
110 WHEN SEND_DATA =>
93 -- ren <= '1';
94
111
95 IF DMAOut.Fault = '1' THEN
112 IF DMAOut.Fault = '1' THEN
96 DMAIn.Reset <= '0';
113 DMAIn.Reset <= '0';
97 DMAIn.Address <= (others => '0');
114 DMAIn.Address <= (OTHERS => '0');
98 -- DMAIn.Data <= (others => '0');
99 DMAIn.Request <= '0';
115 DMAIn.Request <= '0';
100 DMAIn.Store <= '0';
116 DMAIn.Store <= '0';
101 DMAIn.Burst <= '0';
117 DMAIn.Burst <= '0';
@@ -103,31 +119,28 BEGIN -- beh
103 ELSE
119 ELSE
104
120
105 IF DMAOut.Grant = '1' THEN
121 IF DMAOut.Grant = '1' THEN
106 if grant_counter = 15 then
122 IF grant_counter = 15 THEN
107 DMAIn.Reset <= '0';
123 DMAIn.Reset <= '0';
108 DMAIn.Request <= '0';
124 DMAIn.Request <= '0';
109 DMAIn.Store <= '0';
125 DMAIn.Store <= '0';
110 DMAIn.Burst <= '0';
126 DMAIn.Burst <= '0';
111 else
127 ELSE
112 grant_counter <= grant_counter+1;
128 grant_counter <= grant_counter+1;
113 end if;
129 END IF;
114 END IF;
130 END IF;
115
131
116 IF DMAOut.OKAY = '1' THEN
132 IF DMAOut.OKAY = '1' THEN
117 IF data_counter = 15 THEN
133 IF data_counter = 15 THEN
118 DMAIn.Address <= (others => '0');
134 DMAIn.Address <= (OTHERS => '0');
119 state <= WAIT_LAST_READY;
135 state <= WAIT_LAST_READY;
120 ELSE
136 ELSE
121 --DMAIn.Data <= data;
122 data_counter <= data_counter + 1;
137 data_counter <= data_counter + 1;
123 -- ren <= '0';
124 END IF;
138 END IF;
125 END IF;
139 END IF;
126 END IF;
140 END IF;
127
141
128
142
129 WHEN WAIT_LAST_READY =>
143 WHEN WAIT_LAST_READY =>
130 -- ren <= '1';
131 IF DMAOut.Ready = '1' THEN
144 IF DMAOut.Ready = '1' THEN
132 IF grant_counter = 15 THEN
145 IF grant_counter = 15 THEN
133 state <= IDLE;
146 state <= IDLE;
@@ -139,12 +152,10 BEGIN -- beh
139 END IF;
152 END IF;
140
153
141 WHEN ERROR0 =>
154 WHEN ERROR0 =>
142 -- ren <= '1';
143 state <= ERROR1;
155 state <= ERROR1;
144 WHEN ERROR1 =>
156 WHEN ERROR1 =>
145 send_ok <= '0';
157 send_ok <= '0';
146 send_ko <= '1';
158 send_ko <= '1';
147 -- ren <= '1';
148 state <= IDLE;
159 state <= IDLE;
149 WHEN OTHERS => NULL;
160 WHEN OTHERS => NULL;
150 END CASE;
161 END CASE;
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@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1
23
2 LIBRARY ieee;
24 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
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