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LPP DMA v1.0.1...
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 USE grlib.devices.ALL;
29 29 USE GRLIB.DMA2AHB_Package.ALL;
30 --USE GRLIB.DMA2AHB_TestPackage.ALL;
30
31 31 LIBRARY lpp;
32 32 USE lpp.lpp_amba.ALL;
33 33 USE lpp.apb_devices_list.ALL;
34 34 USE lpp.lpp_memory.ALL;
35 35 LIBRARY techmap;
36 36 USE techmap.gencomp.ALL;
37 37
38 38 ENTITY fifo_test_dma IS
39 39 GENERIC (
40 40 tech : INTEGER := apa3;
41 41 pindex : INTEGER := 0;
42 42 paddr : INTEGER := 0;
43 43 pmask : INTEGER := 16#fff#
44 44 );
45 45 PORT (
46 46 -- AMBA AHB system signals
47 47 HCLK : IN STD_ULOGIC;
48 48 HRESETn : IN STD_ULOGIC;
49 49
50 50 -- AMBA APB Slave Interface
51 51 apbi : IN apb_slv_in_type;
52 52 apbo : OUT apb_slv_out_type;
53 53
54 54 -- FIFO Read interface
55 55 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 56 fifo_empty : OUT STD_LOGIC;
57 57 fifo_ren : IN STD_LOGIC;
58 58
59 59 -- header
60 60 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
61 61 header_val : OUT STD_LOGIC;
62 62 header_ack : IN STD_LOGIC
63 63 );
64 64 END;
65 65
66 66 ARCHITECTURE Behavioral OF fifo_test_dma IS
67 67 CONSTANT REVISION : INTEGER := 1;
68 68 CONSTANT pconfig : apb_config_type := (
69 69 0 => ahb_device_reg (VENDOR_LPP, 0 , 0, REVISION, 0),
70 70 1 => apb_iobar(paddr, pmask));
71 71
72 72 TYPE lpp_test_dma_regs IS RECORD
73 73 tt : STD_LOGIC;
74 74 END RECORD;
75 75 SIGNAL reg : lpp_test_dma_regs;
76 76
77 77 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 78 -----------------------------------------------------------------------------
79 79 SIGNAL fifo_empty_s : STD_LOGIC;
80 80 SIGNAL fifo_raddr : STD_LOGIC_VECTOR(7 DOWNTO 0);
81 81 SIGNAL fifo_wen : STD_LOGIC;
82 82 SIGNAL fifo_wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 SIGNAL fifo_full : STD_LOGIC;
84 84 SIGNAL fifo_waddr : STD_LOGIC_VECTOR(7 DOWNTO 0);
85 85 -----------------------------------------------------------------------------
86 86 SIGNAL fifo_nb_data : STD_LOGIC_VECTOR( 7 DOWNTO 0);
87 87 SIGNAL fifo_nb_data_s : STD_LOGIC_VECTOR( 7 DOWNTO 0);
88 88 -----------------------------------------------------------------------------
89 89 SIGNAL header_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
90 90 SIGNAL header_val_s : STD_LOGIC;
91 91 BEGIN
92 92
93 93 lpp_fifo_i : lpp_fifo
94 94 GENERIC MAP (
95 95 tech => tech,
96 96 Enable_ReUse => '0',
97 97 DataSz => 32,
98 98 abits => 8)
99 99 PORT MAP (
100 100 rstn => HRESETn,
101 101 ReUse => '0',
102 102
103 103 rclk => HCLK,
104 104 ren => fifo_ren,
105 105 rdata => fifo_data,
106 106 empty => fifo_empty_s,
107 107 raddr => fifo_raddr,
108 108
109 109 wclk => HCLK,
110 110 wen => fifo_wen,
111 111 wdata => fifo_wdata,
112 112 full => fifo_full,
113 113 waddr => fifo_waddr); -- OUT
114 114
115 115 fifo_nb_data_s(7) <= '1' WHEN (fifo_waddr < fifo_raddr) ELSE '0';
116 116 fifo_nb_data_s(6 DOWNTO 0) <= (OTHERS => '0');
117 117 fifo_nb_data <= (fifo_waddr - fifo_raddr) + fifo_nb_data_s;
118 118
119 119 fifo_empty <= fifo_empty_s;
120 120 header <= header_s;
121 121 header_val <= header_val_s;
122 122 -----------------------------------------------------------------------------
123 123
124 124 apb_reg_p : PROCESS (HCLK, HRESETn)
125 125 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
126 126 BEGIN -- PROCESS lpp_dma_top
127 127 IF HRESETn = '0' THEN -- asynchronous reset (active low)
128 128 prdata <= (OTHERS => '0');
129 129 fifo_wdata <= (OTHERS => '0');
130 130 fifo_wen <= '1';
131 131 header_val_s <= '0';
132 132 header_s <= (OTHERS => '0');
133 133 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
134 134 paddr := "000000";
135 135 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
136 136 fifo_wen <= '1';
137 137 header_val_s <= header_val_s AND (NOT header_ack);
138 138 IF (apbi.psel(pindex)) = '1' THEN
139 139 -- APB DMA READ --
140 140 CASE paddr(7 DOWNTO 2) IS
141 141 WHEN "000000" => prdata( 7 DOWNTO 0) <= fifo_waddr;
142 142 prdata(15 DOWNTO 8) <= fifo_raddr;
143 143 prdata(23 DOWNTO 16) <= fifo_nb_data;
144 144 prdata(24) <= fifo_full;
145 145 prdata(25) <= fifo_empty_s;
146 146 WHEN "000001" => prdata(31 DOWNTO 0) <= header_s;
147 147
148 148 WHEN OTHERS => prdata <= (OTHERS => '0');
149 149 END CASE;
150 150 IF (apbi.pwrite AND apbi.penable) = '1' THEN
151 151 -- APB DMA WRITE --
152 152 CASE paddr(7 DOWNTO 2) IS
153 153 WHEN "000000" => fifo_wdata <= apbi.pwdata;
154 154 fifo_wen <= '0';
155 155 WHEN "000001" => header_s <= apbi.pwdata;
156 156 header_val_s <= '1';
157 157 WHEN OTHERS => NULL;
158 158 END CASE;
159 159 END IF;
160 160 END IF;
161 161 END IF;
162 162 END PROCESS apb_reg_p;
163 163 apbo.pirq <= (OTHERS => '0');
164 164 apbo.pindex <= pindex;
165 165 apbo.pconfig <= pconfig;
166 166 apbo.prdata <= prdata;
167 167
168 168 END Behavioral;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 USE GRLIB.DMA2AHB_Package.ALL;
31 --USE GRLIB.DMA2AHB_TestPackage.ALL;
31
32 32 LIBRARY lpp;
33 33 USE lpp.lpp_amba.ALL;
34 34 USE lpp.apb_devices_list.ALL;
35 35 USE lpp.lpp_memory.ALL;
36 36 USE lpp.lpp_dma_pkg.ALL;
37 37 LIBRARY techmap;
38 38 USE techmap.gencomp.ALL;
39 39
40 40
41 41 ENTITY lpp_dma IS
42 42 GENERIC (
43 43 tech : INTEGER := inferred;
44 44 hindex : INTEGER := 2;
45 45 pindex : INTEGER := 4;
46 46 paddr : INTEGER := 4;
47 47 pmask : INTEGER := 16#fff#;
48 48 pirq : INTEGER := 0);
49 49 PORT (
50 50 -- AMBA AHB system signals
51 51 HCLK : IN STD_ULOGIC;
52 52 HRESETn : IN STD_ULOGIC;
53 53
54 54 -- AMBA APB Slave Interface
55 55 apbi : IN apb_slv_in_type;
56 56 apbo : OUT apb_slv_out_type;
57 57
58 58 -- AMBA AHB Master Interface
59 59 AHB_Master_In : IN AHB_Mst_In_Type;
60 60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
61 61
62 62 -- fifo interface
63 63 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 64 fifo_empty : IN STD_LOGIC;
65 65 fifo_ren : OUT STD_LOGIC;
66 66
67 67 -- header
68 68 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69 header_val : IN STD_LOGIC;
70 70 header_ack : OUT STD_LOGIC
71 71 );
72 72 END;
73 73
74 74 ARCHITECTURE Behavioral OF lpp_dma IS
75 75 -----------------------------------------------------------------------------
76 76 SIGNAL DMAIn : DMA_In_Type;
77 77 SIGNAL header_dmai : DMA_In_Type;
78 78 SIGNAL component_dmai : DMA_In_Type;
79 79 SIGNAL DMAOut : DMA_OUt_Type;
80 80
81 81 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
82 82 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
83 83 SIGNAL ready_matrix_f1 : STD_LOGIC;
84 84 SIGNAL ready_matrix_f2 : STD_LOGIC;
85 85 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
86 86 SIGNAL error_bad_component_error : STD_LOGIC;
87 87
88 88 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
89 89 SIGNAL config_active_interruption_onError : STD_LOGIC;
90 90 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
91 91 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
92 92 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
93 93 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
94 94 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
95 95 SIGNAL status_error_bad_component_error : STD_LOGIC;
96 96 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 97 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 98 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 99 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
100 100 -----------------------------------------------------------------------------
101 101
102 102 -----------------------------------------------------------------------------
103 103 -----------------------------------------------------------------------------
104 104 TYPE state_DMAWriteBurst IS (IDLE,
105 105 TRASH_FIFO,
106 106 WAIT_HEADER_ACK,
107 107 SEND_DATA,
108 108 WAIT_DATA_ACK,
109 109 CHECK_LENGTH
110 110 );
111 111 SIGNAL state : state_DMAWriteBurst := IDLE;
112 112
113 113 SIGNAL nbSend : INTEGER;
114 114 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 115 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 116 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 117 SIGNAL header_check_ok : STD_LOGIC;
118 118 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 119 SIGNAL send_matrix : STD_LOGIC;
120 120 SIGNAL request : STD_LOGIC;
121 121 SIGNAL remaining_data_request : INTEGER;
122 122 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 123 -----------------------------------------------------------------------------
124 124 -----------------------------------------------------------------------------
125 125 SIGNAL header_select : STD_LOGIC;
126 126
127 127 SIGNAL header_send : STD_LOGIC;
128 128 SIGNAL header_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 129 SIGNAL header_send_ok : STD_LOGIC;
130 130 SIGNAL header_send_ko : STD_LOGIC;
131 131
132 132 SIGNAL component_send : STD_LOGIC;
133 133 SIGNAL component_send_ok : STD_LOGIC;
134 134 SIGNAL component_send_ko : STD_LOGIC;
135 135 -----------------------------------------------------------------------------
136 136 SIGNAL fifo_ren_trash : STD_LOGIC;
137 137 SIGNAL component_fifo_ren : STD_LOGIC;
138 138
139 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140
139 141 BEGIN
140 142
141 143 -----------------------------------------------------------------------------
142 144 -- DMA to AHB interface
143 145 -----------------------------------------------------------------------------
144 146
145 147 DMA2AHB_1 : DMA2AHB
146 148 GENERIC MAP (
147 149 hindex => hindex,
148 150 vendorid => VENDOR_LPP,
149 151 deviceid => 0,
150 152 version => 0,
151 153 syncrst => 1,
152 boundary => 0)
154 boundary => 1) -- set TO TEST
153 155 PORT MAP (
154 156 HCLK => HCLK,
155 157 HRESETn => HRESETn,
156 158 DMAIn => DMAIn,
157 159 DMAOut => DMAOut,
158 160 AHBIn => AHB_Master_In,
159 161 AHBOut => AHB_Master_Out);
160 162
163
164 debug_info: PROCESS (HCLK, HRESETn)
165 BEGIN -- PROCESS debug_info
166 IF HRESETn = '0' THEN -- asynchronous reset (active low)
167 debug_reg <= (OTHERS => '0');
168 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
169 debug_reg(0) <= debug_reg(0) OR (DMAOut.Retry );
170 debug_reg(1) <= debug_reg(1) OR (DMAOut.Grant AND DMAOut.Retry) ;
171 IF state = TRASH_FIFO THEN debug_reg(2) <= '1'; END IF;
172 debug_reg(3) <= debug_reg(3) OR (header_send_ko);
173 debug_reg(4) <= debug_reg(4) OR (header_send_ok);
174 debug_reg(5) <= debug_reg(5) OR (component_send_ko);
175 debug_reg(6) <= debug_reg(6) OR (component_send_ok);
176
177 debug_reg(31 DOWNTO 7) <= (OTHERS => '1');
178 END IF;
179 END PROCESS debug_info;
180
181
161 182 matrix_type <= header(1 DOWNTO 0);
162 183 component_type <= header(5 DOWNTO 2);
163 184
164 185 send_matrix <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0_0 = '0' ELSE
165 186 '1' WHEN matrix_type = "01" AND status_ready_matrix_f0_1 = '0' ELSE
166 187 '1' WHEN matrix_type = "10" AND status_ready_matrix_f1 = '0' ELSE
167 188 '1' WHEN matrix_type = "11" AND status_ready_matrix_f2 = '0' ELSE
168 189 '0';
169 190
170 191 header_check_ok <= '0' WHEN component_type = "1111" ELSE
171 192 '1' WHEN component_type = "0000" AND component_type_pre = "1110" ELSE
172 193 '1' WHEN component_type = component_type_pre + "0001" ELSE
173 194 '0';
174 195
175 196 address_matrix <= addr_matrix_f0_0 WHEN matrix_type = "00" ELSE
176 197 addr_matrix_f0_1 WHEN matrix_type = "01" ELSE
177 198 addr_matrix_f1 WHEN matrix_type = "10" ELSE
178 199 addr_matrix_f2 WHEN matrix_type = "11" ELSE
179 200 (OTHERS => '0');
180 201
181 202 -----------------------------------------------------------------------------
182 203 -- DMA control
183 204 -----------------------------------------------------------------------------
184 205 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
185 206 BEGIN -- PROCESS DMAWriteBurst_p
186 207 IF HRESETn = '0' THEN -- asynchronous reset (active low)
187 208 state <= IDLE;
188 209 header_ack <= '0';
189 210 ready_matrix_f0_0 <= '0';
190 211 ready_matrix_f0_1 <= '0';
191 212 ready_matrix_f1 <= '0';
192 213 ready_matrix_f2 <= '0';
193 214 error_anticipating_empty_fifo <= '0';
194 215 error_bad_component_error <= '0';
195 216 component_type_pre <= "1110";
196 217 fifo_ren_trash <= '1';
197 218 component_send <= '0';
198 219 address <= (OTHERS => '0');
199 220 header_select <= '0';
200 221 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
201 222
202 223 CASE state IS
203 224 WHEN IDLE =>
204 225 ready_matrix_f0_0 <= '0';
205 226 ready_matrix_f0_1 <= '0';
206 227 ready_matrix_f1 <= '0';
207 228 ready_matrix_f2 <= '0';
208 229 error_bad_component_error <= '0';
209 230 header_select <= '1';
210 231 IF header_val = '1' AND fifo_empty = '0' AND send_matrix = '1' THEN
211 232 IF header_check_ok = '1' THEN
212 233 header_data <= header;
213 234 component_type_pre <= header(5 DOWNTO 2);
214 235 header_ack <= '1';
215 236 --
216 237 header_send <= '1';
217 238 IF component_type = "0000" THEN
218 239 address <= address_matrix;
219 240 END IF;
220 241 header_data <= header;
221 242 --
222 243 state <= WAIT_HEADER_ACK;
223 244 ELSE
224 245 error_bad_component_error <= '1';
225 246 component_type_pre <= "1110";
226 247 header_ack <= '1';
227 248 state <= TRASH_FIFO;
228 249 END IF;
229 250 END IF;
230 251
231 252 WHEN TRASH_FIFO =>
232 253 error_bad_component_error <= '0';
233 254 error_anticipating_empty_fifo <= '0';
234 255 IF fifo_empty = '1' THEN
235 256 state <= IDLE;
236 257 fifo_ren_trash <= '1';
237 258 ELSE
238 259 fifo_ren_trash <= '0';
239 260 END IF;
240 261
241 262 WHEN WAIT_HEADER_ACK =>
242 263 header_send <= '0';
243 264 IF header_send_ko = '1' THEN
244 265 state <= TRASH_FIFO;
245 266 error_anticipating_empty_fifo <= '1';
246 267 -- TODO : error sending header
247 268 ELSIF header_send_ok = '1' THEN
248 269 header_select <= '0';
249 270 state <= SEND_DATA;
250 271 address <= address + 4;
251 272 END IF;
252 273
253 274 WHEN SEND_DATA =>
254 275 IF fifo_empty = '1' THEN
255 276 state <= IDLE;
256 277 IF component_type = "1110" THEN
257 278 CASE matrix_type IS
258 279 WHEN "00" => ready_matrix_f0_0 <= '1';
259 280 WHEN "01" => ready_matrix_f0_1 <= '1';
260 281 WHEN "10" => ready_matrix_f1 <= '1';
261 282 WHEN "11" => ready_matrix_f2 <= '1';
262 283 WHEN OTHERS => NULL;
263 284 END CASE;
264 285 END IF;
265 286 ELSE
266 287 component_send <= '1';
267 288 address <= address;
268 289 state <= WAIT_DATA_ACK;
269 290 END IF;
270 291
271 292 WHEN WAIT_DATA_ACK =>
272 293 component_send <= '0';
273 294 IF component_send_ok = '1' THEN
274 295 address <= address + 64;
275 296 state <= SEND_DATA;
276 297 ELSIF component_send_ko = '1' THEN
277 298 error_anticipating_empty_fifo <= '0';
278 299 state <= TRASH_FIFO;
279 300 END IF;
280 301
281 302 WHEN CHECK_LENGTH =>
282 303 state <= IDLE;
283 304 WHEN OTHERS => NULL;
284 305 END CASE;
285 306
286 307 END IF;
287 308 END PROCESS DMAWriteFSM_p;
288 309
289 310 -----------------------------------------------------------------------------
290 311 -- SEND 1 word by DMA
291 312 -----------------------------------------------------------------------------
292 313 lpp_dma_send_1word_1 : lpp_dma_send_1word
293 314 PORT MAP (
294 315 HCLK => HCLK,
295 316 HRESETn => HRESETn,
296 317 DMAIn => header_dmai,
297 318 DMAOut => DMAOut,
298 319
299 320 send => header_send,
300 321 address => address,
301 322 data => header_data,
302 323 send_ok => header_send_ok,
303 324 send_ko => header_send_ko
304 325 );
305 326
306 327 -----------------------------------------------------------------------------
307 328 -- SEND 16 word by DMA (in burst mode)
308 329 -----------------------------------------------------------------------------
309 330 lpp_dma_send_16word_1 : lpp_dma_send_16word
310 331 PORT MAP (
311 332 HCLK => HCLK,
312 333 HRESETn => HRESETn,
313 334 DMAIn => component_dmai,
314 335 DMAOut => DMAOut,
315
316 336 send => component_send,
317 337 address => address,
318 338 data => fifo_data,
319 339 ren => component_fifo_ren,
320 340 send_ok => component_send_ok,
321 341 send_ko => component_send_ko);
322 342
323 343 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
324 344 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
325 345
326 346
327 347 -----------------------------------------------------------------------------
328 348 -- APB REGISTER
329 349 -----------------------------------------------------------------------------
330 350
331 351 lpp_dma_apbreg_2 : lpp_dma_apbreg
332 352 GENERIC MAP (
333 353 pindex => pindex,
334 354 paddr => paddr,
335 355 pmask => pmask,
336 356 pirq => pirq)
337 357 PORT MAP (
338 358 HCLK => HCLK,
339 359 HRESETn => HRESETn,
340 360 apbi => apbi,
341 361 apbo => apbo,
342 362 -- IN
343 363 ready_matrix_f0_0 => ready_matrix_f0_0,
344 364 ready_matrix_f0_1 => ready_matrix_f0_1,
345 365 ready_matrix_f1 => ready_matrix_f1,
346 ready_matrix_f2 => ready_matrix_f2,
366 ready_matrix_f2 => ready_matrix_f2,
347 367 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
348 368 error_bad_component_error => error_bad_component_error,
369 --
370 debug_reg => debug_reg,
349 371 -- OUT
350 372 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
351 373 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
352 374 status_ready_matrix_f1 => status_ready_matrix_f1,
353 375 status_ready_matrix_f2 => status_ready_matrix_f2,
354 376 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
355 377 status_error_bad_component_error => status_error_bad_component_error,
356 378 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix, -- TODO
357 379 config_active_interruption_onError => config_active_interruption_onError, -- TODO
358 380 addr_matrix_f0_0 => addr_matrix_f0_0,
359 381 addr_matrix_f0_1 => addr_matrix_f0_1,
360 382 addr_matrix_f1 => addr_matrix_f1,
361 383 addr_matrix_f2 => addr_matrix_f2);
362 384
363 -----------------------------------------------------------------------------
385 -----------------------------------------------------------------------------
364 386
365 387 END Behavioral;
366
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@@ -1,193 +1,198
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26 LIBRARY grlib;
27 27 USE grlib.amba.ALL;
28 28 USE grlib.stdlib.ALL;
29 29 USE grlib.devices.ALL;
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_amba.ALL;
32 32 USE lpp.apb_devices_list.ALL;
33 33 USE lpp.lpp_memory.ALL;
34 34 LIBRARY techmap;
35 35 USE techmap.gencomp.ALL;
36
36 37 ENTITY lpp_dma_apbreg IS
37 38 GENERIC (
38 39 pindex : INTEGER := 4;
39 40 paddr : INTEGER := 4;
40 41 pmask : INTEGER := 16#fff#;
41 42 pirq : INTEGER := 0);
42 43 PORT (
43 44 -- AMBA AHB system signals
44 45 HCLK : IN STD_ULOGIC;
45 46 HRESETn : IN STD_ULOGIC;
46 47
47 48 -- AMBA APB Slave Interface
48 49 apbi : IN apb_slv_in_type;
49 50 apbo : OUT apb_slv_out_type;
50 51
51 52 -- IN
52 53 ready_matrix_f0_0 : IN STD_LOGIC;
53 54 ready_matrix_f0_1 : IN STD_LOGIC;
54 55 ready_matrix_f1 : IN STD_LOGIC;
55 56 ready_matrix_f2 : IN STD_LOGIC;
56 57 error_anticipating_empty_fifo : IN STD_LOGIC;
57 58 error_bad_component_error : IN STD_LOGIC;
59 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 60
59 61 -- OUT
60 62 status_ready_matrix_f0_0 : OUT STD_LOGIC;
61 63 status_ready_matrix_f0_1 : OUT STD_LOGIC;
62 64 status_ready_matrix_f1 : OUT STD_LOGIC;
63 65 status_ready_matrix_f2 : OUT STD_LOGIC;
64 66 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
65 67 status_error_bad_component_error : OUT STD_LOGIC;
66 68
67 69 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
68 70 config_active_interruption_onError : OUT STD_LOGIC;
69 71 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
70 72 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
71 73 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 74 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
73 75 );
74 76
75 77 END lpp_dma_apbreg;
76 78
77 79 ARCHITECTURE beh OF lpp_dma_apbreg IS
78 80
79 81 CONSTANT REVISION : INTEGER := 1;
80 82
81 83 CONSTANT pconfig : apb_config_type := (
82 84 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 0, REVISION, pirq),
83 85 1 => apb_iobar(paddr, pmask));
84 86
85 87 TYPE lpp_dma_regs IS RECORD
86 88 config_active_interruption_onNewMatrix : STD_LOGIC;
87 89 config_active_interruption_onError : STD_LOGIC;
88 90 status_ready_matrix_f0_0 : STD_LOGIC;
89 91 status_ready_matrix_f0_1 : STD_LOGIC;
90 92 status_ready_matrix_f1 : STD_LOGIC;
91 93 status_ready_matrix_f2 : STD_LOGIC;
92 94 status_error_anticipating_empty_fifo : STD_LOGIC;
93 95 status_error_bad_component_error : STD_LOGIC;
94 96 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
95 97 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
96 98 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 99 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 100 END RECORD;
99 101
100 102 SIGNAL reg : lpp_dma_regs;
101 103
102 104 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
103 105
104 106 BEGIN -- beh
105 107
106 108 status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0;
107 109 status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1;
108 110 status_ready_matrix_f1 <= reg.status_ready_matrix_f1;
109 111 status_ready_matrix_f2 <= reg.status_ready_matrix_f2;
110 112 status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo;
111 113 status_error_bad_component_error <= reg.status_error_bad_component_error;
112 114
113 115 config_active_interruption_onNewMatrix <= reg.config_active_interruption_onNewMatrix;
114 116 config_active_interruption_onError <= reg.config_active_interruption_onError;
115 117 addr_matrix_f0_0 <= reg.addr_matrix_f0_0;
116 118 addr_matrix_f0_1 <= reg.addr_matrix_f0_1;
117 119 addr_matrix_f1 <= reg.addr_matrix_f1;
118 120 addr_matrix_f2 <= reg.addr_matrix_f2;
119 121
120 122 lpp_dma_apbreg : PROCESS (HCLK, HRESETn)
121 123 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
122 124 BEGIN -- PROCESS lpp_dma_top
123 125 IF HRESETn = '0' THEN -- asynchronous reset (active low)
124 126 reg.config_active_interruption_onNewMatrix <= '0';
125 127 reg.config_active_interruption_onError <= '0';
126 128 reg.status_ready_matrix_f0_0 <= '0';
127 129 reg.status_ready_matrix_f0_1 <= '0';
128 130 reg.status_ready_matrix_f1 <= '0';
129 131 reg.status_ready_matrix_f2 <= '0';
130 132 reg.status_error_anticipating_empty_fifo <= '0';
131 133 reg.status_error_bad_component_error <= '0';
132 134 reg.addr_matrix_f0_0 <= (OTHERS => '0');
133 135 reg.addr_matrix_f0_1 <= (OTHERS => '0');
134 136 reg.addr_matrix_f1 <= (OTHERS => '0');
135 137 reg.addr_matrix_f2 <= (OTHERS => '0');
136 138 prdata <= (OTHERS => '0');
137 139 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
138 140
139 141 reg.status_ready_matrix_f0_0 <= reg.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
140 142 reg.status_ready_matrix_f0_1 <= reg.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
141 143 reg.status_ready_matrix_f1 <= reg.status_ready_matrix_f1 OR ready_matrix_f1;
142 144 reg.status_ready_matrix_f2 <= reg.status_ready_matrix_f2 OR ready_matrix_f2;
143 145
144 146 reg.status_error_anticipating_empty_fifo <= reg.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
145 147 reg.status_error_bad_component_error <= reg.status_error_bad_component_error OR error_bad_component_error;
146 148
147 149 paddr := "000000";
148 150 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
149 151 prdata <= (OTHERS => '0');
150 152 IF apbi.psel(pindex) = '1' THEN
151 153 -- APB DMA READ --
152 154 CASE paddr(7 DOWNTO 2) IS
153 155 WHEN "000000" => prdata(0) <= reg.config_active_interruption_onNewMatrix;
154 156 prdata(1) <= reg.config_active_interruption_onError;
155 157 WHEN "000001" => prdata(0) <= reg.status_ready_matrix_f0_0;
156 158 prdata(1) <= reg.status_ready_matrix_f0_1;
157 159 prdata(2) <= reg.status_ready_matrix_f1;
158 160 prdata(3) <= reg.status_ready_matrix_f2;
159 161 prdata(4) <= reg.status_error_anticipating_empty_fifo;
160 162 prdata(5) <= reg.status_error_bad_component_error;
161 163 WHEN "000010" => prdata <= reg.addr_matrix_f0_0;
162 164 WHEN "000011" => prdata <= reg.addr_matrix_f0_1;
163 165 WHEN "000100" => prdata <= reg.addr_matrix_f1;
164 166 WHEN "000101" => prdata <= reg.addr_matrix_f2;
167 WHEN "000110" => prdata <= debug_reg;
165 168 WHEN OTHERS => NULL;
166 169 END CASE;
167 170 IF (apbi.pwrite AND apbi.penable) = '1' THEN
168 171 -- APB DMA WRITE --
169 172 CASE paddr(7 DOWNTO 2) IS
170 173 WHEN "000000" => reg.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
171 reg.config_active_interruption_onError <= apbi.pwdata(1);
172 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
173 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
174 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
175 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
176 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
177 reg.status_error_bad_component_error <= apbi.pwdata(5);
178 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
179 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
180 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
181 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
174 reg.config_active_interruption_onError <= apbi.pwdata(1);
175 WHEN "000001" => reg.status_ready_matrix_f0_0 <= apbi.pwdata(0);
176 reg.status_ready_matrix_f0_1 <= apbi.pwdata(1);
177 reg.status_ready_matrix_f1 <= apbi.pwdata(2);
178 reg.status_ready_matrix_f2 <= apbi.pwdata(3);
179 reg.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
180 reg.status_error_bad_component_error <= apbi.pwdata(5);
181 WHEN "000010" => reg.addr_matrix_f0_0 <= apbi.pwdata;
182 WHEN "000011" => reg.addr_matrix_f0_1 <= apbi.pwdata;
183 WHEN "000100" => reg.addr_matrix_f1 <= apbi.pwdata;
184 WHEN "000101" => reg.addr_matrix_f2 <= apbi.pwdata;
182 185 WHEN OTHERS => NULL;
183 186 END CASE;
184 187 END IF;
185 188 END IF;
186 189 END IF;
187 190 END PROCESS lpp_dma_apbreg;
191
188 192 apbo.pirq <= (OTHERS => '0');
189 193 apbo.pindex <= pindex;
190 194 apbo.pconfig <= pconfig;
191 195 apbo.prdata <= prdata;
192 196
197
193 198 END beh;
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@@ -1,163 +1,164
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE std.textio.ALL;
28 28 LIBRARY grlib;
29 29 USE grlib.amba.ALL;
30 30 USE grlib.stdlib.ALL;
31 31 USE GRLIB.DMA2AHB_Package.ALL;
32 32 LIBRARY techmap;
33 33 USE techmap.gencomp.ALL;
34 34 LIBRARY lpp;
35 35 USE lpp.lpp_amba.ALL;
36 36 USE lpp.apb_devices_list.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38
39 39 PACKAGE lpp_dma_pkg IS
40 40
41 41 COMPONENT lpp_dma
42 42 GENERIC (
43 43 tech : INTEGER;
44 44 hindex : INTEGER;
45 45 pindex : INTEGER;
46 46 paddr : INTEGER;
47 47 pmask : INTEGER;
48 48 pirq : INTEGER);
49 49 PORT (
50 50 HCLK : IN STD_ULOGIC;
51 51 HRESETn : IN STD_ULOGIC;
52 52 apbi : IN apb_slv_in_type;
53 53 apbo : OUT apb_slv_out_type;
54 54 AHB_Master_In : IN AHB_Mst_In_Type;
55 55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 56 -- fifo interface
57 57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 58 fifo_empty : IN STD_LOGIC;
59 59 fifo_ren : OUT STD_LOGIC;
60 60 -- header
61 61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 62 header_val : IN STD_LOGIC;
63 63 header_ack : OUT STD_LOGIC);
64 64 END COMPONENT;
65 65
66 66 COMPONENT fifo_test_dma
67 67 GENERIC (
68 68 tech : INTEGER;
69 69 pindex : INTEGER;
70 70 paddr : INTEGER;
71 71 pmask : INTEGER);
72 72 PORT (
73 73 HCLK : IN STD_ULOGIC;
74 74 HRESETn : IN STD_ULOGIC;
75 75 apbi : IN apb_slv_in_type;
76 76 apbo : OUT apb_slv_out_type;
77 77 -- fifo interface
78 78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 79 fifo_empty : OUT STD_LOGIC;
80 80 fifo_ren : IN STD_LOGIC;
81 81 -- header
82 82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 83 header_val : OUT STD_LOGIC;
84 84 header_ack : IN STD_LOGIC
85 85 );
86 86 END COMPONENT;
87 87
88 88 COMPONENT lpp_dma_apbreg
89 89 GENERIC (
90 90 pindex : INTEGER;
91 91 paddr : INTEGER;
92 92 pmask : INTEGER;
93 93 pirq : INTEGER);
94 94 PORT (
95 95 HCLK : IN STD_ULOGIC;
96 96 HRESETn : IN STD_ULOGIC;
97 97 apbi : IN apb_slv_in_type;
98 98 apbo : OUT apb_slv_out_type;
99 99 -- IN
100 100 ready_matrix_f0_0 : IN STD_LOGIC;
101 101 ready_matrix_f0_1 : IN STD_LOGIC;
102 102 ready_matrix_f1 : IN STD_LOGIC;
103 103 ready_matrix_f2 : IN STD_LOGIC;
104 104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 107
107 108 -- OUT
108 109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 111 status_ready_matrix_f1 : OUT STD_LOGIC;
111 112 status_ready_matrix_f2 : OUT STD_LOGIC;
112 113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 114 status_error_bad_component_error : OUT STD_LOGIC;
114 115
115 116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 117 config_active_interruption_onError : OUT STD_LOGIC;
117 118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 122 );
122 123 END COMPONENT;
123 124
124 125 COMPONENT lpp_dma_send_1word
125 126 PORT (
126 127 HCLK : IN STD_ULOGIC;
127 128 HRESETn : IN STD_ULOGIC;
128 129 DMAIn : OUT DMA_In_Type;
129 130 DMAOut : IN DMA_OUt_Type;
130 131 send : IN STD_LOGIC;
131 132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 134 send_ok : OUT STD_LOGIC;
134 135 send_ko : OUT STD_LOGIC);
135 136 END COMPONENT;
136 137
137 138 COMPONENT lpp_dma_send_16word
138 139 PORT (
139 140 HCLK : IN STD_ULOGIC;
140 141 HRESETn : IN STD_ULOGIC;
141 142 DMAIn : OUT DMA_In_Type;
142 143 DMAOut : IN DMA_OUt_Type;
143 144 send : IN STD_LOGIC;
144 145 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 146 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 147 ren : OUT STD_LOGIC;
147 148 send_ok : OUT STD_LOGIC;
148 149 send_ko : OUT STD_LOGIC);
149 150 END COMPONENT;
150 151
151 152 COMPONENT fifo_latency_correction
152 153 PORT (
153 154 HCLK : IN STD_ULOGIC;
154 155 HRESETn : IN STD_ULOGIC;
155 156 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 157 fifo_empty : IN STD_LOGIC;
157 158 fifo_ren : OUT STD_LOGIC;
158 159 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 160 dma_empty : OUT STD_LOGIC;
160 161 dma_ren : IN STD_LOGIC);
161 162 END COMPONENT;
162 163
163 164 END;
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@@ -1,160 +1,171
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1 23
2 24 LIBRARY ieee;
3 25 USE ieee.std_logic_1164.ALL;
4 26 USE ieee.numeric_std.ALL;
5 27 LIBRARY grlib;
6 28 USE grlib.amba.ALL;
7 29 USE grlib.stdlib.ALL;
8 30 USE grlib.devices.ALL;
9 31 USE GRLIB.DMA2AHB_Package.ALL;
10 32 LIBRARY lpp;
11 33 USE lpp.lpp_amba.ALL;
12 34 USE lpp.apb_devices_list.ALL;
13 35 USE lpp.lpp_memory.ALL;
14 36 LIBRARY techmap;
15 37 USE techmap.gencomp.ALL;
16 38
17 39 ENTITY lpp_dma_send_16word IS
18 40 PORT (
19 41 -- AMBA AHB system signals
20 42 HCLK : IN STD_ULOGIC;
21 43 HRESETn : IN STD_ULOGIC;
22 44
23 45 -- DMA
24 46 DMAIn : OUT DMA_In_Type;
25 47 DMAOut : IN DMA_OUt_Type;
26 48
27 49 --
28 50 send : IN STD_LOGIC;
29 51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 ren : OUT STD_LOGIC;
53 ren : OUT STD_LOGIC;
32 54 --
33 55 send_ok : OUT STD_LOGIC;
34 56 send_ko : OUT STD_LOGIC
35 57 );
36 58 END lpp_dma_send_16word;
37 59
38 60 ARCHITECTURE beh OF lpp_dma_send_16word IS
39 61
40 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1,WAIT_LAST_READY);
62 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
41 63 SIGNAL state : state_fsm_send_16word;
42 64
43 SIGNAL data_counter : INTEGER;
65 SIGNAL data_counter : INTEGER;
44 66 SIGNAL grant_counter : INTEGER;
45 67
46 68 BEGIN -- beh
47 69
48 DMAIn.Beat <= HINCR16;
49 DMAIn.Size <= HSIZE32;
70 DMAIn.Beat <= HINCR16;
71 DMAIn.Size <= HSIZE32;
50 72
51 73 PROCESS (HCLK, HRESETn)
52 74 BEGIN -- PROCESS
53 IF HRESETn = '0' THEN -- asynchronous reset (active low)
54 state <= IDLE;
55 send_ok <= '0';
56 send_ko <= '0';
57
58 DMAIn.Reset <= '0';
59 DMAIn.Address <= (OTHERS => '0');
60 -- DMAIn.Data <= (others => '0');
61 DMAIn.Request <= '0';
62 DMAIn.Store <= '0';
63 DMAIn.Burst <= '1';
64 DMAIn.Lock <= '0';
65 data_counter <= 0;
75 IF HRESETn = '0' THEN -- asynchronous reset (active low)
76 state <= IDLE;
77 send_ok <= '0';
78 send_ko <= '0';
79
80 DMAIn.Reset <= '0';
81 DMAIn.Address <= (OTHERS => '0');
82 DMAIn.Request <= '0';
83 DMAIn.Store <= '0';
84 DMAIn.Burst <= '1';
85 DMAIn.Lock <= '0';
86 data_counter <= 0;
66 87 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
67 88
68 89 CASE state IS
69 90 WHEN IDLE =>
70 -- ren <= '1';
71 91 DMAIn.Store <= '1';
72 92 DMAIn.Request <= '0';
73 send_ok <= '0';
74 send_ko <= '0';
75 DMAIn.Address <= address;
76 data_counter <= 0;
77 DMAIn.Lock <= '0'; -- FIX test
93 send_ok <= '0';
94 send_ko <= '0';
95 DMAIn.Address <= address;
96 data_counter <= 0;
97 DMAIn.Lock <= '0'; -- FIX test
78 98 IF send = '1' THEN
79 state <= REQUEST_BUS;
80 DMAIn.Request <= '1';
81 DMAIn.Lock <= '1'; -- FIX test
82 DMAIn.Store <= '1';
99 state <= REQUEST_BUS;
100 DMAIn.Request <= '1';
101 DMAIn.Lock <= '1'; -- FIX test
102 DMAIn.Store <= '1';
83 103 END IF;
84 104 WHEN REQUEST_BUS =>
85 -- ren <= '1';
86 IF DMAOut.Grant='1' THEN
87 data_counter <= 1;
88 grant_counter <= 1;
89 -- ren <= '0';
90 state <= SEND_DATA;
105 IF DMAOut.Grant = '1' THEN
106 data_counter <= 1;
107 grant_counter <= 1;
108 state <= SEND_DATA;
91 109 END IF;
92 110 WHEN SEND_DATA =>
93 -- ren <= '1';
94 111
95 112 IF DMAOut.Fault = '1' THEN
96 DMAIn.Reset <= '0';
97 DMAIn.Address <= (others => '0');
98 -- DMAIn.Data <= (others => '0');
99 DMAIn.Request <= '0';
100 DMAIn.Store <= '0';
101 DMAIn.Burst <= '0';
102 state <= ERROR0;
113 DMAIn.Reset <= '0';
114 DMAIn.Address <= (OTHERS => '0');
115 DMAIn.Request <= '0';
116 DMAIn.Store <= '0';
117 DMAIn.Burst <= '0';
118 state <= ERROR0;
103 119 ELSE
104 120
105 121 IF DMAOut.Grant = '1' THEN
106 if grant_counter = 15 then
107 DMAIn.Reset <= '0';
108 DMAIn.Request <= '0';
109 DMAIn.Store <= '0';
110 DMAIn.Burst <= '0';
111 else
112 grant_counter <= grant_counter+1;
113 end if;
122 IF grant_counter = 15 THEN
123 DMAIn.Reset <= '0';
124 DMAIn.Request <= '0';
125 DMAIn.Store <= '0';
126 DMAIn.Burst <= '0';
127 ELSE
128 grant_counter <= grant_counter+1;
129 END IF;
114 130 END IF;
115 131
116 132 IF DMAOut.OKAY = '1' THEN
117 133 IF data_counter = 15 THEN
118 DMAIn.Address <= (others => '0');
119 state <= WAIT_LAST_READY;
134 DMAIn.Address <= (OTHERS => '0');
135 state <= WAIT_LAST_READY;
120 136 ELSE
121 --DMAIn.Data <= data;
122 data_counter <= data_counter + 1;
123 -- ren <= '0';
137 data_counter <= data_counter + 1;
124 138 END IF;
125 139 END IF;
126 140 END IF;
127
128
141
142
129 143 WHEN WAIT_LAST_READY =>
130 -- ren <= '1';
131 144 IF DMAOut.Ready = '1' THEN
132 145 IF grant_counter = 15 THEN
133 146 state <= IDLE;
134 147 send_ok <= '1';
135 148 send_ko <= '0';
136 149 ELSE
137 state <= ERROR0;
150 state <= ERROR0;
138 151 END IF;
139 152 END IF;
140 153
141 154 WHEN ERROR0 =>
142 -- ren <= '1';
143 155 state <= ERROR1;
144 156 WHEN ERROR1 =>
145 157 send_ok <= '0';
146 158 send_ko <= '1';
147 -- ren <= '1';
148 state <= IDLE;
159 state <= IDLE;
149 160 WHEN OTHERS => NULL;
150 161 END CASE;
151 162 END IF;
152 163 END PROCESS;
153 164
154 DMAIn.Data <= data;
165 DMAIn.Data <= data;
155 166
156 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
157 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
167 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
168 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
158 169 '1';
159 170
160 171 END beh;
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@@ -1,101 +1,123
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
1 23
2 24 LIBRARY ieee;
3 25 USE ieee.std_logic_1164.ALL;
4 26 USE ieee.numeric_std.ALL;
5 27 LIBRARY grlib;
6 28 USE grlib.amba.ALL;
7 29 USE grlib.stdlib.ALL;
8 30 USE grlib.devices.ALL;
9 31 USE GRLIB.DMA2AHB_Package.ALL;
10 32 LIBRARY lpp;
11 33 USE lpp.lpp_amba.ALL;
12 34 USE lpp.apb_devices_list.ALL;
13 35 USE lpp.lpp_memory.ALL;
14 36 LIBRARY techmap;
15 37 USE techmap.gencomp.ALL;
16 38
17 39 ENTITY lpp_dma_send_1word IS
18 40 PORT (
19 41 -- AMBA AHB system signals
20 42 HCLK : IN STD_ULOGIC;
21 43 HRESETn : IN STD_ULOGIC;
22 44
23 45 -- DMA
24 46 DMAIn : OUT DMA_In_Type;
25 47 DMAOut : IN DMA_OUt_Type;
26 48 --
27 49 send : IN STD_LOGIC;
28 50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
29 51 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 52 --
31 53 send_ok : OUT STD_LOGIC;
32 54 send_ko : OUT STD_LOGIC
33 55 );
34 56 END lpp_dma_send_1word;
35 57
36 58 ARCHITECTURE beh OF lpp_dma_send_1word IS
37 59
38 60 TYPE state_fsm_send_1word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1);
39 61 SIGNAL state : state_fsm_send_1word;
40 62
41 63 BEGIN -- beh
42 64
43 65 DMAIn.Reset <= '0';
44 66 DMAIn.Address <= address;
45 67 DMAIn.Data <= data;
46 68 DMAIn.Beat <= (OTHERS => '0');
47 69 DMAIn.Size <= HSIZE32;
48 70 DMAIn.Burst <= '0';
49 71
50 72 PROCESS (HCLK, HRESETn)
51 73 BEGIN -- PROCESS
52 74 IF HRESETn = '0' THEN -- asynchronous reset (active low)
53 75 state <= IDLE;
54 76 DMAIn.Request <= '0';
55 77 DMAIn.Store <= '0';
56 78 send_ok <= '0';
57 79 send_ko <= '0';
58 80 DMAIn.Lock <= '0';
59 81 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
60 82 CASE state IS
61 83 WHEN IDLE =>
62 84 DMAIn.Store <= '1';
63 85 DMAIn.Request <= '0';
64 86 send_ok <= '0';
65 87 send_ko <= '0';
66 88 DMAIn.Lock <= '0';
67 89 IF send = '1' THEN
68 90 DMAIn.Request <= '1';
69 91 DMAIn.Lock <= '1';
70 92 state <= REQUEST_BUS;
71 93 END IF;
72 94 WHEN REQUEST_BUS =>
73 95 IF DMAOut.Grant = '1' THEN
74 96 DMAIn.Request <= '0';
75 97 DMAIn.Store <= '0';
76 98 state <= SEND_DATA;
77 99 END IF;
78 100 WHEN SEND_DATA =>
79 101 IF DMAOut.Fault = '1' THEN
80 102 DMAIn.Request <= '0';
81 103 DMAIn.Store <= '0';
82 104 state <= ERROR0;
83 105 ELSIF DMAOut.Ready = '1' THEN
84 106 DMAIn.Request <= '0';
85 107 DMAIn.Store <= '0';
86 108 send_ok <= '1';
87 109 send_ko <= '0';
88 110 state <= IDLE;
89 111 END IF;
90 112 WHEN ERROR0 =>
91 113 state <= ERROR1;
92 114 WHEN ERROR1 =>
93 115 send_ok <= '0';
94 116 send_ko <= '1';
95 117 state <= IDLE;
96 118 WHEN OTHERS => NULL;
97 119 END CASE;
98 120 END IF;
99 121 END PROCESS;
100 122
101 123 END beh;
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