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r589:ebd290519818 simu_with_Leon3
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.sim.ALL;
31 USE gaisler.sim.ALL;
32 USE gaisler.memctrl.ALL;
32 USE gaisler.memctrl.ALL;
33 USE gaisler.leon3.ALL;
33 USE gaisler.leon3.ALL;
34 USE gaisler.uart.ALL;
34 USE gaisler.uart.ALL;
35 USE gaisler.misc.ALL;
35 USE gaisler.misc.ALL;
36 USE gaisler.spacewire.ALL;
36 USE gaisler.spacewire.ALL;
37 LIBRARY esa;
37 LIBRARY esa;
38 USE esa.memoryctrl.ALL;
38 USE esa.memoryctrl.ALL;
39 LIBRARY lpp;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
44 USE lpp.iir_filter.ALL;
44 USE lpp.iir_filter.ALL;
45 USE lpp.general_purpose.ALL;
45 USE lpp.general_purpose.ALL;
46 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
48 USE lpp.lpp_bootloader_pkg.ALL;
49
49
50 --library proasic3l;
50 --library proasic3l;
51 --use proasic3l.all;
51 --use proasic3l.all;
52
52
53 ENTITY LFR_EQM IS
53 ENTITY LFR_EQM IS
54 GENERIC (
54 GENERIC (
55 Mem_use : INTEGER := use_RAM;
55 Mem_use : INTEGER := use_RAM;
56 USE_BOOTLOADER : INTEGER := 0;
56 USE_BOOTLOADER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 0;
57 USE_ADCDRIVER : INTEGER := 0;
58 tech : INTEGER := apa3e;
58 tech : INTEGER := apa3e;
59 tech_leon : INTEGER := apa3e
59 tech_leon : INTEGER := apa3e;
60 DEBUG_FORCE_DATA_DMA : INTEGER := 1;
61 USE_DEBUG_VECTOR : INTEGER := 1
60 );
62 );
61
63
62 PORT (
64 PORT (
63 clk50MHz : IN STD_ULOGIC;
65 clk50MHz : IN STD_ULOGIC;
64 clk49_152MHz : IN STD_ULOGIC;
66 clk49_152MHz : IN STD_ULOGIC;
65 reset : IN STD_ULOGIC;
67 reset : IN STD_ULOGIC;
66
68
69 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
70
67 -- TAG --------------------------------------------------------------------
71 -- TAG --------------------------------------------------------------------
68 TAG1 : IN STD_ULOGIC; -- DSU rx data
72 --TAG1 : IN STD_ULOGIC; -- DSU rx data
69 TAG3 : OUT STD_ULOGIC; -- DSU tx data
73 --TAG3 : OUT STD_ULOGIC; -- DSU tx data
70 -- UART APB ---------------------------------------------------------------
74 -- UART APB ---------------------------------------------------------------
71 TAG2 : IN STD_ULOGIC; -- UART1 rx data
75 --TAG2 : IN STD_ULOGIC; -- UART1 rx data
72 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
76 --TAG4 : OUT STD_ULOGIC; -- UART1 tx data
73 -- RAM --------------------------------------------------------------------
77 -- RAM --------------------------------------------------------------------
74 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
78 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
75 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76
80
77 nSRAM_MBE : INOUT STD_LOGIC; -- new
81 nSRAM_MBE : INOUT STD_LOGIC; -- new
78 nSRAM_E1 : OUT STD_LOGIC; -- new
82 nSRAM_E1 : OUT STD_LOGIC; -- new
79 nSRAM_E2 : OUT STD_LOGIC; -- new
83 nSRAM_E2 : OUT STD_LOGIC; -- new
80 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
84 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
81 nSRAM_W : OUT STD_LOGIC; -- new
85 nSRAM_W : OUT STD_LOGIC; -- new
82 nSRAM_G : OUT STD_LOGIC; -- new
86 nSRAM_G : OUT STD_LOGIC; -- new
83 nSRAM_BUSY : IN STD_LOGIC; -- new
87 nSRAM_BUSY : IN STD_LOGIC; -- new
84 -- SPW --------------------------------------------------------------------
88 -- SPW --------------------------------------------------------------------
85 spw1_en : OUT STD_LOGIC; -- new
89 spw1_en : OUT STD_LOGIC; -- new
86 spw1_din : IN STD_LOGIC;
90 spw1_din : IN STD_LOGIC;
87 spw1_sin : IN STD_LOGIC;
91 spw1_sin : IN STD_LOGIC;
88 spw1_dout : OUT STD_LOGIC;
92 spw1_dout : OUT STD_LOGIC;
89 spw1_sout : OUT STD_LOGIC;
93 spw1_sout : OUT STD_LOGIC;
90 spw2_en : OUT STD_LOGIC; -- new
94 spw2_en : OUT STD_LOGIC; -- new
91 spw2_din : IN STD_LOGIC;
95 spw2_din : IN STD_LOGIC;
92 spw2_sin : IN STD_LOGIC;
96 spw2_sin : IN STD_LOGIC;
93 spw2_dout : OUT STD_LOGIC;
97 spw2_dout : OUT STD_LOGIC;
94 spw2_sout : OUT STD_LOGIC;
98 spw2_sout : OUT STD_LOGIC;
95 -- ADC --------------------------------------------------------------------
99 -- ADC --------------------------------------------------------------------
96 bias_fail_sw : OUT STD_LOGIC;
100 bias_fail_sw : OUT STD_LOGIC;
97 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
98 ADC_smpclk : OUT STD_LOGIC;
102 ADC_smpclk : OUT STD_LOGIC;
99 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
100 -- DAC --------------------------------------------------------------------
104 -- DAC --------------------------------------------------------------------
101 DAC_SDO : OUT STD_LOGIC;
105 DAC_SDO : OUT STD_LOGIC;
102 DAC_SCK : OUT STD_LOGIC;
106 DAC_SCK : OUT STD_LOGIC;
103 DAC_SYNC : OUT STD_LOGIC;
107 DAC_SYNC : OUT STD_LOGIC;
104 DAC_CAL_EN : OUT STD_LOGIC;
108 DAC_CAL_EN : OUT STD_LOGIC;
105 -- HK ---------------------------------------------------------------------
109 -- HK ---------------------------------------------------------------------
106 HK_smpclk : OUT STD_LOGIC;
110 HK_smpclk : OUT STD_LOGIC;
107 ADC_OEB_bar_HK : OUT STD_LOGIC;
111 ADC_OEB_bar_HK : OUT STD_LOGIC;
108 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
112 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)--;
109 ---------------------------------------------------------------------------
113 ---------------------------------------------------------------------------
110 TAG8 : OUT STD_LOGIC
114 -- TAG8 : OUT STD_LOGIC
111 );
115 );
112
116
113 END LFR_EQM;
117 END LFR_EQM;
114
118
115
119
116 ARCHITECTURE beh OF LFR_EQM IS
120 ARCHITECTURE beh OF LFR_EQM IS
117
121
118 SIGNAL clk_25 : STD_LOGIC := '0';
122 SIGNAL clk_25 : STD_LOGIC := '0';
119 SIGNAL clk_24 : STD_LOGIC := '0';
123 SIGNAL clk_24 : STD_LOGIC := '0';
120 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
121 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
126 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
123
127
124 -- CONSTANTS
128 -- CONSTANTS
125 CONSTANT CFG_PADTECH : INTEGER := inferred;
129 CONSTANT CFG_PADTECH : INTEGER := inferred;
126 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
130 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
127 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
131 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
128 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
132 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
129
133
130 SIGNAL apbi_ext : apb_slv_in_type;
134 SIGNAL apbi_ext : apb_slv_in_type;
131 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
135 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
132 SIGNAL ahbi_s_ext : ahb_slv_in_type;
136 SIGNAL ahbi_s_ext : ahb_slv_in_type;
133 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
137 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
134 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
138 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
135 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
139 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
136
140
137 -- Spacewire signals
141 -- Spacewire signals
138 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
142 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
139 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
143 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
140 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
144 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
141 SIGNAL spw_rxtxclk : STD_ULOGIC;
145 SIGNAL spw_rxtxclk : STD_ULOGIC;
142 SIGNAL spw_rxclkn : STD_ULOGIC;
146 SIGNAL spw_rxclkn : STD_ULOGIC;
143 SIGNAL spw_clk : STD_LOGIC;
147 SIGNAL spw_clk : STD_LOGIC;
144 SIGNAL swni : grspw_in_type;
148 SIGNAL swni : grspw_in_type;
145 SIGNAL swno : grspw_out_type;
149 SIGNAL swno : grspw_out_type;
146
150
147 --GPIO
151 --GPIO
148 SIGNAL gpioi : gpio_in_type;
152 SIGNAL gpioi : gpio_in_type;
149 SIGNAL gpioo : gpio_out_type;
153 SIGNAL gpioo : gpio_out_type;
150
154
151 -- AD Converter ADS7886
155 -- AD Converter ADS7886
152 SIGNAL sample : Samples14v(8 DOWNTO 0);
156 SIGNAL sample : Samples14v(8 DOWNTO 0);
153 SIGNAL sample_s : Samples(8 DOWNTO 0);
157 SIGNAL sample_s : Samples(8 DOWNTO 0);
154 SIGNAL sample_val : STD_LOGIC;
158 SIGNAL sample_val : STD_LOGIC;
155 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
159 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
156
160
157 -----------------------------------------------------------------------------
161 -----------------------------------------------------------------------------
158 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
159
163
160 -----------------------------------------------------------------------------
164 -----------------------------------------------------------------------------
161 SIGNAL rstn_25 : STD_LOGIC;
165 SIGNAL rstn_25 : STD_LOGIC;
162 SIGNAL rstn_24 : STD_LOGIC;
166 SIGNAL rstn_24 : STD_LOGIC;
163
167
164 SIGNAL LFR_soft_rstn : STD_LOGIC;
168 SIGNAL LFR_soft_rstn : STD_LOGIC;
165 SIGNAL LFR_rstn : STD_LOGIC;
169 SIGNAL LFR_rstn : STD_LOGIC;
166
170
167 SIGNAL ADC_smpclk_s : STD_LOGIC;
171 SIGNAL ADC_smpclk_s : STD_LOGIC;
168
172
169 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
173 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
174
171 SIGNAL clk50MHz_int : STD_LOGIC := '0';
175 SIGNAL clk50MHz_int : STD_LOGIC := '0';
172 SIGNAL clk_25_int : STD_LOGIC := '0';
176 SIGNAL clk_25_int : STD_LOGIC := '0';
173
177
174 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
178 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
175
179
176 SIGNAL rstn_50 : STD_LOGIC;
180 SIGNAL rstn_50 : STD_LOGIC;
177 SIGNAL clk_lock : STD_LOGIC;
181 SIGNAL clk_lock : STD_LOGIC;
178 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL clk_busy_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
183 SIGNAL nSRAM_BUSY_reg : STD_LOGIC;
184
185 SIGNAL debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL ahbrxd: STD_LOGIC;
187 SIGNAL ahbtxd: STD_LOGIC;
188 SIGNAL urxd1 : STD_LOGIC;
189 SIGNAL utxd1 : STD_LOGIC;
180 BEGIN -- beh
190 BEGIN -- beh
181
191
182 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
183 -- CLK_LOCK
193 -- CLK_LOCK
184 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
185 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
195 rst_gen_global : rstgen PORT MAP (reset, clk50MHz, '1', rstn_50, OPEN);
186
196
187 PROCESS (clk50MHz_int, rstn_50)
197 PROCESS (clk50MHz_int, rstn_50)
188 BEGIN -- PROCESS
198 BEGIN -- PROCESS
189 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
199 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
190 clk_lock <= '0';
200 clk_lock <= '0';
191 clk_busy_counter <= (OTHERS => '0');
201 clk_busy_counter <= (OTHERS => '0');
192 nSRAM_BUSY_reg <= '0';
202 nSRAM_BUSY_reg <= '0';
193 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
203 ELSIF clk50MHz_int'event AND clk50MHz_int = '1' THEN -- rising clock edge
194 nSRAM_BUSY_reg <= nSRAM_BUSY;
204 nSRAM_BUSY_reg <= nSRAM_BUSY;
195 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
205 IF nSRAM_BUSY_reg = '1' AND nSRAM_BUSY = '0' THEN
196 IF clk_busy_counter = "1111" THEN
206 IF clk_busy_counter = "1111" THEN
197 clk_lock <= '1';
207 clk_lock <= '1';
198 ELSE
208 ELSE
199 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
209 clk_busy_counter <= STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(clk_busy_counter))+1,4));
200 END IF;
210 END IF;
201 END IF;
211 END IF;
202 END IF;
212 END IF;
203 END PROCESS;
213 END PROCESS;
204
214
205 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
206 -- CLK
216 -- CLK
207 -----------------------------------------------------------------------------
217 -----------------------------------------------------------------------------
208 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
218 rst_domain25 : rstgen PORT MAP (reset, clk_25, clk_lock, rstn_25, OPEN);
209 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
219 rst_domain24 : rstgen PORT MAP (reset, clk_24, clk_lock, rstn_24, OPEN);
210
220
211 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
221 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
212 clk50MHz_int <= clk50MHz;
222 clk50MHz_int <= clk50MHz;
213
223
214 PROCESS(clk50MHz_int)
224 PROCESS(clk50MHz_int)
215 BEGIN
225 BEGIN
216 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
226 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
217 --clk_25_int <= NOT clk_25_int;
227 --clk_25_int <= NOT clk_25_int;
218 clk_25 <= NOT clk_25;
228 clk_25 <= NOT clk_25;
219 END IF;
229 END IF;
220 END PROCESS;
230 END PROCESS;
221 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
231 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
222
232
223 PROCESS(clk49_152MHz)
233 PROCESS(clk49_152MHz)
224 BEGIN
234 BEGIN
225 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
235 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
226 clk_24 <= NOT clk_24;
236 clk_24 <= NOT clk_24;
227 END IF;
237 END IF;
228 END PROCESS;
238 END PROCESS;
229
239
230 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
231 --
241 --
232 leon3_soc_1 : leon3_soc
242 leon3_soc_1 : leon3_soc
233 GENERIC MAP (
243 GENERIC MAP (
234 fabtech => tech_leon,
244 fabtech => tech_leon,
235 memtech => tech_leon,
245 memtech => tech_leon,
236 padtech => inferred,
246 padtech => inferred,
237 clktech => inferred,
247 clktech => inferred,
238 disas => 0,
248 disas => 0,
239 dbguart => 0,
249 dbguart => 0,
240 pclow => 2,
250 pclow => 2,
241 clk_freq => 25000,
251 clk_freq => 25000,
242 IS_RADHARD => 0,
252 IS_RADHARD => 0,
243 NB_CPU => 1,
253 NB_CPU => 1,
244 ENABLE_FPU => 1,
254 ENABLE_FPU => 1,
245 FPU_NETLIST => 0,
255 FPU_NETLIST => 0,
246 ENABLE_DSU => 1,
256 ENABLE_DSU => 1,
247 ENABLE_AHB_UART => 1,
257 ENABLE_AHB_UART => 1,
248 ENABLE_APB_UART => 1,
258 ENABLE_APB_UART => 1,
249 ENABLE_IRQMP => 1,
259 ENABLE_IRQMP => 1,
250 ENABLE_GPT => 1,
260 ENABLE_GPT => 1,
251 NB_AHB_MASTER => NB_AHB_MASTER,
261 NB_AHB_MASTER => NB_AHB_MASTER,
252 NB_AHB_SLAVE => NB_AHB_SLAVE,
262 NB_AHB_SLAVE => NB_AHB_SLAVE,
253 NB_APB_SLAVE => NB_APB_SLAVE,
263 NB_APB_SLAVE => NB_APB_SLAVE,
254 ADDRESS_SIZE => 19,
264 ADDRESS_SIZE => 19,
255 USES_IAP_MEMCTRLR => 1,
265 USES_IAP_MEMCTRLR => 1,
256 BYPASS_EDAC_MEMCTRLR => '0',
266 BYPASS_EDAC_MEMCTRLR => '0',
257 SRBANKSZ => 8)
267 SRBANKSZ => 8)
258 PORT MAP (
268 PORT MAP (
259 clk => clk_25,
269 clk => clk_25,
260 reset => rstn_25,
270 reset => rstn_25,
261 errorn => OPEN,
271 errorn => OPEN,
262
272
263 ahbrxd => TAG1,
273 ahbrxd => ahbrxd, -- INPUT
264 ahbtxd => TAG3,
274 ahbtxd => ahbtxd, -- OUTPUT
265 urxd1 => TAG2,
275 urxd1 => urxd1, -- INPUT
266 utxd1 => TAG4,
276 utxd1 => utxd1, -- OUTPUT
267
277
268 address => address,
278 address => address,
269 data => data,
279 data => data,
270 nSRAM_BE0 => OPEN,
280 nSRAM_BE0 => OPEN,
271 nSRAM_BE1 => OPEN,
281 nSRAM_BE1 => OPEN,
272 nSRAM_BE2 => OPEN,
282 nSRAM_BE2 => OPEN,
273 nSRAM_BE3 => OPEN,
283 nSRAM_BE3 => OPEN,
274 nSRAM_WE => nSRAM_W,
284 nSRAM_WE => nSRAM_W,
275 nSRAM_CE => nSRAM_CE,
285 nSRAM_CE => nSRAM_CE,
276 nSRAM_OE => nSRAM_G,
286 nSRAM_OE => nSRAM_G,
277 nSRAM_READY => nSRAM_BUSY,
287 nSRAM_READY => nSRAM_BUSY,
278 SRAM_MBE => nSRAM_MBE,
288 SRAM_MBE => nSRAM_MBE,
279
289
280 apbi_ext => apbi_ext,
290 apbi_ext => apbi_ext,
281 apbo_ext => apbo_ext,
291 apbo_ext => apbo_ext,
282 ahbi_s_ext => ahbi_s_ext,
292 ahbi_s_ext => ahbi_s_ext,
283 ahbo_s_ext => ahbo_s_ext,
293 ahbo_s_ext => ahbo_s_ext,
284 ahbi_m_ext => ahbi_m_ext,
294 ahbi_m_ext => ahbi_m_ext,
285 ahbo_m_ext => ahbo_m_ext);
295 ahbo_m_ext => ahbo_m_ext);
286
296
287
297
288 nSRAM_E1 <= nSRAM_CE(0);
298 nSRAM_E1 <= nSRAM_CE(0);
289 nSRAM_E2 <= nSRAM_CE(1);
299 nSRAM_E2 <= nSRAM_CE(1);
290
300
291 -------------------------------------------------------------------------------
301 -------------------------------------------------------------------------------
292 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
302 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
293 -------------------------------------------------------------------------------
303 -------------------------------------------------------------------------------
294 apb_lfr_management_1 : apb_lfr_management
304 apb_lfr_management_1 : apb_lfr_management
295 GENERIC MAP (
305 GENERIC MAP (
296 tech => tech,
306 tech => tech,
297 pindex => 6,
307 pindex => 6,
298 paddr => 6,
308 paddr => 6,
299 pmask => 16#fff#,
309 pmask => 16#fff#,
300 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
310 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
301 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
311 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
302 PORT MAP (
312 PORT MAP (
303 clk25MHz => clk_25,
313 clk25MHz => clk_25,
304 resetn_25MHz => rstn_25, -- TODO
314 resetn_25MHz => rstn_25, -- TODO
305 --clk24_576MHz => clk_24, -- 49.152MHz/2
315 --clk24_576MHz => clk_24, -- 49.152MHz/2
306 --resetn_24_576MHz => rstn_24, -- TODO
316 --resetn_24_576MHz => rstn_24, -- TODO
307
317
308 grspw_tick => swno.tickout,
318 grspw_tick => swno.tickout,
309 apbi => apbi_ext,
319 apbi => apbi_ext,
310 apbo => apbo_ext(6),
320 apbo => apbo_ext(6),
311
321
312 HK_sample => sample_s(8),
322 HK_sample => sample_s(8),
313 HK_val => sample_val,
323 HK_val => sample_val,
314 HK_sel => HK_SEL,
324 HK_sel => HK_SEL,
315
325
316 DAC_SDO => DAC_SDO,
326 DAC_SDO => DAC_SDO,
317 DAC_SCK => DAC_SCK,
327 DAC_SCK => DAC_SCK,
318 DAC_SYNC => DAC_SYNC,
328 DAC_SYNC => DAC_SYNC,
319 DAC_CAL_EN => DAC_CAL_EN,
329 DAC_CAL_EN => DAC_CAL_EN,
320
330
321 coarse_time => coarse_time,
331 coarse_time => coarse_time,
322 fine_time => fine_time,
332 fine_time => fine_time,
323 LFR_soft_rstn => LFR_soft_rstn
333 LFR_soft_rstn => LFR_soft_rstn
324 );
334 );
325
335
326 -----------------------------------------------------------------------
336 -----------------------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
337 --- SpaceWire --------------------------------------------------------
328 -----------------------------------------------------------------------
338 -----------------------------------------------------------------------
329
339
330 ------------------------------------------------------------------------------
340 ------------------------------------------------------------------------------
331 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
341 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
332 ------------------------------------------------------------------------------
342 ------------------------------------------------------------------------------
333 spw1_en <= '1';
343 spw1_en <= '1';
334 spw2_en <= '1';
344 spw2_en <= '1';
335 ------------------------------------------------------------------------------
345 ------------------------------------------------------------------------------
336 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
346 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
337 ------------------------------------------------------------------------------
347 ------------------------------------------------------------------------------
338
348
339 --spw_clk <= clk50MHz;
349 --spw_clk <= clk50MHz;
340 --spw_rxtxclk <= spw_clk;
350 --spw_rxtxclk <= spw_clk;
341 --spw_rxclkn <= NOT spw_rxtxclk;
351 --spw_rxclkn <= NOT spw_rxtxclk;
342
352
343 -- PADS for SPW1
353 -- PADS for SPW1
344 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
354 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
345 PORT MAP (spw1_din, dtmp(0));
355 PORT MAP (spw1_din, dtmp(0));
346 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
356 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
347 PORT MAP (spw1_sin, stmp(0));
357 PORT MAP (spw1_sin, stmp(0));
348 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
358 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
349 PORT MAP (spw1_dout, swno.d(0));
359 PORT MAP (spw1_dout, swno.d(0));
350 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
360 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (spw1_sout, swno.s(0));
361 PORT MAP (spw1_sout, swno.s(0));
352 -- PADS FOR SPW2
362 -- PADS FOR SPW2
353 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
363 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
354 PORT MAP (spw2_din, dtmp(1));
364 PORT MAP (spw2_din, dtmp(1));
355 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
365 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
356 PORT MAP (spw2_sin, stmp(1));
366 PORT MAP (spw2_sin, stmp(1));
357 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
367 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
358 PORT MAP (spw2_dout, swno.d(1));
368 PORT MAP (spw2_dout, swno.d(1));
359 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
369 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
360 PORT MAP (spw2_sout, swno.s(1));
370 PORT MAP (spw2_sout, swno.s(1));
361
371
362 -- GRSPW PHY
372 -- GRSPW PHY
363 --spw1_input: if CFG_SPW_GRSPW = 1 generate
373 --spw1_input: if CFG_SPW_GRSPW = 1 generate
364 spw_inputloop : FOR j IN 0 TO 1 GENERATE
374 spw_inputloop : FOR j IN 0 TO 1 GENERATE
365 spw_phy0 : grspw_phy
375 spw_phy0 : grspw_phy
366 GENERIC MAP(
376 GENERIC MAP(
367 tech => tech_leon,
377 tech => tech_leon,
368 rxclkbuftype => 1,
378 rxclkbuftype => 1,
369 scantest => 0)
379 scantest => 0)
370 PORT MAP(
380 PORT MAP(
371 rxrst => swno.rxrst,
381 rxrst => swno.rxrst,
372 di => dtmp(j),
382 di => dtmp(j),
373 si => stmp(j),
383 si => stmp(j),
374 rxclko => spw_rxclk(j),
384 rxclko => spw_rxclk(j),
375 do => swni.d(j),
385 do => swni.d(j),
376 ndo => swni.nd(j*5+4 DOWNTO j*5),
386 ndo => swni.nd(j*5+4 DOWNTO j*5),
377 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
387 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
378 END GENERATE spw_inputloop;
388 END GENERATE spw_inputloop;
379
389
380 -- SPW core
390 -- SPW core
381 sw0 : grspwm GENERIC MAP(
391 sw0 : grspwm GENERIC MAP(
382 tech => tech_leon,
392 tech => tech_leon,
383 hindex => 1,
393 hindex => 1,
384 pindex => 5,
394 pindex => 5,
385 paddr => 5,
395 paddr => 5,
386 pirq => 11,
396 pirq => 11,
387 sysfreq => 25000, -- CPU_FREQ
397 sysfreq => 25000, -- CPU_FREQ
388 rmap => 1,
398 rmap => 1,
389 rmapcrc => 1,
399 rmapcrc => 1,
390 fifosize1 => 16,
400 fifosize1 => 16,
391 fifosize2 => 16,
401 fifosize2 => 16,
392 rxclkbuftype => 1,
402 rxclkbuftype => 1,
393 rxunaligned => 0,
403 rxunaligned => 0,
394 rmapbufs => 4,
404 rmapbufs => 4,
395 ft => 0,
405 ft => 0,
396 netlist => 0,
406 netlist => 0,
397 ports => 2,
407 ports => 2,
398 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
408 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
399 memtech => tech_leon,
409 memtech => tech_leon,
400 destkey => 2,
410 destkey => 2,
401 spwcore => 1
411 spwcore => 1
402 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
412 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
403 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
413 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
404 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
414 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
405 )
415 )
406 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
416 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
407 spw_rxclk(1),
417 spw_rxclk(1),
408 clk50MHz_int,
418 clk50MHz_int,
409 clk50MHz_int,
419 clk50MHz_int,
410 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
420 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
411 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
421 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
412 swni, swno);
422 swni, swno);
413
423
414 swni.tickin <= '0';
424 swni.tickin <= '0';
415 swni.rmapen <= '1';
425 swni.rmapen <= '1';
416 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
426 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
417 swni.tickinraw <= '0';
427 swni.tickinraw <= '0';
418 swni.timein <= (OTHERS => '0');
428 swni.timein <= (OTHERS => '0');
419 swni.dcrstval <= (OTHERS => '0');
429 swni.dcrstval <= (OTHERS => '0');
420 swni.timerrstval <= (OTHERS => '0');
430 swni.timerrstval <= (OTHERS => '0');
421
431
422 -------------------------------------------------------------------------------
432 -------------------------------------------------------------------------------
423 -- LFR ------------------------------------------------------------------------
433 -- LFR ------------------------------------------------------------------------
424 -------------------------------------------------------------------------------
434 -------------------------------------------------------------------------------
425 LFR_rstn <= LFR_soft_rstn AND rstn_25;
435 LFR_rstn <= LFR_soft_rstn AND rstn_25;
426
436
427 lpp_lfr_1 : lpp_lfr
437 lpp_lfr_1 : lpp_lfr
428 GENERIC MAP (
438 GENERIC MAP (
429 Mem_use => Mem_use,
439 Mem_use => Mem_use,
440 tech => tech,
430 nb_data_by_buffer_size => 32,
441 nb_data_by_buffer_size => 32,
431 --nb_word_by_buffer_size => 30,
442 --nb_word_by_buffer_size => 30,
432 nb_snapshot_param_size => 32,
443 nb_snapshot_param_size => 32,
433 delta_vector_size => 32,
444 delta_vector_size => 32,
434 delta_vector_size_f0_2 => 7, -- log2(96)
445 delta_vector_size_f0_2 => 7, -- log2(96)
435 pindex => 15,
446 pindex => 15,
436 paddr => 15,
447 paddr => 15,
437 pmask => 16#fff#,
448 pmask => 16#fff#,
438 pirq_ms => 6,
449 pirq_ms => 6,
439 pirq_wfp => 14,
450 pirq_wfp => 14,
440 hindex => 2,
451 hindex => 2,
441 top_lfr_version => X"020147") -- aa.bb.cc version
452 top_lfr_version => X"020148", -- aa.bb.cc version
442 -- AA : BOARD NUMBER
453 -- AA : BOARD NUMBER
443 -- 0 => MINI_LFR
454 -- 0 => MINI_LFR
444 -- 1 => EM
455 -- 1 => EM
445 -- 2 => EQM (with A3PE3000)
456 -- 2 => EQM (with A3PE3000)
457 DEBUG_FORCE_DATA_DMA => DEBUG_FORCE_DATA_DMA)
446 PORT MAP (
458 PORT MAP (
447 clk => clk_25,
459 clk => clk_25,
448 rstn => LFR_rstn,
460 rstn => LFR_rstn,
449 sample_B => sample_s(2 DOWNTO 0),
461 sample_B => sample_s(2 DOWNTO 0),
450 sample_E => sample_s(7 DOWNTO 3),
462 sample_E => sample_s(7 DOWNTO 3),
451 sample_val => sample_val,
463 sample_val => sample_val,
452 apbi => apbi_ext,
464 apbi => apbi_ext,
453 apbo => apbo_ext(15),
465 apbo => apbo_ext(15),
454 ahbi => ahbi_m_ext,
466 ahbi => ahbi_m_ext,
455 ahbo => ahbo_m_ext(2),
467 ahbo => ahbo_m_ext(2),
456 coarse_time => coarse_time,
468 coarse_time => coarse_time,
457 fine_time => fine_time,
469 fine_time => fine_time,
458 data_shaping_BW => bias_fail_sw,
470 data_shaping_BW => bias_fail_sw,
459 debug_vector => OPEN,
471 debug_vector => debug_vector,
460 debug_vector_ms => OPEN); --,
472 debug_vector_ms => OPEN); --,
461 --observation_vector_0 => OPEN,
473 --observation_vector_0 => OPEN,
462 --observation_vector_1 => OPEN,
474 --observation_vector_1 => OPEN,
463 --observation_reg => observation_reg);
475 --observation_reg => observation_reg);
464
476
465
477
466 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
478 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
467 sample_s(I) <= sample(I) & '0' & '0';
479 sample_s(I) <= sample(I) & '0' & '0';
468 END GENERATE all_sample;
480 END GENERATE all_sample;
469 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
481 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
470
482
471 -----------------------------------------------------------------------------
483 -----------------------------------------------------------------------------
472 --
484 --
473 -----------------------------------------------------------------------------
485 -----------------------------------------------------------------------------
474 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
486 USE_ADCDRIVER_true: IF USE_ADCDRIVER = 1 GENERATE
475 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
487 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
476 GENERIC MAP (
488 GENERIC MAP (
477 ChanelCount => 9,
489 ChanelCount => 9,
478 ncycle_cnv_high => 13,
490 ncycle_cnv_high => 13,
479 ncycle_cnv => 25,
491 ncycle_cnv => 25,
480 FILTER_ENABLED => 16#FF#)
492 FILTER_ENABLED => 16#FF#)
481 PORT MAP (
493 PORT MAP (
482 cnv_clk => clk_24,
494 cnv_clk => clk_24,
483 cnv_rstn => rstn_24,
495 cnv_rstn => rstn_24,
484 cnv => ADC_smpclk_s,
496 cnv => ADC_smpclk_s,
485 clk => clk_25,
497 clk => clk_25,
486 rstn => rstn_25,
498 rstn => rstn_25,
487 ADC_data => ADC_data,
499 ADC_data => ADC_data,
488 ADC_nOE => ADC_OEB_bar_CH_s,
500 ADC_nOE => ADC_OEB_bar_CH_s,
489 sample => sample,
501 sample => sample,
490 sample_val => sample_val);
502 sample_val => sample_val);
491
503
492 END GENERATE USE_ADCDRIVER_true;
504 END GENERATE USE_ADCDRIVER_true;
493
505
494 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
506 USE_ADCDRIVER_false: IF USE_ADCDRIVER = 0 GENERATE
495 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
507 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
496 GENERIC MAP (
508 GENERIC MAP (
497 ChanelCount => 9,
509 ChanelCount => 9,
498 ncycle_cnv_high => 13,
510 ncycle_cnv_high => 13,
499 ncycle_cnv => 25,
511 ncycle_cnv => 25,
500 FILTER_ENABLED => 16#FF#)
512 FILTER_ENABLED => 16#FF#)
501 PORT MAP (
513 PORT MAP (
502 cnv_clk => clk_24,
514 cnv_clk => clk_24,
503 cnv_rstn => rstn_24,
515 cnv_rstn => rstn_24,
504 cnv => ADC_smpclk_s,
516 cnv => ADC_smpclk_s,
505 clk => clk_25,
517 clk => clk_25,
506 rstn => rstn_25,
518 rstn => rstn_25,
507 ADC_data => ADC_data,
519 ADC_data => ADC_data,
508 ADC_nOE => OPEN,
520 ADC_nOE => OPEN,
509 sample => OPEN,
521 sample => OPEN,
510 sample_val => sample_val);
522 sample_val => sample_val);
511
523
512 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
524 ADC_OEB_bar_CH_s(8 DOWNTO 0) <= (OTHERS => '1');
513
525
514 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
526 all_sample: FOR I IN 8 DOWNTO 0 GENERATE
515 ramp_generator_1: ramp_generator
527 ramp_generator_1: ramp_generator
516 GENERIC MAP (
528 GENERIC MAP (
517 DATA_SIZE => 14,
529 DATA_SIZE => 14,
518 VALUE_UNSIGNED_INIT => 2**I,
530 VALUE_UNSIGNED_INIT => 2**I,
519 VALUE_UNSIGNED_INCR => 0,
531 VALUE_UNSIGNED_INCR => 0,
520 VALUE_UNSIGNED_MASK => 16#3FFF#)
532 VALUE_UNSIGNED_MASK => 16#3FFF#)
521 PORT MAP (
533 PORT MAP (
522 clk => clk_25,
534 clk => clk_25,
523 rstn => rstn_25,
535 rstn => rstn_25,
524 new_data => sample_val,
536 new_data => sample_val,
525 output_data => sample(I) );
537 output_data => sample(I) );
526 END GENERATE all_sample;
538 END GENERATE all_sample;
527
539
528
540
529 END GENERATE USE_ADCDRIVER_false;
541 END GENERATE USE_ADCDRIVER_false;
530
542
531
543
532
544
533
545
534 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
546 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
535
547
536 ADC_smpclk <= ADC_smpclk_s;
548 ADC_smpclk <= ADC_smpclk_s;
537 HK_smpclk <= ADC_smpclk_s;
549 HK_smpclk <= ADC_smpclk_s;
538
550
539 TAG8 <= nSRAM_BUSY;
540
551
541 -----------------------------------------------------------------------------
552 -----------------------------------------------------------------------------
542 -- HK
553 -- HK
543 -----------------------------------------------------------------------------
554 -----------------------------------------------------------------------------
544 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
555 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
545
556
546 -----------------------------------------------------------------------------
557 -----------------------------------------------------------------------------
547 --
558 --
548 -----------------------------------------------------------------------------
559 -----------------------------------------------------------------------------
549 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
560 inst_bootloader: IF USE_BOOTLOADER = 1 GENERATE
550 lpp_bootloader_1: lpp_bootloader
561 lpp_bootloader_1: lpp_bootloader
551 GENERIC MAP (
562 GENERIC MAP (
552 pindex => 13,
563 pindex => 13,
553 paddr => 13,
564 paddr => 13,
554 pmask => 16#fff#,
565 pmask => 16#fff#,
555 hindex => 3,
566 hindex => 3,
556 haddr => 0,
567 haddr => 0,
557 hmask => 16#fff#)
568 hmask => 16#fff#)
558 PORT MAP (
569 PORT MAP (
559 HCLK => clk_25,
570 HCLK => clk_25,
560 HRESETn => rstn_25,
571 HRESETn => rstn_25,
561 apbi => apbi_ext,
572 apbi => apbi_ext,
562 apbo => apbo_ext(13),
573 apbo => apbo_ext(13),
563 ahbsi => ahbi_s_ext,
574 ahbsi => ahbi_s_ext,
564 ahbso => ahbo_s_ext(3));
575 ahbso => ahbo_s_ext(3));
565 END GENERATE inst_bootloader;
576 END GENERATE inst_bootloader;
577
578 -----------------------------------------------------------------------------
579 --
580 -----------------------------------------------------------------------------
581 USE_DEBUG_VECTOR_IF: IF USE_DEBUG_VECTOR = 1 GENERATE
582 PROCESS (clk_25, rstn_25)
583 BEGIN -- PROCESS
584 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
585 TAG <= (OTHERS => '0');
586 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
587 TAG <= debug_vector(8 DOWNTO 2) & nSRAM_BUSY & debug_vector(0);
588 END IF;
589 END PROCESS;
590
591
592 END GENERATE USE_DEBUG_VECTOR_IF;
593
594 USE_DEBUG_VECTOR_IF2: IF USE_DEBUG_VECTOR = 0 GENERATE
595 ahbrxd <= TAG(1);
596 TAG(3) <= ahbtxd;
597 urxd1 <= TAG(2);
598 TAG(4) <= utxd1;
599 TAG(8) <= nSRAM_BUSY;
600 END GENERATE USE_DEBUG_VECTOR_IF2;
601
566 END beh;
602 END beh;
Show file before | Show file after | Hide comments
@@ -1,672 +1,679
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 LIBRARY techmap;
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
28 USE techmap.gencomp.ALL;
29
29
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_sim_pkg.ALL;
31 USE lpp.lpp_sim_pkg.ALL;
32 USE lpp.lpp_lfr_sim_pkg.ALL;
32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 USE lpp.iir_filter.ALL;
35 USE lpp.iir_filter.ALL;
36 USE lpp.FILTERcfg.ALL;
36 USE lpp.FILTERcfg.ALL;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
38 USE lpp.lpp_waveform_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_top_lfr_pkg.ALL;
40 USE lpp.lpp_top_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.general_purpose.ALL;
42 USE lpp.general_purpose.ALL;
43 --LIBRARY lpp;
43 --LIBRARY lpp;
44 USE lpp.lpp_ad_conv.ALL;
44 USE lpp.lpp_ad_conv.ALL;
45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47
47
48 --USE work.debug.ALL;
48 --USE work.debug.ALL;
49
49
50 LIBRARY gaisler;
50 LIBRARY gaisler;
51 USE gaisler.libdcom.ALL;
51 USE gaisler.libdcom.ALL;
52 USE gaisler.sim.ALL;
52 USE gaisler.sim.ALL;
53 USE gaisler.memctrl.ALL;
53 USE gaisler.memctrl.ALL;
54 USE gaisler.leon3.ALL;
54 USE gaisler.leon3.ALL;
55 USE gaisler.uart.ALL;
55 USE gaisler.uart.ALL;
56 USE gaisler.misc.ALL;
56 USE gaisler.misc.ALL;
57 USE gaisler.spacewire.ALL;
57 USE gaisler.spacewire.ALL;
58
58
59 ENTITY TB IS
59 ENTITY TB IS
60
60
61 END TB;
61 END TB;
62
62
63 ARCHITECTURE beh OF TB IS
63 ARCHITECTURE beh OF TB IS
64 -- CONSTANT sramfile : STRING := "prom.srec";
65 CONSTANT sramfile : STRING;
64
66
65 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
66
68
67 COMPONENT LFR_EQM
69 COMPONENT LFR_EQM
68 GENERIC (
70 GENERIC (
69 Mem_use : INTEGER;
71 Mem_use : INTEGER;
70 USE_BOOTLOADER : INTEGER;
72 USE_BOOTLOADER : INTEGER;
71 USE_ADCDRIVER : INTEGER;
73 USE_ADCDRIVER : INTEGER;
72 tech : INTEGER;
74 tech : INTEGER;
73 tech_leon : INTEGER);
75 tech_leon : INTEGER;
76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 USE_DEBUG_VECTOR : INTEGER );
74 PORT (
78 PORT (
75 clk50MHz : IN STD_ULOGIC;
79 clk50MHz : IN STD_ULOGIC;
76 clk49_152MHz : IN STD_ULOGIC;
80 clk49_152MHz : IN STD_ULOGIC;
77 reset : IN STD_ULOGIC;
81 reset : IN STD_ULOGIC;
78 TAG1 : IN STD_ULOGIC;
82 --TAG1 : IN STD_ULOGIC;
79 TAG3 : OUT STD_ULOGIC;
83 --TAG3 : OUT STD_ULOGIC;
80 TAG2 : IN STD_ULOGIC;
84 --TAG2 : IN STD_ULOGIC;
81 TAG4 : OUT STD_ULOGIC;
85 --TAG4 : OUT STD_ULOGIC;
86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
82 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
83 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 nSRAM_MBE : INOUT STD_LOGIC;
89 nSRAM_MBE : INOUT STD_LOGIC;
85 nSRAM_E1 : OUT STD_LOGIC;
90 nSRAM_E1 : OUT STD_LOGIC;
86 nSRAM_E2 : OUT STD_LOGIC;
91 nSRAM_E2 : OUT STD_LOGIC;
87 nSRAM_W : OUT STD_LOGIC;
92 nSRAM_W : OUT STD_LOGIC;
88 nSRAM_G : OUT STD_LOGIC;
93 nSRAM_G : OUT STD_LOGIC;
89 nSRAM_BUSY : IN STD_LOGIC;
94 nSRAM_BUSY : IN STD_LOGIC;
90 spw1_en : OUT STD_LOGIC;
95 spw1_en : OUT STD_LOGIC;
91 spw1_din : IN STD_LOGIC;
96 spw1_din : IN STD_LOGIC;
92 spw1_sin : IN STD_LOGIC;
97 spw1_sin : IN STD_LOGIC;
93 spw1_dout : OUT STD_LOGIC;
98 spw1_dout : OUT STD_LOGIC;
94 spw1_sout : OUT STD_LOGIC;
99 spw1_sout : OUT STD_LOGIC;
95 spw2_en : OUT STD_LOGIC;
100 spw2_en : OUT STD_LOGIC;
96 spw2_din : IN STD_LOGIC;
101 spw2_din : IN STD_LOGIC;
97 spw2_sin : IN STD_LOGIC;
102 spw2_sin : IN STD_LOGIC;
98 spw2_dout : OUT STD_LOGIC;
103 spw2_dout : OUT STD_LOGIC;
99 spw2_sout : OUT STD_LOGIC;
104 spw2_sout : OUT STD_LOGIC;
100 bias_fail_sw : OUT STD_LOGIC;
105 bias_fail_sw : OUT STD_LOGIC;
101 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
102 ADC_smpclk : OUT STD_LOGIC;
107 ADC_smpclk : OUT STD_LOGIC;
103 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
104 DAC_SDO : OUT STD_LOGIC;
109 DAC_SDO : OUT STD_LOGIC;
105 DAC_SCK : OUT STD_LOGIC;
110 DAC_SCK : OUT STD_LOGIC;
106 DAC_SYNC : OUT STD_LOGIC;
111 DAC_SYNC : OUT STD_LOGIC;
107 DAC_CAL_EN : OUT STD_LOGIC;
112 DAC_CAL_EN : OUT STD_LOGIC;
108 HK_smpclk : OUT STD_LOGIC;
113 HK_smpclk : OUT STD_LOGIC;
109 ADC_OEB_bar_HK : OUT STD_LOGIC;
114 ADC_OEB_bar_HK : OUT STD_LOGIC;
110 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
111 TAG8 : OUT STD_LOGIC);
112 END COMPONENT;
116 END COMPONENT;
113
117
114 SIGNAL clk50MHz : STD_ULOGIC := '0';
118 SIGNAL clk50MHz : STD_ULOGIC := '0';
115 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
116 SIGNAL reset : STD_ULOGIC;
120 SIGNAL reset : STD_ULOGIC;
117 SIGNAL TAG1 : STD_ULOGIC := '1';
121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
118 SIGNAL TAG3 : STD_ULOGIC;
122 --SIGNAL TAG3 : STD_ULOGIC;
119 SIGNAL TAG2 : STD_ULOGIC := '1';
123 --SIGNAL TAG2 : STD_ULOGIC := '1';
120 SIGNAL TAG4 : STD_ULOGIC;
124 --SIGNAL TAG4 : STD_ULOGIC;
121 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
122 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
123 SIGNAL nSRAM_MBE : STD_LOGIC;
127 SIGNAL nSRAM_MBE : STD_LOGIC;
124 SIGNAL nSRAM_E1 : STD_LOGIC;
128 SIGNAL nSRAM_E1 : STD_LOGIC;
125 SIGNAL nSRAM_E2 : STD_LOGIC;
129 SIGNAL nSRAM_E2 : STD_LOGIC;
126 SIGNAL nSRAM_W : STD_LOGIC;
130 SIGNAL nSRAM_W : STD_LOGIC;
127 SIGNAL nSRAM_G : STD_LOGIC;
131 SIGNAL nSRAM_G : STD_LOGIC;
128 SIGNAL nSRAM_BUSY : STD_LOGIC;
132 SIGNAL nSRAM_BUSY : STD_LOGIC;
129 SIGNAL spw1_en : STD_LOGIC;
133 SIGNAL spw1_en : STD_LOGIC;
130 SIGNAL spw1_din : STD_LOGIC := '1';
134 SIGNAL spw1_din : STD_LOGIC := '1';
131 SIGNAL spw1_sin : STD_LOGIC := '1';
135 SIGNAL spw1_sin : STD_LOGIC := '1';
132 SIGNAL spw1_dout : STD_LOGIC;
136 SIGNAL spw1_dout : STD_LOGIC;
133 SIGNAL spw1_sout : STD_LOGIC;
137 SIGNAL spw1_sout : STD_LOGIC;
134 SIGNAL spw2_en : STD_LOGIC;
138 SIGNAL spw2_en : STD_LOGIC;
135 SIGNAL spw2_din : STD_LOGIC := '1';
139 SIGNAL spw2_din : STD_LOGIC := '1';
136 SIGNAL spw2_sin : STD_LOGIC := '1';
140 SIGNAL spw2_sin : STD_LOGIC := '1';
137 SIGNAL spw2_dout : STD_LOGIC;
141 SIGNAL spw2_dout : STD_LOGIC;
138 SIGNAL spw2_sout : STD_LOGIC;
142 SIGNAL spw2_sout : STD_LOGIC;
139 SIGNAL bias_fail_sw : STD_LOGIC;
143 SIGNAL bias_fail_sw : STD_LOGIC;
140 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
141 SIGNAL ADC_smpclk : STD_LOGIC;
145 SIGNAL ADC_smpclk : STD_LOGIC;
142 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
146 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
143 SIGNAL DAC_SDO : STD_LOGIC;
147 SIGNAL DAC_SDO : STD_LOGIC;
144 SIGNAL DAC_SCK : STD_LOGIC;
148 SIGNAL DAC_SCK : STD_LOGIC;
145 SIGNAL DAC_SYNC : STD_LOGIC;
149 SIGNAL DAC_SYNC : STD_LOGIC;
146 SIGNAL DAC_CAL_EN : STD_LOGIC;
150 SIGNAL DAC_CAL_EN : STD_LOGIC;
147 SIGNAL HK_smpclk : STD_LOGIC;
151 SIGNAL HK_smpclk : STD_LOGIC;
148 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
152 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
149 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
153 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL TAG8 : STD_LOGIC;
154 -- SIGNAL TAG8 : STD_LOGIC;
151
155
152 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
156 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
153 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
157 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
154 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
158 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
155 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
159 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
156 SIGNAL counter_scrub_period : INTEGER;
160 SIGNAL counter_scrub_period : INTEGER;
157
161
158
162
159 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
163 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
160 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
164 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
161 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
165 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
162
166
163 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
167 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
164 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
168 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
165 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
169 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
166 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
170 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
167 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
171 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
168 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
172 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
169
173
170 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
174 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
171 SIGNAL data_message : STRING(1 TO 15) := "---------------";
175 SIGNAL data_message : STRING(1 TO 15) := "---------------";
172 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
176 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
173 SIGNAL TXD1 : STD_LOGIC;
177 SIGNAL TXD1 : STD_LOGIC;
174 SIGNAL RXD1 : STD_LOGIC;
178 SIGNAL RXD1 : STD_LOGIC;
175
179
176 -----------------------------------------------------------------------------
180 -----------------------------------------------------------------------------
177 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
181 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
178 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
182 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
179 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
183 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
180 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
184 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
181 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
185 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
182 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
186 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
183 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
187 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
184 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
188 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
185 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
189 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
186 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
190 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
187 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
191 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
188 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
192 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
189 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
193 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
190 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
194 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
191
195
192
196
193 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
197 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
194 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
198 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
195
199
196 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
200 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
197 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
201 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
198
202
199 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
206 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
203
207
204 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
208 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
205 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
209 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
206 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
210 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
207
211
208
212
209 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
213 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
210 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
211 CONSTANT srambanks : INTEGER := 2;
215 CONSTANT srambanks : INTEGER := 2;
212 CONSTANT sramwidth : INTEGER := 32;
216 CONSTANT sramwidth : INTEGER := 32;
213 CONSTANT sramdepth : INTEGER := 19;
217 CONSTANT sramdepth : INTEGER := 19;
214 CONSTANT sramfile : STRING := "prom.srec";
215 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
218 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
216 -----------------------------------------------------------------------------
219 -----------------------------------------------------------------------------
217
220
218 BEGIN -- beh
221 BEGIN -- beh
219
222
220 LFR_EQM_1 : LFR_EQM
223 LFR_EQM_1 : LFR_EQM
221 GENERIC MAP (
224 GENERIC MAP (
222 Mem_use => use_RAM,
225 Mem_use => use_RAM,
223 USE_BOOTLOADER => 0,
226 USE_BOOTLOADER => 0,
224 USE_ADCDRIVER => 0,
227 USE_ADCDRIVER => 0,
225 tech => apa3e,
228 tech => apa3e,
226 tech_leon => inferred)
229 tech_leon => apa3e,
230 DEBUG_FORCE_DATA_DMA => 1,
231 USE_DEBUG_VECTOR => 0)
227 PORT MAP (
232 PORT MAP (
228 clk50MHz => clk50MHz, --IN --ok
233 clk50MHz => clk50MHz, --IN --ok
229 clk49_152MHz => clk49_152MHz, --in --ok
234 clk49_152MHz => clk49_152MHz, --in --ok
230 reset => reset, --IN --ok
235 reset => reset, --IN --ok
231
236
232 TAG1 => TAG1, --in
237 TAG => TAG,
233 TAG3 => TAG3, --out
238 --TAG1 => TAG1, --in
234 TAG2 => TAG2, --IN --ok
239 --TAG3 => TAG3, --out
235 TAG4 => TAG4, --out --ok
240 --TAG2 => TAG2, --IN --ok
241 --TAG4 => TAG4, --out --ok
236
242
237 address => address, --out
243 address => address, --out
238 data => data, --inout
244 data => data, --inout
239 nSRAM_MBE => nSRAM_MBE, --inout
245 nSRAM_MBE => nSRAM_MBE, --inout
240 nSRAM_E1 => nSRAM_E1, --out
246 nSRAM_E1 => nSRAM_E1, --out
241 nSRAM_E2 => nSRAM_E2, --out
247 nSRAM_E2 => nSRAM_E2, --out
242 nSRAM_W => nSRAM_W, --out
248 nSRAM_W => nSRAM_W, --out
243 nSRAM_G => nSRAM_G, --out
249 nSRAM_G => nSRAM_G, --out
244 nSRAM_BUSY => nSRAM_BUSY, --in
250 nSRAM_BUSY => nSRAM_BUSY, --in
245
251
246 spw1_en => spw1_en, --out --ok
252 spw1_en => spw1_en, --out --ok
247 spw1_din => spw1_din, --in --ok
253 spw1_din => spw1_din, --in --ok
248 spw1_sin => spw1_sin, --in --ok
254 spw1_sin => spw1_sin, --in --ok
249 spw1_dout => spw1_dout, --out --ok
255 spw1_dout => spw1_dout, --out --ok
250 spw1_sout => spw1_sout, --out --ok
256 spw1_sout => spw1_sout, --out --ok
251
257
252 spw2_en => spw2_en, --out --ok
258 spw2_en => spw2_en, --out --ok
253 spw2_din => spw2_din, --in --ok
259 spw2_din => spw2_din, --in --ok
254 spw2_sin => spw2_sin, --in --ok
260 spw2_sin => spw2_sin, --in --ok
255 spw2_dout => spw2_dout, --out --ok
261 spw2_dout => spw2_dout, --out --ok
256 spw2_sout => spw2_sout, --out --ok
262 spw2_sout => spw2_sout, --out --ok
257
263
258 bias_fail_sw => bias_fail_sw, --OUT --ok
264 bias_fail_sw => bias_fail_sw, --OUT --ok
259
265
260 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
266 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
261 ADC_smpclk => ADC_smpclk, --out --ok
267 ADC_smpclk => ADC_smpclk, --out --ok
262 ADC_data => ADC_data, --IN --ok
268 ADC_data => ADC_data, --IN --ok
263
269
264 DAC_SDO => DAC_SDO, --out --ok
270 DAC_SDO => DAC_SDO, --out --ok
265 DAC_SCK => DAC_SCK, --out --ok
271 DAC_SCK => DAC_SCK, --out --ok
266 DAC_SYNC => DAC_SYNC, --out --ok
272 DAC_SYNC => DAC_SYNC, --out --ok
267 DAC_CAL_EN => DAC_CAL_EN, --out --ok
273 DAC_CAL_EN => DAC_CAL_EN, --out --ok
268
274
269 HK_smpclk => HK_smpclk, --out --ok
275 HK_smpclk => HK_smpclk, --out --ok
270 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
276 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
271 HK_SEL => HK_SEL, --out --ok
277 HK_SEL => HK_SEL); --out --ok
272 TAG8 => TAG8); --out --ok
273
278
274
279
275 -----------------------------------------------------------------------------
280 -----------------------------------------------------------------------------
276 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
281 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
277 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
282 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
278 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
279
284
280 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
285 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
281 TestModule_RHF1401_1 : TestModule_RHF1401
286 TestModule_RHF1401_1 : TestModule_RHF1401
282 GENERIC MAP (
287 GENERIC MAP (
283 freq => 24*(I+1),
288 freq => 24*(I+1),
284 amplitude => 8000/(I+1),
289 amplitude => 8000/(I+1),
285 impulsion => 0)
290 impulsion => 0)
286 PORT MAP (
291 PORT MAP (
287 ADC_smpclk => ADC_smpclk,
292 ADC_smpclk => ADC_smpclk,
288 ADC_OEB_bar => ADC_OEB_bar_CH(I),
293 ADC_OEB_bar => ADC_OEB_bar_CH(I),
289 ADC_data => ADC_data);
294 ADC_data => ADC_data);
290 END GENERATE MODULE_RHF1401;
295 END GENERATE MODULE_RHF1401;
291
296
292 -----------------------------------------------------------------------------
297 -----------------------------------------------------------------------------
293 PROCESS (clk50MHz, reset)
298 PROCESS (clk50MHz, reset)
294 BEGIN -- PROCESS
299 BEGIN -- PROCESS
295 IF reset = '0' THEN -- asynchronous reset (active low)
300 IF reset = '0' THEN -- asynchronous reset (active low)
296 nSRAM_BUSY <= '1';
301 nSRAM_BUSY <= '1';
297 counter_scrub_period <= 0;
302 counter_scrub_period <= 0;
298 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
303 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
299 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
304 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
300 counter_scrub_period <= 0;
305 counter_scrub_period <= 0;
301 ELSE
306 ELSE
302 counter_scrub_period <= counter_scrub_period + 1;
307 counter_scrub_period <= counter_scrub_period + 1;
303 END IF;
308 END IF;
304
309
305 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
310 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
306 nSRAM_BUSY <= '1';
311 nSRAM_BUSY <= '1';
307 ELSE
312 ELSE
308 nSRAM_BUSY <= '0';
313 nSRAM_BUSY <= '0';
309 END IF;
314 END IF;
310 END IF;
315 END IF;
311 END PROCESS;
316 END PROCESS;
312
317
313 -----------------------------------------------------------------------------
318 -----------------------------------------------------------------------------
314 -- TB
319 -- TB
315 -----------------------------------------------------------------------------
320 -----------------------------------------------------------------------------
316 TAG1 <= TXD1;
321 TAG(1) <= TXD1;
317 RXD1 <= TAG3;
322 TAG(2) <= '1';
323 RXD1 <= TAG(3);
318
324
319 PROCESS
325 PROCESS
320 CONSTANT txp : TIME := 320 ns;
326 CONSTANT txp : TIME := 320 ns;
321 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
327 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
322 BEGIN -- PROCESS
328 BEGIN -- PROCESS
323 TXD1 <= '1';
329 TXD1 <= '1';
324 reset <= '0';
330 reset <= '0';
325 WAIT FOR 500 ns;
331 WAIT FOR 500 ns;
326 reset <= '1';
332 reset <= '1';
327 WAIT FOR 100 us;
333 WAIT FOR 100 us;
328 message_simu <= "0 - UART init ";
334 message_simu <= "0 - UART init ";
329 UART_INIT(TXD1, txp);
335 UART_INIT(TXD1, txp);
330
336
331 ---------------------------------------------------------------------------
337 ---------------------------------------------------------------------------
332 -- LAUNCH leon 3 software
338 -- LAUNCH leon 3 software
333 ---------------------------------------------------------------------------
339 ---------------------------------------------------------------------------
334 message_simu <= "2- GO Leon3....";
340 message_simu <= "2- GO Leon3....";
335
341
336 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
342 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
337 --Force a debug break
343 --Force a debug break
338 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
344 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
339 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
345 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
340 --Clear time tag counter
346 --Clear time tag counter
341 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
347 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
342 --Clear ASR registers
348 --Clear ASR registers
343 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
344 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
345 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
346 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
347 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
348 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
350 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
358
364
359 IF USE_ESA_MEMCTRL = 1 THEN
365 IF USE_ESA_MEMCTRL = 1 THEN
360 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
366 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
361 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
367 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
362 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
368 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
363 END IF;
369 END IF;
364
370
365 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
371 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
366 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
372 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
367 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
373 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
368 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
374 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
369 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
375 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
370
376
371 --memSet(DSUBASEADDRESS+0x300000,0,1567);
377 --memSet(DSUBASEADDRESS+0x300000,0,1567);
372
378
373 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
374 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
380 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
375 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
376 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
377 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
383 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
378 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
379 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
380
386
381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
383 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
386 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
388 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
405
411
406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
407
413
408 --//Disable interrupts
414 --//Disable interrupts
409 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
415 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
410 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
416 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
411 -- return false;
417 -- return false;
412 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
418 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
413 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
419 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
414 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
420 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
415
421
416 -- //Set up timer
422 -- //Set up timer
417 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
423 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
418 --if(APBTIMERBASEADD == (unsigned int)-1)
424 --if(APBTIMERBASEADD == (unsigned int)-1)
419 -- return false;
425 -- return false;
420 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
426 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
421 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
427 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
422 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
428 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
423
429
424
430
425 ---------------------------------------------------------------------------
431 ---------------------------------------------------------------------------
426 --bool dsu3plugin::setCacheEnable(bool enabled)
432 --bool dsu3plugin::setCacheEnable(bool enabled)
427 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
433 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
428 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
434 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
429 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
435 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
430 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
436 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
431 data_read <= data_read_v;
437 data_read <= data_read_v;
432 --if(enabled){
438 --if(enabled){
433 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
439 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
434 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
440 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
435 --}else{
441 --}else{
436 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
442 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
437 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
443 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
438 --}
444 --}
439
445
440
446
441 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
447 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
442 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
448 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
443
449
444 ---------------------------------------------------------------------------
450 ---------------------------------------------------------------------------
445 --message_simu <= "1 - UART test ";
451 --message_simu <= "1 - UART test ";
446 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
452 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
447 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
453 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
448 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
454 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
449 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
455 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
450 --data_read <= data_read_v;
456 --data_read <= data_read_v;
451 --data_message <= "GPIO_data_write";
457 --data_message <= "GPIO_data_write";
452
458
453 -- UNSET the LFR reset
459 -- UNSET the LFR reset
454 message_simu <= "2 - LFR UNRESET";
460 message_simu <= "2 - LFR UNRESET";
455 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
461 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
456 --
462 --
457 message_simu <= "3 - LFR CONFIG ";
463 message_simu <= "3 - LFR CONFIG ";
458 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
464 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
459 ADDR_BUFFER_MS_F0_0,
465 ADDR_BUFFER_MS_F0_0,
460 ADDR_BUFFER_MS_F0_1,
466 ADDR_BUFFER_MS_F0_1,
461 ADDR_BUFFER_MS_F1_0,
467 ADDR_BUFFER_MS_F1_0,
462 ADDR_BUFFER_MS_F1_1,
468 ADDR_BUFFER_MS_F1_1,
463 ADDR_BUFFER_MS_F2_0,
469 ADDR_BUFFER_MS_F2_0,
464 ADDR_BUFFER_MS_F2_1);
470 ADDR_BUFFER_MS_F2_1);
465
471
466
472
467 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
473 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
468 LFR_MODE_SBM1,
474 LFR_MODE_SBM1,
469 X"7FFFFFFF", -- START DATE
475 X"7FFFFFFF", -- START DATE
470
476
471 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
477 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
472 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
478 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
473 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
479 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
474 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
480 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
475 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
481 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
476 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
482 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
477
483
478 ADDR_BASE_LFR,
484 ADDR_BASE_LFR,
479 ADDR_BUFFER_WFP_F0_0,
485 ADDR_BUFFER_WFP_F0_0,
480 ADDR_BUFFER_WFP_F0_1,
486 ADDR_BUFFER_WFP_F0_1,
481 ADDR_BUFFER_WFP_F1_0,
487 ADDR_BUFFER_WFP_F1_0,
482 ADDR_BUFFER_WFP_F1_1,
488 ADDR_BUFFER_WFP_F1_1,
483 ADDR_BUFFER_WFP_F2_0,
489 ADDR_BUFFER_WFP_F2_0,
484 ADDR_BUFFER_WFP_F2_1,
490 ADDR_BUFFER_WFP_F2_1,
485 ADDR_BUFFER_WFP_F3_0,
491 ADDR_BUFFER_WFP_F3_0,
486 ADDR_BUFFER_WFP_F3_1);
492 ADDR_BUFFER_WFP_F3_1);
487
493
488 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
494 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
489 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
495 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
490
496
491
497
492 ---------------------------------------------------------------------------
498 ---------------------------------------------------------------------------
493 -- CONFIG LFR 2
499 -- CONFIG LFR 2
494 ---------------------------------------------------------------------------
500 ---------------------------------------------------------------------------
495 --message_simu <= "3 - LFR2 CONFIG";
501 --message_simu <= "3 - LFR2 CONFIG";
496 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
502 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
497 -- X"40000000",
503 -- X"40000000",
498 -- X"40001000",
504 -- X"40001000",
499 -- X"40002000",
505 -- X"40002000",
500 -- X"40003000",
506 -- X"40003000",
501 -- X"40004000",
507 -- X"40004000",
502 -- X"40005000");
508 -- X"40005000");
503
509
504
510
505 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
511 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
506 -- LFR_MODE_SBM1,
512 -- LFR_MODE_SBM1,
507 -- X"7FFFFFFF", -- START DATE
513 -- X"7FFFFFFF", -- START DATE
508
514
509 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
515 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
510 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
516 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
511 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
517 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
512 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
518 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
513 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
519 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
514 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
520 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
515
521
516 -- ADDR_BASE_LFR_2,
522 -- ADDR_BASE_LFR_2,
517 -- X"40006000",
523 -- X"40006000",
518 -- X"40007000",
524 -- X"40007000",
519 -- X"40008000",
525 -- X"40008000",
520 -- X"40009000",
526 -- X"40009000",
521 -- X"4000A000",
527 -- X"4000A000",
522 -- X"4000B000",
528 -- X"4000B000",
523 -- X"4000C000",
529 -- X"4000C000",
524 -- X"4000D000");
530 -- X"4000D000");
525
531
526 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
532 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
527 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
533 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
528
534
529 ---------------------------------------------------------------------------
535 ---------------------------------------------------------------------------
530 ---------------------------------------------------------------------------
536 ---------------------------------------------------------------------------
537 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"58", X"FFFFFFFF");
531
538
532
539
533 message_simu <= "4 - GO GO GO !!";
540 message_simu <= "4 - GO GO GO !!";
534 data_message <= "---------------";
541 data_message <= "---------------";
535 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
542 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
536 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
543 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
537
544
538
545
539 data_read_v := (OTHERS => '1');
546 data_read_v := (OTHERS => '1');
540 READ_STATUS : LOOP
547 READ_STATUS : LOOP
541 data_message <= "---------------";
548 data_message <= "---------------";
542 WAIT FOR 2 ms;
549 WAIT FOR 2 ms;
543 data_message <= "READ_STATUS_SM_";
550 data_message <= "READ_STATUS_SM_";
544 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
551 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
545 --data_message <= "--------------r";
552 --data_message <= "--------------r";
546 --data_read <= data_read_v;
553 --data_read <= data_read_v;
547 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
554 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
548
555
549 data_message <= "READ_STATUS_WF_";
556 data_message <= "READ_STATUS_WF_";
550 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
557 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
551 --data_message <= "--------------r";
558 --data_message <= "--------------r";
552 --data_read <= data_read_v;
559 --data_read <= data_read_v;
553 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
560 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
554 END LOOP READ_STATUS;
561 END LOOP READ_STATUS;
555
562
556 WAIT;
563 WAIT;
557 END PROCESS;
564 END PROCESS;
558
565
559
566
560 -----------------------------------------------------------------------------
567 -----------------------------------------------------------------------------
561 PROCESS (nSRAM_W, reset)
568 PROCESS (nSRAM_W, reset)
562 BEGIN -- PROCESS
569 BEGIN -- PROCESS
563 IF reset = '0' THEN -- asynchronous reset (active low)
570 IF reset = '0' THEN -- asynchronous reset (active low)
564 data_pre_f0 <= X"00020001";
571 data_pre_f0 <= X"00020001";
565 data_pre_f1 <= X"00020001";
572 data_pre_f1 <= X"00020001";
566 data_pre_f2 <= X"00020001";
573 data_pre_f2 <= X"00020001";
567
574
568 addr_pre_f0 <= (OTHERS => '0');
575 addr_pre_f0 <= (OTHERS => '0');
569 addr_pre_f1 <= (OTHERS => '0');
576 addr_pre_f1 <= (OTHERS => '0');
570 addr_pre_f2 <= (OTHERS => '0');
577 addr_pre_f2 <= (OTHERS => '0');
571
578
572 error_wfp <= "000";
579 error_wfp <= "000";
573 error_wfp_addr <= "000";
580 error_wfp_addr <= "000";
574
581
575 sample_counter <= (0,0,0);
582 sample_counter <= (0,0,0);
576
583
577 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
584 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
578 error_wfp <= "000";
585 error_wfp <= "000";
579 error_wfp_addr <= "000";
586 error_wfp_addr <= "000";
580 -------------------------------------------------------------------------
587 -------------------------------------------------------------------------
581 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
588 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
582 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
589 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
583
590
584 addr_pre_f0 <= address(13 DOWNTO 0);
591 addr_pre_f0 <= address(13 DOWNTO 0);
585 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
592 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
586 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
593 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
587 error_wfp_addr(0) <= '1';
594 error_wfp_addr(0) <= '1';
588 END IF;
595 END IF;
589 END IF;
596 END IF;
590
597
591 data_pre_f0 <= data;
598 data_pre_f0 <= data;
592 CASE data_pre_f0 IS
599 CASE data_pre_f0 IS
593 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
600 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
594 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
601 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
595 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
602 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
596 WHEN OTHERS => error_wfp(0) <= '1';
603 WHEN OTHERS => error_wfp(0) <= '1';
597 END CASE;
604 END CASE;
598
605
599
606
600 END IF;
607 END IF;
601 -------------------------------------------------------------------------
608 -------------------------------------------------------------------------
602 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
609 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
603 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
610 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
604
611
605 addr_pre_f1 <= address(13 DOWNTO 0);
612 addr_pre_f1 <= address(13 DOWNTO 0);
606 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
613 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
607 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
614 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
608 error_wfp_addr(1) <= '1';
615 error_wfp_addr(1) <= '1';
609 END IF;
616 END IF;
610 END IF;
617 END IF;
611
618
612 data_pre_f1 <= data;
619 data_pre_f1 <= data;
613 CASE data_pre_f1 IS
620 CASE data_pre_f1 IS
614 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
621 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
615 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
622 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
616 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
623 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
617 WHEN OTHERS => error_wfp(1) <= '1';
624 WHEN OTHERS => error_wfp(1) <= '1';
618 END CASE;
625 END CASE;
619
626
620 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
627 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
621 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
628 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
622 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
629 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
623
630
624 END IF;
631 END IF;
625 -------------------------------------------------------------------------
632 -------------------------------------------------------------------------
626 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
633 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
627 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
634 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
628
635
629 addr_pre_f2 <= address(13 DOWNTO 0);
636 addr_pre_f2 <= address(13 DOWNTO 0);
630 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
637 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
631 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
638 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
632 error_wfp_addr(2) <= '1';
639 error_wfp_addr(2) <= '1';
633 END IF;
640 END IF;
634 END IF;
641 END IF;
635
642
636 data_pre_f2 <= data;
643 data_pre_f2 <= data;
637 CASE data_pre_f2 IS
644 CASE data_pre_f2 IS
638 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
645 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
639 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
646 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
640 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
647 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
641 WHEN OTHERS => error_wfp(2) <= '1';
648 WHEN OTHERS => error_wfp(2) <= '1';
642 END CASE;
649 END CASE;
643
650
644 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
651 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
645 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
652 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
646 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
653 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
647
654
648 END IF;
655 END IF;
649 END IF;
656 END IF;
650 END PROCESS;
657 END PROCESS;
651 -----------------------------------------------------------------------------
658 -----------------------------------------------------------------------------
652 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
659 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
653
660
654 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
661 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
655 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
662 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
656 sr0 : sram
663 sr0 : sram
657 GENERIC MAP (
664 GENERIC MAP (
658 index => i,
665 index => i,
659 abits => sramdepth,
666 abits => sramdepth,
660 fname => sramfile)
667 fname => sramfile)
661 PORT MAP (
668 PORT MAP (
662 address,
669 address,
663 data(31-i*8 DOWNTO 24-i*8),
670 data(31-i*8 DOWNTO 24-i*8),
664 ramsn(k),
671 ramsn(k),
665 nSRAM_W,
672 nSRAM_W,
666 nSRAM_G
673 nSRAM_G
667 );
674 );
668 END GENERATE;
675 END GENERATE;
669 END GENERATE;
676 END GENERATE;
670
677
671 END beh;
678 END beh;
672
679
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1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd
1 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd
8 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd
9 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd
10 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd
11 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd
12 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd
13 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd
13 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd
14 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd
14 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd
15 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd
15 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd
16 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd
16 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd
17 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd
17 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd
18 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd
18 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd
19 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd
19 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd
20 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd
20 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd
21 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd
21 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd
22 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd
22 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd
23 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd
23 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd
24 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd
24 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd
25 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd
25 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd
26 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd
26 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd
27 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd
27 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd
28 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd
28 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd
29 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd
29 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd
30 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd
30 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd
31 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd
31 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd
32 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd
32 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd
33 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd
33 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd
34 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd
34 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd
35 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd
35 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd
36 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd
36 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd
37 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd
37 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd
38 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd
38 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd
39 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd
39 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd
40 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd
40 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd
41 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd
41 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd
42 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd
42 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd
43 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd
43 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd
44 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd
44 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ramp_generator.vhd
45 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd
45 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd
46 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd
46 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd
47 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd
47 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd
48 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd
48 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd
49 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd
49 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd
50 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
50 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd
51 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd
51 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd
52 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
52 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd
53 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd
53 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd
54 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
54 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd
55 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
55 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd
56 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
56 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd
57 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd
57 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd
58 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd
58 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd
59 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd
59 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd
60 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd
60 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd
61 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd
61 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd
62 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd
62 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd
63 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd
63 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd
64 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd
64 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd
65 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd
65 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd
66 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd
66 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd
67 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd
67 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd
68 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd
68 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd
69 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd
69 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd
70 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd
70 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd
71 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd
71 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd
72 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd
72 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd
73 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd
73 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd
74 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd
74 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd
75 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd
75 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd
76 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd
76 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd
77 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd
77 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd
78 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd
78 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd
79 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
79 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd
80 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd
80 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd
81 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd
81 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd
82 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
82 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd
83 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd
83 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd
84 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd
84 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd
85 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd
85 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd
86 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd
86 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd
87 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
87 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd
88 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd
88 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd
89 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
89 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd
90 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd
90 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd
91 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd
91 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd
92 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd
92 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd
93 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd
93 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd
94 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd
94 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd
95 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd
95 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd
96 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd
96 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd
97 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd
97 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd
98 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd
98 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd
99 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd
99 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd
100 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd
100 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd
101 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd
101 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd
102 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd
102 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd
103 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
103 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd
104 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd
104 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd
105 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd
105 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd
106 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
106 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd
107 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd
107 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd
108 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd
108 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd
109 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd
109 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd
110 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd
110 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd
111 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd
111 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd
112 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd
112 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd
113 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd
113 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd
114 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd
114 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd
115 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd
115 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd
116 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd
116 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd
117 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
117 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd
118 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd
118 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd
119 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd
119 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd
120 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd
120 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd
121 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd
121 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd
122 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
122 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
123 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd
123 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd
124 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd
124 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd
125 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd
125 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd
126 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd
126 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd
127 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd
127 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd
128 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd
128 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd
129 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd
129 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd
130 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd
130 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd
131 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd
131 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd
132 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd
132 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd
133 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
133 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd
134 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
134 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd
135 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
135 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd
136 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
136 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd
137 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
137 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd
138 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
138 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd
139 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
139 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd
140 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd
140 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd
141 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd
141 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd
142 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd
142 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd
143 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd
143 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd
144 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd
144 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd
145 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd
145 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd
146 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd
146 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd
147 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd
147 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd
148 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd
148 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd
149 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd
149 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd
150 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd
150 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd
151 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd
151 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd
152 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd
152 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd
153 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd
153 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd
154 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
154 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd
155 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd
155 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd
156 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd
156 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd
157 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd
157 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd
158 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
158 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd
159 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd
159 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd
160 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd
160 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd
161 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
161 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd
162 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd
162 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd
163 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd
163 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd
164 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd
164 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd
165 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd
165 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd
166 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
166 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd
167 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
167 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd
168 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd
168 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd
169 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd
169 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd
170 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd
170 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd
171 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
171 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd
172 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd
172 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd
173 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
173 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd
174 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd
174 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd
175 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd
175 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd
176 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd
176 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd
177 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd
177 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd
178 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd
178 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd
179 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd
179 vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd
180 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd
180 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd
181 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd
181 vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd
182 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd
182 vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd
183 vcom -quiet -93 -work work LFR-EQM.vhd
183 vcom -quiet -93 -work work LFR-EQM.vhd
184 vcom -quiet -93 -work work TB.vhd
184 vcom -quiet -93 -work work TB.vhd
185
185
186 vsim work.tb
186 vsim work.tb
187 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0
187 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0
188 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0
188 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0
189 #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0
189 #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0
190
190
191 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
191 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
192 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
192 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
193 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
193 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
194 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
194 #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 000000000000000100000000000000100000000000000100000000000000100000000000000100000000000000100000 0
195
195
196 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
196 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(0)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
197 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
197 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(1)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
198 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
198 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(2)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
199 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
199 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_waveform_1/generate_all_fifo(3)/lpp_fifo_1/memRAM/SRAM/inf/x0/rfd
200
200
201 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
201 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_f0_to_f1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
202 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
202 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/IIR_CEL_CTRLR_v2_DATAFLOW_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
203 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
203 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_1/memRAM/SRAM/inf/x0/rfd
204 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd
204 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v3_1/RAM_CTRLR_v2_2/memRAM/SRAM/inf/x0/rfd
205
205
206 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd
206 mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/cic_lfr_1/memRAM/SRAM/inf/x0/rfd
207
207
208 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
208 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
209 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
209 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x0/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
210 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
210 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
211 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
211 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/rf0/s1/dp/x1/proa3e/x0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
212 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
212 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(0)/u0/u0/VITALBehavior/MEM_512_9
213 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
213 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/itags0/proa3e/x0/r2p/u0/a8/x(1)/u0/u0/VITALBehavior/MEM_512_9
214 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9
214 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(0)/u0/u0/VITALBehavior/MEM_512_9
215 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9
215 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(1)/u0/u0/VITALBehavior/MEM_512_9
216 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9
216 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(2)/u0/u0/VITALBehavior/MEM_512_9
217 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9
217 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(3)/u0/u0/VITALBehavior/MEM_512_9
218 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9
218 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(4)/u0/u0/VITALBehavior/MEM_512_9
219 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9
219 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(5)/u0/u0/VITALBehavior/MEM_512_9
220 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9
220 #mem load -skip 0 -filltype value -filldata 0 -fillradix symbolic /tb/LFR_EQM_1/leon3_soc_1/l3/cpu(0)/leon3_non_radhard/u0/cmem0/ime/im0(0)/idata0/proa3e/x0/rdp/u0/a10/x(6)/u0/u0/VITALBehavior/MEM_512_9
221
221
222 log -r *;
222 log -r *;
223 do wave.do ;
223 do wave.do ;
224 run -all
224 run -all
225
225
226
226
Show file before | Show file after | Hide comments
@@ -1,116 +1,125
1 onerror {resume}
1 onerror {resume}
2 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc
2 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc
3 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA
4 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA
3 quietly WaveActivateNextPane {} 0
5 quietly WaveActivateNextPane {} 0
4 add wave -noupdate /tb/data_message
6 add wave -noupdate -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1)
5 add wave -noupdate /tb/message_simu
7 add wave -noupdate -height 74 -max 326.0 -min 256.0 /tb/sample_counter
6 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
8 add wave -noupdate -expand -group ALL /tb/data_message
7 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
9 add wave -noupdate -expand -group ALL /tb/message_simu
8 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
10 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
9 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
11 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
10 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
12 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
11 add wave -noupdate -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
13 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
12 add wave -noupdate -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
14 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
13 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
15 add wave -noupdate -expand -group ALL -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
14 add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
16 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
15 add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
17 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
16 add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
18 add wave -noupdate -expand -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
17 add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
19 add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
18 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
20 add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
19 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
21 add wave -noupdate -expand -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
20 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
22 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
21 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
23 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
22 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
24 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
23 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
25 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
24 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
26 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
25 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
27 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
26 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
28 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
27 add wave -noupdate -expand -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
29 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
28 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
30 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
29 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
31 add wave -noupdate -expand -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
30 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
32 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
31 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
33 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
32 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
34 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
33 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
35 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
34 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
36 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
35 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
37 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
36 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
38 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
37 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
39 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
38 add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
40 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
39 add wave -noupdate -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
41 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
40 add wave -noupdate -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
42 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
41 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
43 add wave -noupdate -expand -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
42 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk
44 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
43 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
45 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
44 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid
46 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk
45 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex
47 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
46 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn
48 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid
47 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
49 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex
48 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
50 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn
49 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid
51 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
50 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version
52 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
51 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
53 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid
52 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
54 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version
53 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
55 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
54 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
56 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
55 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
57 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
56 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
58 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
57 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
59 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
58 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
60 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
59 add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
61 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
60 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
62 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
61 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
63 add wave -noupdate -expand -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
62 add wave -noupdate -expand -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0
64 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
63 add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f1
65 add wave -noupdate -expand -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
64 add wave -noupdate -expand -group TEST -radix hexadecimal /tb/data_pre_f2
66 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0
65 add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f0
67 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1
66 add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f1
68 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2
67 add wave -noupdate -expand -group TEST -radix hexadecimal /tb/addr_pre_f2
69 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0
68 add wave -noupdate /tb/error_wfp
70 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1
69 add wave -noupdate /tb/error_wfp_addr
71 add wave -noupdate -expand -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2
70 add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a
72 add wave -noupdate -expand -group ALL /tb/error_wfp
71 add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1
73 add wave -noupdate -expand -group ALL /tb/error_wfp_addr
72 add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe
74 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a
73 add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we
75 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1
74 add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a
76 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe
75 add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1
77 add wave -noupdate -expand -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we
76 add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe
78 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a
77 add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we
79 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1
78 add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi
80 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe
79 add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo
81 add wave -noupdate -expand -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we
80 add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi
82 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi
81 add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso
83 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo
82 add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbmi
84 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi
83 add wave -noupdate -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo
85 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso
84 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
86 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi
85 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
87 add wave -noupdate -expand -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo
86 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
88 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
87 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
89 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
88 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
90 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
89 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
91 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
90 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
92 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
91 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
93 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
92 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
94 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
93 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
95 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
94 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
96 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
95 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
97 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
96 add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
98 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
97 add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-height 15 -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} /tb/sample(2)(5) {-height 15 -radix decimal} /tb/sample(2)(4) {-height 15 -radix decimal} /tb/sample(2)(3) {-height 15 -radix decimal} /tb/sample(2)(2) {-height 15 -radix decimal} /tb/sample(2)(1) {-height 15 -radix decimal} /tb/sample(2)(0) {-height 15 -radix decimal} /tb/sample(1) {-height 15 -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -expand} /tb/sample(1)(5) {-format Analog-Step -height 74 -min -4.0 -radix decimal} /tb/sample(1)(4) {-format Analog-Step -height 74 -min -8.0 -radix decimal} /tb/sample(1)(3) {-format Analog-Step -height 74 -max 70.0 -radix decimal} /tb/sample(1)(2) {-format Analog-Step -height 74 -max 512.0 -radix decimal} /tb/sample(1)(1) {-format Analog-Step -height 74 -max 256.0 -radix decimal} /tb/sample(1)(0) {-format Analog-Step -height 74 -max 16.0 -radix decimal} /tb/sample(0) {-height 15 -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-height 15 -radix decimal} /tb/sample(0)(4) {-height 15 -radix decimal} /tb/sample(0)(3) {-height 15 -radix decimal} /tb/sample(0)(2) {-height 15 -radix decimal} /tb/sample(0)(1) {-height 15 -radix decimal} /tb/sample(0)(0) {-height 15 -radix decimal}} /tb/sample
99 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
98 add wave -noupdate /tb/sample_counter
100 add wave -noupdate -expand -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
101 add wave -noupdate -expand /tb/LFR_EQM_1/debug_vector
102 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
103 add wave -noupdate -radix unsigned /tb/LFR_EQM_1/HWDATA
104 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
105 add wave -noupdate -radix unsigned /tb/LFR_EQM_1/DMA_DATA
106 add wave -noupdate -label DMA_REN /tb/LFR_EQM_1/debug_vector(8)
107 add wave -noupdate -label HREADY /tb/LFR_EQM_1/debug_vector(5)
99 TreeUpdate [SetDefaultTree]
108 TreeUpdate [SetDefaultTree]
100 WaveRestoreCursors {{Cursor 1} {14590425667 ps} 0} {{Cursor 2} {5525050896 ps} 0} {{Cursor 3} {24728625854 ps} 0}
109 WaveRestoreCursors {{Cursor 1} {13070951696 ps} 0} {{Cursor 2} {6213170000 ps} 0} {{Cursor 3} {102733931000 ps} 0}
101 quietly wave cursor active 1
110 quietly wave cursor active 2
102 configure wave -namecolwidth 517
111 configure wave -namecolwidth 517
103 configure wave -valuecolwidth 347
112 configure wave -valuecolwidth 347
104 configure wave -justifyvalue left
113 configure wave -justifyvalue left
105 configure wave -signalnamewidth 0
114 configure wave -signalnamewidth 0
106 configure wave -snapdistance 10
115 configure wave -snapdistance 10
107 configure wave -datasetprefix 0
116 configure wave -datasetprefix 0
108 configure wave -rowmargin 4
117 configure wave -rowmargin 4
109 configure wave -childrowmargin 2
118 configure wave -childrowmargin 2
110 configure wave -gridoffset 0
119 configure wave -gridoffset 0
111 configure wave -gridperiod 1
120 configure wave -gridperiod 1
112 configure wave -griddelta 40
121 configure wave -griddelta 40
113 configure wave -timeline 0
122 configure wave -timeline 0
114 configure wave -timelineunits ns
123 configure wave -timelineunits ns
115 update
124 update
116 WaveRestoreZoom {0 ps} {40323664500 ps}
125 WaveRestoreZoom {6212445233 ps} {6219679457 ps}
Show file before | Show file after | Hide comments
@@ -1,226 +1,240
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.apb_devices_list.ALL;
6 USE lpp.apb_devices_list.ALL;
7 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
9 USE lpp.FILTERcfg.ALL;
9 USE lpp.FILTERcfg.ALL;
10 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_memory.ALL;
11 --USE lpp.lpp_waveform_pkg.ALL;
11 --USE lpp.lpp_waveform_pkg.ALL;
12 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_dma_pkg.ALL;
13 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_top_lfr_pkg.ALL;
14 --USE lpp.lpp_lfr_pkg.ALL;
14 --USE lpp.lpp_lfr_pkg.ALL;
15 USE lpp.general_purpose.ALL;
15 USE lpp.general_purpose.ALL;
16
16
17 LIBRARY techmap;
17 LIBRARY techmap;
18 USE techmap.gencomp.ALL;
18 USE techmap.gencomp.ALL;
19
19
20 LIBRARY grlib;
20 LIBRARY grlib;
21 USE grlib.amba.ALL;
21 USE grlib.amba.ALL;
22 USE grlib.stdlib.ALL;
22 USE grlib.stdlib.ALL;
23 USE grlib.devices.ALL;
23 USE grlib.devices.ALL;
24 USE GRLIB.DMA2AHB_Package.ALL;
24 USE GRLIB.DMA2AHB_Package.ALL;
25
25
26 ENTITY DMA_SubSystem IS
26 ENTITY DMA_SubSystem IS
27
27
28 GENERIC (
28 GENERIC (
29 hindex : INTEGER := 2;
29 hindex : INTEGER := 2;
30 CUSTOM_DMA : INTEGER := 1);
30 CUSTOM_DMA : INTEGER := 1);
31
31
32 PORT (
32 PORT (
33 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
35 run : IN STD_LOGIC;
36 -- AHB
36 -- AHB
37 ahbi : IN AHB_Mst_In_Type;
37 ahbi : IN AHB_Mst_In_Type;
38 ahbo : OUT AHB_Mst_Out_Type;
38 ahbo : OUT AHB_Mst_Out_Type;
39 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
40 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
41 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
42 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
45 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
45 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
46 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
46 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
47 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 grant_error : OUT STD_LOGIC --
50 grant_error : OUT STD_LOGIC;
51 ---------------------------------------------------------------------------
52 debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
51
53
52 );
54 );
53
55
54 END DMA_SubSystem;
56 END DMA_SubSystem;
55
57
56
58
57 ARCHITECTURE beh OF DMA_SubSystem IS
59 ARCHITECTURE beh OF DMA_SubSystem IS
58
60
59 COMPONENT DMA_SubSystem_GestionBuffer
61 COMPONENT DMA_SubSystem_GestionBuffer
60 GENERIC (
62 GENERIC (
61 BUFFER_ADDR_SIZE : INTEGER;
63 BUFFER_ADDR_SIZE : INTEGER;
62 BUFFER_LENGTH_SIZE : INTEGER);
64 BUFFER_LENGTH_SIZE : INTEGER);
63 PORT (
65 PORT (
64 clk : IN STD_LOGIC;
66 clk : IN STD_LOGIC;
65 rstn : IN STD_LOGIC;
67 rstn : IN STD_LOGIC;
66 run : IN STD_LOGIC;
68 run : IN STD_LOGIC;
67 buffer_new : IN STD_LOGIC;
69 buffer_new : IN STD_LOGIC;
68 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
70 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
69 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
71 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
70 buffer_full : OUT STD_LOGIC;
72 buffer_full : OUT STD_LOGIC;
71 buffer_full_err : OUT STD_LOGIC;
73 buffer_full_err : OUT STD_LOGIC;
72 burst_send : IN STD_LOGIC;
74 burst_send : IN STD_LOGIC;
73 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
75 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
74 END COMPONENT;
76 END COMPONENT;
75
77
76 COMPONENT DMA_SubSystem_Arbiter
78 COMPONENT DMA_SubSystem_Arbiter
77 PORT (
79 PORT (
78 clk : IN STD_LOGIC;
80 clk : IN STD_LOGIC;
79 rstn : IN STD_LOGIC;
81 rstn : IN STD_LOGIC;
80 run : IN STD_LOGIC;
82 run : IN STD_LOGIC;
81 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
84 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
83 END COMPONENT;
85 END COMPONENT;
84
86
85 COMPONENT DMA_SubSystem_MUX
87 COMPONENT DMA_SubSystem_MUX
86 PORT (
88 PORT (
87 clk : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
88 rstn : IN STD_LOGIC;
90 rstn : IN STD_LOGIC;
89 run : IN STD_LOGIC;
91 run : IN STD_LOGIC;
90 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
92 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
91 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
93 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
92 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
94 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
93 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
95 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
94 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
96 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
95 dma_send : OUT STD_LOGIC;
97 dma_send : OUT STD_LOGIC;
96 dma_valid_burst : OUT STD_LOGIC;
98 dma_valid_burst : OUT STD_LOGIC;
97 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 dma_ren : IN STD_LOGIC;
101 dma_ren : IN STD_LOGIC;
100 dma_done : IN STD_LOGIC;
102 dma_done : IN STD_LOGIC;
101 grant_error : OUT STD_LOGIC);
103 grant_error : OUT STD_LOGIC);
102 END COMPONENT;
104 END COMPONENT;
103
105
104 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
105 SIGNAL dma_send : STD_LOGIC;
107 SIGNAL dma_send : STD_LOGIC;
106 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
108 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
107 SIGNAL dma_done : STD_LOGIC;
109 SIGNAL dma_done : STD_LOGIC;
108 SIGNAL dma_ren : STD_LOGIC;
110 SIGNAL dma_ren : STD_LOGIC;
109 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
115 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
114
116
115
117 SIGNAL ahbo_s : AHB_Mst_Out_Type;
118 SIGNAL fifo_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 BEGIN -- beh
119 BEGIN -- beh
117
120
121
122 debug_vector <= fifo_ren_s(0) &
123 dma_data(1 DOWNTO 0) &
124 ahbi.HREADY &
125 ahbo_s.HWDATA(1 DOWNTO 0) &
126 ahbi.HGRANT(hindex) &
127 ahbo_s.HTRANS(0) &
128 ahbo_s.HLOCK;
129
130 ahbo <= ahbo_s;
131 fifo_ren <= fifo_ren_s;
118 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
119 -- DMA
133 -- DMA
120 -----------------------------------------------------------------------------
134 -----------------------------------------------------------------------------
121 GR_DMA : IF CUSTOM_DMA = 0 GENERATE
135 GR_DMA : IF CUSTOM_DMA = 0 GENERATE
122 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
136 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
123 GENERIC MAP (
137 GENERIC MAP (
124 tech => inferred,
138 tech => inferred,
125 hindex => hindex)
139 hindex => hindex)
126 PORT MAP (
140 PORT MAP (
127 HCLK => clk,
141 HCLK => clk,
128 HRESETn => rstn,
142 HRESETn => rstn,
129 run => run,
143 run => run,
130 AHB_Master_In => ahbi,
144 AHB_Master_In => ahbi,
131 AHB_Master_Out => ahbo,
145 AHB_Master_Out => ahbo_s,
132
146
133 send => dma_send,
147 send => dma_send,
134 valid_burst => dma_valid_burst,
148 valid_burst => dma_valid_burst,
135 done => dma_done,
149 done => dma_done,
136 ren => dma_ren,
150 ren => dma_ren,
137 address => dma_address,
151 address => dma_address,
138 data => dma_data);
152 data => dma_data);
139 END GENERATE GR_DMA;
153 END GENERATE GR_DMA;
140
154
141 LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
155 LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
142 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
156 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
143 GENERIC MAP (
157 GENERIC MAP (
144 hindex => hindex,
158 hindex => hindex,
145 vendorid => VENDOR_LPP,
159 vendorid => VENDOR_LPP,
146 deviceid => 10,
160 deviceid => 10,
147 version => 0)
161 version => 0)
148 PORT MAP (
162 PORT MAP (
149 clk => clk,
163 clk => clk,
150 rstn => rstn,
164 rstn => rstn,
151 AHB_Master_In => ahbi,
165 AHB_Master_In => ahbi,
152 AHB_Master_Out => ahbo,
166 AHB_Master_Out => ahbo_s,
153
167
154 ren => dma_ren,
168 ren => dma_ren,
155 data => dma_data,
169 data => dma_data,
156 send => dma_send,
170 send => dma_send,
157 valid_burst => dma_valid_burst,
171 valid_burst => dma_valid_burst,
158 done => dma_done,
172 done => dma_done,
159 address => dma_address);
173 address => dma_address);
160 END GENERATE LPP_DMA_IP;
174 END GENERATE LPP_DMA_IP;
161
175
162
176
163 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
164 -- RoundRobin Selection Channel For DMA
178 -- RoundRobin Selection Channel For DMA
165 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
166 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
180 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
167 PORT MAP (
181 PORT MAP (
168 clk => clk,
182 clk => clk,
169 rstn => rstn,
183 rstn => rstn,
170 run => run,
184 run => run,
171 data_burst_valid => fifo_burst_valid,
185 data_burst_valid => fifo_burst_valid,
172 data_burst_valid_grant => fifo_grant);
186 data_burst_valid_grant => fifo_grant);
173
187
174
188
175 -----------------------------------------------------------------------------
189 -----------------------------------------------------------------------------
176 -- Mux between the channel from Waveform Picker and Spectral Matrix
190 -- Mux between the channel from Waveform Picker and Spectral Matrix
177 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
178 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
192 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
179 PORT MAP (
193 PORT MAP (
180 clk => clk,
194 clk => clk,
181 rstn => rstn,
195 rstn => rstn,
182 run => run,
196 run => run,
183
197
184 fifo_grant => fifo_grant,
198 fifo_grant => fifo_grant,
185 fifo_data => fifo_data,
199 fifo_data => fifo_data,
186 fifo_address => fifo_address,
200 fifo_address => fifo_address,
187 fifo_ren => fifo_ren,
201 fifo_ren => fifo_ren_s,
188 fifo_burst_done => burst_send,
202 fifo_burst_done => burst_send,
189
203
190 dma_send => dma_send,
204 dma_send => dma_send,
191 dma_valid_burst => dma_valid_burst,
205 dma_valid_burst => dma_valid_burst,
192 dma_address => dma_address,
206 dma_address => dma_address,
193 dma_data => dma_data,
207 dma_data => dma_data,
194 dma_ren => dma_ren,
208 dma_ren => dma_ren,
195 dma_done => dma_done,
209 dma_done => dma_done,
196
210
197 grant_error => grant_error);
211 grant_error => grant_error);
198
212
199
213
200 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
201 -- GEN ADDR
215 -- GEN ADDR
202 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
203 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
217 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
204 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
218 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
205 GENERIC MAP (
219 GENERIC MAP (
206 BUFFER_ADDR_SIZE => 32,
220 BUFFER_ADDR_SIZE => 32,
207 BUFFER_LENGTH_SIZE => 26)
221 BUFFER_LENGTH_SIZE => 26)
208 PORT MAP (
222 PORT MAP (
209 clk => clk,
223 clk => clk,
210 rstn => rstn,
224 rstn => rstn,
211 run => run,
225 run => run,
212
226
213 buffer_new => buffer_new(I),
227 buffer_new => buffer_new(I),
214 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
228 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
215 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
229 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
216 buffer_full => buffer_full(I),
230 buffer_full => buffer_full(I),
217 buffer_full_err => buffer_full_err(I),
231 buffer_full_err => buffer_full_err(I),
218
232
219 burst_send => burst_send(I),
233 burst_send => burst_send(I),
220 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
234 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
221 );
235 );
222 END GENERATE all_buffer;
236 END GENERATE all_buffer;
223
237
224
238
225
239
226 END beh;
240 END beh;
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@@ -1,233 +1,255
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
24 -------------------------------------------------------------------------------
25 LIBRARY ieee;
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
26 USE ieee.std_logic_1164.ALL;
27 USE ieee.numeric_std.ALL;
27 USE ieee.numeric_std.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
31 USE grlib.devices.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_amba.ALL;
34 USE lpp.lpp_amba.ALL;
35 USE lpp.apb_devices_list.ALL;
35 USE lpp.apb_devices_list.ALL;
36 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.general_purpose.ALL;
38 USE lpp.general_purpose.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
40 LIBRARY techmap;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
41 USE techmap.gencomp.ALL;
42
42
43
43
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 GENERIC (
45 GENERIC (
46 hindex : INTEGER := 2;
46 hindex : INTEGER := 2;
47 vendorid : IN INTEGER := 0;
47 vendorid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
49 version : IN INTEGER := 0
49 version : IN INTEGER := 0
50 );
50 );
51 PORT (
51 PORT (
52 clk : IN STD_LOGIC;
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
54
55 -- AMBA AHB Master Interface
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
58
59 -- FIFO Interface
59 -- FIFO Interface
60 ren : OUT STD_LOGIC;
60 ren : OUT STD_LOGIC;
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62
62
63 -- Controls
63 -- Controls
64 send : IN STD_LOGIC;
64 send : IN STD_LOGIC;
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 done : OUT STD_LOGIC;
66 done : OUT STD_LOGIC;
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 );
68 );
69 END;
69 END;
70
70
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72
72
73 CONSTANT HConfig : AHB_Config_Type := (
73 CONSTANT HConfig : AHB_Config_Type := (
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
75 OTHERS => (OTHERS => '0'));
76
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_INIT_TRANS, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82
82
83 SIGNAL data_window : STD_LOGIC;
83 SIGNAL data_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
85
85
86 SIGNAL bus_request : STD_LOGIC;
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
88
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
89 SIGNAL data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
90
91 SIGNAL HREADY_pre : STD_LOGIC;
92 SIGNAL HREADY_falling : STD_LOGIC;
93
94 SIGNAL inhib_ren : STD_LOGIC;
90
95
91 BEGIN
96 BEGIN
92
97
93 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
94 AHB_Master_Out.HCONFIG <= HConfig;
99 AHB_Master_Out.HCONFIG <= HConfig;
95 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
100 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
96 AHB_Master_Out.HINDEX <= hindex;
101 AHB_Master_Out.HINDEX <= hindex;
97 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
102 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
98 AHB_Master_Out.HIRQ <= (OTHERS => '0');
103 AHB_Master_Out.HIRQ <= (OTHERS => '0');
99 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
104 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
100 AHB_Master_Out.HWRITE <= '1';
105 AHB_Master_Out.HWRITE <= '1';
101
106
102 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
107 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
103
108
104 --AHB_Master_Out.HBUSREQ <= bus_request;
109 --AHB_Master_Out.HBUSREQ <= bus_request;
105 --AHB_Master_Out.HLOCK <= data_window;
110 --AHB_Master_Out.HLOCK <= data_window;
106
111
107 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
112 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
108 -- '1' WHEN ctrl_window = '1' ELSE
113 -- '1' WHEN ctrl_window = '1' ELSE
109 -- '0';
114 -- '0';
110
115
111 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
116 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
112 -- '1' WHEN ctrl_window = '1' ELSE '0';
117 -- '1' WHEN ctrl_window = '1' ELSE '0';
113
118
114 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
115 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
120 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
116 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
121 AHB_Master_Out.HWDATA <= ahbdrivedata(data) WHEN AHB_Master_In.HREADY = '1' ELSE ahbdrivedata(data_reg);
117
122
118 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
119 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
124 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
120 --ren <= NOT beat;
125 --ren <= NOT beat;
121 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
127
128 HREADY_falling <= inhib_ren WHEN AHB_Master_In.HREADY = '0' AND HREADY_pre = '1' ELSE '1';
129
130
122 PROCESS (clk, rstn)
131 PROCESS (clk, rstn)
123 BEGIN -- PROCESS
132 BEGIN -- PROCESS
124 IF rstn = '0' THEN -- asynchronous reset (active low)
133 IF rstn = '0' THEN -- asynchronous reset (active low)
125 state <= IDLE;
134 state <= IDLE;
126 done <= '0';
135 done <= '0';
127 ren <= '1';
136 ren <= '1';
128 address_counter_reg <= (OTHERS => '0');
137 address_counter_reg <= (OTHERS => '0');
129 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
138 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
130 AHB_Master_Out.HBUSREQ <= '0';
139 AHB_Master_Out.HBUSREQ <= '0';
131 AHB_Master_Out.HLOCK <= '0';
140 AHB_Master_Out.HLOCK <= '0';
132
141
133 data_reg <= (OTHERS => '0');
142 data_reg <= (OTHERS => '0');
143
144 HREADY_pre <= '0';
145 inhib_ren <= '0';
134 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
146 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
135
147 HREADY_pre <= AHB_Master_In.HREADY;
148
136 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
149 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
137 data_reg <= data;
150 data_reg <= data;
138 END IF;
151 END IF;
139
152
140 done <= '0';
153 done <= '0';
141 ren <= '1';
154 ren <= '1';
155 inhib_ren <= '0';
142 CASE state IS
156 CASE state IS
143 WHEN IDLE =>
157 WHEN IDLE =>
144 AHB_Master_Out.HBUSREQ <= '0';
158 AHB_Master_Out.HBUSREQ <= '0';
145 AHB_Master_Out.HLOCK <= '0';
159 AHB_Master_Out.HLOCK <= '0';
146 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
160 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
147 address_counter_reg <= (OTHERS => '0');
161 address_counter_reg <= (OTHERS => '0');
148 IF send = '1' THEN
162 IF send = '1' THEN
149 AHB_Master_Out.HBUSREQ <= '1';
163 state <= s_INIT_TRANS;
150 AHB_Master_Out.HLOCK <= '1';
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_ARBITER;
153 END IF;
164 END IF;
154
165
166 WHEN s_INIT_TRANS =>
167 AHB_Master_Out.HBUSREQ <= '1';
168 AHB_Master_Out.HLOCK <= '1';
169 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
170 state <= s_ARBITER;
171
155 WHEN s_ARBITER =>
172 WHEN s_ARBITER =>
156 AHB_Master_Out.HBUSREQ <= '1';
173 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
174 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
159 address_counter_reg <= (OTHERS => '0');
176 address_counter_reg <= (OTHERS => '0');
160
177
161 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
178 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
162 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
179 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
163 state <= s_CTRL;
180 state <= s_CTRL;
164 END IF;
181 END IF;
165
182
166 WHEN s_CTRL =>
183 WHEN s_CTRL =>
184 inhib_ren <= '1';
167 AHB_Master_Out.HBUSREQ <= '1';
185 AHB_Master_Out.HBUSREQ <= '1';
168 AHB_Master_Out.HLOCK <= '1';
186 AHB_Master_Out.HLOCK <= '1';
169 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
187 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
170 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
188 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
171 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
189 --AHB_Master_Out.HTRANS <= HTRANS_SEQ;
172 state <= s_CTRL_DATA;
190 state <= s_CTRL_DATA;
173 ren <= '0';
191 --ren <= '0';
174 END IF;
192 END IF;
175
193
176 WHEN s_CTRL_DATA =>
194 WHEN s_CTRL_DATA =>
177 AHB_Master_Out.HBUSREQ <= '1';
195 AHB_Master_Out.HBUSREQ <= '1';
178 AHB_Master_Out.HLOCK <= '1';
196 AHB_Master_Out.HLOCK <= '1';
179 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
197 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
180 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
198 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
181 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
199 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
182 END IF;
200 END IF;
183
201
184 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
202 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
185 AHB_Master_Out.HBUSREQ <= '0';
203 AHB_Master_Out.HBUSREQ <= '0';
186 AHB_Master_Out.HLOCK <= '1';--'0';
204 AHB_Master_Out.HLOCK <= '1';--'0';
187 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
205 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
188 state <= s_DATA;
206 state <= s_DATA;
189 END IF;
207 END IF;
190
208
191 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
209 ren <= HREADY_falling;
192 ren <= '0';
210
193 END IF;
211 --IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' AND address_counter_reg /= "1111" THEN
212 -- ren <= '0';
213 --END IF;
194
214
195
215
196 WHEN s_DATA =>
216 WHEN s_DATA =>
217 ren <= HREADY_falling;
218
197 AHB_Master_Out.HBUSREQ <= '0';
219 AHB_Master_Out.HBUSREQ <= '0';
198 --AHB_Master_Out.HLOCK <= '0';
220 --AHB_Master_Out.HLOCK <= '0';
199 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
221 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
200 IF AHB_Master_In.HREADY = '1' THEN
222 IF AHB_Master_In.HREADY = '1' THEN
201 AHB_Master_Out.HLOCK <= '0';
223 AHB_Master_Out.HLOCK <= '0';
202 state <= IDLE;
224 state <= IDLE;
203 done <= '1';
225 done <= '1';
204 END IF;
226 END IF;
205
227
206 WHEN OTHERS => NULL;
228 WHEN OTHERS => NULL;
207 END CASE;
229 END CASE;
208 END IF;
230 END IF;
209 END PROCESS;
231 END PROCESS;
210
232
211 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
233 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
212 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
234 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
213 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
214
236
215
237
216 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
238 --ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
217
239
218 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
219 --PROCESS (clk, rstn)
241 --PROCESS (clk, rstn)
220 --BEGIN -- PROCESS
242 --BEGIN -- PROCESS
221 -- IF rstn = '0' THEN -- asynchronous reset (active low)
243 -- IF rstn = '0' THEN -- asynchronous reset (active low)
222 -- address_counter_reg <= (OTHERS => '0');
244 -- address_counter_reg <= (OTHERS => '0');
223 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
245 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
224 -- address_counter_reg <= address_counter;
246 -- address_counter_reg <= address_counter;
225 -- END IF;
247 -- END IF;
226 --END PROCESS;
248 --END PROCESS;
227
249
228 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
250 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
229 -- address_counter_reg;
251 -- address_counter_reg;
230 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
231
253
232
254
233 END Behavioral;
255 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,309 +1,311
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE std.textio.ALL;
27 USE std.textio.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 --LIBRARY lpp;
34 --LIBRARY lpp;
35 --USE lpp.lpp_amba.ALL;
35 --USE lpp.lpp_amba.ALL;
36 --USE lpp.apb_devices_list.ALL;
36 --USE lpp.apb_devices_list.ALL;
37 --USE lpp.lpp_memory.ALL;
37 --USE lpp.lpp_memory.ALL;
38
38
39 PACKAGE lpp_dma_pkg IS
39 PACKAGE lpp_dma_pkg IS
40
40
41 COMPONENT lpp_dma
41 COMPONENT lpp_dma
42 GENERIC (
42 GENERIC (
43 tech : INTEGER;
43 tech : INTEGER;
44 hindex : INTEGER;
44 hindex : INTEGER;
45 pindex : INTEGER;
45 pindex : INTEGER;
46 paddr : INTEGER;
46 paddr : INTEGER;
47 pmask : INTEGER;
47 pmask : INTEGER;
48 pirq : INTEGER);
48 pirq : INTEGER);
49 PORT (
49 PORT (
50 HCLK : IN STD_ULOGIC;
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 -- fifo interface
56 -- fifo interface
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 fifo_empty : IN STD_LOGIC;
58 fifo_empty : IN STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
60 -- header
60 -- header
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 header_val : IN STD_LOGIC;
62 header_val : IN STD_LOGIC;
63 header_ack : OUT STD_LOGIC);
63 header_ack : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66 COMPONENT fifo_test_dma
66 COMPONENT fifo_test_dma
67 GENERIC (
67 GENERIC (
68 tech : INTEGER;
68 tech : INTEGER;
69 pindex : INTEGER;
69 pindex : INTEGER;
70 paddr : INTEGER;
70 paddr : INTEGER;
71 pmask : INTEGER);
71 pmask : INTEGER);
72 PORT (
72 PORT (
73 HCLK : IN STD_ULOGIC;
73 HCLK : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
75 apbi : IN apb_slv_in_type;
75 apbi : IN apb_slv_in_type;
76 apbo : OUT apb_slv_out_type;
76 apbo : OUT apb_slv_out_type;
77 -- fifo interface
77 -- fifo interface
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fifo_empty : OUT STD_LOGIC;
79 fifo_empty : OUT STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
81 -- header
81 -- header
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 header_val : OUT STD_LOGIC;
83 header_val : OUT STD_LOGIC;
84 header_ack : IN STD_LOGIC
84 header_ack : IN STD_LOGIC
85 );
85 );
86 END COMPONENT;
86 END COMPONENT;
87
87
88 COMPONENT lpp_dma_apbreg
88 COMPONENT lpp_dma_apbreg
89 GENERIC (
89 GENERIC (
90 pindex : INTEGER;
90 pindex : INTEGER;
91 paddr : INTEGER;
91 paddr : INTEGER;
92 pmask : INTEGER;
92 pmask : INTEGER;
93 pirq : INTEGER);
93 pirq : INTEGER);
94 PORT (
94 PORT (
95 HCLK : IN STD_ULOGIC;
95 HCLK : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
97 apbi : IN apb_slv_in_type;
97 apbi : IN apb_slv_in_type;
98 apbo : OUT apb_slv_out_type;
98 apbo : OUT apb_slv_out_type;
99 -- IN
99 -- IN
100 ready_matrix_f0_0 : IN STD_LOGIC;
100 ready_matrix_f0_0 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107
107
108 -- OUT
108 -- OUT
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
115
115
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 );
122 );
123 END COMPONENT;
123 END COMPONENT;
124
124
125 COMPONENT lpp_dma_send_1word
125 COMPONENT lpp_dma_send_1word
126 PORT (
126 PORT (
127 HCLK : IN STD_ULOGIC;
127 HCLK : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
129 DMAIn : OUT DMA_In_Type;
129 DMAIn : OUT DMA_In_Type;
130 DMAOut : IN DMA_OUt_Type;
130 DMAOut : IN DMA_OUt_Type;
131 send : IN STD_LOGIC;
131 send : IN STD_LOGIC;
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 ren : OUT STD_LOGIC;
134 ren : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
136 send_ko : OUT STD_LOGIC);
136 send_ko : OUT STD_LOGIC);
137 END COMPONENT;
137 END COMPONENT;
138
138
139 COMPONENT lpp_dma_send_16word
139 COMPONENT lpp_dma_send_16word
140 PORT (
140 PORT (
141 HCLK : IN STD_ULOGIC;
141 HCLK : IN STD_ULOGIC;
142 HRESETn : IN STD_ULOGIC;
142 HRESETn : IN STD_ULOGIC;
143 DMAIn : OUT DMA_In_Type;
143 DMAIn : OUT DMA_In_Type;
144 DMAOut : IN DMA_OUt_Type;
144 DMAOut : IN DMA_OUt_Type;
145 send : IN STD_LOGIC;
145 send : IN STD_LOGIC;
146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 ren : OUT STD_LOGIC;
148 ren : OUT STD_LOGIC;
149 send_ok : OUT STD_LOGIC;
149 send_ok : OUT STD_LOGIC;
150 send_ko : OUT STD_LOGIC);
150 send_ko : OUT STD_LOGIC);
151 END COMPONENT;
151 END COMPONENT;
152
152
153 COMPONENT fifo_latency_correction
153 COMPONENT fifo_latency_correction
154 PORT (
154 PORT (
155 HCLK : IN STD_ULOGIC;
155 HCLK : IN STD_ULOGIC;
156 HRESETn : IN STD_ULOGIC;
156 HRESETn : IN STD_ULOGIC;
157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 fifo_empty : IN STD_LOGIC;
158 fifo_empty : IN STD_LOGIC;
159 fifo_ren : OUT STD_LOGIC;
159 fifo_ren : OUT STD_LOGIC;
160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 dma_empty : OUT STD_LOGIC;
161 dma_empty : OUT STD_LOGIC;
162 dma_ren : IN STD_LOGIC);
162 dma_ren : IN STD_LOGIC);
163 END COMPONENT;
163 END COMPONENT;
164
164
165 COMPONENT lpp_dma_ip
165 COMPONENT lpp_dma_ip
166 GENERIC (
166 GENERIC (
167 tech : INTEGER;
167 tech : INTEGER;
168 hindex : INTEGER);
168 hindex : INTEGER);
169 PORT (
169 PORT (
170 HCLK : IN STD_ULOGIC;
170 HCLK : IN STD_ULOGIC;
171 HRESETn : IN STD_ULOGIC;
171 HRESETn : IN STD_ULOGIC;
172 AHB_Master_In : IN AHB_Mst_In_Type;
172 AHB_Master_In : IN AHB_Mst_In_Type;
173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 fifo_empty : IN STD_LOGIC;
175 fifo_empty : IN STD_LOGIC;
176 fifo_ren : OUT STD_LOGIC;
176 fifo_ren : OUT STD_LOGIC;
177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 header_val : IN STD_LOGIC;
178 header_val : IN STD_LOGIC;
179 header_ack : OUT STD_LOGIC;
179 header_ack : OUT STD_LOGIC;
180 ready_matrix_f0_0 : OUT STD_LOGIC;
180 ready_matrix_f0_0 : OUT STD_LOGIC;
181 ready_matrix_f0_1 : OUT STD_LOGIC;
181 ready_matrix_f0_1 : OUT STD_LOGIC;
182 ready_matrix_f1 : OUT STD_LOGIC;
182 ready_matrix_f1 : OUT STD_LOGIC;
183 ready_matrix_f2 : OUT STD_LOGIC;
183 ready_matrix_f2 : OUT STD_LOGIC;
184 error_anticipating_empty_fifo : OUT STD_LOGIC;
184 error_anticipating_empty_fifo : OUT STD_LOGIC;
185 error_bad_component_error : OUT STD_LOGIC;
185 error_bad_component_error : OUT STD_LOGIC;
186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 status_ready_matrix_f0_0 : IN STD_LOGIC;
187 status_ready_matrix_f0_0 : IN STD_LOGIC;
188 status_ready_matrix_f0_1 : IN STD_LOGIC;
188 status_ready_matrix_f0_1 : IN STD_LOGIC;
189 status_ready_matrix_f1 : IN STD_LOGIC;
189 status_ready_matrix_f1 : IN STD_LOGIC;
190 status_ready_matrix_f2 : IN STD_LOGIC;
190 status_ready_matrix_f2 : IN STD_LOGIC;
191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
192 status_error_bad_component_error : IN STD_LOGIC;
192 status_error_bad_component_error : IN STD_LOGIC;
193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
194 config_active_interruption_onError : IN STD_LOGIC;
194 config_active_interruption_onError : IN STD_LOGIC;
195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
199 END COMPONENT;
199 END COMPONENT;
200
200
201 COMPONENT lpp_dma_singleOrBurst
201 COMPONENT lpp_dma_singleOrBurst
202 GENERIC (
202 GENERIC (
203 tech : INTEGER;
203 tech : INTEGER;
204 hindex : INTEGER);
204 hindex : INTEGER);
205 PORT (
205 PORT (
206 HCLK : IN STD_ULOGIC;
206 HCLK : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
208 run : IN STD_LOGIC;
208 run : IN STD_LOGIC;
209 AHB_Master_In : IN AHB_Mst_In_Type;
209 AHB_Master_In : IN AHB_Mst_In_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 send : IN STD_LOGIC;
211 send : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
213 done : OUT STD_LOGIC;
213 done : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_dmaout_okay : OUT STD_LOGIC);
217 debug_dmaout_okay : OUT STD_LOGIC);
218 END COMPONENT;
218 END COMPONENT;
219
219
220
220
221 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
222 -- DMA_SubSystem
222 -- DMA_SubSystem
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 COMPONENT DMA_SubSystem
224 COMPONENT DMA_SubSystem
225 GENERIC (
225 GENERIC (
226 hindex : INTEGER;
226 hindex : INTEGER;
227 CUSTOM_DMA : INTEGER := 1);
227 CUSTOM_DMA : INTEGER := 1);
228 PORT (
228 PORT (
229 clk : IN STD_LOGIC;
229 clk : IN STD_LOGIC;
230 rstn : IN STD_LOGIC;
230 rstn : IN STD_LOGIC;
231 run : IN STD_LOGIC;
231 run : IN STD_LOGIC;
232 ahbi : IN AHB_Mst_In_Type;
232 ahbi : IN AHB_Mst_In_Type;
233 ahbo : OUT AHB_Mst_Out_Type;
233 ahbo : OUT AHB_Mst_Out_Type;
234 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
234 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
235 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
236 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
236 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
237 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
237 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
238 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
239 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
240 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
240 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
242 grant_error : OUT STD_LOGIC);
242 grant_error : OUT STD_LOGIC;
243 debug_vector : OUT STD_LOGIC_VECTOR(8 DOWNTO 0)
244 );
243 END COMPONENT;
245 END COMPONENT;
244
246
245 COMPONENT DMA_SubSystem_GestionBuffer
247 COMPONENT DMA_SubSystem_GestionBuffer
246 GENERIC (
248 GENERIC (
247 BUFFER_ADDR_SIZE : INTEGER;
249 BUFFER_ADDR_SIZE : INTEGER;
248 BUFFER_LENGTH_SIZE : INTEGER);
250 BUFFER_LENGTH_SIZE : INTEGER);
249 PORT (
251 PORT (
250 clk : IN STD_LOGIC;
252 clk : IN STD_LOGIC;
251 rstn : IN STD_LOGIC;
253 rstn : IN STD_LOGIC;
252 run : IN STD_LOGIC;
254 run : IN STD_LOGIC;
253 buffer_new : IN STD_LOGIC;
255 buffer_new : IN STD_LOGIC;
254 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
256 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
255 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
257 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
256 buffer_full : OUT STD_LOGIC;
258 buffer_full : OUT STD_LOGIC;
257 buffer_full_err : OUT STD_LOGIC;
259 buffer_full_err : OUT STD_LOGIC;
258 burst_send : IN STD_LOGIC;
260 burst_send : IN STD_LOGIC;
259 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
261 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
260 END COMPONENT;
262 END COMPONENT;
261
263
262 COMPONENT DMA_SubSystem_Arbiter
264 COMPONENT DMA_SubSystem_Arbiter
263 PORT (
265 PORT (
264 clk : IN STD_LOGIC;
266 clk : IN STD_LOGIC;
265 rstn : IN STD_LOGIC;
267 rstn : IN STD_LOGIC;
266 run : IN STD_LOGIC;
268 run : IN STD_LOGIC;
267 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
269 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
268 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
270 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
269 END COMPONENT;
271 END COMPONENT;
270
272
271 COMPONENT DMA_SubSystem_MUX
273 COMPONENT DMA_SubSystem_MUX
272 PORT (
274 PORT (
273 clk : IN STD_LOGIC;
275 clk : IN STD_LOGIC;
274 rstn : IN STD_LOGIC;
276 rstn : IN STD_LOGIC;
275 run : IN STD_LOGIC;
277 run : IN STD_LOGIC;
276 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
278 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
277 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
279 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
280 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
279 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
281 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
280 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
282 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
281 dma_send : OUT STD_LOGIC;
283 dma_send : OUT STD_LOGIC;
282 dma_valid_burst : OUT STD_LOGIC;
284 dma_valid_burst : OUT STD_LOGIC;
283 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
286 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 dma_ren : IN STD_LOGIC;
287 dma_ren : IN STD_LOGIC;
286 dma_done : IN STD_LOGIC;
288 dma_done : IN STD_LOGIC;
287 grant_error : OUT STD_LOGIC);
289 grant_error : OUT STD_LOGIC);
288 END COMPONENT;
290 END COMPONENT;
289
291
290 COMPONENT lpp_dma_SEND16B_FIFO2DMA
292 COMPONENT lpp_dma_SEND16B_FIFO2DMA
291 GENERIC (
293 GENERIC (
292 hindex : INTEGER;
294 hindex : INTEGER;
293 vendorid : in Integer;
295 vendorid : in Integer;
294 deviceid : in Integer;
296 deviceid : in Integer;
295 version : in Integer);
297 version : in Integer);
296 PORT (
298 PORT (
297 clk : IN STD_LOGIC;
299 clk : IN STD_LOGIC;
298 rstn : IN STD_LOGIC;
300 rstn : IN STD_LOGIC;
299 AHB_Master_In : IN AHB_Mst_In_Type;
301 AHB_Master_In : IN AHB_Mst_In_Type;
300 AHB_Master_Out : OUT AHB_Mst_Out_Type;
302 AHB_Master_Out : OUT AHB_Mst_Out_Type;
301 ren : OUT STD_LOGIC;
303 ren : OUT STD_LOGIC;
302 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
304 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 send : IN STD_LOGIC;
305 send : IN STD_LOGIC;
304 valid_burst : IN STD_LOGIC;
306 valid_burst : IN STD_LOGIC;
305 done : OUT STD_LOGIC;
307 done : OUT STD_LOGIC;
306 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
308 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
307 END COMPONENT;
309 END COMPONENT;
308
310
309 END;
311 END;
Show file before | Show file after | Hide comments
@@ -1,545 +1,579
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 tech : INTEGER := inferred;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_data_by_buffer_size : INTEGER := 11;
29 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
32
33
33 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
34 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
35 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
36 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
37 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
38
39
39 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
40
41
41 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0');
42
43
44 DEBUG_FORCE_DATA_DMA : INTEGER := 0
45
43 );
46 );
44 PORT (
47 PORT (
45 clk : IN STD_LOGIC;
48 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
49 rstn : IN STD_LOGIC;
47 -- SAMPLE
50 -- SAMPLE
48 sample_B : IN Samples(2 DOWNTO 0);
51 sample_B : IN Samples(2 DOWNTO 0);
49 sample_E : IN Samples(4 DOWNTO 0);
52 sample_E : IN Samples(4 DOWNTO 0);
50 sample_val : IN STD_LOGIC;
53 sample_val : IN STD_LOGIC;
51 -- APB
54 -- APB
52 apbi : IN apb_slv_in_type;
55 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
56 apbo : OUT apb_slv_out_type;
54 -- AHB
57 -- AHB
55 ahbi : IN AHB_Mst_In_Type;
58 ahbi : IN AHB_Mst_In_Type;
56 ahbo : OUT AHB_Mst_Out_Type;
59 ahbo : OUT AHB_Mst_Out_Type;
57 -- TIME
60 -- TIME
58 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
61 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
62 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 --
63 --
61 data_shaping_BW : OUT STD_LOGIC;
64 data_shaping_BW : OUT STD_LOGIC;
62 --
65 --
63 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
64 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
67 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
65 );
68 );
66 END lpp_lfr;
69 END lpp_lfr;
67
70
68 ARCHITECTURE beh OF lpp_lfr IS
71 ARCHITECTURE beh OF lpp_lfr IS
69 SIGNAL sample_s : Samples(7 DOWNTO 0);
72 SIGNAL sample_s : Samples(7 DOWNTO 0);
70 --
73 --
71 SIGNAL data_shaping_SP0 : STD_LOGIC;
74 SIGNAL data_shaping_SP0 : STD_LOGIC;
72 SIGNAL data_shaping_SP1 : STD_LOGIC;
75 SIGNAL data_shaping_SP1 : STD_LOGIC;
73 SIGNAL data_shaping_R0 : STD_LOGIC;
76 SIGNAL data_shaping_R0 : STD_LOGIC;
74 SIGNAL data_shaping_R1 : STD_LOGIC;
77 SIGNAL data_shaping_R1 : STD_LOGIC;
75 SIGNAL data_shaping_R2 : STD_LOGIC;
78 SIGNAL data_shaping_R2 : STD_LOGIC;
76 --
79 --
77 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
78 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
81 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
79 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
82 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
80 --
83 --
81 SIGNAL sample_f0_val : STD_LOGIC;
84 SIGNAL sample_f0_val : STD_LOGIC;
82 SIGNAL sample_f1_val : STD_LOGIC;
85 SIGNAL sample_f1_val : STD_LOGIC;
83 SIGNAL sample_f2_val : STD_LOGIC;
86 SIGNAL sample_f2_val : STD_LOGIC;
84 SIGNAL sample_f3_val : STD_LOGIC;
87 SIGNAL sample_f3_val : STD_LOGIC;
85 --
88 --
86 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
89 SIGNAL sample_f_val : STD_LOGIC_VECTOR(3 DOWNTO 0);
87 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
90 SIGNAL sample_f_data : STD_LOGIC_VECTOR((6*16)*4-1 DOWNTO 0);
88 --
91 --
89 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
90 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
91 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
94 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
92 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
93 --
96 --
94 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
95 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
98 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
99 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
97
100
98 -- SM
101 -- SM
99 SIGNAL ready_matrix_f0 : STD_LOGIC;
102 SIGNAL ready_matrix_f0 : STD_LOGIC;
100 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
103 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
101 SIGNAL ready_matrix_f1 : STD_LOGIC;
104 SIGNAL ready_matrix_f1 : STD_LOGIC;
102 SIGNAL ready_matrix_f2 : STD_LOGIC;
105 SIGNAL ready_matrix_f2 : STD_LOGIC;
103 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
106 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
104 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
107 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
105 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
108 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
106 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
109 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
107 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
113 SIGNAL length_matrix_f0 : STD_LOGIC_VECTOR(25 DOWNTO 0);
111 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
114 SIGNAL length_matrix_f1 : STD_LOGIC_VECTOR(25 DOWNTO 0);
112 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
115 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
113
116
114 -- WFP
117 -- WFP
115 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
121 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
123 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121
124
122 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
125 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
123 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
126 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
124 SIGNAL enable_f0 : STD_LOGIC;
127 SIGNAL enable_f0 : STD_LOGIC;
125 SIGNAL enable_f1 : STD_LOGIC;
128 SIGNAL enable_f1 : STD_LOGIC;
126 SIGNAL enable_f2 : STD_LOGIC;
129 SIGNAL enable_f2 : STD_LOGIC;
127 SIGNAL enable_f3 : STD_LOGIC;
130 SIGNAL enable_f3 : STD_LOGIC;
128 SIGNAL burst_f0 : STD_LOGIC;
131 SIGNAL burst_f0 : STD_LOGIC;
129 SIGNAL burst_f1 : STD_LOGIC;
132 SIGNAL burst_f1 : STD_LOGIC;
130 SIGNAL burst_f2 : STD_LOGIC;
133 SIGNAL burst_f2 : STD_LOGIC;
131
134
132 --SIGNAL run : STD_LOGIC;
135 --SIGNAL run : STD_LOGIC;
133 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
136 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
134
137
135 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
136 --
139 --
137 -----------------------------------------------------------------------------
140 -----------------------------------------------------------------------------
138 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 -- SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
142 -- SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
140 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
143 -- SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
141 --f1
144 --f1
142 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
145 -- SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
146 -- SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
144 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
147 -- SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
145 --f2
148 --f2
146 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 -- SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
150 -- SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
148 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
151 -- SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
149 --f3
152 --f3
150 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 -- SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
154 -- SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
152 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
155 -- SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
153
156
154 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
158 SIGNAL wfp_addr_buffer : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
156 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
159 SIGNAL wfp_length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0);
157 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL wfp_ready_buffer : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
161 SIGNAL wfp_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
159 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL wfp_error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
161 -- DMA RR
164 -- DMA RR
162 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
163 -- SIGNAL dma_sel_valid : STD_LOGIC;
166 -- SIGNAL dma_sel_valid : STD_LOGIC;
164 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 -- SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 -- SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 -- SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
170 -- SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
168
171
169 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
172 -- SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
173 -- SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
171
174
172 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
173 -- DMA_REG
176 -- DMA_REG
174 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
175 -- SIGNAL ongoing_reg : STD_LOGIC;
178 -- SIGNAL ongoing_reg : STD_LOGIC;
176 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 -- SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 -- SIGNAL dma_send_reg : STD_LOGIC;
180 -- SIGNAL dma_send_reg : STD_LOGIC;
178 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
181 -- SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
179 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 -- SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 -- SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
184
182
185
183 -----------------------------------------------------------------------------
186 -----------------------------------------------------------------------------
184 -- DMA
187 -- DMA
185 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
186 -- SIGNAL dma_send : STD_LOGIC;
189 -- SIGNAL dma_send : STD_LOGIC;
187 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
190 -- SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
188 -- SIGNAL dma_done : STD_LOGIC;
191 -- SIGNAL dma_done : STD_LOGIC;
189 -- SIGNAL dma_ren : STD_LOGIC;
192 -- SIGNAL dma_ren : STD_LOGIC;
190 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 -- SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
194 -- SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 -- SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
193
196
194 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
195 -- MS
198 -- MS
196 -----------------------------------------------------------------------------
199 -----------------------------------------------------------------------------
197
200
198 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 -- SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 -- SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 -- SIGNAL data_ms_valid : STD_LOGIC;
203 -- SIGNAL data_ms_valid : STD_LOGIC;
201 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
204 -- SIGNAL data_ms_valid_burst : STD_LOGIC;
202 -- SIGNAL data_ms_ren : STD_LOGIC;
205 -- SIGNAL data_ms_ren : STD_LOGIC;
203 -- SIGNAL data_ms_done : STD_LOGIC;
206 -- SIGNAL data_ms_done : STD_LOGIC;
204 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
207 -- SIGNAL dma_ms_ongoing : STD_LOGIC;
205
208
206 -- SIGNAL run_ms : STD_LOGIC;
209 -- SIGNAL run_ms : STD_LOGIC;
207 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
210 -- SIGNAL ms_softandhard_rstn : STD_LOGIC;
208
211
209 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
210 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
213 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
214 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
212 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
215 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
213
216
214
217
215 SIGNAL error_buffer_full : STD_LOGIC;
218 SIGNAL error_buffer_full : STD_LOGIC;
216 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
219 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
217
220
218 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 -- SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
219 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 -- SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
220
223
221 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
222 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
226 SIGNAL dma_fifo_data : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
227 SIGNAL dma_fifo_data_forced_gen : STD_LOGIC_VECTOR(32-1 DOWNTO 0); --21-04-2015
228 SIGNAL dma_fifo_data_forced : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
229 SIGNAL dma_fifo_data_debug : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --21-04-2015
224 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
230 SIGNAL dma_fifo_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
231 SIGNAL dma_buffer_new : STD_LOGIC_VECTOR(4 DOWNTO 0);
226 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
232 SIGNAL dma_buffer_addr : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
227 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
233 SIGNAL dma_buffer_length : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
228 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
234 SIGNAL dma_buffer_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
229 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
235 SIGNAL dma_buffer_full_err : STD_LOGIC_VECTOR(4 DOWNTO 0);
230 SIGNAL dma_grant_error : STD_LOGIC;
236 SIGNAL dma_grant_error : STD_LOGIC;
231
237
232 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
238 SIGNAL apb_reg_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
233 -----------------------------------------------------------------------------
239 -----------------------------------------------------------------------------
234 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
240 SIGNAL sample_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
241 SIGNAL sample_f0_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
242 SIGNAL sample_f1_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
237 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
243 SIGNAL sample_f2_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
244 SIGNAL sample_f3_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
239
245
240 BEGIN
246 BEGIN
241
247
242 debug_vector <= apb_reg_debug_vector;
248 --apb_reg_debug_vector;
243 -----------------------------------------------------------------------------
249 -----------------------------------------------------------------------------
244
250
245 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
251 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
246 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
252 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
247 sample_time <= coarse_time & fine_time;
253 sample_time <= coarse_time & fine_time;
248
254
249 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
255 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
250 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
256 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
251 --END GENERATE all_channel;
257 --END GENERATE all_channel;
252
258
253 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
254 lpp_lfr_filter_1 : lpp_lfr_filter
260 lpp_lfr_filter_1 : lpp_lfr_filter
255 GENERIC MAP (
261 GENERIC MAP (
256 Mem_use => Mem_use)
262 Mem_use => Mem_use)
257 PORT MAP (
263 PORT MAP (
258 sample => sample_s,
264 sample => sample_s,
259 sample_val => sample_val,
265 sample_val => sample_val,
260 sample_time => sample_time,
266 sample_time => sample_time,
261 clk => clk,
267 clk => clk,
262 rstn => rstn,
268 rstn => rstn,
263 data_shaping_SP0 => data_shaping_SP0,
269 data_shaping_SP0 => data_shaping_SP0,
264 data_shaping_SP1 => data_shaping_SP1,
270 data_shaping_SP1 => data_shaping_SP1,
265 data_shaping_R0 => data_shaping_R0,
271 data_shaping_R0 => data_shaping_R0,
266 data_shaping_R1 => data_shaping_R1,
272 data_shaping_R1 => data_shaping_R1,
267 data_shaping_R2 => data_shaping_R2,
273 data_shaping_R2 => data_shaping_R2,
268 sample_f0_val => sample_f0_val,
274 sample_f0_val => sample_f0_val,
269 sample_f1_val => sample_f1_val,
275 sample_f1_val => sample_f1_val,
270 sample_f2_val => sample_f2_val,
276 sample_f2_val => sample_f2_val,
271 sample_f3_val => sample_f3_val,
277 sample_f3_val => sample_f3_val,
272 sample_f0_wdata => sample_f0_data,
278 sample_f0_wdata => sample_f0_data,
273 sample_f1_wdata => sample_f1_data,
279 sample_f1_wdata => sample_f1_data,
274 sample_f2_wdata => sample_f2_data,
280 sample_f2_wdata => sample_f2_data,
275 sample_f3_wdata => sample_f3_data,
281 sample_f3_wdata => sample_f3_data,
276 sample_f0_time => sample_f0_time,
282 sample_f0_time => sample_f0_time,
277 sample_f1_time => sample_f1_time,
283 sample_f1_time => sample_f1_time,
278 sample_f2_time => sample_f2_time,
284 sample_f2_time => sample_f2_time,
279 sample_f3_time => sample_f3_time
285 sample_f3_time => sample_f3_time
280 );
286 );
281
287
282 -----------------------------------------------------------------------------
288 -----------------------------------------------------------------------------
283 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
289 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
284 GENERIC MAP (
290 GENERIC MAP (
285 nb_data_by_buffer_size => nb_data_by_buffer_size,
291 nb_data_by_buffer_size => nb_data_by_buffer_size,
286 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
292 -- nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
287 nb_snapshot_param_size => nb_snapshot_param_size,
293 nb_snapshot_param_size => nb_snapshot_param_size,
288 delta_vector_size => delta_vector_size,
294 delta_vector_size => delta_vector_size,
289 delta_vector_size_f0_2 => delta_vector_size_f0_2,
295 delta_vector_size_f0_2 => delta_vector_size_f0_2,
290 pindex => pindex,
296 pindex => pindex,
291 paddr => paddr,
297 paddr => paddr,
292 pmask => pmask,
298 pmask => pmask,
293 pirq_ms => pirq_ms,
299 pirq_ms => pirq_ms,
294 pirq_wfp => pirq_wfp,
300 pirq_wfp => pirq_wfp,
295 top_lfr_version => top_lfr_version)
301 top_lfr_version => top_lfr_version)
296 PORT MAP (
302 PORT MAP (
297 HCLK => clk,
303 HCLK => clk,
298 HRESETn => rstn,
304 HRESETn => rstn,
299 apbi => apbi,
305 apbi => apbi,
300 apbo => apbo,
306 apbo => apbo,
301
307
302 run_ms => OPEN,--run_ms,
308 run_ms => OPEN,--run_ms,
303
309
304 ready_matrix_f0 => ready_matrix_f0,
310 ready_matrix_f0 => ready_matrix_f0,
305 ready_matrix_f1 => ready_matrix_f1,
311 ready_matrix_f1 => ready_matrix_f1,
306 ready_matrix_f2 => ready_matrix_f2,
312 ready_matrix_f2 => ready_matrix_f2,
307 error_buffer_full => error_buffer_full, -- TODO
313 error_buffer_full => error_buffer_full, -- TODO
308 error_input_fifo_write => error_input_fifo_write, -- TODO
314 error_input_fifo_write => error_input_fifo_write, -- TODO
309 status_ready_matrix_f0 => status_ready_matrix_f0,
315 status_ready_matrix_f0 => status_ready_matrix_f0,
310 status_ready_matrix_f1 => status_ready_matrix_f1,
316 status_ready_matrix_f1 => status_ready_matrix_f1,
311 status_ready_matrix_f2 => status_ready_matrix_f2,
317 status_ready_matrix_f2 => status_ready_matrix_f2,
312
318
313 matrix_time_f0 => matrix_time_f0,
319 matrix_time_f0 => matrix_time_f0,
314 matrix_time_f1 => matrix_time_f1,
320 matrix_time_f1 => matrix_time_f1,
315 matrix_time_f2 => matrix_time_f2,
321 matrix_time_f2 => matrix_time_f2,
316
322
317 addr_matrix_f0 => addr_matrix_f0,
323 addr_matrix_f0 => addr_matrix_f0,
318 addr_matrix_f1 => addr_matrix_f1,
324 addr_matrix_f1 => addr_matrix_f1,
319 addr_matrix_f2 => addr_matrix_f2,
325 addr_matrix_f2 => addr_matrix_f2,
320
326
321 length_matrix_f0 => length_matrix_f0,
327 length_matrix_f0 => length_matrix_f0,
322 length_matrix_f1 => length_matrix_f1,
328 length_matrix_f1 => length_matrix_f1,
323 length_matrix_f2 => length_matrix_f2,
329 length_matrix_f2 => length_matrix_f2,
324 -------------------------------------------------------------------------
330 -------------------------------------------------------------------------
325 --status_full => status_full, -- TODo
331 --status_full => status_full, -- TODo
326 --status_full_ack => status_full_ack, -- TODo
332 --status_full_ack => status_full_ack, -- TODo
327 --status_full_err => status_full_err, -- TODo
333 --status_full_err => status_full_err, -- TODo
328 status_new_err => status_new_err,
334 status_new_err => status_new_err,
329 data_shaping_BW => data_shaping_BW,
335 data_shaping_BW => data_shaping_BW,
330 data_shaping_SP0 => data_shaping_SP0,
336 data_shaping_SP0 => data_shaping_SP0,
331 data_shaping_SP1 => data_shaping_SP1,
337 data_shaping_SP1 => data_shaping_SP1,
332 data_shaping_R0 => data_shaping_R0,
338 data_shaping_R0 => data_shaping_R0,
333 data_shaping_R1 => data_shaping_R1,
339 data_shaping_R1 => data_shaping_R1,
334 data_shaping_R2 => data_shaping_R2,
340 data_shaping_R2 => data_shaping_R2,
335 delta_snapshot => delta_snapshot,
341 delta_snapshot => delta_snapshot,
336 delta_f0 => delta_f0,
342 delta_f0 => delta_f0,
337 delta_f0_2 => delta_f0_2,
343 delta_f0_2 => delta_f0_2,
338 delta_f1 => delta_f1,
344 delta_f1 => delta_f1,
339 delta_f2 => delta_f2,
345 delta_f2 => delta_f2,
340 nb_data_by_buffer => nb_data_by_buffer,
346 nb_data_by_buffer => nb_data_by_buffer,
341 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
347 -- nb_word_by_buffer => nb_word_by_buffer, -- TODO
342 nb_snapshot_param => nb_snapshot_param,
348 nb_snapshot_param => nb_snapshot_param,
343 enable_f0 => enable_f0,
349 enable_f0 => enable_f0,
344 enable_f1 => enable_f1,
350 enable_f1 => enable_f1,
345 enable_f2 => enable_f2,
351 enable_f2 => enable_f2,
346 enable_f3 => enable_f3,
352 enable_f3 => enable_f3,
347 burst_f0 => burst_f0,
353 burst_f0 => burst_f0,
348 burst_f1 => burst_f1,
354 burst_f1 => burst_f1,
349 burst_f2 => burst_f2,
355 burst_f2 => burst_f2,
350 run => OPEN, --run,
356 run => OPEN, --run,
351 start_date => start_date,
357 start_date => start_date,
352 -- debug_signal => debug_signal,
358 -- debug_signal => debug_signal,
353 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
359 wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
354 wfp_addr_buffer => wfp_addr_buffer,-- TODO
360 wfp_addr_buffer => wfp_addr_buffer,-- TODO
355 wfp_length_buffer => wfp_length_buffer,-- TODO
361 wfp_length_buffer => wfp_length_buffer,-- TODO
356
362
357 wfp_ready_buffer => wfp_ready_buffer,-- TODO
363 wfp_ready_buffer => wfp_ready_buffer,-- TODO
358 wfp_buffer_time => wfp_buffer_time,-- TODO
364 wfp_buffer_time => wfp_buffer_time,-- TODO
359 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
365 wfp_error_buffer_full => wfp_error_buffer_full, -- TODO
360 -------------------------------------------------------------------------
366 -------------------------------------------------------------------------
361 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
367 sample_f3_v => sample_f3_data(1*16-1 DOWNTO 0*16),
362 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
368 sample_f3_e1 => sample_f3_data(2*16-1 DOWNTO 1*16),
363 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
369 sample_f3_e2 => sample_f3_data(3*16-1 DOWNTO 2*16),
364 sample_f3_valid => sample_f3_val,
370 sample_f3_valid => sample_f3_val,
365 debug_vector => apb_reg_debug_vector
371 debug_vector => apb_reg_debug_vector
366 );
372 );
367
373
368 -----------------------------------------------------------------------------
374 -----------------------------------------------------------------------------
369 -----------------------------------------------------------------------------
375 -----------------------------------------------------------------------------
370 lpp_waveform_1 : lpp_waveform
376 lpp_waveform_1 : lpp_waveform
371 GENERIC MAP (
377 GENERIC MAP (
372 tech => inferred,
378 tech => tech,
373 data_size => 6*16,
379 data_size => 6*16,
374 nb_data_by_buffer_size => nb_data_by_buffer_size,
380 nb_data_by_buffer_size => nb_data_by_buffer_size,
375 nb_snapshot_param_size => nb_snapshot_param_size,
381 nb_snapshot_param_size => nb_snapshot_param_size,
376 delta_vector_size => delta_vector_size,
382 delta_vector_size => delta_vector_size,
377 delta_vector_size_f0_2 => delta_vector_size_f0_2
383 delta_vector_size_f0_2 => delta_vector_size_f0_2
378 )
384 )
379 PORT MAP (
385 PORT MAP (
380 clk => clk,
386 clk => clk,
381 rstn => rstn,
387 rstn => rstn,
382
388
383 reg_run => '1',--run,
389 reg_run => '1',--run,
384 reg_start_date => start_date,
390 reg_start_date => start_date,
385 reg_delta_snapshot => delta_snapshot,
391 reg_delta_snapshot => delta_snapshot,
386 reg_delta_f0 => delta_f0,
392 reg_delta_f0 => delta_f0,
387 reg_delta_f0_2 => delta_f0_2,
393 reg_delta_f0_2 => delta_f0_2,
388 reg_delta_f1 => delta_f1,
394 reg_delta_f1 => delta_f1,
389 reg_delta_f2 => delta_f2,
395 reg_delta_f2 => delta_f2,
390
396
391 enable_f0 => enable_f0,
397 enable_f0 => enable_f0,
392 enable_f1 => enable_f1,
398 enable_f1 => enable_f1,
393 enable_f2 => enable_f2,
399 enable_f2 => enable_f2,
394 enable_f3 => enable_f3,
400 enable_f3 => enable_f3,
395 burst_f0 => burst_f0,
401 burst_f0 => burst_f0,
396 burst_f1 => burst_f1,
402 burst_f1 => burst_f1,
397 burst_f2 => burst_f2,
403 burst_f2 => burst_f2,
398
404
399 nb_data_by_buffer => nb_data_by_buffer,
405 nb_data_by_buffer => nb_data_by_buffer,
400 nb_snapshot_param => nb_snapshot_param,
406 nb_snapshot_param => nb_snapshot_param,
401 status_new_err => status_new_err,
407 status_new_err => status_new_err,
402
408
403 status_buffer_ready => wfp_status_buffer_ready,
409 status_buffer_ready => wfp_status_buffer_ready,
404 addr_buffer => wfp_addr_buffer,
410 addr_buffer => wfp_addr_buffer,
405 length_buffer => wfp_length_buffer,
411 length_buffer => wfp_length_buffer,
406 ready_buffer => wfp_ready_buffer,
412 ready_buffer => wfp_ready_buffer,
407 buffer_time => wfp_buffer_time,
413 buffer_time => wfp_buffer_time,
408 error_buffer_full => wfp_error_buffer_full,
414 error_buffer_full => wfp_error_buffer_full,
409
415
410 coarse_time => coarse_time,
416 coarse_time => coarse_time,
411 -- fine_time => fine_time,
417 -- fine_time => fine_time,
412
418
413 --f0
419 --f0
414 data_f0_in_valid => sample_f0_val,
420 data_f0_in_valid => sample_f0_val,
415 data_f0_in => sample_f0_data,
421 data_f0_in => sample_f0_data,
416 data_f0_time => sample_f0_time,
422 data_f0_time => sample_f0_time,
417 --f1
423 --f1
418 data_f1_in_valid => sample_f1_val,
424 data_f1_in_valid => sample_f1_val,
419 data_f1_in => sample_f1_data,
425 data_f1_in => sample_f1_data,
420 data_f1_time => sample_f1_time,
426 data_f1_time => sample_f1_time,
421 --f2
427 --f2
422 data_f2_in_valid => sample_f2_val,
428 data_f2_in_valid => sample_f2_val,
423 data_f2_in => sample_f2_data,
429 data_f2_in => sample_f2_data,
424 data_f2_time => sample_f2_time,
430 data_f2_time => sample_f2_time,
425 --f3
431 --f3
426 data_f3_in_valid => sample_f3_val,
432 data_f3_in_valid => sample_f3_val,
427 data_f3_in => sample_f3_data,
433 data_f3_in => sample_f3_data,
428 data_f3_time => sample_f3_time,
434 data_f3_time => sample_f3_time,
429 -- OUTPUT -- DMA interface
435 -- OUTPUT -- DMA interface
430
436
431 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
437 dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
432 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
438 dma_fifo_data => dma_fifo_data(32*4-1 DOWNTO 0),
433 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
439 dma_fifo_ren => dma_fifo_ren(3 DOWNTO 0),
434 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
440 dma_buffer_new => dma_buffer_new(3 DOWNTO 0),
435 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
441 dma_buffer_addr => dma_buffer_addr(32*4-1 DOWNTO 0),
436 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
442 dma_buffer_length => dma_buffer_length(26*4-1 DOWNTO 0),
437 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
443 dma_buffer_full => dma_buffer_full(3 DOWNTO 0),
438 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
444 dma_buffer_full_err => dma_buffer_full_err(3 DOWNTO 0)
439
445
440 );
446 );
441
447
442 -----------------------------------------------------------------------------
448 -----------------------------------------------------------------------------
443 -- Matrix Spectral
449 -- Matrix Spectral
444 -----------------------------------------------------------------------------
450 -----------------------------------------------------------------------------
445 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
451 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
446 NOT(sample_f0_val) & NOT(sample_f0_val);
452 NOT(sample_f0_val) & NOT(sample_f0_val);
447 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
453 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
448 NOT(sample_f1_val) & NOT(sample_f1_val);
454 NOT(sample_f1_val) & NOT(sample_f1_val);
449 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
455 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
450 NOT(sample_f2_val) & NOT(sample_f2_val);
456 NOT(sample_f2_val) & NOT(sample_f2_val);
451
457
458
452 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
459 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
453 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
460 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
454 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
461 sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
455
462
456 -------------------------------------------------------------------------------
463 -------------------------------------------------------------------------------
457
464
458 --ms_softandhard_rstn <= rstn AND run_ms AND run;
465 --ms_softandhard_rstn <= rstn AND run_ms AND run;
459
466
460 -----------------------------------------------------------------------------
467 -----------------------------------------------------------------------------
461 lpp_lfr_ms_1 : lpp_lfr_ms
468 lpp_lfr_ms_1 : lpp_lfr_ms
462 GENERIC MAP (
469 GENERIC MAP (
463 Mem_use => Mem_use)
470 Mem_use => Mem_use)
464 PORT MAP (
471 PORT MAP (
465 clk => clk,
472 clk => clk,
466 --rstn => ms_softandhard_rstn, --rstn,
473 --rstn => ms_softandhard_rstn, --rstn,
467 rstn => rstn,
474 rstn => rstn,
468
475
469 run => '1',--run_ms,
476 run => '1',--run_ms,
470
477
471 start_date => start_date,
478 start_date => start_date,
472
479
473 coarse_time => coarse_time,
480 coarse_time => coarse_time,
474
481
475 sample_f0_wen => sample_f0_wen,
482 sample_f0_wen => sample_f0_wen,
476 sample_f0_wdata => sample_f0_wdata,
483 sample_f0_wdata => sample_f0_wdata,
477 sample_f0_time => sample_f0_time,
484 sample_f0_time => sample_f0_time,
478 sample_f1_wen => sample_f1_wen,
485 sample_f1_wen => sample_f1_wen,
479 sample_f1_wdata => sample_f1_wdata,
486 sample_f1_wdata => sample_f1_wdata,
480 sample_f1_time => sample_f1_time,
487 sample_f1_time => sample_f1_time,
481 sample_f2_wen => sample_f2_wen,
488 sample_f2_wen => sample_f2_wen,
482 sample_f2_wdata => sample_f2_wdata,
489 sample_f2_wdata => sample_f2_wdata,
483 sample_f2_time => sample_f2_time,
490 sample_f2_time => sample_f2_time,
484
491
485 --DMA
492 --DMA
486 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
493 dma_fifo_burst_valid => dma_fifo_burst_valid(4), -- OUT
487 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
494 dma_fifo_data => dma_fifo_data((4+1)*32-1 DOWNTO 4*32), -- OUT
488 dma_fifo_ren => dma_fifo_ren(4), -- IN
495 dma_fifo_ren => dma_fifo_ren(4), -- IN
489 dma_buffer_new => dma_buffer_new(4), -- OUT
496 dma_buffer_new => dma_buffer_new(4), -- OUT
490 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
497 dma_buffer_addr => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32), -- OUT
491 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
498 dma_buffer_length => dma_buffer_length((4+1)*26-1 DOWNTO 4*26), -- OUT
492 dma_buffer_full => dma_buffer_full(4), -- IN
499 dma_buffer_full => dma_buffer_full(4), -- IN
493 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
500 dma_buffer_full_err => dma_buffer_full_err(4), -- IN
494
501
495
502
496
503
497 --REG
504 --REG
498 ready_matrix_f0 => ready_matrix_f0,
505 ready_matrix_f0 => ready_matrix_f0,
499 ready_matrix_f1 => ready_matrix_f1,
506 ready_matrix_f1 => ready_matrix_f1,
500 ready_matrix_f2 => ready_matrix_f2,
507 ready_matrix_f2 => ready_matrix_f2,
501 error_buffer_full => error_buffer_full,
508 error_buffer_full => error_buffer_full,
502 error_input_fifo_write => error_input_fifo_write,
509 error_input_fifo_write => error_input_fifo_write,
503
510
504 status_ready_matrix_f0 => status_ready_matrix_f0,
511 status_ready_matrix_f0 => status_ready_matrix_f0,
505 status_ready_matrix_f1 => status_ready_matrix_f1,
512 status_ready_matrix_f1 => status_ready_matrix_f1,
506 status_ready_matrix_f2 => status_ready_matrix_f2,
513 status_ready_matrix_f2 => status_ready_matrix_f2,
507 addr_matrix_f0 => addr_matrix_f0,
514 addr_matrix_f0 => addr_matrix_f0,
508 addr_matrix_f1 => addr_matrix_f1,
515 addr_matrix_f1 => addr_matrix_f1,
509 addr_matrix_f2 => addr_matrix_f2,
516 addr_matrix_f2 => addr_matrix_f2,
510
517
511 length_matrix_f0 => length_matrix_f0,
518 length_matrix_f0 => length_matrix_f0,
512 length_matrix_f1 => length_matrix_f1,
519 length_matrix_f1 => length_matrix_f1,
513 length_matrix_f2 => length_matrix_f2,
520 length_matrix_f2 => length_matrix_f2,
514
521
515 matrix_time_f0 => matrix_time_f0,
522 matrix_time_f0 => matrix_time_f0,
516 matrix_time_f1 => matrix_time_f1,
523 matrix_time_f1 => matrix_time_f1,
517 matrix_time_f2 => matrix_time_f2,
524 matrix_time_f2 => matrix_time_f2,
518
525
519 debug_vector => debug_vector_ms);
526 debug_vector => debug_vector_ms);
520
527
521 -----------------------------------------------------------------------------
528 -----------------------------------------------------------------------------
522 --run_dma <= run_ms OR run;
529 PROCESS (clk, rstn)
530 BEGIN
531 IF rstn = '0' THEN
532 dma_fifo_data_forced_gen <= X"00040003";
533 ELSIF clk'event AND clk = '1' THEN
534 IF dma_fifo_ren(0) = '0' THEN
535 CASE dma_fifo_data_forced_gen IS
536 WHEN X"00040003" => dma_fifo_data_forced_gen <= X"00050002";
537 WHEN X"00050002" => dma_fifo_data_forced_gen <= X"00060001";
538 WHEN X"00060001" => dma_fifo_data_forced_gen <= X"00040003";
539 WHEN OTHERS => NULL;
540 END CASE;
541 END IF;
542 END IF;
543 END PROCESS;
544
545 dma_fifo_data_forced(32 * 1 -1 DOWNTO 32 * 0) <= dma_fifo_data_forced_gen;
546 dma_fifo_data_forced(32 * 2 -1 DOWNTO 32 * 1) <= X"A0000100";
547 dma_fifo_data_forced(32 * 3 -1 DOWNTO 32 * 2) <= X"08001000";
548 dma_fifo_data_forced(32 * 4 -1 DOWNTO 32 * 3) <= X"80007000";
549 dma_fifo_data_forced(32 * 5 -1 DOWNTO 32 * 4) <= X"0A000B00";
550
551 dma_fifo_data_debug <= dma_fifo_data WHEN DEBUG_FORCE_DATA_DMA = 0 ELSE dma_fifo_data_forced;
523
552
524 DMA_SubSystem_1 : DMA_SubSystem
553 DMA_SubSystem_1 : DMA_SubSystem
525 GENERIC MAP (
554 GENERIC MAP (
526 hindex => hindex)
555 hindex => hindex,
556 CUSTOM_DMA => 1)
527 PORT MAP (
557 PORT MAP (
528 clk => clk,
558 clk => clk,
529 rstn => rstn,
559 rstn => rstn,
530 run => '1',--run_dma,
560 run => '1',--run_dma,
531 ahbi => ahbi,
561 ahbi => ahbi,
532 ahbo => ahbo,
562 ahbo => ahbo,
533
563
534 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
564 fifo_burst_valid => dma_fifo_burst_valid, --fifo_burst_valid,
535 fifo_data => dma_fifo_data, --fifo_data,
565 fifo_data => dma_fifo_data_debug, --fifo_data,
536 fifo_ren => dma_fifo_ren, --fifo_ren,
566 fifo_ren => dma_fifo_ren, --fifo_ren,
537
567
538 buffer_new => dma_buffer_new, --buffer_new,
568 buffer_new => dma_buffer_new, --buffer_new,
539 buffer_addr => dma_buffer_addr, --buffer_addr,
569 buffer_addr => dma_buffer_addr, --buffer_addr,
540 buffer_length => dma_buffer_length, --buffer_length,
570 buffer_length => dma_buffer_length, --buffer_length,
541 buffer_full => dma_buffer_full, --buffer_full,
571 buffer_full => dma_buffer_full, --buffer_full,
542 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
572 buffer_full_err => dma_buffer_full_err, --buffer_full_err,
543 grant_error => dma_grant_error); --grant_error);
573 grant_error => dma_grant_error,
574 debug_vector => debug_vector(8 DOWNTO 0)
575 ); --grant_error);
544
576
577
578
545 END beh;
579 END beh;
Show file before | Show file after | Hide comments
@@ -1,403 +1,405
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER);
72 Mem_use : INTEGER);
73 PORT (
73 PORT (
74 clk : IN STD_LOGIC;
74 clk : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
75 rstn : IN STD_LOGIC;
76 run : IN STD_LOGIC;
76 run : IN STD_LOGIC;
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
77 start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
79 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
80 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
81 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
81 sample_f0_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
84 sample_f1_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
85 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
86 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
87 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
87 sample_f2_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 dma_fifo_burst_valid : OUT STD_LOGIC;
88 dma_fifo_burst_valid : OUT STD_LOGIC;
89 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_fifo_ren : IN STD_LOGIC;
90 dma_fifo_ren : IN STD_LOGIC;
91 dma_buffer_new : OUT STD_LOGIC;
91 dma_buffer_new : OUT STD_LOGIC;
92 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
93 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
94 dma_buffer_full : IN STD_LOGIC;
94 dma_buffer_full : IN STD_LOGIC;
95 dma_buffer_full_err : IN STD_LOGIC;
95 dma_buffer_full_err : IN STD_LOGIC;
96 ready_matrix_f0 : OUT STD_LOGIC;
96 ready_matrix_f0 : OUT STD_LOGIC;
97 ready_matrix_f1 : OUT STD_LOGIC;
97 ready_matrix_f1 : OUT STD_LOGIC;
98 ready_matrix_f2 : OUT STD_LOGIC;
98 ready_matrix_f2 : OUT STD_LOGIC;
99 error_buffer_full : OUT STD_LOGIC;
99 error_buffer_full : OUT STD_LOGIC;
100 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
100 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
101 status_ready_matrix_f0 : IN STD_LOGIC;
101 status_ready_matrix_f0 : IN STD_LOGIC;
102 status_ready_matrix_f1 : IN STD_LOGIC;
102 status_ready_matrix_f1 : IN STD_LOGIC;
103 status_ready_matrix_f2 : IN STD_LOGIC;
103 status_ready_matrix_f2 : IN STD_LOGIC;
104 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
104 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
107 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
108 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
109 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
109 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
110 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
110 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
111 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
112 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
112 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
113 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
113 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
114 END COMPONENT;
114 END COMPONENT;
115
115
116 COMPONENT lpp_lfr_ms_fsmdma
116 COMPONENT lpp_lfr_ms_fsmdma
117 PORT (
117 PORT (
118 clk : IN STD_ULOGIC;
118 clk : IN STD_ULOGIC;
119 rstn : IN STD_ULOGIC;
119 rstn : IN STD_ULOGIC;
120 run : IN STD_LOGIC;
120 run : IN STD_LOGIC;
121 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
121 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
122 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
122 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
123 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
123 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
124 fifo_empty : IN STD_LOGIC;
124 fifo_empty : IN STD_LOGIC;
125 fifo_empty_threshold : IN STD_LOGIC;
125 fifo_empty_threshold : IN STD_LOGIC;
126 fifo_ren : OUT STD_LOGIC;
126 fifo_ren : OUT STD_LOGIC;
127 dma_fifo_valid_burst : OUT STD_LOGIC;
127 dma_fifo_valid_burst : OUT STD_LOGIC;
128 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 dma_fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 dma_fifo_ren : IN STD_LOGIC;
129 dma_fifo_ren : IN STD_LOGIC;
130 dma_buffer_new : OUT STD_LOGIC;
130 dma_buffer_new : OUT STD_LOGIC;
131 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
131 dma_buffer_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
132 dma_buffer_length : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
133 dma_buffer_full : IN STD_LOGIC;
133 dma_buffer_full : IN STD_LOGIC;
134 dma_buffer_full_err : IN STD_LOGIC;
134 dma_buffer_full_err : IN STD_LOGIC;
135 status_ready_matrix_f0 : IN STD_LOGIC;
135 status_ready_matrix_f0 : IN STD_LOGIC;
136 status_ready_matrix_f1 : IN STD_LOGIC;
136 status_ready_matrix_f1 : IN STD_LOGIC;
137 status_ready_matrix_f2 : IN STD_LOGIC;
137 status_ready_matrix_f2 : IN STD_LOGIC;
138 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
141 length_matrix_f0 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
142 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
142 length_matrix_f1 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
143 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
143 length_matrix_f2 : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
144 ready_matrix_f0 : OUT STD_LOGIC;
144 ready_matrix_f0 : OUT STD_LOGIC;
145 ready_matrix_f1 : OUT STD_LOGIC;
145 ready_matrix_f1 : OUT STD_LOGIC;
146 ready_matrix_f2 : OUT STD_LOGIC;
146 ready_matrix_f2 : OUT STD_LOGIC;
147 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
147 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
148 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
148 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
149 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
149 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
150 error_buffer_full : OUT STD_LOGIC);
150 error_buffer_full : OUT STD_LOGIC);
151 END COMPONENT;
151 END COMPONENT;
152
152
153 COMPONENT lpp_lfr_ms_FFT
153 COMPONENT lpp_lfr_ms_FFT
154 PORT (
154 PORT (
155 clk : IN STD_LOGIC;
155 clk : IN STD_LOGIC;
156 rstn : IN STD_LOGIC;
156 rstn : IN STD_LOGIC;
157 sample_valid : IN STD_LOGIC;
157 sample_valid : IN STD_LOGIC;
158 fft_read : IN STD_LOGIC;
158 fft_read : IN STD_LOGIC;
159 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
159 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
160 sample_load : OUT STD_LOGIC;
160 sample_load : OUT STD_LOGIC;
161 fft_pong : OUT STD_LOGIC;
161 fft_pong : OUT STD_LOGIC;
162 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
162 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
163 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
163 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
164 fft_data_valid : OUT STD_LOGIC;
164 fft_data_valid : OUT STD_LOGIC;
165 fft_ready : OUT STD_LOGIC);
165 fft_ready : OUT STD_LOGIC);
166 END COMPONENT;
166 END COMPONENT;
167
167
168 COMPONENT lpp_lfr_filter
168 COMPONENT lpp_lfr_filter
169 GENERIC (
169 GENERIC (
170 Mem_use : INTEGER);
170 Mem_use : INTEGER);
171 PORT (
171 PORT (
172 sample : IN Samples(7 DOWNTO 0);
172 sample : IN Samples(7 DOWNTO 0);
173 sample_val : IN STD_LOGIC;
173 sample_val : IN STD_LOGIC;
174 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
174 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
175 clk : IN STD_LOGIC;
175 clk : IN STD_LOGIC;
176 rstn : IN STD_LOGIC;
176 rstn : IN STD_LOGIC;
177 data_shaping_SP0 : IN STD_LOGIC;
177 data_shaping_SP0 : IN STD_LOGIC;
178 data_shaping_SP1 : IN STD_LOGIC;
178 data_shaping_SP1 : IN STD_LOGIC;
179 data_shaping_R0 : IN STD_LOGIC;
179 data_shaping_R0 : IN STD_LOGIC;
180 data_shaping_R1 : IN STD_LOGIC;
180 data_shaping_R1 : IN STD_LOGIC;
181 data_shaping_R2 : IN STD_LOGIC;
181 data_shaping_R2 : IN STD_LOGIC;
182 sample_f0_val : OUT STD_LOGIC;
182 sample_f0_val : OUT STD_LOGIC;
183 sample_f1_val : OUT STD_LOGIC;
183 sample_f1_val : OUT STD_LOGIC;
184 sample_f2_val : OUT STD_LOGIC;
184 sample_f2_val : OUT STD_LOGIC;
185 sample_f3_val : OUT STD_LOGIC;
185 sample_f3_val : OUT STD_LOGIC;
186 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
186 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
187 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
187 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
188 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
188 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
189 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
189 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
190 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
190 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
191 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
191 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
192 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
192 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
193 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
193 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
194 );
194 );
195 END COMPONENT;
195 END COMPONENT;
196
196
197 COMPONENT lpp_lfr
197 COMPONENT lpp_lfr
198 GENERIC (
198 GENERIC (
199 Mem_use : INTEGER;
199 Mem_use : INTEGER;
200 tech : INTEGER;
200 nb_data_by_buffer_size : INTEGER;
201 nb_data_by_buffer_size : INTEGER;
201 -- nb_word_by_buffer_size : INTEGER;
202 -- nb_word_by_buffer_size : INTEGER;
202 nb_snapshot_param_size : INTEGER;
203 nb_snapshot_param_size : INTEGER;
203 delta_vector_size : INTEGER;
204 delta_vector_size : INTEGER;
204 delta_vector_size_f0_2 : INTEGER;
205 delta_vector_size_f0_2 : INTEGER;
205 pindex : INTEGER;
206 pindex : INTEGER;
206 paddr : INTEGER;
207 paddr : INTEGER;
207 pmask : INTEGER;
208 pmask : INTEGER;
208 pirq_ms : INTEGER;
209 pirq_ms : INTEGER;
209 pirq_wfp : INTEGER;
210 pirq_wfp : INTEGER;
210 hindex : INTEGER;
211 hindex : INTEGER;
211 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
212 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0);
213 DEBUG_FORCE_DATA_DMA : INTEGER
212 );
214 );
213 PORT (
215 PORT (
214 clk : IN STD_LOGIC;
216 clk : IN STD_LOGIC;
215 rstn : IN STD_LOGIC;
217 rstn : IN STD_LOGIC;
216 sample_B : IN Samples(2 DOWNTO 0);
218 sample_B : IN Samples(2 DOWNTO 0);
217 sample_E : IN Samples(4 DOWNTO 0);
219 sample_E : IN Samples(4 DOWNTO 0);
218 sample_val : IN STD_LOGIC;
220 sample_val : IN STD_LOGIC;
219 apbi : IN apb_slv_in_type;
221 apbi : IN apb_slv_in_type;
220 apbo : OUT apb_slv_out_type;
222 apbo : OUT apb_slv_out_type;
221 ahbi : IN AHB_Mst_In_Type;
223 ahbi : IN AHB_Mst_In_Type;
222 ahbo : OUT AHB_Mst_Out_Type;
224 ahbo : OUT AHB_Mst_Out_Type;
223 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
225 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
224 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
226 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
225 data_shaping_BW : OUT STD_LOGIC;
227 data_shaping_BW : OUT STD_LOGIC;
226 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
228 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
227 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
229 debug_vector_ms : OUT STD_LOGIC_VECTOR(11 DOWNTO 0)
228 );
230 );
229 END COMPONENT;
231 END COMPONENT;
230
232
231 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
232 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
234 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
233 -----------------------------------------------------------------------------
235 -----------------------------------------------------------------------------
234 COMPONENT lpp_lfr_WFP_nMS
236 COMPONENT lpp_lfr_WFP_nMS
235 GENERIC (
237 GENERIC (
236 Mem_use : INTEGER;
238 Mem_use : INTEGER;
237 nb_data_by_buffer_size : INTEGER;
239 nb_data_by_buffer_size : INTEGER;
238 nb_word_by_buffer_size : INTEGER;
240 nb_word_by_buffer_size : INTEGER;
239 nb_snapshot_param_size : INTEGER;
241 nb_snapshot_param_size : INTEGER;
240 delta_vector_size : INTEGER;
242 delta_vector_size : INTEGER;
241 delta_vector_size_f0_2 : INTEGER;
243 delta_vector_size_f0_2 : INTEGER;
242 pindex : INTEGER;
244 pindex : INTEGER;
243 paddr : INTEGER;
245 paddr : INTEGER;
244 pmask : INTEGER;
246 pmask : INTEGER;
245 pirq_ms : INTEGER;
247 pirq_ms : INTEGER;
246 pirq_wfp : INTEGER;
248 pirq_wfp : INTEGER;
247 hindex : INTEGER;
249 hindex : INTEGER;
248 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
250 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
249 PORT (
251 PORT (
250 clk : IN STD_LOGIC;
252 clk : IN STD_LOGIC;
251 rstn : IN STD_LOGIC;
253 rstn : IN STD_LOGIC;
252 sample_B : IN Samples(2 DOWNTO 0);
254 sample_B : IN Samples(2 DOWNTO 0);
253 sample_E : IN Samples(4 DOWNTO 0);
255 sample_E : IN Samples(4 DOWNTO 0);
254 sample_val : IN STD_LOGIC;
256 sample_val : IN STD_LOGIC;
255 apbi : IN apb_slv_in_type;
257 apbi : IN apb_slv_in_type;
256 apbo : OUT apb_slv_out_type;
258 apbo : OUT apb_slv_out_type;
257 ahbi : IN AHB_Mst_In_Type;
259 ahbi : IN AHB_Mst_In_Type;
258 ahbo : OUT AHB_Mst_Out_Type;
260 ahbo : OUT AHB_Mst_Out_Type;
259 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
261 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
260 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
262 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
261 data_shaping_BW : OUT STD_LOGIC;
263 data_shaping_BW : OUT STD_LOGIC;
262 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
264 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
263 END COMPONENT;
265 END COMPONENT;
264 -----------------------------------------------------------------------------
266 -----------------------------------------------------------------------------
265
267
266 COMPONENT lpp_lfr_apbreg
268 COMPONENT lpp_lfr_apbreg
267 GENERIC (
269 GENERIC (
268 nb_data_by_buffer_size : INTEGER;
270 nb_data_by_buffer_size : INTEGER;
269 nb_snapshot_param_size : INTEGER;
271 nb_snapshot_param_size : INTEGER;
270 delta_vector_size : INTEGER;
272 delta_vector_size : INTEGER;
271 delta_vector_size_f0_2 : INTEGER;
273 delta_vector_size_f0_2 : INTEGER;
272 pindex : INTEGER;
274 pindex : INTEGER;
273 paddr : INTEGER;
275 paddr : INTEGER;
274 pmask : INTEGER;
276 pmask : INTEGER;
275 pirq_ms : INTEGER;
277 pirq_ms : INTEGER;
276 pirq_wfp : INTEGER;
278 pirq_wfp : INTEGER;
277 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
279 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
278 PORT (
280 PORT (
279 HCLK : IN STD_ULOGIC;
281 HCLK : IN STD_ULOGIC;
280 HRESETn : IN STD_ULOGIC;
282 HRESETn : IN STD_ULOGIC;
281 apbi : IN apb_slv_in_type;
283 apbi : IN apb_slv_in_type;
282 apbo : OUT apb_slv_out_type;
284 apbo : OUT apb_slv_out_type;
283 run_ms : OUT STD_LOGIC;
285 run_ms : OUT STD_LOGIC;
284 ready_matrix_f0 : IN STD_LOGIC;
286 ready_matrix_f0 : IN STD_LOGIC;
285 ready_matrix_f1 : IN STD_LOGIC;
287 ready_matrix_f1 : IN STD_LOGIC;
286 ready_matrix_f2 : IN STD_LOGIC;
288 ready_matrix_f2 : IN STD_LOGIC;
287 error_buffer_full : IN STD_LOGIC;
289 error_buffer_full : IN STD_LOGIC;
288 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
290 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
289 status_ready_matrix_f0 : OUT STD_LOGIC;
291 status_ready_matrix_f0 : OUT STD_LOGIC;
290 status_ready_matrix_f1 : OUT STD_LOGIC;
292 status_ready_matrix_f1 : OUT STD_LOGIC;
291 status_ready_matrix_f2 : OUT STD_LOGIC;
293 status_ready_matrix_f2 : OUT STD_LOGIC;
292 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
294 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
293 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
295 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
294 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
296 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
295 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
297 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
296 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
298 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
297 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
299 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
298 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
300 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
299 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
301 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
300 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
302 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
301 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
303 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
302 data_shaping_BW : OUT STD_LOGIC;
304 data_shaping_BW : OUT STD_LOGIC;
303 data_shaping_SP0 : OUT STD_LOGIC;
305 data_shaping_SP0 : OUT STD_LOGIC;
304 data_shaping_SP1 : OUT STD_LOGIC;
306 data_shaping_SP1 : OUT STD_LOGIC;
305 data_shaping_R0 : OUT STD_LOGIC;
307 data_shaping_R0 : OUT STD_LOGIC;
306 data_shaping_R1 : OUT STD_LOGIC;
308 data_shaping_R1 : OUT STD_LOGIC;
307 data_shaping_R2 : OUT STD_LOGIC;
309 data_shaping_R2 : OUT STD_LOGIC;
308 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
310 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
309 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
311 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
310 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
312 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
311 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
313 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
312 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
314 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
313 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
315 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
314 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
316 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
315 enable_f0 : OUT STD_LOGIC;
317 enable_f0 : OUT STD_LOGIC;
316 enable_f1 : OUT STD_LOGIC;
318 enable_f1 : OUT STD_LOGIC;
317 enable_f2 : OUT STD_LOGIC;
319 enable_f2 : OUT STD_LOGIC;
318 enable_f3 : OUT STD_LOGIC;
320 enable_f3 : OUT STD_LOGIC;
319 burst_f0 : OUT STD_LOGIC;
321 burst_f0 : OUT STD_LOGIC;
320 burst_f1 : OUT STD_LOGIC;
322 burst_f1 : OUT STD_LOGIC;
321 burst_f2 : OUT STD_LOGIC;
323 burst_f2 : OUT STD_LOGIC;
322 run : OUT STD_LOGIC;
324 run : OUT STD_LOGIC;
323 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
325 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
324 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
326 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
325 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
327 wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
326 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
328 wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
327 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
330 wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
329 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
331 wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
330 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
332 sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
331 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
333 sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
332 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
334 sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
333 sample_f3_valid : IN STD_LOGIC;
335 sample_f3_valid : IN STD_LOGIC;
334 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
336 debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0));
335 END COMPONENT;
337 END COMPONENT;
336
338
337 COMPONENT lpp_top_ms
339 COMPONENT lpp_top_ms
338 GENERIC (
340 GENERIC (
339 Mem_use : INTEGER;
341 Mem_use : INTEGER;
340 nb_burst_available_size : INTEGER;
342 nb_burst_available_size : INTEGER;
341 nb_snapshot_param_size : INTEGER;
343 nb_snapshot_param_size : INTEGER;
342 delta_snapshot_size : INTEGER;
344 delta_snapshot_size : INTEGER;
343 delta_f2_f0_size : INTEGER;
345 delta_f2_f0_size : INTEGER;
344 delta_f2_f1_size : INTEGER;
346 delta_f2_f1_size : INTEGER;
345 pindex : INTEGER;
347 pindex : INTEGER;
346 paddr : INTEGER;
348 paddr : INTEGER;
347 pmask : INTEGER;
349 pmask : INTEGER;
348 pirq_ms : INTEGER;
350 pirq_ms : INTEGER;
349 pirq_wfp : INTEGER;
351 pirq_wfp : INTEGER;
350 hindex_wfp : INTEGER;
352 hindex_wfp : INTEGER;
351 hindex_ms : INTEGER);
353 hindex_ms : INTEGER);
352 PORT (
354 PORT (
353 clk : IN STD_LOGIC;
355 clk : IN STD_LOGIC;
354 rstn : IN STD_LOGIC;
356 rstn : IN STD_LOGIC;
355 sample_B : IN Samples14v(2 DOWNTO 0);
357 sample_B : IN Samples14v(2 DOWNTO 0);
356 sample_E : IN Samples14v(4 DOWNTO 0);
358 sample_E : IN Samples14v(4 DOWNTO 0);
357 sample_val : IN STD_LOGIC;
359 sample_val : IN STD_LOGIC;
358 apbi : IN apb_slv_in_type;
360 apbi : IN apb_slv_in_type;
359 apbo : OUT apb_slv_out_type;
361 apbo : OUT apb_slv_out_type;
360 ahbi_ms : IN AHB_Mst_In_Type;
362 ahbi_ms : IN AHB_Mst_In_Type;
361 ahbo_ms : OUT AHB_Mst_Out_Type;
363 ahbo_ms : OUT AHB_Mst_Out_Type;
362 data_shaping_BW : OUT STD_LOGIC;
364 data_shaping_BW : OUT STD_LOGIC;
363 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
365 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
364 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
366 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
365 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
367 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
366 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
368 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
367 );
369 );
368 END COMPONENT;
370 END COMPONENT;
369
371
370 COMPONENT lpp_apbreg_ms_pointer
372 COMPONENT lpp_apbreg_ms_pointer
371 PORT (
373 PORT (
372 clk : IN STD_LOGIC;
374 clk : IN STD_LOGIC;
373 rstn : IN STD_LOGIC;
375 rstn : IN STD_LOGIC;
374 run : IN STD_LOGIC;
376 run : IN STD_LOGIC;
375 reg0_status_ready_matrix : IN STD_LOGIC;
377 reg0_status_ready_matrix : IN STD_LOGIC;
376 reg0_ready_matrix : OUT STD_LOGIC;
378 reg0_ready_matrix : OUT STD_LOGIC;
377 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
379 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
378 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
380 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
379 reg1_status_ready_matrix : IN STD_LOGIC;
381 reg1_status_ready_matrix : IN STD_LOGIC;
380 reg1_ready_matrix : OUT STD_LOGIC;
382 reg1_ready_matrix : OUT STD_LOGIC;
381 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
383 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
382 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
384 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
383 ready_matrix : IN STD_LOGIC;
385 ready_matrix : IN STD_LOGIC;
384 status_ready_matrix : OUT STD_LOGIC;
386 status_ready_matrix : OUT STD_LOGIC;
385 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
387 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
386 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
388 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
387 END COMPONENT;
389 END COMPONENT;
388
390
389 COMPONENT lpp_lfr_ms_reg_head
391 COMPONENT lpp_lfr_ms_reg_head
390 PORT (
392 PORT (
391 clk : IN STD_LOGIC;
393 clk : IN STD_LOGIC;
392 rstn : IN STD_LOGIC;
394 rstn : IN STD_LOGIC;
393 in_wen : IN STD_LOGIC;
395 in_wen : IN STD_LOGIC;
394 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
396 in_data : IN STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
395 in_full : IN STD_LOGIC;
397 in_full : IN STD_LOGIC;
396 in_empty : IN STD_LOGIC;
398 in_empty : IN STD_LOGIC;
397 out_write_error : OUT STD_LOGIC;
399 out_write_error : OUT STD_LOGIC;
398 out_wen : OUT STD_LOGIC;
400 out_wen : OUT STD_LOGIC;
399 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
401 out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
400 out_full : OUT STD_LOGIC);
402 out_full : OUT STD_LOGIC);
401 END COMPONENT;
403 END COMPONENT;
402
404
403 END lpp_lfr_pkg; No newline at end of file
405 END lpp_lfr_pkg;
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