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register the data outputed by ADC_driver
pellion -
r595:eb603d70d051 simu_with_Leon3
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1 1 ################################################################################
2 2 # SDC WRITER VERSION "3.1";
3 3 # DESIGN "LFR_EQM";
4 4 # Timing constraints scenario: "Primary";
5 5 # DATE "Fri Apr 24 16:02:16 2015";
6 6 # VENDOR "Actel";
7 7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 9 ################################################################################
10 10
11 11
12 12 set sdc_version 1.7
13 13
14 14
15 15 ######## Clock Constraints ########
16 16
17 17 create_clock -name { clk50MHz } -period 20.000 -waveform { 0.000 10.000 } { clk50MHz }
18 18
19 19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20 20
21 21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22 22
23 23 #create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24 24
25 25 create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y }
26 26
27 27 create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y }
28 28
29 29
30 30
31 31 ######## Generated Clock Constraints ########
32 32
33 33
34 34
35 35 ######## Clock Source Latency Constraints #########
36 36
37 37
38 38
39 39 ######## Input Delay Constraints ########
40 40
41 41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
42 42 set_max_delay 30.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
43 43 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
44 44 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
45 45 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
46 46 set_min_delay 0.000 -from [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] \
47 47 data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] \
48 48 data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] \
49 49 data[4] data[5] data[6] data[7] data[8] data[9] }] -to [get_clocks {clk_25:Q}]
50 50
51 51 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 52 set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 53 set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54 54
55 55
56 56
57 57 ######## Output Delay Constraints ########
58 58
59 59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { data[0] data[10] data[11] data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
60 60 set_max_delay 10.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
61 61 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
62 62 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
63 63 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
64 64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { data[0] data[10] data[11] \
65 65 data[12] data[13] data[14] data[15] data[16] data[17] data[18] data[19] data[1] data[20] \
66 66 data[21] data[22] data[23] data[24] data[25] data[26] data[27] data[28] data[29] data[2] \
67 67 data[30] data[31] data[3] data[4] data[5] data[6] data[7] data[8] data[9] }]
68 68
69 69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { address[0] address[10] address[11] address[12] address[13] address[14] address[15] address[16] address[17] address[18] address[1] address[2] address[3] address[4] address[5] address[6] address[7] address[8] address[9] }]
70 70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
71 71 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
72 72 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
73 73 address[7] address[8] address[9] }]
74 74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { address[0] address[10] \
75 75 address[11] address[12] address[13] address[14] address[15] address[16] address[17] \
76 76 address[18] address[1] address[2] address[3] address[4] address[5] address[6] \
77 77 address[7] address[8] address[9] }]
78 78
79 79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
80 80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
81 81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_E1 nSRAM_E2 nSRAM_W }]
82 82
83 83 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_G }]
84 84 set_max_delay 30.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
85 85 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_G }]
86 86
87 87 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_MBE }]
88 88 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
89 89 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_MBE }]
90 90
91 91
92 92
93 93 ######## Delay Constraints ########
94 94
95 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
96 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
97 {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
95 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/rxclki_RNO:Y}]
98 96
99 set_max_delay 4.000 -from [get_ports { clk50MHz ADC_data spw2_sin spw2_din spw1_sin spw1_din \
100 nSRAM_BUSY data TAG2 TAG1 reset clk49_152MHz }] -to [get_clocks \
101 {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
97 set_max_delay 4.000 -from [get_ports { spw2_sin spw2_din spw1_sin spw1_din reset }] -to [get_clocks {spw_inputloop.1.spw_phy0/rxclki_RNO:Y}]
102 98
103 99
104 100
105 101 ######## Delay Constraints ########
106 102
107 103
108 104
109 105 ######## Multicycle Constraints ########
110 106
111 107
112 108
113 109 ######## False Path Constraints ########
114 110
115 111
116 112
117 113 ######## Output load Constraints ########
118 114
119 115
120 116
121 117 ######## Disable Timing Constraints #########
122 118
123 119
124 120
125 121 ######## Clock Uncertainty Constraints #########
126 122
127 123
128 124
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22
23 23 LIBRARY IEEE;
24 24 USE IEEE.STD_LOGIC_1164.ALL;
25 25 USE IEEE.NUMERIC_STD.ALL;
26 26
27 27 LIBRARY techmap;
28 28 USE techmap.gencomp.ALL;
29 29
30 30 LIBRARY lpp;
31 31 USE lpp.lpp_sim_pkg.ALL;
32 32 USE lpp.lpp_lfr_sim_pkg.ALL;
33 33 USE lpp.lpp_lfr_apbreg_pkg.ALL;
34 34 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
35 35 USE lpp.iir_filter.ALL;
36 36 USE lpp.FILTERcfg.ALL;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_waveform_pkg.ALL;
39 39 USE lpp.lpp_dma_pkg.ALL;
40 40 USE lpp.lpp_top_lfr_pkg.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL;
42 42 USE lpp.general_purpose.ALL;
43 43 --LIBRARY lpp;
44 44 USE lpp.lpp_ad_conv.ALL;
45 45 --USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
46 46 --USE lpp.lpp_lfr_apbreg_pkg.ALL;
47 47
48 48 --USE work.debug.ALL;
49 49
50 50 LIBRARY gaisler;
51 51 USE gaisler.libdcom.ALL;
52 52 USE gaisler.sim.ALL;
53 53 USE gaisler.memctrl.ALL;
54 54 USE gaisler.leon3.ALL;
55 55 USE gaisler.uart.ALL;
56 56 USE gaisler.misc.ALL;
57 57 USE gaisler.spacewire.ALL;
58 58
59 59 ENTITY TB IS
60 60
61 61 END TB;
62 62
63 63 ARCHITECTURE beh OF TB IS
64 64 CONSTANT sramfile : STRING := "prom.srec";
65 65 -- CONSTANT sramfile : STRING;
66 66
67 67 CONSTANT USE_ESA_MEMCTRL : INTEGER := 0;
68 68
69 69 COMPONENT LFR_EQM
70 70 GENERIC (
71 71 Mem_use : INTEGER;
72 72 USE_BOOTLOADER : INTEGER;
73 73 USE_ADCDRIVER : INTEGER;
74 74 tech : INTEGER;
75 75 tech_leon : INTEGER;
76 76 DEBUG_FORCE_DATA_DMA : INTEGER;
77 77 USE_DEBUG_VECTOR : INTEGER );
78 78 PORT (
79 79 clk50MHz : IN STD_ULOGIC;
80 80 clk49_152MHz : IN STD_ULOGIC;
81 81 reset : IN STD_ULOGIC;
82 82 --TAG1 : IN STD_ULOGIC;
83 83 --TAG3 : OUT STD_ULOGIC;
84 84 --TAG2 : IN STD_ULOGIC;
85 85 --TAG4 : OUT STD_ULOGIC;
86 86 TAG : INOUT STD_LOGIC_VECTOR(9 DOWNTO 1);
87 87 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
88 88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 89 nSRAM_MBE : INOUT STD_LOGIC;
90 90 nSRAM_E1 : OUT STD_LOGIC;
91 91 nSRAM_E2 : OUT STD_LOGIC;
92 92 nSRAM_W : OUT STD_LOGIC;
93 93 nSRAM_G : OUT STD_LOGIC;
94 94 nSRAM_BUSY : IN STD_LOGIC;
95 95 spw1_en : OUT STD_LOGIC;
96 96 spw1_din : IN STD_LOGIC;
97 97 spw1_sin : IN STD_LOGIC;
98 98 spw1_dout : OUT STD_LOGIC;
99 99 spw1_sout : OUT STD_LOGIC;
100 100 spw2_en : OUT STD_LOGIC;
101 101 spw2_din : IN STD_LOGIC;
102 102 spw2_sin : IN STD_LOGIC;
103 103 spw2_dout : OUT STD_LOGIC;
104 104 spw2_sout : OUT STD_LOGIC;
105 105 bias_fail_sw : OUT STD_LOGIC;
106 106 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
107 107 ADC_smpclk : OUT STD_LOGIC;
108 108 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
109 109 DAC_SDO : OUT STD_LOGIC;
110 110 DAC_SCK : OUT STD_LOGIC;
111 111 DAC_SYNC : OUT STD_LOGIC;
112 112 DAC_CAL_EN : OUT STD_LOGIC;
113 113 HK_smpclk : OUT STD_LOGIC;
114 114 ADC_OEB_bar_HK : OUT STD_LOGIC;
115 115 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0));
116 116 END COMPONENT;
117 117
118 118 SIGNAL clk50MHz : STD_ULOGIC := '0';
119 119 SIGNAL clk49_152MHz : STD_ULOGIC := '0';
120 120 SIGNAL reset : STD_ULOGIC;
121 121 SIGNAL TAG : STD_LOGIC_VECTOR(9 DOWNTO 1);
122 122 --SIGNAL TAG3 : STD_ULOGIC;
123 123 --SIGNAL TAG2 : STD_ULOGIC := '1';
124 124 --SIGNAL TAG4 : STD_ULOGIC;
125 125 SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0);
126 126 SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 127 SIGNAL nSRAM_MBE : STD_LOGIC;
128 128 SIGNAL nSRAM_E1 : STD_LOGIC;
129 129 SIGNAL nSRAM_E2 : STD_LOGIC;
130 130 SIGNAL nSRAM_W : STD_LOGIC;
131 131 SIGNAL nSRAM_G : STD_LOGIC;
132 132 SIGNAL nSRAM_BUSY : STD_LOGIC;
133 133 SIGNAL spw1_en : STD_LOGIC;
134 134 SIGNAL spw1_din : STD_LOGIC := '1';
135 135 SIGNAL spw1_sin : STD_LOGIC := '1';
136 136 SIGNAL spw1_dout : STD_LOGIC;
137 137 SIGNAL spw1_sout : STD_LOGIC;
138 138 SIGNAL spw2_en : STD_LOGIC;
139 139 SIGNAL spw2_din : STD_LOGIC := '1';
140 140 SIGNAL spw2_sin : STD_LOGIC := '1';
141 141 SIGNAL spw2_dout : STD_LOGIC;
142 142 SIGNAL spw2_sout : STD_LOGIC;
143 143 SIGNAL bias_fail_sw : STD_LOGIC;
144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
144 SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 SIGNAL ADC_OEB_bar_CH_r : STD_LOGIC_VECTOR(7 DOWNTO 0);
146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
145 147 SIGNAL ADC_smpclk : STD_LOGIC;
146 148 SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0);
147 149 SIGNAL DAC_SDO : STD_LOGIC;
148 150 SIGNAL DAC_SCK : STD_LOGIC;
149 151 SIGNAL DAC_SYNC : STD_LOGIC;
150 152 SIGNAL DAC_CAL_EN : STD_LOGIC;
151 153 SIGNAL HK_smpclk : STD_LOGIC;
152 154 SIGNAL ADC_OEB_bar_HK : STD_LOGIC;
153 155 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
154 156 -- SIGNAL TAG8 : STD_LOGIC;
155 157
156 158 CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20;
157 159 CONSTANT SCRUB_PERIOD : INTEGER := 200/20;
158 160 CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20;
159 161 CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20;
160 162 SIGNAL counter_scrub_period : INTEGER;
161 163
162 164
163 165 --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800";
164 166 --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006";
165 167 --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F";
166 168
167 169 CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90";
168 170 CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
169 171 CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E";
170 172 CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
171 173 CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
172 174 CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000";
173 175
174 176 SIGNAL message_simu : STRING(1 TO 15) := "---------------";
175 177 SIGNAL data_message : STRING(1 TO 15) := "---------------";
176 178 SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0');
177 179 SIGNAL TXD1 : STD_LOGIC;
178 180 SIGNAL RXD1 : STD_LOGIC;
179 181
180 182 -----------------------------------------------------------------------------
181 183 CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000";
182 184 CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000";
183 185 CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000";
184 186 CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000";
185 187 CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000";
186 188 CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000";
187 189 CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000";
188 190 CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000";
189 191 CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000";
190 192 CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000";
191 193 CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000";
192 194 CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000";
193 195 CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000";
194 196 CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000";
195 197
196 198
197 199 TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
198 200 SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0);
199 201
200 202 TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
201 203 SIGNAL sample_counter : counter_vector( 2 DOWNTO 0);
202 204
203 205 SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 206 SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 207 SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
206 208 SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0);
207 209
208 210 SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0);
209 211 SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0);
210 212 SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0);
211 213
212 214
213 215 SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0);
214 216 -----------------------------------------------------------------------------
215 217 CONSTANT srambanks : INTEGER := 2;
216 218 CONSTANT sramwidth : INTEGER := 32;
217 219 CONSTANT sramdepth : INTEGER := 19;
218 220 SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0);
219 221 -----------------------------------------------------------------------------
220 222
221 223 BEGIN -- beh
222 224
223 225 LFR_EQM_1 : LFR_EQM
224 226 GENERIC MAP (
225 227 Mem_use => use_RAM,
226 228 USE_BOOTLOADER => 0,
227 229 USE_ADCDRIVER => 1,
228 230 tech => apa3e,
229 231 tech_leon => apa3e,
230 232 DEBUG_FORCE_DATA_DMA => 1,
231 233 USE_DEBUG_VECTOR => 0)
232 234 PORT MAP (
233 235 clk50MHz => clk50MHz, --IN --ok
234 236 clk49_152MHz => clk49_152MHz, --in --ok
235 237 reset => reset, --IN --ok
236 238
237 239 TAG => TAG,
238 240 --TAG1 => TAG1, --in
239 241 --TAG3 => TAG3, --out
240 242 --TAG2 => TAG2, --IN --ok
241 243 --TAG4 => TAG4, --out --ok
242 244
243 245 address => address, --out
244 246 data => data, --inout
245 247 nSRAM_MBE => nSRAM_MBE, --inout
246 248 nSRAM_E1 => nSRAM_E1, --out
247 249 nSRAM_E2 => nSRAM_E2, --out
248 250 nSRAM_W => nSRAM_W, --out
249 251 nSRAM_G => nSRAM_G, --out
250 252 nSRAM_BUSY => nSRAM_BUSY, --in
251 253
252 254 spw1_en => spw1_en, --out --ok
253 255 spw1_din => spw1_din, --in --ok
254 256 spw1_sin => spw1_sin, --in --ok
255 257 spw1_dout => spw1_dout, --out --ok
256 258 spw1_sout => spw1_sout, --out --ok
257 259
258 260 spw2_en => spw2_en, --out --ok
259 261 spw2_din => spw2_din, --in --ok
260 262 spw2_sin => spw2_sin, --in --ok
261 263 spw2_dout => spw2_dout, --out --ok
262 264 spw2_sout => spw2_sout, --out --ok
263 265
264 266 bias_fail_sw => bias_fail_sw, --OUT --ok
265 267
266 268 ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok
267 269 ADC_smpclk => ADC_smpclk, --out --ok
268 270 ADC_data => ADC_data, --IN --ok
269 271
270 272 DAC_SDO => DAC_SDO, --out --ok
271 273 DAC_SCK => DAC_SCK, --out --ok
272 274 DAC_SYNC => DAC_SYNC, --out --ok
273 275 DAC_CAL_EN => DAC_CAL_EN, --out --ok
274 276
275 277 HK_smpclk => HK_smpclk, --out --ok
276 278 ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok
277 279 HK_SEL => HK_SEL); --out --ok
278 280
279 281
280 282 -----------------------------------------------------------------------------
281 283 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
282 284 clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz
283 285 -----------------------------------------------------------------------------
284
286
285 287 MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE
286 288 TestModule_RHF1401_1 : TestModule_RHF1401
287 289 GENERIC MAP (
288 290 freq => 24*(I+1),
289 291 amplitude => 8000/(I+1),
290 292 impulsion => 0)
291 293 PORT MAP (
292 294 ADC_smpclk => ADC_smpclk,
293 295 ADC_OEB_bar => ADC_OEB_bar_CH(I),
294 296 ADC_data => ADC_data);
295 297 END GENERATE MODULE_RHF1401;
296 298
297 299 -----------------------------------------------------------------------------
298 300 PROCESS (clk50MHz, reset)
299 301 BEGIN -- PROCESS
300 302 IF reset = '0' THEN -- asynchronous reset (active low)
301 303 nSRAM_BUSY <= '1';
302 304 counter_scrub_period <= 0;
303 305 ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge
304 306 IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN
305 307 counter_scrub_period <= 0;
306 308 ELSE
307 309 counter_scrub_period <= counter_scrub_period + 1;
308 310 END IF;
309 311
310 312 IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN
311 313 nSRAM_BUSY <= '1';
312 314 ELSE
313 315 nSRAM_BUSY <= '0';
314 316 END IF;
315 317 END IF;
316 318 END PROCESS;
317 319
318 320 -----------------------------------------------------------------------------
319 321 -- TB
320 322 -----------------------------------------------------------------------------
321 323 TAG(1) <= TXD1;
322 324 TAG(2) <= '1';
323 325 RXD1 <= TAG(3);
324 326
325 327 PROCESS
326 328 CONSTANT txp : TIME := 320 ns;
327 329 VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0);
328 330 BEGIN -- PROCESS
329 331 TXD1 <= '1';
330 332 reset <= '0';
331 333 WAIT FOR 500 ns;
332 334 reset <= '1';
333 335 WAIT FOR 100 us;
334 336 message_simu <= "0 - UART init ";
335 337 UART_INIT(TXD1, txp);
336 338
337 339 ---------------------------------------------------------------------------
338 340 -- LAUNCH leon 3 software
339 341 ---------------------------------------------------------------------------
340 342 message_simu <= "2- GO Leon3....";
341 343
342 344 -- bool dsu3plugin::configureTarget() ---------------------------------------------------------------------------------------------------------------------------
343 345 --Force a debug break
344 346 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS);
345 347 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20);
346 348 --Clear time tag counter
347 349 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8);
348 350 --Clear ASR registers
349 351 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040);
350 352 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000");
351 353 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000");
352 354 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024);
353 355 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
354 356 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
355 357 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
356 358 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
357 359 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000");
358 360 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000");
359 361 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000");
360 362 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000");
361 363 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48);
362 364 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C);
363 365 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040);
364 366
365 367 IF USE_ESA_MEMCTRL = 1 THEN
366 368 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS);
367 369 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60");
368 370 UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000");
369 371 END IF;
370 372
371 373 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060);
372 374 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000");
373 375 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000");
374 376 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000");
375 377 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24);
376 378
377 379 --memSet(DSUBASEADDRESS+0x300000,0,1567);
378 380
379 381 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000);
380 382 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0");
381 383 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002");
382 384 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000");
383 385 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000");
384 386 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004");
385 387 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000");
386 388
387 389 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020);
388 390 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000");
389 391 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000");
390 392 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000");
391 393 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000");
392 394 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000");
393 395 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0");
394 396 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000");
395 397 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000");
396 398 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000");
397 399 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000");
398 400 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000");
399 401 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000");
400 402 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000");
401 403 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000");
402 404 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000");
403 405 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000");
404 406 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000");
405 407 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000");
406 408 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000");
407 409 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000");
408 410 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000");
409 411 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000");
410 412 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000");
411 413
412 414 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS);
413 415
414 416 --//Disable interrupts
415 417 --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0);
416 418 --if(APBIRQCTRLRBASEADD == (unsigned int)-1)
417 419 -- return false;
418 420 --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040);
419 421 --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080);
420 422 --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD);
421 423
422 424 -- //Set up timer
423 425 --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0);
424 426 --if(APBTIMERBASEADD == (unsigned int)-1)
425 427 -- return false;
426 428 --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014);
427 429 --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04);
428 430 --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018);
429 431
430 432
431 433 ---------------------------------------------------------------------------
432 434 --bool dsu3plugin::setCacheEnable(bool enabled)
433 435 --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0);
434 436 --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000;
435 437 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024);
436 438 UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000);
437 439 data_read <= data_read_v;
438 440 --if(enabled){
439 441 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000);
440 442 UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000);
441 443 --}else{
442 444 --WriteRegs(uIntlist()<<((!0x0001000F)&reg),DSUBASEADDRESS+0x700000);
443 445 --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000);
444 446 --}
445 447
446 448
447 449 -- void dsu3plugin::run() ---------------------------------------------------------------------------------------------------------------------------------------
448 450 UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020);
449 451
450 452 ---------------------------------------------------------------------------
451 453 --message_simu <= "1 - UART test ";
452 454 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF");
453 455 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A");
454 456 --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B");
455 457 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v);
456 458 --data_read <= data_read_v;
457 459 --data_message <= "GPIO_data_write";
458 460
459 461 -- UNSET the LFR reset
460 462 message_simu <= "2 - LFR UNRESET";
461 463 UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT);
462 464 --
463 465 message_simu <= "3 - LFR CONFIG ";
464 466 LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR,
465 467 ADDR_BUFFER_MS_F0_0,
466 468 ADDR_BUFFER_MS_F0_1,
467 469 ADDR_BUFFER_MS_F1_0,
468 470 ADDR_BUFFER_MS_F1_1,
469 471 ADDR_BUFFER_MS_F2_0,
470 472 ADDR_BUFFER_MS_F2_1);
471 473
472 474
473 475 LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp,
474 476 LFR_MODE_SBM1,
475 477 X"7FFFFFFF", -- START DATE
476 478
477 479 "00000", --DATA_SHAPING ( 4 DOWNTO 0)
478 480 X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0)
479 481 X"0001280A", --DELTA_F0 (31 DOWNTO 0)
480 482 X"00000007", --DELTA_F0_2 (31 DOWNTO 0)
481 483 X"0001283F", --DELTA_F1 (31 DOWNTO 0)
482 484 X"000127FF", --DELTA_F2 (31 DOWNTO 0)
483 485
484 486 ADDR_BASE_LFR,
485 487 ADDR_BUFFER_WFP_F0_0,
486 488 ADDR_BUFFER_WFP_F0_1,
487 489 ADDR_BUFFER_WFP_F1_0,
488 490 ADDR_BUFFER_WFP_F1_1,
489 491 ADDR_BUFFER_WFP_F2_0,
490 492 ADDR_BUFFER_WFP_F2_1,
491 493 ADDR_BUFFER_WFP_F3_0,
492 494 ADDR_BUFFER_WFP_F3_1);
493 495
494 496 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F");
495 497 UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
496 498
497 499
498 500 ---------------------------------------------------------------------------
499 501 -- CONFIG LFR 2
500 502 ---------------------------------------------------------------------------
501 503 --message_simu <= "3 - LFR2 CONFIG";
502 504 --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2,
503 505 -- X"40000000",
504 506 -- X"40001000",
505 507 -- X"40002000",
506 508 -- X"40003000",
507 509 -- X"40004000",
508 510 -- X"40005000");
509 511
510 512
511 513 --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp,
512 514 -- LFR_MODE_SBM1,
513 515 -- X"7FFFFFFF", -- START DATE
514 516
515 517 -- "00000",--DATA_SHAPING ( 4 DOWNTO 0)
516 518 -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0)
517 519 -- X"0001280A",--DELTA_F0 (31 DOWNTO 0)
518 520 -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0)
519 521 -- X"0001283F",--DELTA_F1 (31 DOWNTO 0)
520 522 -- X"000127FF",--DELTA_F2 (31 DOWNTO 0)
521 523
522 524 -- ADDR_BASE_LFR_2,
523 525 -- X"40006000",
524 526 -- X"40007000",
525 527 -- X"40008000",
526 528 -- X"40009000",
527 529 -- X"4000A000",
528 530 -- X"4000B000",
529 531 -- X"4000C000",
530 532 -- X"4000D000");
531 533
532 534 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F");
533 535 --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050");
534 536
535 537 ---------------------------------------------------------------------------
536 538 ---------------------------------------------------------------------------
537 539 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & X"5" & "10", X"FFFFFFFF");
538 540
539 541
540 542 message_simu <= "4 - GO GO GO !!";
541 543 data_message <= "---------------";
542 544 UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000");
543 545 -- UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000");
544 546
545 547
546 548 data_read_v := (OTHERS => '1');
547 549 READ_STATUS : LOOP
548 550 data_message <= "---------------";
549 551 WAIT FOR 2 ms;
550 552 data_message <= "READ_STATUS_SM_";
551 553 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
552 554 --data_message <= "--------------r";
553 555 --data_read <= data_read_v;
554 556 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v);
555 557
556 558 data_message <= "READ_STATUS_WF_";
557 559 --UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
558 560 --data_message <= "--------------r";
559 561 --data_read <= data_read_v;
560 562 UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v);
561 563 END LOOP READ_STATUS;
562 564
563 565 WAIT;
564 566 END PROCESS;
565 567
566 568
567 569 -----------------------------------------------------------------------------
568 570 PROCESS (nSRAM_W, reset)
569 571 BEGIN -- PROCESS
570 572 IF reset = '0' THEN -- asynchronous reset (active low)
571 573 data_pre_f0 <= X"00020001";
572 574 data_pre_f1 <= X"00020001";
573 575 data_pre_f2 <= X"00020001";
574 576
575 577 addr_pre_f0 <= (OTHERS => '0');
576 578 addr_pre_f1 <= (OTHERS => '0');
577 579 addr_pre_f2 <= (OTHERS => '0');
578 580
579 581 error_wfp <= "000";
580 582 error_wfp_addr <= "000";
581 583
582 584 sample_counter <= (0,0,0);
583 585
584 586 ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge
585 587 error_wfp <= "000";
586 588 error_wfp_addr <= "000";
587 589 -------------------------------------------------------------------------
588 590 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR
589 591 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN
590 592
591 593 addr_pre_f0 <= address(13 DOWNTO 0);
592 594 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN
593 595 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
594 596 error_wfp_addr(0) <= '1';
595 597 END IF;
596 598 END IF;
597 599
598 600 data_pre_f0 <= data;
599 601 CASE data_pre_f0 IS
600 602 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF;
601 603 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF;
602 604 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF;
603 605 WHEN OTHERS => error_wfp(0) <= '1';
604 606 END CASE;
605 607
606 608
607 609 END IF;
608 610 -------------------------------------------------------------------------
609 611 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR
610 612 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN
611 613
612 614 addr_pre_f1 <= address(13 DOWNTO 0);
613 615 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN
614 616 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
615 617 error_wfp_addr(1) <= '1';
616 618 END IF;
617 619 END IF;
618 620
619 621 data_pre_f1 <= data;
620 622 CASE data_pre_f1 IS
621 623 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF;
622 624 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF;
623 625 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF;
624 626 WHEN OTHERS => error_wfp(1) <= '1';
625 627 END CASE;
626 628
627 629 sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16);
628 630 sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0);
629 631 sample_counter(1) <= (sample_counter(1) + 1) MOD 3;
630 632
631 633 END IF;
632 634 -------------------------------------------------------------------------
633 635 IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR
634 636 address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN
635 637
636 638 addr_pre_f2 <= address(13 DOWNTO 0);
637 639 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN
638 640 IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN
639 641 error_wfp_addr(2) <= '1';
640 642 END IF;
641 643 END IF;
642 644
643 645 data_pre_f2 <= data;
644 646 CASE data_pre_f2 IS
645 647 WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF;
646 648 WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF;
647 649 WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF;
648 650 WHEN OTHERS => error_wfp(2) <= '1';
649 651 END CASE;
650 652
651 653 sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16);
652 654 sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0);
653 655 sample_counter(2) <= (sample_counter(2) + 1) MOD 3;
654 656
655 657 END IF;
656 658 END IF;
657 659 END PROCESS;
658 660 -----------------------------------------------------------------------------
659 661 ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1;
660 662
661 663 sbanks : FOR k IN 0 TO srambanks-1 GENERATE
662 664 sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE
663 665 sr0 : sram
664 666 GENERIC MAP (
665 667 index => i,
666 668 abits => sramdepth,
667 669 fname => sramfile)
668 670 PORT MAP (
669 671 address,
670 672 data(31-i*8 DOWNTO 24-i*8),
671 673 ramsn(k),
672 674 nSRAM_W,
673 675 nSRAM_G
674 676 );
675 677 END GENERATE;
676 678 END GENERATE;
677 679
678 680 END beh;
679 681
Show file before | Show file after | Hide comments
@@ -1,146 +1,170
1 1 onerror {resume}
2 2 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc
3 3 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(4 downto 3)} HWDATA
4 4 quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/debug_vector(7 downto 6)} DMA_DATA
5 5 quietly WaveActivateNextPane {} 0
6 add wave -noupdate -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1)
7 add wave -noupdate -height 74 -max 326.0 -min 256.0 /tb/sample_counter
8 6 add wave -noupdate -group ALL /tb/data_message
9 7 add wave -noupdate -group ALL /tb/message_simu
10 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
11 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
12 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
13 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
14 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
15 add wave -noupdate -group ALL -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
16 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
17 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
18 add wave -noupdate -group ALL -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
8 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1
9 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2
10 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G
11 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W
12 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/data
13 add wave -noupdate -group ALL -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc
14 add wave -noupdate -group ALL -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address
15 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
16 add wave -noupdate -group ALL -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE
19 17 add wave -noupdate -group ALL -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data
20 18 add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk
21 19 add wave -noupdate -group ALL -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH
22 20 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample
23 21 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val
24 22 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val
25 23 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata
26 24 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val
27 25 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata
28 26 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val
29 27 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata
30 28 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val
31 29 add wave -noupdate -group ALL -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata
32 30 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
33 31 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
34 32 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
35 33 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
36 34 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
37 35 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
38 36 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
39 37 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
40 38 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
41 39 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
42 40 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
43 41 add wave -noupdate -group ALL -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
44 42 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
45 43 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
46 44 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk
47 45 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
48 46 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid
49 47 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex
50 48 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn
51 49 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
52 50 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
53 51 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid
54 52 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version
55 53 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
56 54 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
57 55 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
58 56 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
59 57 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter
60 58 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
61 59 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
62 60 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
63 61 add wave -noupdate -group ALL -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
64 62 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp
65 63 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp
66 64 add wave -noupdate -group ALL -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0
67 65 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f1
68 66 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/data_pre_f2
69 67 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f0
70 68 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f1
71 69 add wave -noupdate -group ALL -group TEST -radix hexadecimal /tb/addr_pre_f2
72 70 add wave -noupdate -group ALL /tb/error_wfp
73 71 add wave -noupdate -group ALL /tb/error_wfp_addr
74 72 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a
75 73 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1
76 74 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe
77 75 add wave -noupdate -group ALL -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we
78 76 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a
79 77 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1
80 78 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe
81 79 add wave -noupdate -group ALL -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we
82 80 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi
83 81 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo
84 82 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi
85 83 add wave -noupdate -group ALL -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso
86 84 add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) -radix hexadecimal}} -expand} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmi.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmi
87 85 add wave -noupdate -group ALL -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo
88 86 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In
89 87 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out
90 88 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address
91 89 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst
92 90 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data
93 91 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send
94 92 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
95 93 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg
96 94 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig
97 95 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window
98 96 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window
99 97 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done
100 98 add wave -noupdate -group ALL -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren
101 add wave -noupdate /tb/LFR_EQM_1/debug_vector
102 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
103 add wave -noupdate -radix unsigned /tb/LFR_EQM_1/HWDATA
104 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
105 add wave -noupdate -radix unsigned /tb/LFR_EQM_1/DMA_DATA
106 add wave -noupdate -label DMA_REN /tb/LFR_EQM_1/debug_vector(8)
107 add wave -noupdate -label HREADY /tb/LFR_EQM_1/debug_vector(5)
108 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk
109 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn
110 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
111 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
112 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
113 add wave -noupdate -expand -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
114 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv
115 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
116 add wave -noupdate -expand -group ADC -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
117 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
118 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
119 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
120 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
121 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
122 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
123 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
124 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
125 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
126 add wave -noupdate /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
127 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
128 add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
99 add wave -noupdate -group ALL -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}} -subitemconfig {/tb/sample(1)(5) {-height 15 -radix decimal} /tb/sample(1)(4) {-height 15 -radix decimal} /tb/sample(1)(3) {-height 15 -radix decimal} /tb/sample(1)(2) {-height 15 -radix decimal} /tb/sample(1)(1) {-height 15 -radix decimal} /tb/sample(1)(0) {-height 15 -radix decimal}} /tb/sample(1)
100 add wave -noupdate -group ALL -height 74 -max 326.0 -min 256.0 /tb/sample_counter
101 add wave -noupdate -group ALL /tb/LFR_EQM_1/debug_vector
102 add wave -noupdate -group ALL /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state
103 add wave -noupdate -group ALL -radix unsigned /tb/LFR_EQM_1/HWDATA
104 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY
105 add wave -noupdate -group ALL -radix unsigned /tb/LFR_EQM_1/DMA_DATA
106 add wave -noupdate -group ALL -label DMA_REN /tb/LFR_EQM_1/debug_vector(8)
107 add wave -noupdate -group ALL -label HREADY /tb/LFR_EQM_1/debug_vector(5)
108 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_clk
109 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv_rstn
110 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/rstn
111 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/clk
112 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
113 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE
114 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(8)
115 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(7)
116 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(6)
117 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(5)
118 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(4)
119 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(3)
120 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(2)
121 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(1)
122 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_nOE(0)
123 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/cnv
124 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
125 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_val
126 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv_high
127 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ncycle_cnv
128 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current
129 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
130 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_result
131 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_current_cycle_enabled
132 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_valid
133 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data
134 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_reg
135 add wave -noupdate -group ALL /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/ADC_data_selected
136 add wave -noupdate -group ALL -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) -radix hexadecimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample_reg
137 add wave -noupdate -group ALL -radix hexadecimal /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
138 add wave -noupdate -group ALL /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
139 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) -radix decimal} {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) -radix decimal}} -expand -subitemconfig {/tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(8) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(7) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(6) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(5) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(4) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(3) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(2) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(1) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample(0) {-format Analog-Step -height 40 -max 7517.0 -min -7504.0 -radix decimal}} /tb/LFR_EQM_1/USE_ADCDRIVER_true/top_ad_conv_RHF1401_withFilter_1/sample
140 add wave -noupdate -radix decimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in_val
141 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(7) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(6) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(5) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(4) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(3) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(2) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(1) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in(0) {-format Analog-Step -height 40 -max 12000.0 -min -12000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_in
142 add wave -noupdate /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out_val
143 add wave -noupdate -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) -radix decimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(7) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(6) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(5) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(4) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(3) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(2) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(1) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out(0) {-format Analog-Step -height 40 -max 10065.0 -min -10213.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/IIR_CEL_CTRLR_v2_1/sample_out
144 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(7)/TestModule_RHF1401_1/reg
145 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(6)/TestModule_RHF1401_1/reg
146 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(5)/TestModule_RHF1401_1/reg
147 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(4)/TestModule_RHF1401_1/reg
148 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(3)/TestModule_RHF1401_1/reg
149 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(2)/TestModule_RHF1401_1/reg
150 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(1)/TestModule_RHF1401_1/reg
151 add wave -noupdate -expand -group ADC_DATA -format Analog-Step -height 40 -max 7000.0 -min -7000.0 /tb/MODULE_RHF1401(0)/TestModule_RHF1401_1/reg
152 add wave -noupdate -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) -radix decimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7) {-format Analog-Step -height 15 -max 32000.0 -min -32000.0 -radix decimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) -radix decimal} {/tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) -radix decimal}}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(17) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(16) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(15) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(14) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(13) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(12) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(11) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(10) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(9) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(8) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(7) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(6) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(5) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(4) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(3) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(2) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(1) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(7)(0) {-height 15 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(6) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(5) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(4) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(3) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(2) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(1) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim(0) {-format Analog-Step -height 40 -max 32000.0 -min -32000.0 -radix decimal}} /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_filter_v2_out_sim
129 153 TreeUpdate [SetDefaultTree]
130 WaveRestoreCursors {{Cursor 1} {12871601883 ps} 0} {{Cursor 2} {32570000 ps} 0} {{Cursor 3} {14130170000 ps} 0}
154 WaveRestoreCursors {{Cursor 1} {10205370000 ps} 0} {{Cursor 2} {3082130000 ps} 0} {{Cursor 3} {13658690000 ps} 0}
131 155 quietly wave cursor active 2
132 156 configure wave -namecolwidth 571
133 157 configure wave -valuecolwidth 347
134 158 configure wave -justifyvalue left
135 159 configure wave -signalnamewidth 0
136 160 configure wave -snapdistance 10
137 161 configure wave -datasetprefix 0
138 162 configure wave -rowmargin 4
139 163 configure wave -childrowmargin 2
140 164 configure wave -gridoffset 0
141 165 configure wave -gridperiod 1
142 166 configure wave -griddelta 40
143 167 configure wave -timeline 0
144 168 configure wave -timelineunits ns
145 169 update
146 WaveRestoreZoom {32208206 ps} {33843459 ps}
170 WaveRestoreZoom {0 ps} {6597182550 ps}
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@@ -1,248 +1,250
1 1
2 2 LIBRARY IEEE;
3 3 USE IEEE.STD_LOGIC_1164.ALL;
4 4 USE IEEE.numeric_std.ALL;
5 5 LIBRARY lpp;
6 6 USE lpp.lpp_ad_conv.ALL;
7 7 USE lpp.general_purpose.SYNC_FF;
8 8
9 9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 10 GENERIC(
11 11 ChanelCount : INTEGER := 8;
12 12 ncycle_cnv_high : INTEGER := 25;
13 13 ncycle_cnv : INTEGER := 50;
14 14 FILTER_ENABLED : INTEGER := 16#FF#
15 15 );
16 16 PORT (
17 17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 18 cnv_rstn : IN STD_LOGIC;
19 19
20 20 cnv : OUT STD_LOGIC;
21 21
22 22 clk : IN STD_LOGIC; -- 25MHz
23 23 rstn : IN STD_LOGIC;
24 24 ADC_data : IN Samples14;
25 25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 27 sample_val : OUT STD_LOGIC
28 28 );
29 29 END top_ad_conv_RHF1401_withFilter;
30 30
31 31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32 32
33 33 SIGNAL cnv_cycle_counter : INTEGER;
34 34 SIGNAL cnv_s : STD_LOGIC;
35 35 SIGNAL cnv_s_reg : STD_LOGIC;
36 36 SIGNAL cnv_sync : STD_LOGIC;
37 37 SIGNAL cnv_sync_reg : STD_LOGIC;
38 38 SIGNAL cnv_sync_rising : STD_LOGIC;
39 39
40 40 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
41 41 SIGNAL enable_ADC : STD_LOGIC;
42 42
43 43
44 44 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
45 45
46 46 SIGNAL channel_counter : INTEGER;
47 47 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
48 48
49 49 SIGNAL ADC_data_selected : Samples14;
50 50 SIGNAL ADC_data_result : Samples15;
51 51
52 52 SIGNAL sample_counter : INTEGER;
53 53 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
54 54
55 55 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
56 56
57 57 -----------------------------------------------------------------------------
58 58 CONSTANT OE_NB_CYCLE_ENABLED : INTEGER := 2;
59 59 CONSTANT DATA_CYCLE_VALID : INTEGER := 3;
60 60
61 61 -- GEN OutPut Enable
62 62 TYPE FSM_GEN_OEn_state IS (IDLE, GEN_OE, WAIT_CYCLE);
63 63 SIGNAL state_GEN_OEn : FSM_GEN_OEn_state;
64 64 SIGNAL ADC_current : INTEGER RANGE 0 TO ChanelCount-1;
65 65 SIGNAL ADC_current_cycle_enabled : INTEGER RANGE 0 TO OE_NB_CYCLE_ENABLED + 1;
66 66 SIGNAL ADC_data_valid : STD_LOGIC;
67 67 SIGNAL ADC_data_reg : Samples14;
68 68 -----------------------------------------------------------------------------
69 CONSTANT SAMPLE_DIVISION : INTEGER := 2;
69 CONSTANT SAMPLE_DIVISION : INTEGER := 5;
70 70 SIGNAL sample_val_s : STD_LOGIC;
71 71 SIGNAL sample_val_counter : INTEGER RANGE 0 TO SAMPLE_DIVISION;
72 72 BEGIN
73 73
74 74
75 75 -----------------------------------------------------------------------------
76 76 -- CNV GEN
77 77 -----------------------------------------------------------------------------
78 78 PROCESS (cnv_clk, cnv_rstn)
79 79 BEGIN -- PROCESS
80 80 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
81 81 cnv_cycle_counter <= 0;
82 82 cnv_s <= '0';
83 83 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
84 84 IF cnv_cycle_counter < ncycle_cnv-1 THEN
85 85 cnv_cycle_counter <= cnv_cycle_counter + 1;
86 86 IF cnv_cycle_counter < ncycle_cnv_high-1 THEN
87 87 cnv_s <= '1';
88 88 ELSE
89 89 cnv_s <= '0';
90 90 END IF;
91 91 ELSE
92 92 cnv_s <= '1';
93 93 cnv_cycle_counter <= 0;
94 94 END IF;
95 95 END IF;
96 96 END PROCESS;
97 97
98 98 cnv <= cnv_s;
99 99
100 100 PROCESS (cnv_clk, cnv_rstn)
101 101 BEGIN -- PROCESS
102 102 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
103 103 cnv_s_reg <= '0';
104 104 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
105 105 cnv_s_reg <= cnv_s;
106 106 END IF;
107 107 END PROCESS;
108 108
109 109
110 110 -----------------------------------------------------------------------------
111 111 -- SYNC CNV
112 112 -----------------------------------------------------------------------------
113 113
114 114 SYNC_FF_cnv : SYNC_FF
115 115 GENERIC MAP (
116 116 NB_FF_OF_SYNC => 2)
117 117 PORT MAP (
118 118 clk => clk,
119 119 rstn => rstn,
120 120 A => cnv_s_reg,
121 121 A_sync => cnv_sync);
122 122
123 123 -----------------------------------------------------------------------------
124 124 --
125 125 -----------------------------------------------------------------------------
126 126 PROCESS (clk, rstn)
127 127 BEGIN -- PROCESS
128 128 IF rstn = '0' THEN -- asynchronous reset (active low)
129 129 cnv_sync_reg <= '0';
130 130 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
131 131 cnv_sync_reg <= cnv_sync;
132 132 END IF;
133 133 END PROCESS;
134 134
135 135 cnv_sync_rising <= '1' WHEN cnv_sync = '1' AND cnv_sync_reg = '0' ELSE '0';
136 136
137 137 -----------------------------------------------------------------------------
138 138 -- GEN OutPut Enable
139 139 -----------------------------------------------------------------------------
140 140 PROCESS (clk, rstn)
141 141 BEGIN -- PROCESS
142 142 IF rstn = '0' THEN
143 143 -------------------------------------------------------------------------
144 144 ADC_nOE <= (OTHERS => '1');
145 145 ADC_current <= 0;
146 146 ADC_current_cycle_enabled <= 0;
147 147 state_GEN_OEn <= IDLE;
148 148 -------------------------------------------------------------------------
149 149 ADC_data_reg <= (OTHERS => '0');
150 150 all_channel_sample_reg_init: FOR I IN 0 TO ChanelCount-1 LOOP
151 151 sample_reg(I) <= (OTHERS => '0');
152 sample(I) <= (OTHERS => '0');
152 153 END LOOP all_channel_sample_reg_init;
153 154 sample_val <= '0';
154 155 sample_val_s <= '0';
155 156 sample_val_counter <= 0;
156 157 -------------------------------------------------------------------------
157 158 ELSIF clk'event AND clk = '1' THEN
158 159 -------------------------------------------------------------------------
159 160 sample_val_s <= '0';
160 161 ADC_nOE <= (OTHERS => '1');
161 162 CASE state_GEN_OEn IS
162 163 WHEN IDLE =>
163 164 IF cnv_sync_rising = '1' THEN
164 165 ADC_nOE(0) <= '0';
165 166 state_GEN_OEn <= GEN_OE;
166 167 ADC_current <= 0;
167 168 ADC_current_cycle_enabled <= 1;
168 169 END IF;
169 170
170 171 WHEN GEN_OE =>
171 172 ADC_nOE(ADC_current) <= '0';
172 173 ADC_current_cycle_enabled <= ADC_current_cycle_enabled + 1;
173 174 IF ADC_current_cycle_enabled = OE_NB_CYCLE_ENABLED THEN
174 175 state_GEN_OEn <= WAIT_CYCLE;
175 176 END IF;
176 177
177 178 WHEN WAIT_CYCLE =>
178 179 ADC_current_cycle_enabled <= 0;
179 180 IF ADC_current = ChanelCount-1 THEN
180 181 state_GEN_OEn <= IDLE;
181 182 sample_val_s <= '1';
182 183 ELSE
183 184 ADC_current <= ADC_current + 1;
184 185 state_GEN_OEn <= GEN_OE;
185 186 END IF;
186 187 WHEN OTHERS => NULL;
187 188 END CASE;
188 189 -------------------------------------------------------------------------
189 190 ADC_data_reg <= ADC_data;
190 191
191 192 all_channel_sample_reg: FOR I IN 0 TO ChanelCount-1 LOOP
192 193 IF ADC_data_valid = '1' AND ADC_current = I THEN
193 194 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
194 195 ELSE
195 196 sample_reg(I) <= sample_reg(I);
196 197 END IF;
197 198 END LOOP all_channel_sample_reg;
198 199 -------------------------------------------------------------------------
199 200 sample_val <= '0';
200 201 IF sample_val_s = '1' THEN
201 202 IF sample_val_counter = SAMPLE_DIVISION-1 THEN
202 203 sample_val_counter <= 0;
203 204 sample_val <= '1'; -- TODO
205 sample <= sample_reg;
204 206 ELSE
205 207 sample_val_counter <= sample_val_counter + 1;
206 208 sample_val <= '0';
207 209 END IF;
208 210 END IF;
209 211
210 212 END IF;
211 213 END PROCESS;
212 214
213 215 ADC_data_valid <= '1' WHEN ADC_current_cycle_enabled = DATA_CYCLE_VALID ELSE '0';
214 216
215 217 WITH ADC_current SELECT
216 218 ADC_data_selected <= sample_reg(0) WHEN 0,
217 219 sample_reg(1) WHEN 1,
218 220 sample_reg(2) WHEN 2,
219 221 sample_reg(3) WHEN 3,
220 222 sample_reg(4) WHEN 4,
221 223 sample_reg(5) WHEN 5,
222 224 sample_reg(6) WHEN 6,
223 225 sample_reg(7) WHEN 7,
224 226 sample_reg(8) WHEN OTHERS ;
225 227
226 228 ADC_data_result <= std_logic_vector((
227 229 signed( ADC_data_selected(13) & ADC_data_selected) +
228 230 signed( ADC_data_reg(13) & ADC_data_reg)
229 231 ));
230 232
231 sample <= sample_reg;
233 -- sample <= sample_reg;
232 234
233 235 END ar_top_ad_conv_RHF1401;
234 236
235 237
236 238
237 239
238 240
239 241
240 242
241 243
242 244
243 245
244 246
245 247
246 248
247 249
248 250
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@@ -1,640 +1,659
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23 LIBRARY ieee;
24 24 USE ieee.std_logic_1164.ALL;
25 25 USE ieee.numeric_std.ALL;
26 26
27 27 LIBRARY lpp;
28 28 USE lpp.lpp_ad_conv.ALL;
29 29 USE lpp.iir_filter.ALL;
30 30 USE lpp.FILTERcfg.ALL;
31 31 USE lpp.lpp_memory.ALL;
32 32 USE lpp.lpp_waveform_pkg.ALL;
33 33 USE lpp.cic_pkg.ALL;
34 34 USE lpp.data_type_pkg.ALL;
35 35 USE lpp.lpp_lfr_filter_coeff.ALL;
36 36
37 37 LIBRARY techmap;
38 38 USE techmap.gencomp.ALL;
39 39
40 40 LIBRARY grlib;
41 41 USE grlib.amba.ALL;
42 42 USE grlib.stdlib.ALL;
43 43 USE grlib.devices.ALL;
44 44 USE GRLIB.DMA2AHB_Package.ALL;
45 45
46 46 ENTITY lpp_lfr_filter IS
47 47 GENERIC(
48 48 Mem_use : INTEGER := use_RAM
49 49 );
50 50 PORT (
51 51 sample : IN Samples(7 DOWNTO 0);
52 52 sample_val : IN STD_LOGIC;
53 53 sample_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
54 54 --
55 55 clk : IN STD_LOGIC;
56 56 rstn : IN STD_LOGIC;
57 57 --
58 58 data_shaping_SP0 : IN STD_LOGIC;
59 59 data_shaping_SP1 : IN STD_LOGIC;
60 60 data_shaping_R0 : IN STD_LOGIC;
61 61 data_shaping_R1 : IN STD_LOGIC;
62 62 data_shaping_R2 : IN STD_LOGIC;
63 63 --
64 64 sample_f0_val : OUT STD_LOGIC;
65 65 sample_f1_val : OUT STD_LOGIC;
66 66 sample_f2_val : OUT STD_LOGIC;
67 67 sample_f3_val : OUT STD_LOGIC;
68 68 --
69 69 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 70 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 71 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
72 72 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
73 73 --
74 74 sample_f0_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 75 sample_f1_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 76 sample_f2_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
77 77 sample_f3_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
78 78 );
79 79 END lpp_lfr_filter;
80 80
81 81 ARCHITECTURE tb OF lpp_lfr_filter IS
82 82
83 83 COMPONENT Downsampling
84 84 GENERIC (
85 85 ChanelCount : INTEGER;
86 86 SampleSize : INTEGER;
87 87 DivideParam : INTEGER);
88 88 PORT (
89 89 clk : IN STD_LOGIC;
90 90 rstn : IN STD_LOGIC;
91 91 sample_in_val : IN STD_LOGIC;
92 92 sample_in : IN samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0);
93 93 sample_out_val : OUT STD_LOGIC;
94 94 sample_out : OUT samplT(ChanelCount-1 DOWNTO 0, SampleSize-1 DOWNTO 0));
95 95 END COMPONENT;
96 96
97 97 -----------------------------------------------------------------------------
98 98 CONSTANT ChanelCount : INTEGER := 8;
99 99
100 100 -----------------------------------------------------------------------------
101 101 SIGNAL sample_val_delay : STD_LOGIC;
102 102 -----------------------------------------------------------------------------
103 103 CONSTANT Coef_SZ : INTEGER := 9;
104 104 CONSTANT CoefCntPerCel : INTEGER := 6;
105 105 CONSTANT CoefPerCel : INTEGER := 5;
106 106 CONSTANT Cels_count : INTEGER := 5;
107 107
108 108 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
109 109 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
110 110 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
111 111 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
112 112 --
113 SIGNAL sample_filter_v2_out_sim : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
114
113 115 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
114 116 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
115 117 -----------------------------------------------------------------------------
116 118 SIGNAL sample_data_shaping_out_val : STD_LOGIC;
117 119 SIGNAL sample_data_shaping_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
118 120 SIGNAL sample_data_shaping_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
119 121 SIGNAL sample_data_shaping_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
120 122 SIGNAL sample_data_shaping_f2_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
121 123 SIGNAL sample_data_shaping_f1_f0_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
122 124 SIGNAL sample_data_shaping_f2_f1_s : STD_LOGIC_VECTOR(17 DOWNTO 0);
123 125 -----------------------------------------------------------------------------
124 126 SIGNAL sample_filter_v2_out_val_s : STD_LOGIC;
125 127 SIGNAL sample_filter_v2_out_s : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
126 128 -----------------------------------------------------------------------------
127 129 -- SIGNAL sample_f0_val : STD_LOGIC;
128 130 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 15 DOWNTO 0);
129 131 SIGNAL sample_f0_s : sample_vector(7 DOWNTO 0, 15 DOWNTO 0);
130 132 --
131 133 -- SIGNAL sample_f1_val : STD_LOGIC;
132 134
133 135 SIGNAL sample_f0_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
134 136 SIGNAL sample_f1_s : samplT(5 DOWNTO 0, 17 DOWNTO 0);
135 137 SIGNAL sample_f1 : samplT(5 DOWNTO 0, 17 DOWNTO 0);
136 138 --
137 139 -- SIGNAL sample_f2_val : STD_LOGIC;
138 140 SIGNAL sample_f2 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
139 141 SIGNAL sample_f2_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
140 142 SIGNAL sample_f2_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
141 143 SIGNAL sample_f2_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
142 144 SIGNAL sample_f2_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
143 145 SIGNAL sample_f2_cic_val : STD_LOGIC;
144 146 SIGNAL sample_f2_filter_val : STD_LOGIC;
145 147
146 148 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
147 149 SIGNAL sample_f3_cic_s : samplT(5 DOWNTO 0, 15 DOWNTO 0);
148 150 SIGNAL sample_f3_cic_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
149 151 SIGNAL sample_f3_filter : samplT(5 DOWNTO 0, 17 DOWNTO 0);
150 152 SIGNAL sample_f3_cic : sample_vector(5 DOWNTO 0, 15 DOWNTO 0);
151 153 SIGNAL sample_f3_cic_val : STD_LOGIC;
152 154 SIGNAL sample_f3_filter_val : STD_LOGIC;
153 155
154 156 -----------------------------------------------------------------------------
155 157 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
156 158 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
157 159 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
158 160 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
159 161 -----------------------------------------------------------------------------
160 162
161 163 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
162 164 SIGNAL sample_f1_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
163 165 SIGNAL sample_f2_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
164 166 SIGNAL sample_f3_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
165 167
166 168 SIGNAL sample_f0_val_s : STD_LOGIC;
167 169 SIGNAL sample_f1_val_s : STD_LOGIC;
168 170 SIGNAL sample_f1_val_ss : STD_LOGIC;
169 171 SIGNAL sample_f2_val_s : STD_LOGIC;
170 172 SIGNAL sample_f3_val_s : STD_LOGIC;
171 173
172 174 -----------------------------------------------------------------------------
173 175 -- CONFIG FILTER IIR f0 to f1
174 176 -----------------------------------------------------------------------------
175 177 CONSTANT f0_to_f1_CEL_NUMBER : INTEGER := 5;
176 178 CONSTANT f0_to_f1_COEFFICIENT_SIZE : INTEGER := 10;
177 179 CONSTANT f0_to_f1_POINT_POSITION : INTEGER := 8;
178 180
179 181 CONSTANT f0_to_f1_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
180 182 (
181 183 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
182 184 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
183 185 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
184 186 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
185 187 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
186 188 );
187 189 CONSTANT f0_to_f1_gain : COEFF_CEL_REAL :=
188 190 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
189 191
190 192 CONSTANT coefs_iir_cel_f0_to_f1 : STD_LOGIC_VECTOR((f0_to_f1_CEL_NUMBER*f0_to_f1_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
191 193 := get_IIR_CEL_FILTER_CONFIG(
192 194 f0_to_f1_COEFFICIENT_SIZE,
193 195 f0_to_f1_POINT_POSITION,
194 196 f0_to_f1_CEL_NUMBER,
195 197 f0_to_f1_sos,
196 198 f0_to_f1_gain);
197 199 -----------------------------------------------------------------------------
198 200
199 201 -----------------------------------------------------------------------------
200 202 -- CONFIG FILTER IIR f2 and f3
201 203 -----------------------------------------------------------------------------
202 204 CONSTANT f2_f3_CEL_NUMBER : INTEGER := 5;
203 205 CONSTANT f2_f3_COEFFICIENT_SIZE : INTEGER := 10;
204 206 CONSTANT f2_f3_POINT_POSITION : INTEGER := 8;
205 207
206 208 CONSTANT f2_f3_sos : COEFF_CEL_ARRAY_REAL(1 TO 5) :=
207 209 (
208 210 (1.0, -1.61171504942096, 1.0, 1.0, -1.68876443778669, 0.908610171614583),
209 211 (1.0, -1.53324505744412, 1.0, 1.0, -1.51088513595779, 0.732564401274351),
210 212 (1.0, -1.30646173160060, 1.0, 1.0, -1.30571711968384, 0.546869268827102),
211 213 (1.0, -0.651038739239370, 1.0, 1.0, -1.08747326287406, 0.358436944718464),
212 214 (1.0, 1.24322747034001, 1.0, 1.0, -0.929530176676438, 0.224862726961691)
213 215 );
214 216 CONSTANT f2_f3_gain : COEFF_CEL_REAL :=
215 217 ( 0.566196896119831, 0.474937156750133, 0.347712822970540, 0.200868393871900, 0.0910613125308450, 1.0);
216 218
217 219 CONSTANT coefs_iir_cel_f2_f3 : STD_LOGIC_VECTOR((f2_f3_CEL_NUMBER*f2_f3_COEFFICIENT_SIZE*5)-1 DOWNTO 0)
218 220 := get_IIR_CEL_FILTER_CONFIG(
219 221 f2_f3_COEFFICIENT_SIZE,
220 222 f2_f3_POINT_POSITION,
221 223 f2_f3_CEL_NUMBER,
222 224 f2_f3_sos,
223 225 f2_f3_gain);
224 226 -----------------------------------------------------------------------------
225 227
226 228 SIGNAL sample_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
227 229 SIGNAL sample_f0_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
228 230 SIGNAL sample_f1_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
229 231 SIGNAL sample_f2_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 232 SIGNAL sample_f3_time_reg : STD_LOGIC_VECTOR(47 DOWNTO 0);
231 233 SIGNAL sample_f0_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
232 234 SIGNAL sample_f1_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
233 235 -- SIGNAL sample_f2_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 236 -- SIGNAL sample_f3_time_s : STD_LOGIC_VECTOR(47 DOWNTO 0);
235 237 SIGNAL sample_filter_v2_out_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
236 238
237 239 BEGIN
238 240
239 241 -----------------------------------------------------------------------------
240 242 PROCESS (clk, rstn)
241 243 BEGIN -- PROCESS
242 244 IF rstn = '0' THEN -- asynchronous reset (active low)
243 245 sample_val_delay <= '0';
244 246 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
245 247 sample_val_delay <= sample_val;
246 248 END IF;
247 249 END PROCESS;
248 250
249 251 -----------------------------------------------------------------------------
250 252 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
251 253 SampleLoop : FOR j IN 0 TO 15 GENERATE
252 254 sample_filter_in(i, j) <= sample(i)(j);
253 255 END GENERATE;
254 256
255 257 sample_filter_in(i, 16) <= sample(i)(15);
256 258 sample_filter_in(i, 17) <= sample(i)(15);
257 259 END GENERATE;
258 260
259 261 coefs_v2 <= CoefsInitValCst_v2;
260 262
261 263 IIR_CEL_CTRLR_v2_1 : IIR_CEL_CTRLR_v2
262 264 GENERIC MAP (
263 265 tech => 0,
264 266 Mem_use => Mem_use, -- use_RAM
265 267 Sample_SZ => 18,
266 268 Coef_SZ => Coef_SZ,
267 269 Coef_Nb => 25,
268 270 Coef_sel_SZ => 5,
269 271 Cels_count => Cels_count,
270 272 ChanelsCount => ChanelCount)
271 273 PORT MAP (
272 274 rstn => rstn,
273 275 clk => clk,
274 276 virg_pos => 7,
275 277 coefs => coefs_v2,
276 278 sample_in_val => sample_val_delay,
277 279 sample_in => sample_filter_in,
278 280 sample_out_val => sample_filter_v2_out_val,
279 281 sample_out => sample_filter_v2_out);
280 282
281 283 -- TIME --
282 284 PROCESS (clk, rstn)
283 285 BEGIN -- PROCESS
284 286 IF rstn = '0' THEN -- asynchronous reset (active low)
285 287 sample_time_reg <= (OTHERS => '0');
286 288 sample_filter_v2_out_time <= (OTHERS => '0');
287 289 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
288 290 IF sample_val = '1' THEN
289 291 sample_time_reg <= sample_time;
290 292 END IF;
291 293 IF sample_filter_v2_out_val = '1' THEN
292 294 sample_filter_v2_out_time <= sample_time_reg;
293 295 END IF;
294 296 END IF;
295 297 END PROCESS;
296 298 ----------
299
300 --for simulation/observation-------------------------------------------------
301 ALL_channel_f0_sim: FOR I IN 0 TO ChanelCount-1 GENERATE
302 all_bit: FOR J IN 0 TO 17 GENERATE
303 PROCESS (clk, rstn)
304 BEGIN -- PROCESS
305 IF rstn = '0' THEN -- asynchronous reset (active low)
306 sample_filter_v2_out_sim(I,J) <= '0';
307 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
308 IF sample_filter_v2_out_val = '1' THEN
309 sample_filter_v2_out_sim(I,J) <= sample_filter_v2_out(I,J);
310 END IF;
311 END IF;
312 END PROCESS;
313 END GENERATE all_bit;
314 END GENERATE ALL_channel_f0_sim;
315 -----------------------------------------------------------------------------
297 316
298 317
299 318 -----------------------------------------------------------------------------
300 319 -- DATA_SHAPING
301 320 -----------------------------------------------------------------------------
302 321 all_data_shaping_in_loop : FOR I IN 17 DOWNTO 0 GENERATE
303 322 sample_data_shaping_f0_s(I) <= sample_filter_v2_out(0, I);
304 323 sample_data_shaping_f1_s(I) <= sample_filter_v2_out(1, I);
305 324 sample_data_shaping_f2_s(I) <= sample_filter_v2_out(2, I);
306 325 END GENERATE all_data_shaping_in_loop;
307 326
308 327 sample_data_shaping_f1_f0_s <= sample_data_shaping_f1_s - sample_data_shaping_f0_s;
309 328 sample_data_shaping_f2_f1_s <= sample_data_shaping_f2_s - sample_data_shaping_f1_s;
310 329
311 330 PROCESS (clk, rstn)
312 331 BEGIN -- PROCESS
313 332 IF rstn = '0' THEN -- asynchronous reset (active low)
314 333 sample_data_shaping_out_val <= '0';
315 334 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
316 335 sample_data_shaping_out_val <= sample_filter_v2_out_val;
317 336 END IF;
318 337 END PROCESS;
319 338
320 339 SampleLoop_data_shaping : FOR j IN 0 TO 17 GENERATE
321 340 PROCESS (clk, rstn)
322 341 BEGIN
323 342 IF rstn = '0' THEN
324 343 sample_data_shaping_out(0, j) <= '0';
325 344 sample_data_shaping_out(1, j) <= '0';
326 345 sample_data_shaping_out(2, j) <= '0';
327 346 sample_data_shaping_out(3, j) <= '0';
328 347 sample_data_shaping_out(4, j) <= '0';
329 348 sample_data_shaping_out(5, j) <= '0';
330 349 sample_data_shaping_out(6, j) <= '0';
331 350 sample_data_shaping_out(7, j) <= '0';
332 351 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
333 352 sample_data_shaping_out(0, j) <= sample_filter_v2_out(0, j);
334 353 IF data_shaping_SP0 = '1' THEN
335 354 sample_data_shaping_out(1, j) <= sample_data_shaping_f1_f0_s(j);
336 355 ELSE
337 356 sample_data_shaping_out(1, j) <= sample_filter_v2_out(1, j);
338 357 END IF;
339 358 IF data_shaping_SP1 = '1' THEN
340 359 sample_data_shaping_out(2, j) <= sample_data_shaping_f2_f1_s(j);
341 360 ELSE
342 361 sample_data_shaping_out(2, j) <= sample_filter_v2_out(2, j);
343 362 END IF;
344 363 sample_data_shaping_out(3, j) <= sample_filter_v2_out(3, j);
345 364 sample_data_shaping_out(4, j) <= sample_filter_v2_out(4, j);
346 365 sample_data_shaping_out(5, j) <= sample_filter_v2_out(5, j);
347 366 sample_data_shaping_out(6, j) <= sample_filter_v2_out(6, j);
348 367 sample_data_shaping_out(7, j) <= sample_filter_v2_out(7, j);
349 368 END IF;
350 369 END PROCESS;
351 370 END GENERATE;
352 371
353 372 sample_filter_v2_out_val_s <= sample_data_shaping_out_val;
354 373 ChanelLoopOut : FOR i IN 0 TO 7 GENERATE
355 374 SampleLoopOut : FOR j IN 0 TO 15 GENERATE
356 375 sample_filter_v2_out_s(i, j) <= sample_data_shaping_out(i, j);
357 376 END GENERATE;
358 377 END GENERATE;
359 378 -----------------------------------------------------------------------------
360 379 -- F0 -- @24.576 kHz
361 380 -----------------------------------------------------------------------------
362 381
363 382 Downsampling_f0 : Downsampling
364 383 GENERIC MAP (
365 384 ChanelCount => 8,
366 385 SampleSize => 16,
367 386 DivideParam => 4)
368 387 PORT MAP (
369 388 clk => clk,
370 389 rstn => rstn,
371 390 sample_in_val => sample_filter_v2_out_val_s,
372 391 sample_in => sample_filter_v2_out_s,
373 392 sample_out_val => sample_f0_val_s,
374 393 sample_out => sample_f0);
375 394
376 395 -- TIME --
377 396 PROCESS (clk, rstn)
378 397 BEGIN
379 398 IF rstn = '0' THEN
380 399 sample_f0_time_reg <= (OTHERS => '0');
381 400 ELSIF clk'event AND clk = '1' THEN
382 401 IF sample_f0_val_s = '1' THEN
383 402 sample_f0_time_reg <= sample_filter_v2_out_time;
384 403 END IF;
385 404 END IF;
386 405 END PROCESS;
387 406 sample_f0_time_s <= sample_filter_v2_out_time WHEN sample_f0_val_s = '1' ELSE sample_f0_time_reg;
388 407 sample_f0_time <= sample_f0_time_s;
389 408 ----------
390 409
391 410 sample_f0_val <= sample_f0_val_s;
392 411
393 412 all_bit_sample_f0 : FOR I IN 15 DOWNTO 0 GENERATE
394 413 sample_f0_wdata_s(I) <= sample_f0(0, I); -- V
395 414 sample_f0_wdata_s(16*1+I) <= sample_f0(1, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(3, I); -- E1
396 415 sample_f0_wdata_s(16*2+I) <= sample_f0(2, I) WHEN data_shaping_R0 = '1' ELSE sample_f0(4, I); -- E2
397 416 sample_f0_wdata_s(16*3+I) <= sample_f0(5, I); -- B1
398 417 sample_f0_wdata_s(16*4+I) <= sample_f0(6, I); -- B2
399 418 sample_f0_wdata_s(16*5+I) <= sample_f0(7, I); -- B3
400 419 END GENERATE all_bit_sample_f0;
401 420
402 421 -----------------------------------------------------------------------------
403 422 -- F1 -- @4096 Hz
404 423 -----------------------------------------------------------------------------
405 424
406 425 all_bit_sample_f0_f1 : FOR I IN 15 DOWNTO 0 GENERATE
407 426 sample_f0_f1_s(0,I) <= sample_f0(0,I); --V
408 427 sample_f0_f1_s(1,I) <= sample_f0(1,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,I); --E1
409 428 sample_f0_f1_s(2,I) <= sample_f0(2,I) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,I); --E2
410 429 sample_f0_f1_s(3,I) <= sample_f0(5,I); --B1
411 430 sample_f0_f1_s(4,I) <= sample_f0(6,I); --B2
412 431 sample_f0_f1_s(5,I) <= sample_f0(7,I); --B3
413 432 END GENERATE all_bit_sample_f0_f1;
414 433 all_bit_sample_f0_f1_extended : FOR I IN 17 DOWNTO 16 GENERATE
415 434 sample_f0_f1_s(0,I) <= sample_f0(0,15);
416 435 sample_f0_f1_s(1,I) <= sample_f0(1,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(3,15); --E1
417 436 sample_f0_f1_s(2,I) <= sample_f0(2,15) WHEN data_shaping_R1 = '1' ELSE sample_f0(4,15); --E2
418 437 sample_f0_f1_s(3,I) <= sample_f0(5,15); --B1
419 438 sample_f0_f1_s(4,I) <= sample_f0(6,15); --B2
420 439 sample_f0_f1_s(5,I) <= sample_f0(7,15); --B3
421 440 END GENERATE all_bit_sample_f0_f1_extended;
422 441
423 442
424 443 IIR_CEL_f0_to_f1 : IIR_CEL_CTRLR_v2
425 444 GENERIC MAP (
426 445 tech => 0,
427 446 Mem_use => Mem_use, -- use_RAM
428 447 Sample_SZ => 18,
429 448 Coef_SZ => f0_to_f1_COEFFICIENT_SIZE,
430 449 Coef_Nb => f0_to_f1_CEL_NUMBER*5,
431 450 Coef_sel_SZ => 5,
432 451 Cels_count => f0_to_f1_CEL_NUMBER,
433 452 ChanelsCount => 6)
434 453 PORT MAP (
435 454 rstn => rstn,
436 455 clk => clk,
437 456 virg_pos => f0_to_f1_POINT_POSITION,
438 457 coefs => coefs_iir_cel_f0_to_f1,
439 458
440 459 sample_in_val => sample_f0_val_s,
441 460 sample_in => sample_f0_f1_s,
442 461
443 462 sample_out_val => sample_f1_val_s,
444 463 sample_out => sample_f1_s);
445 464
446 465 Downsampling_f1 : Downsampling
447 466 GENERIC MAP (
448 467 ChanelCount => 6,
449 468 SampleSize => 18,
450 469 DivideParam => 6)
451 470 PORT MAP (
452 471 clk => clk,
453 472 rstn => rstn,
454 473 sample_in_val => sample_f1_val_s,
455 474 sample_in => sample_f1_s,
456 475 sample_out_val => sample_f1_val_ss,
457 476 sample_out => sample_f1);
458 477
459 478 sample_f1_val <= sample_f1_val_ss;
460 479
461 480 -- TIME --
462 481 PROCESS (clk, rstn)
463 482 BEGIN
464 483 IF rstn = '0' THEN
465 484 sample_f1_time_reg <= (OTHERS => '0');
466 485 ELSIF clk'event AND clk = '1' THEN
467 486 IF sample_f1_val_ss = '1' THEN
468 487 sample_f1_time_reg <= sample_f0_time_s;
469 488 END IF;
470 489 END IF;
471 490 END PROCESS;
472 491 sample_f1_time_s <= sample_f0_time_s WHEN sample_f1_val_ss = '1' ELSE sample_f1_time_reg;
473 492 sample_f1_time <= sample_f1_time_s;
474 493 ----------
475 494
476 495
477 496 all_bit_sample_f1 : FOR I IN 15 DOWNTO 0 GENERATE
478 497 all_channel_sample_f1: FOR J IN 5 DOWNTO 0 GENERATE
479 498 sample_f1_wdata_s(16*J+I) <= sample_f1(J, I);
480 499 END GENERATE all_channel_sample_f1;
481 500 END GENERATE all_bit_sample_f1;
482 501
483 502 -----------------------------------------------------------------------------
484 503 -- F2 -- @256 Hz
485 504 -- F3 -- @16 Hz
486 505 -----------------------------------------------------------------------------
487 506 all_bit_sample_f0_s : FOR I IN 15 DOWNTO 0 GENERATE
488 507 sample_f0_s(0, I) <= sample_f0(0, I); -- V
489 508 sample_f0_s(1, I) <= sample_f0(1, I); -- E1
490 509 sample_f0_s(2, I) <= sample_f0(2, I); -- E2
491 510 sample_f0_s(3, I) <= sample_f0(5, I); -- B1
492 511 sample_f0_s(4, I) <= sample_f0(6, I); -- B2
493 512 sample_f0_s(5, I) <= sample_f0(7, I); -- B3
494 513 sample_f0_s(6, I) <= sample_f0(3, I); --
495 514 sample_f0_s(7, I) <= sample_f0(4, I); --
496 515 END GENERATE all_bit_sample_f0_s;
497 516
498 517
499 518 cic_lfr_1: cic_lfr_r2
500 519 GENERIC MAP (
501 520 tech => 0,
502 521 use_RAM_nCEL => Mem_use)
503 522 PORT MAP (
504 523 clk => clk,
505 524 rstn => rstn,
506 525 run => '1',
507 526
508 527 param_r2 => data_shaping_R2,
509 528
510 529 data_in => sample_f0_s,
511 530 data_in_valid => sample_f0_val_s,
512 531
513 532 data_out_16 => sample_f2_cic,
514 533 data_out_16_valid => sample_f2_cic_val,
515 534
516 535 data_out_256 => sample_f3_cic,
517 536 data_out_256_valid => sample_f3_cic_val);
518 537
519 538
520 539
521 540 all_channel_sample_f_cic : FOR J IN 5 DOWNTO 0 GENERATE
522 541 all_bit_sample_f_cic : FOR I IN 15 DOWNTO 0 GENERATE
523 542 sample_f2_cic_filter(J,I) <= sample_f2_cic(J,I);
524 543 sample_f3_cic_filter(J,I) <= sample_f3_cic(J,I);
525 544 END GENERATE all_bit_sample_f_cic;
526 545 sample_f2_cic_filter(J,16) <= sample_f2_cic(J,15);
527 546 sample_f2_cic_filter(J,17) <= sample_f2_cic(J,15);
528 547
529 548 sample_f3_cic_filter(J,16) <= sample_f3_cic(J,15);
530 549 sample_f3_cic_filter(J,17) <= sample_f3_cic(J,15);
531 550 END GENERATE all_channel_sample_f_cic;
532 551
533 552
534 553 IIR_CEL_CTRLR_v3_1:IIR_CEL_CTRLR_v3
535 554 GENERIC MAP (
536 555 tech => 0,
537 556 Mem_use => Mem_use,
538 557 Sample_SZ => 18,
539 558 Coef_SZ => f2_f3_COEFFICIENT_SIZE,
540 559 Coef_Nb => f2_f3_CEL_NUMBER*5,
541 560 Coef_sel_SZ => 5,
542 561 Cels_count => f2_f3_CEL_NUMBER,
543 562 ChanelsCount => 6)
544 563 PORT MAP (
545 564 rstn => rstn,
546 565 clk => clk,
547 566 virg_pos => f2_f3_POINT_POSITION,
548 567 coefs => coefs_iir_cel_f2_f3,
549 568
550 569 sample_in1_val => sample_f2_cic_val,
551 570 sample_in1 => sample_f2_cic_filter,
552 571
553 572 sample_in2_val => sample_f3_cic_val,
554 573 sample_in2 => sample_f3_cic_filter,
555 574
556 575 sample_out1_val => sample_f2_filter_val,
557 576 sample_out1 => sample_f2_filter,
558 577 sample_out2_val => sample_f3_filter_val,
559 578 sample_out2 => sample_f3_filter);
560 579
561 580
562 581 all_channel_sample_f_filter : FOR J IN 5 DOWNTO 0 GENERATE
563 582 all_bit_sample_f_filter : FOR I IN 15 DOWNTO 0 GENERATE
564 583 sample_f2_cic_s(J,I) <= sample_f2_filter(J,I);
565 584 sample_f3_cic_s(J,I) <= sample_f3_filter(J,I);
566 585 END GENERATE all_bit_sample_f_filter;
567 586 END GENERATE all_channel_sample_f_filter;
568 587
569 588
570 589 -----------------------------------------------------------------------------
571 590
572 591 Downsampling_f2 : Downsampling
573 592 GENERIC MAP (
574 593 ChanelCount => 6,
575 594 SampleSize => 16,
576 595 DivideParam => 6)
577 596 PORT MAP (
578 597 clk => clk,
579 598 rstn => rstn,
580 599 sample_in_val => sample_f2_filter_val ,
581 600 sample_in => sample_f2_cic_s,
582 601 sample_out_val => sample_f2_val_s,
583 602 sample_out => sample_f2);
584 603
585 604 sample_f2_val <= sample_f2_val_s;
586 605
587 606 all_bit_sample_f2 : FOR I IN 15 DOWNTO 0 GENERATE
588 607 all_channel_sample_f2 : FOR J IN 5 DOWNTO 0 GENERATE
589 608 sample_f2_wdata_s(16*J+I) <= sample_f2(J,I);
590 609 END GENERATE all_channel_sample_f2;
591 610 END GENERATE all_bit_sample_f2;
592 611
593 612 -----------------------------------------------------------------------------
594 613
595 614 Downsampling_f3 : Downsampling
596 615 GENERIC MAP (
597 616 ChanelCount => 6,
598 617 SampleSize => 16,
599 618 DivideParam => 6)
600 619 PORT MAP (
601 620 clk => clk,
602 621 rstn => rstn,
603 622 sample_in_val => sample_f3_filter_val ,
604 623 sample_in => sample_f3_cic_s,
605 624 sample_out_val => sample_f3_val_s,
606 625 sample_out => sample_f3);
607 626 sample_f3_val <= sample_f3_val_s;
608 627
609 628 all_bit_sample_f3 : FOR I IN 15 DOWNTO 0 GENERATE
610 629 all_channel_sample_f3 : FOR J IN 5 DOWNTO 0 GENERATE
611 630 sample_f3_wdata_s(16*J+I) <= sample_f3(J,I);
612 631 END GENERATE all_channel_sample_f3;
613 632 END GENERATE all_bit_sample_f3;
614 633
615 634 -----------------------------------------------------------------------------
616 635
617 636 -- TIME --
618 637 PROCESS (clk, rstn)
619 638 BEGIN
620 639 IF rstn = '0' THEN
621 640 sample_f2_time_reg <= (OTHERS => '0');
622 641 sample_f3_time_reg <= (OTHERS => '0');
623 642 ELSIF clk'event AND clk = '1' THEN
624 643 IF sample_f2_val_s = '1' THEN sample_f2_time_reg <= sample_f0_time_s; END IF;
625 644 IF sample_f3_val_s = '1' THEN sample_f3_time_reg <= sample_f0_time_s; END IF;
626 645 END IF;
627 646 END PROCESS;
628 647 sample_f2_time <= sample_f0_time_s WHEN sample_f2_val_s = '1' ELSE sample_f2_time_reg;
629 648 sample_f3_time <= sample_f0_time_s WHEN sample_f3_val_s = '1' ELSE sample_f3_time_reg;
630 649 ----------
631 650
632 651 -----------------------------------------------------------------------------
633 652 --
634 653 -----------------------------------------------------------------------------
635 654 sample_f0_wdata <= sample_f0_wdata_s;
636 655 sample_f1_wdata <= sample_f1_wdata_s;
637 656 sample_f2_wdata <= sample_f2_wdata_s;
638 657 sample_f3_wdata <= sample_f3_wdata_s;
639 658
640 659 END tb;
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