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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe Pellion | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | ||||
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23 | LIBRARY IEEE; | |||
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24 | USE IEEE.STD_LOGIC_1164.ALL; | |||
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25 | USE IEEE.NUMERIC_STD.ALL; | |||
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26 | ||||
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27 | ||||
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28 | LIBRARY lpp; | |||
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29 | USE lpp.lpp_sim_pkg.ALL; | |||
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30 | USE lpp.lpp_lfr_sim_pkg.ALL; | |||
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31 | USE lpp.lpp_lfr_apbreg_pkg.ALL; | |||
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32 | USE lpp.lpp_lfr_management_apbreg_pkg.ALL; | |||
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33 | USE lpp.iir_filter.ALL; | |||
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34 | USE lpp.FILTERcfg.ALL; | |||
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35 | USE lpp.lpp_memory.ALL; | |||
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36 | USE lpp.lpp_waveform_pkg.ALL; | |||
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37 | USE lpp.lpp_dma_pkg.ALL; | |||
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38 | USE lpp.lpp_top_lfr_pkg.ALL; | |||
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39 | USE lpp.lpp_lfr_pkg.ALL; | |||
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40 | USE lpp.general_purpose.ALL; | |||
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41 | --LIBRARY lpp; | |||
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42 | USE lpp.lpp_ad_conv.ALL; | |||
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43 | --USE lpp.lpp_lfr_management_apbreg_pkg.ALL; | |||
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44 | --USE lpp.lpp_lfr_apbreg_pkg.ALL; | |||
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45 | ||||
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46 | --USE work.debug.ALL; | |||
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47 | ||||
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48 | LIBRARY gaisler; | |||
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49 | USE gaisler.libdcom.ALL; | |||
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50 | USE gaisler.sim.ALL; | |||
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51 | USE gaisler.memctrl.ALL; | |||
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52 | USE gaisler.leon3.ALL; | |||
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53 | USE gaisler.uart.ALL; | |||
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54 | USE gaisler.misc.ALL; | |||
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55 | USE gaisler.spacewire.ALL; | |||
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56 | ||||
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57 | ENTITY TB IS | |||
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58 | ||||
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59 | END TB; | |||
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60 | ||||
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61 | ARCHITECTURE beh OF TB IS | |||
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62 | ||||
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63 | CONSTANT USE_ESA_MEMCTRL : INTEGER := 0; | |||
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64 | ||||
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65 | COMPONENT LFR_EQM | |||
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66 | GENERIC ( | |||
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67 | Mem_use : INTEGER; | |||
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68 | USE_BOOTLOADER : INTEGER); | |||
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69 | PORT ( | |||
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70 | clk50MHz : IN STD_ULOGIC; | |||
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71 | clk49_152MHz : IN STD_ULOGIC; | |||
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72 | reset : IN STD_ULOGIC; | |||
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73 | TAG1 : IN STD_ULOGIC; | |||
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74 | TAG3 : OUT STD_ULOGIC; | |||
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75 | TAG2 : IN STD_ULOGIC; | |||
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76 | TAG4 : OUT STD_ULOGIC; | |||
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77 | address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0); | |||
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78 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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79 | nSRAM_MBE : INOUT STD_LOGIC; | |||
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80 | nSRAM_E1 : OUT STD_LOGIC; | |||
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81 | nSRAM_E2 : OUT STD_LOGIC; | |||
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82 | nSRAM_W : OUT STD_LOGIC; | |||
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83 | nSRAM_G : OUT STD_LOGIC; | |||
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84 | nSRAM_BUSY : IN STD_LOGIC; | |||
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85 | spw1_en : OUT STD_LOGIC; | |||
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86 | spw1_din : IN STD_LOGIC; | |||
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87 | spw1_sin : IN STD_LOGIC; | |||
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88 | spw1_dout : OUT STD_LOGIC; | |||
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89 | spw1_sout : OUT STD_LOGIC; | |||
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90 | spw2_en : OUT STD_LOGIC; | |||
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91 | spw2_din : IN STD_LOGIC; | |||
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92 | spw2_sin : IN STD_LOGIC; | |||
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93 | spw2_dout : OUT STD_LOGIC; | |||
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94 | spw2_sout : OUT STD_LOGIC; | |||
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95 | bias_fail_sw : OUT STD_LOGIC; | |||
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96 | ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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97 | ADC_smpclk : OUT STD_LOGIC; | |||
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98 | ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0); | |||
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99 | DAC_SDO : OUT STD_LOGIC; | |||
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100 | DAC_SCK : OUT STD_LOGIC; | |||
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101 | DAC_SYNC : OUT STD_LOGIC; | |||
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102 | DAC_CAL_EN : OUT STD_LOGIC; | |||
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103 | HK_smpclk : OUT STD_LOGIC; | |||
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104 | ADC_OEB_bar_HK : OUT STD_LOGIC; | |||
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105 | HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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106 | TAG8 : OUT STD_LOGIC); | |||
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107 | END COMPONENT; | |||
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108 | ||||
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109 | SIGNAL clk50MHz : STD_ULOGIC := '0'; | |||
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110 | SIGNAL clk49_152MHz : STD_ULOGIC := '0'; | |||
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111 | SIGNAL reset : STD_ULOGIC; | |||
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112 | SIGNAL TAG1 : STD_ULOGIC := '1'; | |||
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113 | SIGNAL TAG3 : STD_ULOGIC; | |||
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114 | SIGNAL TAG2 : STD_ULOGIC := '1'; | |||
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115 | SIGNAL TAG4 : STD_ULOGIC; | |||
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116 | SIGNAL address : STD_LOGIC_VECTOR(18 DOWNTO 0); | |||
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117 | SIGNAL data : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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118 | SIGNAL nSRAM_MBE : STD_LOGIC; | |||
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119 | SIGNAL nSRAM_E1 : STD_LOGIC; | |||
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120 | SIGNAL nSRAM_E2 : STD_LOGIC; | |||
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121 | SIGNAL nSRAM_W : STD_LOGIC; | |||
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122 | SIGNAL nSRAM_G : STD_LOGIC; | |||
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123 | SIGNAL nSRAM_BUSY : STD_LOGIC; | |||
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124 | SIGNAL spw1_en : STD_LOGIC; | |||
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125 | SIGNAL spw1_din : STD_LOGIC := '1'; | |||
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126 | SIGNAL spw1_sin : STD_LOGIC := '1'; | |||
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127 | SIGNAL spw1_dout : STD_LOGIC; | |||
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128 | SIGNAL spw1_sout : STD_LOGIC; | |||
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129 | SIGNAL spw2_en : STD_LOGIC; | |||
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130 | SIGNAL spw2_din : STD_LOGIC := '1'; | |||
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131 | SIGNAL spw2_sin : STD_LOGIC := '1'; | |||
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132 | SIGNAL spw2_dout : STD_LOGIC; | |||
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133 | SIGNAL spw2_sout : STD_LOGIC; | |||
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134 | SIGNAL bias_fail_sw : STD_LOGIC; | |||
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135 | SIGNAL ADC_OEB_bar_CH : STD_LOGIC_VECTOR(7 DOWNTO 0); | |||
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136 | SIGNAL ADC_smpclk : STD_LOGIC; | |||
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137 | SIGNAL ADC_data : STD_LOGIC_VECTOR(13 DOWNTO 0); | |||
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138 | SIGNAL DAC_SDO : STD_LOGIC; | |||
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139 | SIGNAL DAC_SCK : STD_LOGIC; | |||
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140 | SIGNAL DAC_SYNC : STD_LOGIC; | |||
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141 | SIGNAL DAC_CAL_EN : STD_LOGIC; | |||
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142 | SIGNAL HK_smpclk : STD_LOGIC; | |||
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143 | SIGNAL ADC_OEB_bar_HK : STD_LOGIC; | |||
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144 | SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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145 | SIGNAL TAG8 : STD_LOGIC; | |||
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146 | ||||
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147 | CONSTANT SCRUB_RATE_PERIOD : INTEGER := 1800/20; | |||
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148 | CONSTANT SCRUB_PERIOD : INTEGER := 200/20; | |||
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149 | CONSTANT SCRUB_BUSY_TO_SCRUB : INTEGER := 700/20; | |||
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150 | CONSTANT SCRUB_SCRUB_TO_BUSY : INTEGER := 60/20; | |||
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151 | SIGNAL counter_scrub_period : INTEGER; | |||
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152 | ||||
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153 | ||||
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154 | --CONSTANT AHBADDR_APB : STD_LOGIC_VECTOR(11 DOWNTO 0) := X"800"; | |||
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155 | --CONSTANT AHBADDR_LFR_MANAGEMENT : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"006"; | |||
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156 | --CONSTANT AHBADDR_LFR : STD_LOGIC_VECTOR(23 DOWNTO 0) := AHBADDR_APB & X"00F"; | |||
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157 | ||||
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158 | CONSTANT ADDR_BASE_DSU : STD_LOGIC_VECTOR(31 DOWNTO 24) := X"90"; | |||
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159 | CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F"; | |||
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160 | CONSTANT ADDR_BASE_LFR_2 : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000E"; | |||
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161 | CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006"; | |||
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162 | CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B"; | |||
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163 | CONSTANT ADDR_BASE_ESA_MEMCTRL : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800000"; | |||
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164 | ||||
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165 | SIGNAL message_simu : STRING(1 TO 15) := "---------------"; | |||
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166 | SIGNAL data_message : STRING(1 TO 15) := "---------------"; | |||
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167 | SIGNAL data_read : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0'); | |||
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168 | SIGNAL TXD1 : STD_LOGIC; | |||
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169 | SIGNAL RXD1 : STD_LOGIC; | |||
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170 | ||||
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171 | ----------------------------------------------------------------------------- | |||
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172 | CONSTANT ADDR_BUFFER_WFP_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40100000"; | |||
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173 | CONSTANT ADDR_BUFFER_WFP_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40110000"; | |||
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174 | CONSTANT ADDR_BUFFER_WFP_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40120000"; | |||
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175 | CONSTANT ADDR_BUFFER_WFP_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40130000"; | |||
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176 | CONSTANT ADDR_BUFFER_WFP_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40140000"; | |||
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177 | CONSTANT ADDR_BUFFER_WFP_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40150000"; | |||
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178 | CONSTANT ADDR_BUFFER_WFP_F3_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40160000"; | |||
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179 | CONSTANT ADDR_BUFFER_WFP_F3_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40170000"; | |||
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180 | CONSTANT ADDR_BUFFER_MS_F0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40180000"; | |||
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181 | CONSTANT ADDR_BUFFER_MS_F0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"40190000"; | |||
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182 | CONSTANT ADDR_BUFFER_MS_F1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401A0000"; | |||
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183 | CONSTANT ADDR_BUFFER_MS_F1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401B0000"; | |||
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184 | CONSTANT ADDR_BUFFER_MS_F2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401C0000"; | |||
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185 | CONSTANT ADDR_BUFFER_MS_F2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0) := X"401D0000"; | |||
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186 | ||||
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187 | ||||
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188 | TYPE sample_vector_16b IS ARRAY (NATURAL RANGE <> , NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0); | |||
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189 | SIGNAL sample : sample_vector_16b(2 DOWNTO 0, 5 DOWNTO 0); | |||
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190 | ||||
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191 | TYPE counter_vector IS ARRAY (NATURAL RANGE <>) OF INTEGER; | |||
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192 | SIGNAL sample_counter : counter_vector( 2 DOWNTO 0); | |||
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193 | ||||
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194 | SIGNAL data_pre_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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195 | SIGNAL data_pre_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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196 | SIGNAL data_pre_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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197 | SIGNAL error_wfp : STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
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198 | ||||
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199 | SIGNAL addr_pre_f0 : STD_LOGIC_VECTOR(13 DOWNTO 0); | |||
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200 | SIGNAL addr_pre_f1 : STD_LOGIC_VECTOR(13 DOWNTO 0); | |||
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201 | SIGNAL addr_pre_f2 : STD_LOGIC_VECTOR(13 DOWNTO 0); | |||
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202 | ||||
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203 | ||||
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204 | SIGNAL error_wfp_addr : STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
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205 | ----------------------------------------------------------------------------- | |||
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206 | CONSTANT srambanks : INTEGER := 2; | |||
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207 | CONSTANT sramwidth : INTEGER := 32; | |||
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208 | CONSTANT sramdepth : INTEGER := 19; | |||
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209 | CONSTANT sramfile : STRING := "prom.srec"; | |||
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210 | SIGNAL ramsn : STD_LOGIC_VECTOR(srambanks-1 DOWNTO 0); | |||
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211 | ----------------------------------------------------------------------------- | |||
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212 | ||||
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213 | BEGIN -- beh | |||
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214 | ||||
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215 | LFR_EQM_1 : LFR_EQM | |||
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216 | GENERIC MAP ( | |||
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217 | Mem_use => use_RAM, | |||
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218 | USE_BOOTLOADER => 0) | |||
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219 | PORT MAP ( | |||
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220 | clk50MHz => clk50MHz, --IN --ok | |||
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221 | clk49_152MHz => clk49_152MHz, --in --ok | |||
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222 | reset => reset, --IN --ok | |||
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223 | ||||
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224 | TAG1 => TAG1, --in | |||
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225 | TAG3 => TAG3, --out | |||
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226 | TAG2 => TAG2, --IN --ok | |||
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227 | TAG4 => TAG4, --out --ok | |||
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228 | ||||
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229 | address => address, --out | |||
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230 | data => data, --inout | |||
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231 | nSRAM_MBE => nSRAM_MBE, --inout | |||
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232 | nSRAM_E1 => nSRAM_E1, --out | |||
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233 | nSRAM_E2 => nSRAM_E2, --out | |||
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234 | nSRAM_W => nSRAM_W, --out | |||
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235 | nSRAM_G => nSRAM_G, --out | |||
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236 | nSRAM_BUSY => nSRAM_BUSY, --in | |||
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237 | ||||
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238 | spw1_en => spw1_en, --out --ok | |||
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239 | spw1_din => spw1_din, --in --ok | |||
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240 | spw1_sin => spw1_sin, --in --ok | |||
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241 | spw1_dout => spw1_dout, --out --ok | |||
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242 | spw1_sout => spw1_sout, --out --ok | |||
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243 | ||||
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244 | spw2_en => spw2_en, --out --ok | |||
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245 | spw2_din => spw2_din, --in --ok | |||
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246 | spw2_sin => spw2_sin, --in --ok | |||
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247 | spw2_dout => spw2_dout, --out --ok | |||
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248 | spw2_sout => spw2_sout, --out --ok | |||
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249 | ||||
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250 | bias_fail_sw => bias_fail_sw, --OUT --ok | |||
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251 | ||||
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252 | ADC_OEB_bar_CH => ADC_OEB_bar_CH, --out --ok | |||
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253 | ADC_smpclk => ADC_smpclk, --out --ok | |||
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254 | ADC_data => ADC_data, --IN --ok | |||
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255 | ||||
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256 | DAC_SDO => DAC_SDO, --out --ok | |||
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257 | DAC_SCK => DAC_SCK, --out --ok | |||
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258 | DAC_SYNC => DAC_SYNC, --out --ok | |||
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259 | DAC_CAL_EN => DAC_CAL_EN, --out --ok | |||
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260 | ||||
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261 | HK_smpclk => HK_smpclk, --out --ok | |||
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262 | ADC_OEB_bar_HK => ADC_OEB_bar_HK, --out --ok | |||
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263 | HK_SEL => HK_SEL, --out --ok | |||
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264 | TAG8 => TAG8); --out --ok | |||
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265 | ||||
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266 | ||||
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267 | ----------------------------------------------------------------------------- | |||
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268 | clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz | |||
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269 | clk50MHz <= NOT clk50MHz AFTER 10 ns; -- 50 MHz | |||
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270 | ----------------------------------------------------------------------------- | |||
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271 | ||||
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272 | MODULE_RHF1401 : FOR I IN 0 TO 7 GENERATE | |||
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273 | TestModule_RHF1401_1 : TestModule_RHF1401 | |||
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274 | GENERIC MAP ( | |||
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275 | freq => 24*(I+1), | |||
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276 | amplitude => 8000/(I+1), | |||
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277 | impulsion => 0) | |||
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278 | PORT MAP ( | |||
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279 | ADC_smpclk => ADC_smpclk, | |||
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280 | ADC_OEB_bar => ADC_OEB_bar_CH(I), | |||
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281 | ADC_data => ADC_data); | |||
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282 | END GENERATE MODULE_RHF1401; | |||
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283 | ||||
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284 | ----------------------------------------------------------------------------- | |||
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285 | PROCESS (clk50MHz, reset) | |||
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286 | BEGIN -- PROCESS | |||
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287 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
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288 | nSRAM_BUSY <= '1'; | |||
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289 | counter_scrub_period <= 0; | |||
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290 | ELSIF clk50MHz'EVENT AND clk50MHz = '1' THEN -- rising clock edge | |||
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291 | IF SCRUB_RATE_PERIOD + SCRUB_PERIOD < counter_scrub_period THEN | |||
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292 | counter_scrub_period <= 0; | |||
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293 | ELSE | |||
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294 | counter_scrub_period <= counter_scrub_period + 1; | |||
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295 | END IF; | |||
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296 | ||||
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297 | IF counter_scrub_period < (SCRUB_RATE_PERIOD + SCRUB_PERIOD) - (SCRUB_PERIOD + SCRUB_BUSY_TO_SCRUB + SCRUB_SCRUB_TO_BUSY) THEN | |||
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298 | nSRAM_BUSY <= '1'; | |||
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299 | ELSE | |||
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300 | nSRAM_BUSY <= '0'; | |||
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301 | END IF; | |||
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302 | END IF; | |||
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303 | END PROCESS; | |||
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304 | ||||
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305 | ----------------------------------------------------------------------------- | |||
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306 | -- TB | |||
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307 | ----------------------------------------------------------------------------- | |||
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308 | TAG1 <= TXD1; | |||
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309 | RXD1 <= TAG3; | |||
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310 | ||||
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311 | PROCESS | |||
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312 | CONSTANT txp : TIME := 320 ns; | |||
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313 | VARIABLE data_read_v : STD_LOGIC_VECTOR(31 DOWNTO 0); | |||
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314 | BEGIN -- PROCESS | |||
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315 | TXD1 <= '1'; | |||
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316 | reset <= '0'; | |||
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317 | WAIT FOR 500 ns; | |||
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318 | reset <= '1'; | |||
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319 | WAIT FOR 10000 ns; | |||
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320 | message_simu <= "0 - UART init "; | |||
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321 | UART_INIT(TXD1, txp); | |||
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322 | ||||
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323 | --------------------------------------------------------------------------- | |||
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324 | -- LAUNCH leon 3 software | |||
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325 | --------------------------------------------------------------------------- | |||
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326 | message_simu <= "2- GO Leon3...."; | |||
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327 | ||||
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328 | -- bool dsu3plugin::configureTarget() --------------------------------------------------------------------------------------------------------------------------- | |||
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329 | --Force a debug break | |||
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330 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"0000002f"); --WriteRegs(uIntlist()<<,(unsigned int)DSUBASEADDRESS); | |||
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331 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000ffff,(unsigned int)DSUBASEADDRESS+0x20); | |||
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332 | --Clear time tag counter | |||
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333 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x8); | |||
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334 | --Clear ASR registers | |||
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335 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400040); | |||
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336 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "01", X"00000000"); | |||
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337 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "10", X"00000000"); | |||
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338 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<0x2,(unsigned int)DSUBASEADDRESS+0x400024); | |||
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339 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); | |||
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340 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); | |||
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341 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); | |||
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342 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); | |||
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343 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "00", X"00000000"); | |||
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344 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "01", X"00000000"); | |||
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345 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "10", X"00000000"); | |||
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346 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"7" & "11", X"00000000"); | |||
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347 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "10", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x48); | |||
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348 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"4" & "11", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x000004C); | |||
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349 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"4" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,(unsigned int)DSUBASEADDRESS+0x400040); | |||
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350 | ||||
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351 | IF USE_ESA_MEMCTRL = 1 THEN | |||
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352 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000000", X"000002FF"); --WriteRegs(uIntlist()<<0x2FF<<0xE60<<0,(unsigned int)MCTRLBASEADDRESS); | |||
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353 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000001", X"00000E60"); | |||
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354 | UART_WRITE(TXD1, txp, ADDR_BASE_ESA_MEMCTRL & "000010", X"00000000"); | |||
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355 | END IF; | |||
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356 | ||||
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357 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x400060); | |||
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358 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "01", X"00000000"); | |||
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359 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "10", X"00000000"); | |||
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360 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"6" & "11", X"00000000"); | |||
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361 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "01", X"0000ffff"); --WriteRegs(uIntlist()<<0x0000FFFF,(unsigned int)DSUBASEADDRESS+0x24); | |||
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362 | ||||
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363 | --memSet(DSUBASEADDRESS+0x300000,0,1567); | |||
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364 | ||||
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365 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0xF30000E0<<0x00000002<<0x40000000<<0x40000000<<0x40000004<<0x1000000,(unsigned int)DSUBASEADDRESS+0x400000); | |||
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366 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "01", X"F30000E0"); | |||
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367 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "10", X"00000002"); | |||
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368 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"0" & "11", X"40000000"); | |||
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369 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "00", X"40000000"); | |||
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370 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "01", X"40000004"); | |||
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371 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"1" & "10", X"10000000"); | |||
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372 | ||||
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373 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0<<0<<0<<0<<0<<0<<0x403ffff0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0<<0,(unsigned int)DSUBASEADDRESS+0x300020); | |||
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374 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "01", X"00000000"); | |||
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375 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "10", X"00000000"); | |||
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376 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"2" & "11", X"00000000"); | |||
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377 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "00", X"00000000"); | |||
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378 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "01", X"00000000"); | |||
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379 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "10", X"403ffff0"); | |||
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380 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"3" & "11", X"00000000"); | |||
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381 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "00", X"00000000"); | |||
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382 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "01", X"00000000"); | |||
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383 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "10", X"00000000"); | |||
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384 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"4" & "11", X"00000000"); | |||
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385 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "00", X"00000000"); | |||
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386 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "01", X"00000000"); | |||
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387 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "10", X"00000000"); | |||
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388 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"5" & "11", X"00000000"); | |||
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389 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "00", X"00000000"); | |||
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390 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "01", X"00000000"); | |||
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391 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "10", X"00000000"); | |||
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392 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"6" & "11", X"00000000"); | |||
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393 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "00", X"00000000"); | |||
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394 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "01", X"00000000"); | |||
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395 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "10", X"00000000"); | |||
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396 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"3000" & X"7" & "11", X"00000000"); | |||
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397 | ||||
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398 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"0" & "00", X"000002EF"); --WriteRegs(uIntlist()<<0x000002EF,(unsigned int)DSUBASEADDRESS); | |||
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399 | ||||
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400 | --//Disable interrupts | |||
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401 | --unsigned int APBIRQCTRLRBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x0d,0); | |||
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402 | --if(APBIRQCTRLRBASEADD == (unsigned int)-1) | |||
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403 | -- return false; | |||
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404 | --WriteRegs(uIntlist()<<0x00000000,APBIRQCTRLRBASEADD+0x040); | |||
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405 | --WriteRegs(uIntlist()<<0xFFFE0000,APBIRQCTRLRBASEADD+0x080); | |||
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406 | --WriteRegs(uIntlist()<<0<<0,APBIRQCTRLRBASEADD); | |||
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407 | ||||
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408 | -- //Set up timer | |||
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409 | --unsigned int APBTIMERBASEADD = (unsigned int)SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,1,0x11,0); | |||
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410 | --if(APBTIMERBASEADD == (unsigned int)-1) | |||
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411 | -- return false; | |||
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412 | --WriteRegs(uIntlist()<<0xffffffff,APBTIMERBASEADD+0x014); | |||
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413 | --WriteRegs(uIntlist()<<0x00000018,APBTIMERBASEADD+0x04); | |||
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414 | --WriteRegs(uIntlist()<<0x00000007,APBTIMERBASEADD+0x018); | |||
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415 | ||||
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416 | ||||
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417 | --------------------------------------------------------------------------- | |||
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418 | --bool dsu3plugin::setCacheEnable(bool enabled) | |||
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419 | --unsigned int DSUBASEADDRESS = SocExplorerEngine::self()->getEnumDeviceBaseAddress(this,0x01 , 0x004,0); | |||
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420 | --if(DSUBASEADDRESS == (unsigned int)-1) DSUBASEADDRESS = 0x90000000; | |||
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421 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"4000" & X"2" & "01", X"00000002"); --WriteRegs(uIntlist()<<2,DSUBASEADDRESS+0x400024); | |||
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422 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00", data_read_v);--unsigned int reg = ReadReg(DSUBASEADDRESS+0x700000); | |||
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423 | data_read <= data_read_v; | |||
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424 | --if(enabled){ | |||
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425 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0001000F"); --WriteRegs(uIntlist()<<(0x0001000F|reg),DSUBASEADDRESS+0x700000); | |||
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426 | UART_WRITE(TXD1, txp, ADDR_BASE_DSU & X"7000" & X"0" & "00" , data_read_v OR X"0061000F"); --WriteRegs(uIntlist()<<(0x0061000F|reg),DSUBASEADDRESS+0x700000); | |||
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427 | --}else{ | |||
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428 | --WriteRegs(uIntlist()<<((!0x0001000F)®),DSUBASEADDRESS+0x700000); | |||
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429 | --WriteRegs(uIntlist()<<(0x00600000|reg),DSUBASEADDRESS+0x700000); | |||
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430 | --} | |||
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|
431 | ||||
|
|
432 | ||||
|
|
433 | -- void dsu3plugin::run() --------------------------------------------------------------------------------------------------------------------------------------- | |||
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434 | UART_WRITE(TXD1 , txp, ADDR_BASE_DSU & X"0000" & X"2" & "00", X"00000000"); --WriteRegs(uIntlist()<<0,DSUBASEADDRESS+0x020); | |||
|
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435 | ||||
|
|
436 | --------------------------------------------------------------------------- | |||
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|
437 | --message_simu <= "1 - UART test "; | |||
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438 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000010", X"0000FFFF"); | |||
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439 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000A0A"); | |||
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440 | --UART_WRITE(TXD1, txp, ADDR_BASE_GPIO & "000001", X"00000B0B"); | |||
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441 | --UART_READ(TXD1, RXD1, txp, ADDR_BASE_GPIO & "000001", data_read_v); | |||
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442 | --data_read <= data_read_v; | |||
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443 | --data_message <= "GPIO_data_write"; | |||
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444 | ||||
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445 | -- UNSET the LFR reset | |||
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446 | message_simu <= "2 - LFR UNRESET"; | |||
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447 | UNRESET_LFR(TXD1, txp, ADDR_BASE_TIME_MANAGMENT); | |||
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448 | -- | |||
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449 | message_simu <= "3 - LFR CONFIG "; | |||
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450 | LAUNCH_SPECTRAL_MATRIX(TXD1, RXD1, txp, ADDR_BASE_LFR, | |||
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451 | ADDR_BUFFER_MS_F0_0, | |||
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452 | ADDR_BUFFER_MS_F0_1, | |||
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453 | ADDR_BUFFER_MS_F1_0, | |||
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454 | ADDR_BUFFER_MS_F1_1, | |||
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455 | ADDR_BUFFER_MS_F2_0, | |||
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456 | ADDR_BUFFER_MS_F2_1); | |||
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457 | ||||
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458 | ||||
|
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459 | LAUNCH_WAVEFORM_PICKER(TXD1, RXD1, txp, | |||
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460 | LFR_MODE_SBM1, | |||
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461 | X"7FFFFFFF", -- START DATE | |||
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462 | ||||
|
|
463 | "00000", --DATA_SHAPING ( 4 DOWNTO 0) | |||
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464 | X"00012BFF", --DELTA_SNAPSHOT(31 DOWNTO 0) | |||
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465 | X"0001280A", --DELTA_F0 (31 DOWNTO 0) | |||
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466 | X"00000007", --DELTA_F0_2 (31 DOWNTO 0) | |||
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467 | X"0001283F", --DELTA_F1 (31 DOWNTO 0) | |||
|
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468 | X"000127FF", --DELTA_F2 (31 DOWNTO 0) | |||
|
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469 | ||||
|
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470 | ADDR_BASE_LFR, | |||
|
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471 | ADDR_BUFFER_WFP_F0_0, | |||
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472 | ADDR_BUFFER_WFP_F0_1, | |||
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473 | ADDR_BUFFER_WFP_F1_0, | |||
|
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474 | ADDR_BUFFER_WFP_F1_1, | |||
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475 | ADDR_BUFFER_WFP_F2_0, | |||
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476 | ADDR_BUFFER_WFP_F2_1, | |||
|
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477 | ADDR_BUFFER_WFP_F3_0, | |||
|
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478 | ADDR_BUFFER_WFP_F3_1); | |||
|
|
479 | ||||
|
|
480 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_LENGTH, X"0000000F"); | |||
|
|
481 | UART_WRITE(TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); | |||
|
|
482 | ||||
|
|
483 | ||||
|
|
484 | --------------------------------------------------------------------------- | |||
|
|
485 | -- CONFIG LFR 2 | |||
|
|
486 | --------------------------------------------------------------------------- | |||
|
|
487 | --message_simu <= "3 - LFR2 CONFIG"; | |||
|
|
488 | --LAUNCH_SPECTRAL_MATRIX(TXD1,RXD1,txp,ADDR_BASE_LFR_2, | |||
|
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489 | -- X"40000000", | |||
|
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490 | -- X"40001000", | |||
|
|
491 | -- X"40002000", | |||
|
|
492 | -- X"40003000", | |||
|
|
493 | -- X"40004000", | |||
|
|
494 | -- X"40005000"); | |||
|
|
495 | ||||
|
|
496 | ||||
|
|
497 | --LAUNCH_WAVEFORM_PICKER(TXD1,RXD1,txp, | |||
|
|
498 | -- LFR_MODE_SBM1, | |||
|
|
499 | -- X"7FFFFFFF", -- START DATE | |||
|
|
500 | ||||
|
|
501 | -- "00000",--DATA_SHAPING ( 4 DOWNTO 0) | |||
|
|
502 | -- X"00012BFF",--DELTA_SNAPSHOT(31 DOWNTO 0) | |||
|
|
503 | -- X"0001280A",--DELTA_F0 (31 DOWNTO 0) | |||
|
|
504 | -- X"00000007",--DELTA_F0_2 (31 DOWNTO 0) | |||
|
|
505 | -- X"0001283F",--DELTA_F1 (31 DOWNTO 0) | |||
|
|
506 | -- X"000127FF",--DELTA_F2 (31 DOWNTO 0) | |||
|
|
507 | ||||
|
|
508 | -- ADDR_BASE_LFR_2, | |||
|
|
509 | -- X"40006000", | |||
|
|
510 | -- X"40007000", | |||
|
|
511 | -- X"40008000", | |||
|
|
512 | -- X"40009000", | |||
|
|
513 | -- X"4000A000", | |||
|
|
514 | -- X"4000B000", | |||
|
|
515 | -- X"4000C000", | |||
|
|
516 | -- X"4000D000"); | |||
|
|
517 | ||||
|
|
518 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_LENGTH, X"0000000F"); | |||
|
|
519 | --UART_WRITE(TXD1 ,txp,ADDR_BASE_LFR_2 & ADDR_LFR_WP_DATA_IN_BUFFER, X"00000050"); | |||
|
|
520 | ||||
|
|
521 | --------------------------------------------------------------------------- | |||
|
|
522 | --------------------------------------------------------------------------- | |||
|
|
523 | ||||
|
|
524 | ||||
|
|
525 | message_simu <= "4 - GO GO GO !!"; | |||
|
|
526 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR & ADDR_LFR_WP_START_DATE, X"00000000"); | |||
|
|
527 | UART_WRITE (TXD1 , txp, ADDR_BASE_LFR_2 & ADDR_LFR_WP_START_DATE, X"00000000"); | |||
|
|
528 | ||||
|
|
529 | READ_STATUS : LOOP | |||
|
|
530 | WAIT FOR 2 ms; | |||
|
|
531 | data_message <= "READ_NEW_STATUS"; | |||
|
|
532 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |||
|
|
533 | data_read <= data_read_v; | |||
|
|
534 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_SM_STATUS, data_read_v); | |||
|
|
535 | ||||
|
|
536 | UART_READ(TXD1, RXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |||
|
|
537 | data_read <= data_read_v; | |||
|
|
538 | UART_WRITE(TXD1, txp, ADDR_BASE_LFR & ADDR_LFR_WP_STATUS, data_read_v); | |||
|
|
539 | END LOOP READ_STATUS; | |||
|
|
540 | ||||
|
|
541 | WAIT; | |||
|
|
542 | END PROCESS; | |||
|
|
543 | ||||
|
|
544 | ||||
|
|
545 | ----------------------------------------------------------------------------- | |||
|
|
546 | PROCESS (nSRAM_W, reset) | |||
|
|
547 | BEGIN -- PROCESS | |||
|
|
548 | IF reset = '0' THEN -- asynchronous reset (active low) | |||
|
|
549 | data_pre_f0 <= X"00020001"; | |||
|
|
550 | data_pre_f1 <= X"00020001"; | |||
|
|
551 | data_pre_f2 <= X"00020001"; | |||
|
|
552 | ||||
|
|
553 | addr_pre_f0 <= (OTHERS => '0'); | |||
|
|
554 | addr_pre_f1 <= (OTHERS => '0'); | |||
|
|
555 | addr_pre_f2 <= (OTHERS => '0'); | |||
|
|
556 | ||||
|
|
557 | error_wfp <= "000"; | |||
|
|
558 | error_wfp_addr <= "000"; | |||
|
|
559 | ||||
|
|
560 | sample_counter <= (0,0,0); | |||
|
|
561 | ||||
|
|
562 | ELSIF nSRAM_W'EVENT AND nSRAM_W = '0' THEN -- rising clock edge | |||
|
|
563 | error_wfp <= "000"; | |||
|
|
564 | error_wfp_addr <= "000"; | |||
|
|
565 | ------------------------------------------------------------------------- | |||
|
|
566 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_0(20 DOWNTO 16) OR | |||
|
|
567 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F0_1(20 DOWNTO 16) THEN | |||
|
|
568 | ||||
|
|
569 | addr_pre_f0 <= address(13 DOWNTO 0); | |||
|
|
570 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f0))+1) THEN | |||
|
|
571 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN | |||
|
|
572 | error_wfp_addr(0) <= '1'; | |||
|
|
573 | END IF; | |||
|
|
574 | END IF; | |||
|
|
575 | ||||
|
|
576 | data_pre_f0 <= data; | |||
|
|
577 | CASE data_pre_f0 IS | |||
|
|
578 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(0) <= '1'; END IF; | |||
|
|
579 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(0) <= '1'; END IF; | |||
|
|
580 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(0) <= '1'; END IF; | |||
|
|
581 | WHEN OTHERS => error_wfp(0) <= '1'; | |||
|
|
582 | END CASE; | |||
|
|
583 | ||||
|
|
584 | ||||
|
|
585 | END IF; | |||
|
|
586 | ------------------------------------------------------------------------- | |||
|
|
587 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_0(20 DOWNTO 16) OR | |||
|
|
588 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F1_1(20 DOWNTO 16) THEN | |||
|
|
589 | ||||
|
|
590 | addr_pre_f1 <= address(13 DOWNTO 0); | |||
|
|
591 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f1))+1) THEN | |||
|
|
592 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN | |||
|
|
593 | error_wfp_addr(1) <= '1'; | |||
|
|
594 | END IF; | |||
|
|
595 | END IF; | |||
|
|
596 | ||||
|
|
597 | data_pre_f1 <= data; | |||
|
|
598 | CASE data_pre_f1 IS | |||
|
|
599 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(1) <= '1'; END IF; | |||
|
|
600 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(1) <= '1'; END IF; | |||
|
|
601 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(1) <= '1'; END IF; | |||
|
|
602 | WHEN OTHERS => error_wfp(1) <= '1'; | |||
|
|
603 | END CASE; | |||
|
|
604 | ||||
|
|
605 | sample(1,0 + sample_counter(1)*2) <= data(31 DOWNTO 16); | |||
|
|
606 | sample(1,1 + sample_counter(1)*2) <= data(15 DOWNTO 0); | |||
|
|
607 | sample_counter(1) <= (sample_counter(1) + 1) MOD 3; | |||
|
|
608 | ||||
|
|
609 | END IF; | |||
|
|
610 | ------------------------------------------------------------------------- | |||
|
|
611 | IF address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_0(20 DOWNTO 16) OR | |||
|
|
612 | address(18 DOWNTO 14) = ADDR_BUFFER_WFP_F2_1(20 DOWNTO 16) THEN | |||
|
|
613 | ||||
|
|
614 | addr_pre_f2 <= address(13 DOWNTO 0); | |||
|
|
615 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= (to_integer(UNSIGNED(addr_pre_f2))+1) THEN | |||
|
|
616 | IF to_integer(UNSIGNED(address(13 DOWNTO 0))) /= 0 THEN | |||
|
|
617 | error_wfp_addr(2) <= '1'; | |||
|
|
618 | END IF; | |||
|
|
619 | END IF; | |||
|
|
620 | ||||
|
|
621 | data_pre_f2 <= data; | |||
|
|
622 | CASE data_pre_f2 IS | |||
|
|
623 | WHEN X"00200010" => IF data /= X"00080004" THEN error_wfp(2) <= '1'; END IF; | |||
|
|
624 | WHEN X"00080004" => IF data /= X"00020001" THEN error_wfp(2) <= '1'; END IF; | |||
|
|
625 | WHEN X"00020001" => IF data /= X"00200010" THEN error_wfp(2) <= '1'; END IF; | |||
|
|
626 | WHEN OTHERS => error_wfp(2) <= '1'; | |||
|
|
627 | END CASE; | |||
|
|
628 | ||||
|
|
629 | sample(2,0 + sample_counter(2)*2) <= data(31 DOWNTO 16); | |||
|
|
630 | sample(2,1 + sample_counter(2)*2) <= data(15 DOWNTO 0); | |||
|
|
631 | sample_counter(2) <= (sample_counter(2) + 1) MOD 3; | |||
|
|
632 | ||||
|
|
633 | END IF; | |||
|
|
634 | END IF; | |||
|
|
635 | END PROCESS; | |||
|
|
636 | ----------------------------------------------------------------------------- | |||
|
|
637 | ramsn(1 DOWNTO 0) <= nSRAM_E2 & nSRAM_E1; | |||
|
|
638 | ||||
|
|
639 | sbanks : FOR k IN 0 TO srambanks-1 GENERATE | |||
|
|
640 | sram0 : FOR i IN 0 TO (sramwidth/8)-1 GENERATE | |||
|
|
641 | sr0 : sram | |||
|
|
642 | GENERIC MAP ( | |||
|
|
643 | index => i, | |||
|
|
644 | abits => sramdepth, | |||
|
|
645 | fname => sramfile) | |||
|
|
646 | PORT MAP ( | |||
|
|
647 | address, | |||
|
|
648 | data(31-i*8 DOWNTO 24-i*8), | |||
|
|
649 | ramsn(k), | |||
|
|
650 | nSRAM_W, | |||
|
|
651 | nSRAM_G | |||
|
|
652 | ); | |||
|
|
653 | END GENERATE; | |||
|
|
654 | END GENERATE; | |||
|
|
655 | ||||
|
|
656 | END beh; | |||
|
|
657 | ||||
| @@ -0,0 +1,199 | |||||
|
|
1 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_pkg.vhd | |||
|
|
2 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd | |||
|
|
3 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd | |||
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|
4 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
|
|
5 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management.vhd | |||
|
|
6 | vcom -quiet -93 -work lpp ../../lib/lpp/lfr_management/lpp_lfr_management_apbreg_pkg.vhd | |||
|
|
7 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd | |||
|
|
8 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_sim_pkg.vhd | |||
|
|
9 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_sim/lpp_lfr_sim_pkg.vhd | |||
|
|
10 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd | |||
|
|
11 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_bootloader/lpp_bootloader_pkg.vhd | |||
|
|
12 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/lpp_leon3_soc_pkg.vhd | |||
|
|
13 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices_list.vhd | |||
|
|
14 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./apb_devices/apb_devices.vhd | |||
|
|
15 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/memctrlr.vhd | |||
|
|
16 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd | |||
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17 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-1ws.vhd | |||
|
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18 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/data_type_pkg.vhd | |||
|
|
19 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_purpose.vhd | |||
|
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20 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ADDRcntr.vhd | |||
|
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21 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/ALU.vhd | |||
|
|
22 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Adder.vhd | |||
|
|
23 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_Divider2.vhd | |||
|
|
24 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clk_divider.vhd | |||
|
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25 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC.vhd | |||
|
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26 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_CONTROLER.vhd | |||
|
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27 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX.vhd | |||
|
|
28 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_MUX2.vhd | |||
|
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29 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MAC_REG.vhd | |||
|
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30 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUX2.vhd | |||
|
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31 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/MUXN.vhd | |||
|
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32 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Multiplier.vhd | |||
|
|
33 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/REG.vhd | |||
|
|
34 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_FF.vhd | |||
|
|
35 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Shifter.vhd | |||
|
|
36 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/TwoComplementer.vhd | |||
|
|
37 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/Clock_Divider.vhd | |||
|
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38 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_to_level.vhd | |||
|
|
39 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_detection.vhd | |||
|
|
40 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/lpp_front_positive_detection.vhd | |||
|
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41 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/SYNC_VALID_BIT.vhd | |||
|
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42 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/RR_Arbiter_4.vhd | |||
|
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43 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./general_purpose/general_counter.vhd | |||
|
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44 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/apb_devices_list.vhd | |||
|
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45 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_amba/lpp_amba.vhd | |||
|
|
46 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp_pkg.vhd | |||
|
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47 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/chirp/chirp.vhd | |||
|
|
48 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/iir_filter.vhd | |||
|
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49 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/FILTERcfg.vhd | |||
|
|
50 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM.vhd | |||
|
|
51 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CEL.vhd | |||
|
|
52 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/RAM_CTRLR_v2.vhd | |||
|
|
53 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_CONTROL.vhd | |||
|
|
54 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |||
|
|
55 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v2.vhd | |||
|
|
56 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3_DATAFLOW.vhd | |||
|
|
57 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/iir_filter/IIR_CEL_CTRLR_v3.vhd | |||
|
|
58 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_pkg.vhd | |||
|
|
59 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic.vhd | |||
|
|
60 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_integrator.vhd | |||
|
|
61 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_downsampler.vhd | |||
|
|
62 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_comb.vhd | |||
|
|
63 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr.vhd | |||
|
|
64 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control.vhd | |||
|
|
65 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_add_sub.vhd | |||
|
|
66 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_address_gen.vhd | |||
|
|
67 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_r2.vhd | |||
|
|
68 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/cic/cic_lfr_control_r2.vhd | |||
|
|
69 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_downsampling/Downsampling.vhd | |||
|
|
70 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_memory.vhd | |||
|
|
71 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO.vhd | |||
|
|
72 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared.vhd | |||
|
|
73 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_control.vhd | |||
|
|
74 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_0.vhd | |||
|
|
75 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lpp_FIFO_4_Shared_headreg_latency_1.vhd | |||
|
|
76 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_memory/lppFIFOxN.vhd | |||
|
|
77 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fft_components.vhd | |||
|
|
78 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/lpp_fft.vhd | |||
|
|
79 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actar.vhd | |||
|
|
80 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/actram.vhd | |||
|
|
81 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/CoreFFT.vhd | |||
|
|
82 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftDp.vhd | |||
|
|
83 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/fftSm.vhd | |||
|
|
84 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/primitives.vhd | |||
|
|
85 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/twiddle.vhd | |||
|
|
86 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Driver_FFT.vhd | |||
|
|
87 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/FFT.vhd | |||
|
|
88 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./dsp/lpp_fft/Linker_FFT.vhd | |||
|
|
89 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lpp_cna.vhd | |||
|
|
90 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_READER.vhd | |||
|
|
91 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/RAM_WRITER.vhd | |||
|
|
92 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/SPI_DAC_DRIVER.vhd | |||
|
|
93 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/dynamic_freq_div.vhd | |||
|
|
94 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_cna/lfr_cal_driver.vhd | |||
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95 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management.vhd | |||
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96 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lpp_lfr_management_apbreg_pkg.vhd | |||
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97 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/apb_lfr_management.vhd | |||
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98 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/lfr_time_management.vhd | |||
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99 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_counter.vhd | |||
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100 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/coarse_time_counter.vhd | |||
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101 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lfr_management/fine_time_max_value_gen.vhd | |||
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102 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_ad_Conv.vhd | |||
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103 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/RHF1401.vhd | |||
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104 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401.vhd | |||
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105 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_RHF1401_withFilter.vhd | |||
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106 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/TestModule_RHF1401.vhd | |||
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107 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/top_ad_conv_ADS7886_v2.vhd | |||
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108 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/ADS7886_drvr_v2.vhd | |||
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109 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_ad_Conv/lpp_lfr_hk.vhd | |||
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110 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/bootrom.vhd | |||
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111 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader_pkg.vhd | |||
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112 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_bootloader/lpp_bootloader.vhd | |||
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113 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_package.vhd | |||
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114 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_calculation.vhd | |||
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115 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/MS_control.vhd | |||
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116 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_switch_f0.vhd | |||
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117 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_spectral_matrix/spectral_matrix_time_managment.vhd | |||
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118 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/DEMUX.vhd | |||
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119 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_demux/lpp_demux.vhd | |||
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120 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd | |||
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121 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |||
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122 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/lpp_matrix.vhd | |||
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123 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ALU_Driver.vhd | |||
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124 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/ReUse_CTRLR.vhd | |||
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125 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Dispatch.vhd | |||
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126 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/DriveInputs.vhd | |||
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127 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/GetResult.vhd | |||
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128 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/MatriceSpectrale.vhd | |||
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129 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/Matrix.vhd | |||
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130 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/SpectralMatrix.vhd | |||
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131 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_matrix/TopSpecMatrix.vhd | |||
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132 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_pkg.vhd | |||
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133 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/fifo_latency_correction.vhd | |||
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134 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma.vhd | |||
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135 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_ip.vhd | |||
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136 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_16word.vhd | |||
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137 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_send_1word.vhd | |||
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138 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_singleOrBurst.vhd | |||
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139 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem.vhd | |||
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|
140 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_GestionBuffer.vhd | |||
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141 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_Arbiter.vhd | |||
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142 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/DMA_SubSystem_MUX.vhd | |||
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143 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd | |||
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|
144 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_pkg.vhd | |||
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145 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform.vhd | |||
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|
146 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_burst.vhd | |||
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147 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_withoutLatency.vhd | |||
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|
148 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_latencyCorrection.vhd | |||
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149 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo.vhd | |||
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150 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter.vhd | |||
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|
151 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_ctrl.vhd | |||
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152 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_headreg.vhd | |||
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153 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot.vhd | |||
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154 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_snapshot_controler.vhd | |||
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155 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_genaddress.vhd | |||
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156 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_dma_genvalid.vhd | |||
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|
157 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd | |||
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|
158 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_waveform/lpp_waveform_fsmdma.vhd | |||
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|
159 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_top_lfr_pkg.vhd | |||
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160 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_pkg.vhd | |||
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|
161 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_pkg.vhd | |||
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162 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter_coeff.vhd | |||
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|
163 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_filter.vhd | |||
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164 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg.vhd | |||
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165 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_apbreg_ms_pointer.vhd | |||
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166 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_fsmdma.vhd | |||
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167 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_FFT.vhd | |||
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168 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms.vhd | |||
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169 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr_ms_reg_head.vhd | |||
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170 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_top_lfr/lpp_lfr.vhd | |||
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171 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/lpp_Header.vhd | |||
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172 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_Header/HeaderBuilder.vhd | |||
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173 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/lpp_leon3_soc_pkg.vhd | |||
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|
174 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_leon3_soc/leon3_soc.vhd | |||
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175 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr_pkg.vhd | |||
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176 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_dma_singleOrBurst.vhd | |||
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177 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_debug_lfr/lpp_debug_lfr.vhd | |||
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178 | vcom -quiet -93 -work lpp ../../../grlib/lib/../../tortoiseHG_vhdlib/lib/lpp/./lpp_sim/lpp_sim_pkg.vhd | |||
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179 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_dma/lpp_dma_SEND16B_FIFO2DMA.vhd | |||
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180 | vcom -quiet -93 -work lpp ../../lib/lpp/lpp_leon3_soc/leon3_soc.vhd | |||
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|
181 | vcom -quiet -93 -work iap ../../../grlib/lib/../../VHDLIB_non_free/lib/iap/./memctrlr/srctrle-0ws.vhd | |||
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182 | vcom -quiet -93 -work work LFR-EQM.vhd | |||
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183 | vcom -quiet -93 -work work TB.vhd | |||
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184 | ||||
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185 | vsim work.tb | |||
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186 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_2/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 00000000000000000000000000000000 0 | |||
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187 | #force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data 11111111111111111111111111111111 0 | |||
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188 | #force -freeze sim:/tb/LFR_EQM_1/inst_bootloader/lpp_bootloader_1/reg.config_wait_on_boot 0 0 | |||
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189 | ||||
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190 | force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f0_data 000100000000000100100000000000100001000000000100000100000000100000010000000100000001000000100000 0 | |||
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191 | force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f1_data 001000000000000100100000000000100010000000000100001000000000100000100000000100000010000000100000 0 | |||
|
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192 | force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f2_data 010000000000000101000000000000100100000000000100010000000000100001000000000100000100000000100000 0 | |||
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193 | force -freeze sim:/tb/LFR_EQM_1/lpp_lfr_1/sample_f3_data 100000000000000110000000000000101000000000000100100000000000100010000000000100001000000000100000 0 | |||
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194 | ||||
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195 | log -r *; | |||
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|
196 | do wave.do ; | |||
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|
197 | run -all | |||
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198 | ||||
|
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199 | ||||
| @@ -0,0 +1,116 | |||||
|
|
1 | onerror {resume} | |||
|
|
2 | quietly virtual signal -install /tb/LFR_EQM_1 { /tb/LFR_EQM_1/address(3 downto 0)} Sgyzarbjhxc | |||
|
|
3 | quietly WaveActivateNextPane {} 0 | |||
|
|
4 | add wave -noupdate /tb/data_message | |||
|
|
5 | add wave -noupdate /tb/message_simu | |||
|
|
6 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E1 | |||
|
|
7 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_E2 | |||
|
|
8 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_G | |||
|
|
9 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_W | |||
|
|
10 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/data | |||
|
|
11 | add wave -noupdate -expand -group RAM -format Analog-Step -height 74 -max 14.999999999999998 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/Sgyzarbjhxc(3) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(2) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(1) -radix hexadecimal} {/tb/LFR_EQM_1/Sgyzarbjhxc(0) -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/address(3) {-radix hexadecimal} /tb/LFR_EQM_1/address(2) {-radix hexadecimal} /tb/LFR_EQM_1/address(1) {-radix hexadecimal} /tb/LFR_EQM_1/address(0) {-radix hexadecimal}} /tb/LFR_EQM_1/Sgyzarbjhxc | |||
|
|
12 | add wave -noupdate -expand -group RAM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/address(18) -radix hexadecimal} {/tb/LFR_EQM_1/address(17) -radix hexadecimal} {/tb/LFR_EQM_1/address(16) -radix hexadecimal} {/tb/LFR_EQM_1/address(15) -radix hexadecimal} {/tb/LFR_EQM_1/address(14) -radix hexadecimal} {/tb/LFR_EQM_1/address(13) -radix hexadecimal} {/tb/LFR_EQM_1/address(12) -radix hexadecimal} {/tb/LFR_EQM_1/address(11) -radix hexadecimal} {/tb/LFR_EQM_1/address(10) -radix hexadecimal} {/tb/LFR_EQM_1/address(9) -radix hexadecimal} {/tb/LFR_EQM_1/address(8) -radix hexadecimal} {/tb/LFR_EQM_1/address(7) -radix hexadecimal} {/tb/LFR_EQM_1/address(6) -radix hexadecimal} {/tb/LFR_EQM_1/address(5) -radix hexadecimal} {/tb/LFR_EQM_1/address(4) -radix hexadecimal} {/tb/LFR_EQM_1/address(3) -radix hexadecimal} {/tb/LFR_EQM_1/address(2) -radix hexadecimal} {/tb/LFR_EQM_1/address(1) -radix hexadecimal} {/tb/LFR_EQM_1/address(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/address(18) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(17) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(16) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/address(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/address | |||
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13 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_BUSY | |||
|
|
14 | add wave -noupdate -expand -group RAM -radix hexadecimal /tb/LFR_EQM_1/nSRAM_MBE | |||
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15 | add wave -noupdate -group ADC -radix hexadecimal -childformat {{/tb/LFR_EQM_1/ADC_data(13) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(12) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(11) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(10) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(9) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(8) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(7) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(6) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(5) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(4) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(3) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(2) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(1) -radix hexadecimal} {/tb/LFR_EQM_1/ADC_data(0) -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/ADC_data(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/ADC_data(0) {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/ADC_data | |||
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16 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_smpclk | |||
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17 | add wave -noupdate -group ADC -radix hexadecimal /tb/LFR_EQM_1/ADC_OEB_bar_CH | |||
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18 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample | |||
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19 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_val | |||
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20 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_val | |||
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21 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f0_wdata | |||
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22 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_val | |||
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23 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f1_wdata | |||
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24 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_val | |||
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25 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f2_wdata | |||
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26 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_val | |||
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27 | add wave -noupdate -group SAMPLE_FILTER -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_filter_1/sample_f3_wdata | |||
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28 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |||
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29 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |||
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30 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |||
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31 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |||
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32 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |||
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33 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |||
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34 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |||
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35 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |||
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36 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |||
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37 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |||
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38 | add wave -noupdate -group DMA_SEND_FIFO2DMA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |||
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39 | add wave -noupdate -group DMA_SEND_FIFO2DMA /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |||
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40 | add wave -noupdate -group LFR1_s -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |||
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41 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |||
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42 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/clk | |||
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43 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |||
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44 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/deviceid | |||
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45 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/hindex | |||
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46 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/rstn | |||
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47 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |||
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48 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |||
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49 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/vendorid | |||
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50 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/version | |||
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51 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |||
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52 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |||
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53 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |||
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54 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |||
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55 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter | |||
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56 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |||
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57 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |||
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58 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |||
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59 | add wave -noupdate -group LFR1_s -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |||
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60 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_wp | |||
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61 | add wave -noupdate -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/lpp_lfr_apbreg_1/reg_sp | |||
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62 | add wave -noupdate -group TEST -radix hexadecimal -childformat {{/tb/data_pre_f0(31) -radix hexadecimal} {/tb/data_pre_f0(30) -radix hexadecimal} {/tb/data_pre_f0(29) -radix hexadecimal} {/tb/data_pre_f0(28) -radix hexadecimal} {/tb/data_pre_f0(27) -radix hexadecimal} {/tb/data_pre_f0(26) -radix hexadecimal} {/tb/data_pre_f0(25) -radix hexadecimal} {/tb/data_pre_f0(24) -radix hexadecimal} {/tb/data_pre_f0(23) -radix hexadecimal} {/tb/data_pre_f0(22) -radix hexadecimal} {/tb/data_pre_f0(21) -radix hexadecimal} {/tb/data_pre_f0(20) -radix hexadecimal} {/tb/data_pre_f0(19) -radix hexadecimal} {/tb/data_pre_f0(18) -radix hexadecimal} {/tb/data_pre_f0(17) -radix hexadecimal} {/tb/data_pre_f0(16) -radix hexadecimal} {/tb/data_pre_f0(15) -radix hexadecimal} {/tb/data_pre_f0(14) -radix hexadecimal} {/tb/data_pre_f0(13) -radix hexadecimal} {/tb/data_pre_f0(12) -radix hexadecimal} {/tb/data_pre_f0(11) -radix hexadecimal} {/tb/data_pre_f0(10) -radix hexadecimal} {/tb/data_pre_f0(9) -radix hexadecimal} {/tb/data_pre_f0(8) -radix hexadecimal} {/tb/data_pre_f0(7) -radix hexadecimal} {/tb/data_pre_f0(6) -radix hexadecimal} {/tb/data_pre_f0(5) -radix hexadecimal} {/tb/data_pre_f0(4) -radix hexadecimal} {/tb/data_pre_f0(3) -radix hexadecimal} {/tb/data_pre_f0(2) -radix hexadecimal} {/tb/data_pre_f0(1) -radix hexadecimal} {/tb/data_pre_f0(0) -radix hexadecimal}} -subitemconfig {/tb/data_pre_f0(31) {-height 15 -radix hexadecimal} /tb/data_pre_f0(30) {-height 15 -radix hexadecimal} /tb/data_pre_f0(29) {-height 15 -radix hexadecimal} /tb/data_pre_f0(28) {-height 15 -radix hexadecimal} /tb/data_pre_f0(27) {-height 15 -radix hexadecimal} /tb/data_pre_f0(26) {-height 15 -radix hexadecimal} /tb/data_pre_f0(25) {-height 15 -radix hexadecimal} /tb/data_pre_f0(24) {-height 15 -radix hexadecimal} /tb/data_pre_f0(23) {-height 15 -radix hexadecimal} /tb/data_pre_f0(22) {-height 15 -radix hexadecimal} /tb/data_pre_f0(21) {-height 15 -radix hexadecimal} /tb/data_pre_f0(20) {-height 15 -radix hexadecimal} /tb/data_pre_f0(19) {-height 15 -radix hexadecimal} /tb/data_pre_f0(18) {-height 15 -radix hexadecimal} /tb/data_pre_f0(17) {-height 15 -radix hexadecimal} /tb/data_pre_f0(16) {-height 15 -radix hexadecimal} /tb/data_pre_f0(15) {-height 15 -radix hexadecimal} /tb/data_pre_f0(14) {-height 15 -radix hexadecimal} /tb/data_pre_f0(13) {-height 15 -radix hexadecimal} /tb/data_pre_f0(12) {-height 15 -radix hexadecimal} /tb/data_pre_f0(11) {-height 15 -radix hexadecimal} /tb/data_pre_f0(10) {-height 15 -radix hexadecimal} /tb/data_pre_f0(9) {-height 15 -radix hexadecimal} /tb/data_pre_f0(8) {-height 15 -radix hexadecimal} /tb/data_pre_f0(7) {-height 15 -radix hexadecimal} /tb/data_pre_f0(6) {-height 15 -radix hexadecimal} /tb/data_pre_f0(5) {-height 15 -radix hexadecimal} /tb/data_pre_f0(4) {-height 15 -radix hexadecimal} /tb/data_pre_f0(3) {-height 15 -radix hexadecimal} /tb/data_pre_f0(2) {-height 15 -radix hexadecimal} /tb/data_pre_f0(1) {-height 15 -radix hexadecimal} /tb/data_pre_f0(0) {-height 15 -radix hexadecimal}} /tb/data_pre_f0 | |||
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63 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f1 | |||
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64 | add wave -noupdate -group TEST -radix hexadecimal /tb/data_pre_f2 | |||
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65 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f0 | |||
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66 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f1 | |||
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67 | add wave -noupdate -group TEST -radix hexadecimal /tb/addr_pre_f2 | |||
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68 | add wave -noupdate /tb/error_wfp | |||
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69 | add wave -noupdate /tb/error_wfp_addr | |||
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70 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(0)/sr0/a | |||
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71 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/ce1 | |||
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72 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/oe | |||
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73 | add wave -noupdate -group sbanks_0 -radix hexadecimal /tb/sbanks(0)/sram0(1)/sr0/we | |||
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74 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/a | |||
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75 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/ce1 | |||
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76 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/oe | |||
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77 | add wave -noupdate -group sbanks_1 -radix hexadecimal /tb/sbanks(1)/sram0(0)/sr0/we | |||
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78 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbi | |||
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79 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/apbo | |||
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80 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbsi | |||
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81 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbso | |||
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82 | add wave -noupdate -group AMBA -radix hexadecimal /tb/LFR_EQM_1/leon3_soc_1/ahbmi | |||
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83 | add wave -noupdate -group AMBA -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}}} -subitemconfig {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(3).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(2).hindex {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0) {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig -radix hexadecimal} {/tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex -radix hexadecimal}}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/leon3_soc_1/ahbmo(0).hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/leon3_soc_1/ahbmo | |||
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84 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant {-height 15 -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) -radix hexadecimal}}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(0) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(1) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(2) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(3) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(4) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(5) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(6) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(7) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(8) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(9) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(10) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(11) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(12) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(13) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(14) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hgrant(15) {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hready {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hresp {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hrdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testrst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.scanen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testoen {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In.testin {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_In | |||
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85 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal -childformat {{/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig -radix hexadecimal} {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex -radix hexadecimal}} -expand -subitemconfig {/tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hbusreq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hlock {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.htrans {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.haddr {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwrite {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hsize {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hburst {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hprot {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hwdata {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hirq {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hconfig {-height 15 -radix hexadecimal} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out.hindex {-height 15 -radix hexadecimal}} /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/AHB_Master_Out | |||
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86 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address | |||
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87 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/valid_burst | |||
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88 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data | |||
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89 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/send | |||
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90 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/state | |||
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91 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/address_counter_reg | |||
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92 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/HConfig | |||
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93 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/data_window | |||
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94 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ctrl_window | |||
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95 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/done | |||
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96 | add wave -noupdate -group LPP_DMA_FSM -radix hexadecimal /tb/LFR_EQM_1/lpp_lfr_1/DMA_SubSystem_1/LPP_DMA_IP/lpp_dma_SEND16B_FIFO2DMA_1/ren | |||
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97 | add wave -noupdate -childformat {{/tb/sample(2) -radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}}} {/tb/sample(1) -radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} {/tb/sample(0) -radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}}} -expand -subitemconfig {/tb/sample(2) {-radix decimal -childformat {{/tb/sample(2)(5) -radix decimal} {/tb/sample(2)(4) -radix decimal} {/tb/sample(2)(3) -radix decimal} {/tb/sample(2)(2) -radix decimal} {/tb/sample(2)(1) -radix decimal} {/tb/sample(2)(0) -radix decimal}} -expand} /tb/sample(2)(5) {-radix decimal} /tb/sample(2)(4) {-radix decimal} /tb/sample(2)(3) {-radix decimal} /tb/sample(2)(2) {-radix decimal} /tb/sample(2)(1) {-radix decimal} /tb/sample(2)(0) {-radix decimal} /tb/sample(1) {-radix decimal -childformat {{/tb/sample(1)(5) -radix decimal} {/tb/sample(1)(4) -radix decimal} {/tb/sample(1)(3) -radix decimal} {/tb/sample(1)(2) -radix decimal} {/tb/sample(1)(1) -radix decimal} {/tb/sample(1)(0) -radix decimal}}} /tb/sample(1)(5) {-radix decimal} /tb/sample(1)(4) {-radix decimal} /tb/sample(1)(3) {-radix decimal} /tb/sample(1)(2) {-radix decimal} /tb/sample(1)(1) {-radix decimal} /tb/sample(1)(0) {-radix decimal} /tb/sample(0) {-radix decimal -childformat {{/tb/sample(0)(5) -radix decimal} {/tb/sample(0)(4) -radix decimal} {/tb/sample(0)(3) -radix decimal} {/tb/sample(0)(2) -radix decimal} {/tb/sample(0)(1) -radix decimal} {/tb/sample(0)(0) -radix decimal}}} /tb/sample(0)(5) {-radix decimal} /tb/sample(0)(4) {-radix decimal} /tb/sample(0)(3) {-radix decimal} /tb/sample(0)(2) {-radix decimal} /tb/sample(0)(1) {-radix decimal} /tb/sample(0)(0) {-radix decimal}} /tb/sample | |||
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98 | add wave -noupdate -expand /tb/sample_counter | |||
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99 | TreeUpdate [SetDefaultTree] | |||
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100 | WaveRestoreCursors {{Cursor 1} {279190000 ps} 0} {{Cursor 2} {277950000 ps} 0} {{Cursor 3} {11005133000 ps} 0} | |||
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101 | quietly wave cursor active 3 | |||
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102 | configure wave -namecolwidth 517 | |||
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103 | configure wave -valuecolwidth 347 | |||
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104 | configure wave -justifyvalue left | |||
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105 | configure wave -signalnamewidth 0 | |||
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106 | configure wave -snapdistance 10 | |||
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107 | configure wave -datasetprefix 0 | |||
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108 | configure wave -rowmargin 4 | |||
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109 | configure wave -childrowmargin 2 | |||
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110 | configure wave -gridoffset 0 | |||
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111 | configure wave -gridperiod 1 | |||
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112 | configure wave -griddelta 40 | |||
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113 | configure wave -timeline 0 | |||
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114 | configure wave -timelineunits ns | |||
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115 | update | |||
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116 | WaveRestoreZoom {0 ps} {27243436500 ps} | |||
| @@ -1,29 +1,29 | |||||
| 1 |
vendor VENDOR_LPP 19 |
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1 | vendor VENDOR_LPP 19 | |
| 2 |
|
2 | |||
| 3 |
device ROCKET_TM 1 |
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3 | device ROCKET_TM 1 | |
| 4 |
device otherCore 2 |
|
4 | device otherCore 2 | |
| 5 |
device LPP_SIMPLE_DIODE 3 |
|
5 | device LPP_SIMPLE_DIODE 3 | |
| 6 |
device LPP_MULTI_DIODE 4 |
|
6 | device LPP_MULTI_DIODE 4 | |
| 7 |
device LPP_LCD_CTRLR 5 |
|
7 | device LPP_LCD_CTRLR 5 | |
| 8 |
device LPP_UART 6 |
|
8 | device LPP_UART 6 | |
| 9 |
device LPP_CNA 7 |
|
9 | device LPP_CNA 7 | |
| 10 |
device LPP_APB_ADC 8 |
|
10 | device LPP_APB_ADC 8 | |
| 11 |
device LPP_CHENILLARD 9 |
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11 | device LPP_CHENILLARD 9 | |
| 12 |
device LPP_IIR_CEL_FILTER 10 |
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12 | device LPP_IIR_CEL_FILTER 10 | |
| 13 |
device LPP_FIFO_PID 11 |
|
13 | device LPP_FIFO_PID 11 | |
| 14 |
device LPP_FFT 12 |
|
14 | device LPP_FFT 12 | |
| 15 |
device LPP_MATRIX 13 |
|
15 | device LPP_MATRIX 13 | |
| 16 |
device LPP_DELAY 14 |
|
16 | device LPP_DELAY 14 | |
| 17 |
device LPP_USB 15 |
|
17 | device LPP_USB 15 | |
| 18 |
device LPP_BALISE 16 |
|
18 | device LPP_BALISE 16 | |
| 19 |
device LPP_DMA_TYPE 17 |
|
19 | device LPP_DMA_TYPE 17 | |
| 20 |
device LPP_BOOTLOADER_TYPE 18 |
|
20 | device LPP_BOOTLOADER_TYPE 18 | |
| 21 |
device LPP_LFR 19 |
|
21 | device LPP_LFR 19 | |
| 22 |
device LPP_CLKSETTING 20 |
|
22 | device LPP_CLKSETTING 20 | |
| 23 |
device LPP_LFR_HK_DEVICE 21 |
|
23 | device LPP_LFR_HK_DEVICE 21 | |
| 24 |
device LPP_LFR_MANAGEMENT 22 |
|
24 | device LPP_LFR_MANAGEMENT 22 | |
| 25 |
device LPP_DEBUG_DMA A0 |
|
25 | device LPP_DEBUG_DMA A0 | |
| 26 |
device LPP_DEBUG_LFR A1 |
|
26 | device LPP_DEBUG_LFR A1 | |
| 27 |
device LPP_DEBUG_LFR_ID A2 |
|
27 | device LPP_DEBUG_LFR_ID A2 | |
| 28 |
device APB_ADC_READER F1 |
|
28 | device APB_ADC_READER F1 | |
| 29 |
|
29 | |||
| @@ -1,49 +1,48 | |||||
| 1 |
|
1 | |||
| 2 | --================================================================================= |
|
2 | --================================================================================= | |
| 3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT |
|
3 | --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT | |
| 4 | -- |
|
4 | -- | |
| 5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID |
|
5 | --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID | |
| 6 | --================================================================================= |
|
6 | --================================================================================= | |
| 7 |
|
7 | |||
| 8 |
|
8 | |||
| 9 | library ieee; |
|
9 | LIBRARY ieee; | |
| 10 |
|
|
10 | USE ieee.std_logic_1164.ALL; | |
| 11 | library grlib; |
|
11 | LIBRARY grlib; | |
| 12 |
|
|
12 | USE grlib.amba.ALL; | |
| 13 |
|
|
13 | USE std.textio.ALL; | |
| 14 |
|
14 | |||
| 15 |
|
15 | |||
| 16 |
|
|
16 | PACKAGE apb_devices_list IS | |
| 17 |
|
17 | |||
| 18 |
|
18 | |||
| 19 |
|
|
19 | CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#; | |
| 20 |
|
20 | |||
| 21 |
|
|
21 | CONSTANT ROCKET_TM : amba_device_type := 16#1#; | |
| 22 |
|
|
22 | CONSTANT otherCore : amba_device_type := 16#2#; | |
| 23 |
|
|
23 | CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#; | |
| 24 |
|
|
24 | CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#; | |
| 25 |
|
|
25 | CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#; | |
| 26 |
|
|
26 | CONSTANT LPP_UART : amba_device_type := 16#6#; | |
| 27 |
|
|
27 | CONSTANT LPP_CNA : amba_device_type := 16#7#; | |
| 28 |
|
|
28 | CONSTANT LPP_APB_ADC : amba_device_type := 16#8#; | |
| 29 |
|
|
29 | CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#; | |
| 30 |
|
|
30 | CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#; | |
| 31 |
|
|
31 | CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#; | |
| 32 |
|
|
32 | CONSTANT LPP_FFT : amba_device_type := 16#12#; | |
| 33 |
|
|
33 | CONSTANT LPP_MATRIX : amba_device_type := 16#13#; | |
| 34 |
|
|
34 | CONSTANT LPP_DELAY : amba_device_type := 16#14#; | |
| 35 |
|
|
35 | CONSTANT LPP_USB : amba_device_type := 16#15#; | |
| 36 |
|
|
36 | CONSTANT LPP_BALISE : amba_device_type := 16#16#; | |
| 37 |
|
|
37 | CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#; | |
| 38 |
|
|
38 | CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#; | |
| 39 |
|
|
39 | CONSTANT LPP_LFR : amba_device_type := 16#19#; | |
| 40 |
|
|
40 | CONSTANT LPP_CLKSETTING : amba_device_type := 16#20#; | |
| 41 |
|
|
41 | CONSTANT LPP_LFR_HK_DEVICE : amba_device_type := 16#21#; | |
| 42 |
|
|
42 | CONSTANT LPP_LFR_MANAGEMENT : amba_device_type := 16#22#; | |
| 43 |
|
|
43 | CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#; | |
| 44 |
|
|
44 | CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#; | |
| 45 |
constant |
|
45 | constant APB_ADC_READER : amba_device_type := 16#F1#; | |
| 46 |
|
|
46 | CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#; | |
| 47 |
|
47 | |||
| 48 |
|
48 | END; | ||
| 49 | end; No newline at end of file |
|
|||
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