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IP FFT modified/cleaned, FFT C Driver added
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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_uart_Driver
25 INPUTFILE=main.c
26 EXEC=BenchFFT.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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@@ -0,0 +1,43
1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_uart_Driver.h"
4 #include "apb_fft_Driver.h"
5
6
7 int main()
8 {
9 char temp[256];
10 int i;
11 int Table[256];
12 //Somme de 2 sinus//
13 //int Tablo[256] = {0x00000000,0x0DA20000,0x1B080000,0x27F70000,0x34380000,0x3F960000,0x49E10000,0x52F10000,0x5AA10000,0x60D60000,0x657D0000,0x688C0000,0x69FE0000,0x69DB0000,0x68310000,0x65170000,0x60A90000,0x5B0D0000,0x546D0000,0x4CF90000,0x44E30000,0x3C610000,0x33AA0000,0x2AF40000,0x22750000,0x1A610000,0x12E70000,0x0C310000,0x06660000,0x01A30000,0xFE010000,0xFB8E0000,0xFA520000,0xFA4D0000,0xFB770000,0xFDBE0000,0x010A0000,0x053E0000,0x0A330000,0x0FBF0000,0x15B30000,0x1BDE0000,0x220C0000,0x28080000,0x2D9D0000,0x329B0000,0x36D20000,0x3A170000,0x3C440000,0x3D390000,0x3CDE0000,0x3B210000,0x37F90000,0x33650000,0x2D6D0000,0x26210000,0x1D990000,0x13F30000,0x09570000,0xFDF10000,0xF1F20000,0xE58F0000,0xD9030000,0xCC870000,0xC0560000,0xB4AA0000,0xA9BC0000,0x9FBF0000,0x96E40000,0x8F570000,0x893A0000,0x84AB0000,0x81BF0000,0x80830000,0x80FB0000,0x83220000,0x86EC0000,0x8C430000,0x93090000,0x9B1B0000,0xA44D0000,0xAE700000,0xB9500000,0xC4B40000,0xD0630000,0xDC240000,0xE7BD0000,0xF2F60000,0xFD9A0000,0x077A0000,0x106B0000,0x18480000,0x1EF30000,0x24570000,0x28650000,0x2B160000,0x2C6F0000,0x2C790000,0x2B470000,0x28F30000,0x259E0000,0x216E0000,0x1C8F0000,0x17310000,0x11860000,0x0BC10000,0x06170000,0x00BA0000,0xFBDD0000,0xF7AC0000,0xF44F0000,0xF1EA0000,0xF09C0000,0xF0790000,0xF1900000,0xF3E80000,0xF77E0000,0xFC4A0000,0x02370000,0x092E0000,0x110E0000,0x19AF0000,0x22E40000,0x2C7C0000,0x36420000,0x3FFF0000,0x497C0000,0x52810000,0x5AD70000,0x624B0000,0x68AD0000,0x6DD40000,0x71990000,0x73E10000,0x74950000,0x73A60000,0x71100000,0x6CD60000,0x67040000,0x5FAD0000,0x56EE0000,0x4CEA0000,0x41CD0000,0x35C50000,0x29070000,0x1BCC0000,0x0E4E0000,0x00CA0000,0xF37C0000,0xE69C0000,0xDA620000,0xCF040000,0xC4AE0000,0xBB8B0000,0xB3BC0000,0xAD5C0000,0xA87D0000,0xA5290000,0xA3630000,0xA3220000,0xA4590000,0xA6EF0000,0xAAC80000,0xAFBD0000,0xB5A40000,0xBC4F0000,0xC38B0000,0xCB220000,0xD2E00000,0xDA8E0000,0xE1F70000,0xE8EC0000,0xEF3C0000,0xF4C10000,0xF9560000,0xFCDF0000,0xFF470000,0x007F0000,0x00850000,0xFF5C0000,0xFD0B0000,0xF9A80000,0xF54B0000,0xF0170000,0xEA320000,0xE3C90000,0xDD0B0000,0xD62B0000,0xCF5F0000,0xC8DA0000,0xC2D30000,0xBD7A0000,0xB8FF0000,0xB58D0000,0xB3490000,0xB2510000,0xB2BE0000,0xB49F0000,0xB7FC0000,0xBCD60000,0xC3220000,0xCAD10000,0xD3C70000,0xDDE50000,0xE9030000,0xF4F20000,0x01800000,0x0E770000,0x1B9D0000,0x28B70000,0x35880000,0x41D70000,0x4D6C0000,0x58100000,0x61950000,0x69D00000,0x709C0000,0x75DE0000,0x79800000,0x7B750000,0x7BBB0000,0x7A570000,0x77550000,0x72CB0000,0x6CD70000,0x659E0000,0x5D490000,0x54090000,0x4A110000,0x3F980000,0x34D80000,0x2A090000,0x1F630000,0x151D0000,0x0B690000,0x02760000,0xFA6F0000,0xF3730000,0xEDA10000,0xE90B0000,0xE5BF0000,0xE3C00000,0xE30A0000,0xE38F0000,0xE53D0000,0xE7F80000,0xEB9D0000,0xF0050000,0xF5030000,0xFA680000,0x00000000,0x05980000,0x0AFD0000,0x0FFB0000,0x14630000,0x18080000};
14 //1 Sinus//
15 int Tablo[256] = {0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000,0xD0E10000,0xC9800000,0xC2560000,0xBB6A0000,0xB4C30000,0xAE690000,0xA8610000,0xA2B10000,0x9D600000,0x98720000,0x93ED0000,0x8FD50000,0x8C2F0000,0x88FD0000,0x86440000,0x84050000,0x82440000,0x81020000,0x80410000,0x80000000,0x80410000,0x81020000,0x82440000,0x84050000,0x86440000,0x88FD0000,0x8C2F0000,0x8FD50000,0x93ED0000,0x98720000,0x9D600000,0xA2B10000,0xA8610000,0xAE690000,0xB4C30000,0xBB6A0000,0xC2560000,0xC9800000,0xD0E10000,0xD8720000,0xE02B0000,0xE8040000,0xEFF50000,0xF7F60000,0x00000000,0x080A0000,0x100B0000,0x17FC0000,0x1FD50000,0x278E0000,0x2F1F0000,0x36800000,0x3DAA0000,0x44960000,0x4B3D0000,0x51970000,0x579F0000,0x5D4F0000,0x62A00000,0x678E0000,0x6C130000,0x702B0000,0x73D10000,0x77030000,0x79BC0000,0x7BFB0000,0x7DBC0000,0x7EFE0000,0x7FBF0000,0x80000000,0x7FBF0000,0x7EFE0000,0x7DBC0000,0x7BFB0000,0x79BC0000,0x77030000,0x73D10000,0x702B0000,0x6C130000,0x678E0000,0x62A00000,0x5D4F0000,0x579F0000,0x51970000,0x4B3D0000,0x44960000,0x3DAA0000,0x36800000,0x2F1F0000,0x278E0000,0x1FD50000,0x17FC0000,0x100B0000,0x080A0000,0x00000000,0xF7F60000,0xEFF50000,0xE8040000,0xE02B0000,0xD8720000};
16 printf("Debut Main\n\n");
17 UART_Device* uart0 = openUART(0);
18 FFT_Device* fft0 = openFFT(0);
19
20 printf("addr_fft: %x\n",(unsigned int)fft0);
21 printf("addr_uart: %x\n\n",(unsigned int)uart0);
22 printf("cfg_fft: %x\n",fft0->ConfigReg);
23 printf("cfg_uart: %x\n\n",uart0->ConfigReg);
24
25 while(1)
26 {
27 FftInput(Tablo,fft0);
28 /* for (i = 0 ; i < 256 ; i++)
29 {
30 sprintf(temp,"%x/in",Tablo[i]);
31 uartputs(uart0,temp);
32 }*/
33
34 FftOutput(Table,fft0);
35 for (i = 0 ; i < 128 ; i++)
36 {
37 sprintf(temp,"%x/out",Table[i]);
38 uartputs(uart0,temp);
39 }
40 }
41 return 0;
42 }
43
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@@ -0,0 +1,56
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24
25 #define FFT_Empty 0x00100
26 #define FFT_Full 0x01000
27
28
29 /*===================================================
30 T Y P E S D E F
31 ====================================================*/
32
33 struct FFT_Driver
34 {
35 int RWDataReg;
36 int ReadAddrReg;
37 int ConfigReg;
38 int Dummy1;
39 int Dummy0;
40 int WriteAddrReg;
41 };
42
43 typedef struct FFT_Driver FFT_Device;
44
45
46 /*===================================================
47 F U N C T I O N S
48 ====================================================*/
49
50 FFT_Device* openFFT(int count);
51 int FftInput(int Tbl[],FFT_Device*);
52 int FftOutput(int Tbl[],FFT_Device*);
53
54
55
56 #endif
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@@ -0,0 +1,25
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = apb_fft_Driver
20 LIB = liblpp_fft_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
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@@ -0,0 +1,90
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #include "apb_fft_Driver.h"
23 #include "lpp_apb_functions.h"
24 #include <stdio.h>
25
26
27 FFT_Device* openFFT(int count)
28 {
29 FFT_Device* FFT0;
30 FFT0 = (FFT_Device*) apbgetdevice(LPP_FFT,VENDOR_LPP,count);
31 return FFT0;
32 }
33
34
35 int FftInput(int * Tbl,FFT_Device* fft)
36 {
37 int i;
38 printf("\nFftInput\n\n");
39
40 while((fft->ConfigReg & FFT_Full) != FFT_Full) // full a 0
41 {
42 printf("\nWrite\n\n");
43 for (i = 0 ; i < 256 ; i++)
44 {
45 fft->RWDataReg = Tbl[i];
46 if((fft->ConfigReg & FFT_Full) == FFT_Full) // full a 1
47 {
48 printf("\nBreak\n\n");
49 break;
50 }
51 }
52 }
53
54 printf("\nFULL\n\n");
55 return 0;
56 }
57
58
59 int FftOutput(int * Tbl, FFT_Device* fft)
60 {
61 int i;
62 printf("\nFftOutput\n\n");
63
64 while((fft->ConfigReg & FFT_Empty) != FFT_Empty) // empty a 0
65 {
66 printf("\nRead\n\n");
67 for (i = 0 ; i < 256 ; i++)
68 {
69 //printf("\noutFor%d\n\n",i);
70 Tbl[i] = fft->RWDataReg;
71 if((fft->ConfigReg & FFT_Empty) == FFT_Empty) // empty a 1
72 {
73 printf("\nBreak\n\n");
74 break;
75 }
76 }
77 }
78 printf("\nEMPTY\n\n");
79 return 0;
80 }
81
82
83
84
85
86
87
88
89
90
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@@ -0,0 +1,56
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24
25 #define FFT_Empty 0x00100
26 #define FFT_Full 0x01000
27
28
29 /*===================================================
30 T Y P E S D E F
31 ====================================================*/
32
33 struct FFT_Driver
34 {
35 int RWDataReg;
36 int ReadAddrReg;
37 int ConfigReg;
38 int Dummy1;
39 int Dummy0;
40 int WriteAddrReg;
41 };
42
43 typedef struct FFT_Driver FFT_Device;
44
45
46 /*===================================================
47 F U N C T I O N S
48 ====================================================*/
49
50 FFT_Device* openFFT(int count);
51 int FftInput(int Tbl[],FFT_Device*);
52 int FftOutput(int Tbl[],FFT_Device*);
53
54
55
56 #endif
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@@ -24,4 +24,5 all:
24 make all -C APB_lcd_ctrlr
24 make all -C APB_lcd_ctrlr
25 make all -C BenchFIFO
25 make all -C BenchFIFO
26 make all -C BenchUART
26 make all -C BenchUART
27 make all -C BenchFFT
27
28
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@@ -27,6 +27,7 all:
27 make all -C DAC
27 make all -C DAC
28 make all -C FIFO
28 make all -C FIFO
29 make all -C UART
29 make all -C UART
30 make all -C FFT
30
31
31
32
32 cleanall:
33 cleanall:
@@ -35,4 +36,5 cleanall:
35 make clean -C DAC
36 make clean -C DAC
36 make clean -C FIFO
37 make clean -C FIFO
37 make clean -C UART
38 make clean -C UART
39 make clean -C FFT
38
40
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@@ -47,10 +47,6 entity APB_FFT is
47 port (
47 port (
48 clk : in std_logic; --! Horloge du composant
48 clk : in std_logic; --! Horloge du composant
49 rst : in std_logic; --! Reset general du composant
49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
50 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
52 );
@@ -69,24 +65,22 signal DataIn_im : std_logic_vecto
69 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
65 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
70 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
66 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
71 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
67 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
72 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
68 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
73 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
69 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
74
70
75 signal start : std_logic;
71 signal start : std_logic;
76 signal load : std_logic;
72 signal load : std_logic;
77 signal rdy : std_logic;
73 signal rdy : std_logic;
78 signal raz : std_logic;
79
80
74
81 begin
75 begin
82
76
83 APB : ApbDriver
77 APB : ApbDriver
84 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
78 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
85 port map(clk,rst,raz,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
79 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
86
80
87
81
88 Extremum : Flag_Extremum
82 Extremum : Flag_Extremum
89 port map(clk,raz,load,rdy,FlagFull,FlagEmpty);
83 port map(clk,rst,load,rdy,FlagFull,FlagEmpty);
90
84
91
85
92 DEVICE : CoreFFT
86 DEVICE : CoreFFT
@@ -102,22 +96,12 begin
102 PTS => gPTS,
96 PTS => gPTS,
103 HALFPTS => gHALFPTS,
97 HALFPTS => gHALFPTS,
104 inBuf_RWDLY => gInBuf_RWDLY)
98 inBuf_RWDLY => gInBuf_RWDLY)
105 port map(clk,start,raz,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
99 port map(clk,start,rst,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
106
100
107 start <= not rst;
101 start <= not rst;
108
102
109 DataIn_re <= DataIn(31 downto 16);
103 DataIn_re <= DataIn(31 downto 16);
110 DataIn_im <= DataIn(15 downto 0);
104 DataIn_im <= DataIn(15 downto 0);
111 DataOut <= DataOut_re & DataOut_im;
105 DataOut <= DataOut_re & DataOut_im;
112
113
114 full <= FlagFull;
115 empty <= FlagEmpty;
116 WR <= WriteEnable;
117 RE <= ReadEnable;
118 flg_load <= load;
119 flg_rdy <= rdy;
120 RZ <= raz;
121
122
106
123 end ar_APB_FFT; No newline at end of file
107 end ar_APB_FFT;
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@@ -24,42 +24,37 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 use work.FFT_config.all;
25 use work.FFT_config.all;
26
26
27 --! Programme qui va permettre de g�n�rer des flags utilis�s au niveau du driver C
28
27 entity Flag_Extremum is
29 entity Flag_Extremum is
28 port(
30 port(
29 clk,raz : in std_logic;
31 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
30 load : in std_logic;
32 load : in std_logic; --! Signal en provenance de CoreFFT
31 y_rdy : in std_logic;
33 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
32 full : out std_logic;
34 full : out std_logic; --! Flag, Va permettre d'autoriser l'�criture (Driver C)
33 empty : out std_logic
35 empty : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
34 );
36 );
35 end Flag_Extremum;
37 end Flag_Extremum;
36
38
39 --! @details Flags g�n�r�s a partir de signaux fourni par l'IP FFT d'actel
40
37 architecture ar_Flag_Extremum of Flag_Extremum is
41 architecture ar_Flag_Extremum of Flag_Extremum is
38
42
39 --type etat is (eA,eB,eC,e0,e1,e2);
43 begin
40 --signal ect : etat;
41
42 signal load_reg : std_logic;
43 signal y_rdy_reg : std_logic;
44
45 begin
46 process (clk,raz)
44 process (clk,raz)
47 begin
45 begin
48 if(raz='0')then
46 if(raz='0')then
49 full <= '1';
47 full <= '1';
50 empty <= '1';
48 empty <= '1';
51 -- ect <= eA;
49
52
50 elsif(clk' event and clk='1')then
53 elsif(clk' event and clk='1')then
54 -- load_reg <= load;
55 -- y_rdy_reg <= y_rdy;
56
51
57 if(load='1' and y_rdy='0')then
52 if(load='1' and y_rdy='0')then
58 full <= '0';
53 full <= '0';
59 empty <= '1';
54 empty <= '1';
60
55
61 elsif(y_rdy='1')then
56 elsif(y_rdy='1')then
62 full <= '1';
57 full <= '1';
63 empty <= '0';
58 empty <= '0';
64
59
65 else
60 else
@@ -67,49 +62,6 begin
67 empty <= '1';
62 empty <= '1';
68
63
69 end if;
64 end if;
70
71 -- case ect is
72
73 -- when eA =>
74 -- if(load_reg='0' and load='1')then
75 -- full <= '0';
76 -- ect <= eB;
77 -- end if;
78 --
79 -- when eB =>
80 -- if(load_reg='1' and load='0')then
81 -- ect <= eC;
82 -- end if;
83 --
84 -- when eC =>
85 -- if(load_reg='1' and load='0')then
86 -- full <= '1';
87 -- ect <= e0;
88 -- end if;
89
90 --===================================================================================
91
92 -- when e0 =>
93 -- if(load_reg='0' and load='1')then
94 -- full <= '0';
95 -- ect <= e1;
96 -- end if;
97 --
98 -- when e1 =>
99 -- if(load_reg='1' and load='0')then
100 -- full <= '1';
101 -- empty <= '0';
102 -- ect <= e2;
103 -- end if;
104 --
105 -- when e2 =>
106 -- if(y_rdy_reg='1' and y_rdy='0')then
107 -- empty <= '1';
108 -- ect <= e0;
109 -- end if;
110 --
111 --
112 -- end case;
113 end if;
65 end if;
114 end process;
66 end process;
115
67
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@@ -29,7 +29,6 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32
33 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
34
33
35 package lpp_fft is
34 package lpp_fft is
@@ -45,14 +44,10 component APB_FFT is
45 Addr_sz : integer := 8;
44 Addr_sz : integer := 8;
46 addr_max_int : integer := 256);
45 addr_max_int : integer := 256);
47 port (
46 port (
48 clk : in std_logic; --! Horloge du composant
47 clk : in std_logic;
49 rst : in std_logic; --! Reset general du composant
48 rst : in std_logic;
50 full,empty : out std_logic;
49 apbi : in apb_slv_in_type;
51 WR,RE : out std_logic;
50 apbo : out apb_slv_out_type
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
56 );
51 );
57 end component;
52 end component;
58
53
@@ -67,6 +62,10 component Flag_Extremum is
67 );
62 );
68 end component;
63 end component;
69
64
65 --==============================================================|
66 --================== IP VHDL de la FFT actel ===================|
67 --================ non partag� dans la VHD_Lib =================|
68 --==============================================================|
70
69
71 component CoreFFT IS
70 component CoreFFT IS
72 GENERIC (
71 GENERIC (
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@@ -45,7 +45,6 entity ApbDriver is
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 RZ : out std_logic;
49 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
48 ReadEnable : out std_logic; --! Instruction de lecture en m�moire
50 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
49 WriteEnable : out std_logic; --! Instruction d'�criture en m�moire
51 FlagEmpty : in std_logic; --! Flag, M�moire vide
50 FlagEmpty : in std_logic; --! Flag, M�moire vide
@@ -70,7 +69,7 constant pconfig : apb_config_type := (
70 1 => apb_iobar(paddr, pmask));
69 1 => apb_iobar(paddr, pmask));
71
70
72 type DEVICE_ctrlr_Reg is record
71 type DEVICE_ctrlr_Reg is record
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
72 DEVICE_Cfg : std_logic_vector(3 downto 0);
74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
73 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
74 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
75 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
@@ -82,13 +81,13 signal Rdata : std_logic_vector(31 down
82
81
83 signal FlagRE : std_logic;
82 signal FlagRE : std_logic;
84 signal FlagWR : std_logic;
83 signal FlagWR : std_logic;
84
85 begin
85 begin
86
86
87 Rec.DEVICE_Cfg(0) <= FlagRE;
87 Rec.DEVICE_Cfg(0) <= FlagRE;
88 Rec.DEVICE_Cfg(1) <= FlagWR;
88 Rec.DEVICE_Cfg(1) <= FlagWR;
89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
90 Rec.DEVICE_Cfg(3) <= FlagFull;
90 Rec.DEVICE_Cfg(3) <= FlagFull;
91 Rz <= Rec.DEVICE_Cfg(4);
92
91
93 DataIn <= Rec.DEVICE_DataW;
92 DataIn <= Rec.DEVICE_DataW;
94 Rec.DEVICE_DataR <= DataOut;
93 Rec.DEVICE_DataR <= DataOut;
@@ -101,7 +100,6 Rec.DEVICE_AddrR <= AddrOut;
101 begin
100 begin
102 if(rst='0')then
101 if(rst='0')then
103 Rec.DEVICE_DataW <= (others => '0');
102 Rec.DEVICE_DataW <= (others => '0');
104 Rec.DEVICE_Cfg(4) <= '0';
105 FlagWR <= '0';
103 FlagWR <= '0';
106 FlagRE <= '0';
104 FlagRE <= '0';
107
105
@@ -113,8 +111,6 Rec.DEVICE_AddrR <= AddrOut;
113 when "000000" =>
111 when "000000" =>
114 FlagWR <= '1';
112 FlagWR <= '1';
115 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
113 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
116 when "000010" =>
117 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
118 when others =>
114 when others =>
119 null;
115 null;
120 end case;
116 end case;
@@ -139,8 +135,7 Rec.DEVICE_AddrR <= AddrOut;
139 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
135 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
140 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
136 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
141 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
137 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
142 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
138 Rdata(31 downto 16) <= X"CCCC";
143 Rdata(31 downto 20) <= X"CCC";
144 when others =>
139 when others =>
145 Rdata <= (others => '0');
140 Rdata <= (others => '0');
146 end case;
141 end case;
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@@ -27,13 +27,12 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29
29
30
31 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
32
31
33 package lpp_memory is
32 package lpp_memory is
34
33
35 --===========================================================|
34 --===========================================================|
36 --================= FIFOW SRAM FIFOR ========================|
35 --=================== FIFO Compl�te =========================|
37 --===========================================================|
36 --===========================================================|
38
37
39 component APB_FIFO is
38 component APB_FIFO is
@@ -69,7 +68,6 component ApbDriver is
69 port (
68 port (
70 clk : in std_logic;
69 clk : in std_logic;
71 rst : in std_logic;
70 rst : in std_logic;
72 RZ : out std_logic;
73 ReadEnable : in std_logic;
71 ReadEnable : in std_logic;
74 WriteEnable : in std_logic;
72 WriteEnable : in std_logic;
75 FlagEmpty : in std_logic;
73 FlagEmpty : in std_logic;
@@ -91,15 +89,15 component Top_FIFO is
91 addr_max_int : integer := 256
89 addr_max_int : integer := 256
92 );
90 );
93 port(
91 port(
94 clk,raz : in std_logic; --! Horloge et reset general du composant
92 clk,raz : in std_logic;
95 flag_RE : in std_logic; --! Flag, Demande la lecture de la m�moire
93 flag_RE : in std_logic;
96 flag_WR : in std_logic; --! Flag, Demande l'�criture dans la m�moire
94 flag_WR : in std_logic;
97 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entr�e du composant
95 Data_in : in std_logic_vector(Data_sz-1 downto 0);
98 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'�criture
96 Addr_RE : out std_logic_vector(addr_sz-1 downto 0);
99 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
97 Addr_WR : out std_logic_vector(addr_sz-1 downto 0);
100 full : out std_logic; --! Flag, M�moire pleine
98 full : out std_logic;
101 empty : out std_logic; --! Flag, M�moire vide
99 empty : out std_logic;
102 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
100 Data_out : out std_logic_vector(Data_sz-1 downto 0)
103 );
101 );
104 end component;
102 end component;
105
103
@@ -148,7 +146,7 component Link_Reg is
148 end component;
146 end component;
149
147
150 --===========================================================|
148 --===========================================================|
151 --===================== FIFOW SRAM ==========================|
149 --================= Demi FIFO Ecriture ======================|
152 --===========================================================|
150 --===========================================================|
153
151
154 component APB_FifoWrite is
152 component APB_FifoWrite is
@@ -190,7 +188,7 component Top_FifoWrite is
190 end component;
188 end component;
191
189
192 --===========================================================|
190 --===========================================================|
193 --===================== SRAM FIFOR ==========================|
191 --================== Demi FIFO Lecture ======================|
194 --===========================================================|
192 --===========================================================|
195
193
196 component APB_FifoRead is
194 component APB_FifoRead is
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