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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Activated F2 and F3 IIR Filters for LFR_FILTERS tests....
Alexis Jeandet -
r654:d239e3167642 default draft
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1 1 VHDLIB=../..
2 2 SELFDIR := $(dir $(lastword $(MAKEFILE_LIST)))
3 3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 5 TOP=testbench
6 6 BOARD=LFR-EQM
7 7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 9 UCF=
10 10 QSF=
11 11 EFFORT=high
12 12 XSTOPT=
13 13 SYNPOPT=
14 14 VHDLSYNFILES=
15 15 VHDLSIMFILES= $(SELFDIR)/tb.vhd
16 16 SIMTOP=testbench
17 17 CLEAN=soft-clean
18 18
19 19 TECHLIBS = axcelerator
20 20
21 21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 22 tmtc openchip hynix ihp gleichmann micron usbhc opencores fmf ftlib gsi
23 23
24 24 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
25 25 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 srmmu atf \
26 26 grlfpc \
27 27 ./dsp/lpp_fft_rtax \
28 28 ./amba_lcd_16x2_ctrlr \
29 29 ./general_purpose/lpp_AMR \
30 30 ./general_purpose/lpp_balise \
31 31 ./general_purpose/lpp_delay \
32 32 ./lpp_bootloader \
33 33 ./lfr_management \
34 34 ./lpp_sim/CY7C1061DV33 \
35 35 ./lpp_cna \
36 36 ./lpp_uart \
37 37 ./lpp_usb \
38 38 ./dsp/lpp_fft \
39 39 ./lpp_leon3_soc \
40 40 ./lpp_debug_lfr
41 41
42 42 FILESKIP = i2cmst.vhd \
43 43 APB_MULTI_DIODE.vhd \
44 44 APB_MULTI_DIODE.vhd \
45 45 Top_MatrixSpec.vhd \
46 46 APB_FFT.vhd \
47 47 lpp_lfr_ms_FFT.vhd \
48 48 lpp_lfr_apbreg.vhd \
49 49 CoreFFT.vhd \
50 50 lpp_lfr_ms.vhd \
51 51 lpp_lfr_sim_pkg.vhd \
52 52 mtie_maps.vhd \
53 53 ftsrctrlc.vhd \
54 54 ftsdctrl.vhd \
55 55 ftsrctrl8.vhd \
56 56 ftmctrl.vhd \
57 57 ftsdctrl64.vhd \
58 58 ftahbram.vhd \
59 59 ftahbram2.vhd \
60 60 sramft.vhd \
61 61 nandfctrlx.vhd
62 62
63 63 include $(GRLIB)/bin/Makefile
64 64 include $(GRLIB)/software/leon3/Makefile
65 65 ################## project specific targets ##########################
66 66 distclean:myclean
67 67 vsim:cp_for_vsim
68 68
69 69 myclean:
70 70 rm -f input.txt output_f*.txt *.log
71 71 rm -rf ./2016*
72 72
73 73 generate :
74 74 python ./generate.py
75 75
76 76 cp_for_vsim: generate
77 77 cp ./input.txt simulation/
78 78
79 79 archivate:
80 80 python ./archivate.py
81 81
82 82 test-common: | generate ghdl ghdl-run archivate
83 83
84 test-vsim-common: | generate vsim vsim-run archivate
85
86 test-vsim:
87 @echo "not a Test"
88
84 89 test:
85 90 @echo "not a Test"
86 91
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@@ -1,259 +1,259
1 1
2 2 LIBRARY ieee;
3 3 USE ieee.std_logic_1164.ALL;
4 4 use ieee.numeric_std.all;
5 5 USE IEEE.std_logic_signed.ALL;
6 6 USE IEEE.MATH_real.ALL;
7 7
8 8 LIBRARY techmap;
9 9 USE techmap.gencomp.ALL;
10 10
11 11 library std;
12 12 use std.textio.all;
13 13
14 14 LIBRARY lpp;
15 15 USE lpp.iir_filter.ALL;
16 16 USE lpp.lpp_ad_conv.ALL;
17 17 USE lpp.FILTERcfg.ALL;
18 18 USE lpp.lpp_lfr_filter_coeff.ALL;
19 19 USE lpp.general_purpose.ALL;
20 20 USE lpp.data_type_pkg.ALL;
21 21 USE lpp.lpp_lfr_pkg.ALL;
22 22 USE lpp.general_purpose.ALL;
23 23 USE lpp.lpp_sim_pkg.ALL;
24 24
25 25 ENTITY testbench IS
26 26 GENERIC(
27 27 tech : INTEGER := 0; --axcel,0
28 28 Mem_use : INTEGER := use_CEL --use_RAM,use_CEL
29 29 );
30 30 END;
31 31
32 32 ARCHITECTURE behav OF testbench IS
33 33 CONSTANT ChanelCount : INTEGER := 8;
34 34
35 35 SIGNAL TSTAMP : INTEGER:=0;
36 36 SIGNAL clk : STD_LOGIC := '0';
37 37 SIGNAL clk_98304Hz : STD_LOGIC := '0';
38 38 SIGNAL clk_98304Hz_r : STD_LOGIC := '0';
39 39 SIGNAL rstn : STD_LOGIC;
40 40
41 41 SIGNAL signal_gen : sample_vector(0 to ChanelCount-1,15 downto 0);
42 42
43 43 SIGNAL sample : Samples(7 DOWNTO 0);
44 44
45 45 SIGNAL sample_val : STD_LOGIC;
46 46
47 47 SIGNAL sample_f0_val : STD_LOGIC;
48 48 SIGNAL sample_f1_val : STD_LOGIC;
49 49 SIGNAL sample_f2_val : STD_LOGIC;
50 50 SIGNAL sample_f3_val : STD_LOGIC;
51 51
52 52 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
53 53 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
54 54 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
55 55 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
56 56
57 57 SIGNAL signal_f0_rec : sample_vector(0 to 5,15 downto 0);
58 58 SIGNAL signal_f1_rec : sample_vector(0 to 5,15 downto 0);
59 59 SIGNAL signal_f2_rec : sample_vector(0 to 5,15 downto 0);
60 60 SIGNAL signal_f3_rec : sample_vector(0 to 5,15 downto 0);
61 61
62 62 SIGNAL end_of_simu : STD_LOGIC := '0';
63 63
64 64 CONSTANT half_samplig_period : time := 5086263 ps;--INTEGER( REAL(REAL(1000**4) / REAL(2.0*4.0*24576.0))) * 1 ps;
65 65
66 66
67 67
68 68 BEGIN
69 69
70 70 -----------------------------------------------------------------------------
71 71 -- CLOCK and RESET
72 72 -----------------------------------------------------------------------------
73 73 PROCESS
74 74 BEGIN -- PROCESS
75 75 WAIT UNTIL clk = '1';
76 76 rstn <= '0';
77 77 WAIT UNTIL clk = '1';
78 78 WAIT UNTIL clk = '1';
79 79 WAIT UNTIL clk = '1';
80 80 rstn <= '1';
81 81 WAIT UNTIL end_of_simu = '1';
82 82 WAIT FOR 10 ps;
83 83 assert false report "end of test" severity note;
84 84 -- Wait forever; this will finish the simulation.
85 85 wait;
86 86 END PROCESS;
87 87 -----------------------------------------------------------------------------
88 88
89 89
90 90 clk_98304Hz_gen:PROCESS
91 91 BEGIN
92 92 IF end_of_simu /= '1' THEN
93 93 clk_98304Hz <= NOT clk_98304Hz;
94 94 WAIT FOR half_samplig_period;
95 95 ELSE
96 96 WAIT FOR 10 ps;
97 97 assert false report "end of test" severity note;
98 98 WAIT;
99 99 END IF;
100 100 END PROCESS;
101 101
102 102 clk_25M_gen:PROCESS
103 103 BEGIN
104 104 IF end_of_simu /= '1' THEN
105 105 clk <= NOT clk;
106 106 TSTAMP <= TSTAMP+20;
107 107 WAIT FOR 20 ns;
108 108 ELSE
109 109 WAIT FOR 10 ps;
110 110 assert false report "end of test" severity note;
111 111 WAIT;
112 112 END IF;
113 113 END PROCESS;
114 114
115 115
116 116 -----------------------------------------------------------------------------
117 117 -- LPP_LFR_FILTER
118 118 -----------------------------------------------------------------------------
119 119 lpp_lfr_filter_1: lpp_lfr_filter
120 120 GENERIC MAP (
121 121 tech => tech,
122 122 Mem_use => Mem_use,
123 RTL_DESIGN_LIGHT =>1
123 RTL_DESIGN_LIGHT =>0
124 124 )
125 125 PORT MAP (
126 126 sample => sample,
127 127 sample_val => sample_val,
128 128 sample_time => (others=>'0'),
129 129 clk => clk,
130 130 rstn => rstn,
131 131
132 132 data_shaping_SP0 => '0',
133 133 data_shaping_SP1 => '0',
134 134 data_shaping_R0 => '0',
135 135 data_shaping_R1 => '0',
136 136 data_shaping_R2 => '0',
137 137
138 138 sample_f0_val => sample_f0_val,
139 139 sample_f1_val => sample_f1_val,
140 140 sample_f2_val => sample_f2_val,
141 141 sample_f3_val => sample_f3_val,
142 142
143 143 sample_f0_wdata => sample_f0_wdata,
144 144 sample_f1_wdata => sample_f1_wdata,
145 145 sample_f2_wdata => sample_f2_wdata,
146 146 sample_f3_wdata => sample_f3_wdata
147 147 );
148 148 -----------------------------------------------------------------------------
149 149
150 150
151 151 -----------------------------------------------------------------------------
152 152 -- SAMPLE PULSE GENERATION
153 153 -----------------------------------------------------------------------------
154 154 PROCESS (clk, rstn)
155 155 BEGIN -- PROCESS
156 156 IF rstn = '0' THEN -- asynchronous reset (active low)
157 157 sample_val <= '0';
158 158 clk_98304Hz_r <= '0';
159 159 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
160 160 clk_98304Hz_r <= clk_98304Hz;
161 161 IF clk_98304Hz = '1' AND clk_98304Hz_r = '0' THEN
162 162 sample_val <= '1';
163 163 ELSE
164 164 sample_val <= '0';
165 165 END IF;
166 166 END IF;
167 167 END PROCESS;
168 168 -----------------------------------------------------------------------------
169 169
170 170
171 171 -----------------------------------------------------------------------------
172 172 -- READ INPUT SIGNALS
173 173 -----------------------------------------------------------------------------
174 174 gen: sig_reader
175 175 GENERIC MAP(
176 176 FNAME => "input.txt",
177 177 WIDTH => ChanelCount,
178 178 RESOLUTION => 16,
179 179 GAIN => 1.0
180 180 )
181 181 PORT MAP(
182 182 clk => sample_val,
183 183 end_of_simu => end_of_simu,
184 184 out_signal => signal_gen
185 185 );
186 186
187 187 ChanelLoop : FOR i IN 0 TO ChanelCount-1 GENERATE
188 188 SampleLoop : FOR j IN 0 TO 15 GENERATE
189 189 sample(I)(J) <= signal_gen(I,J);
190 190 END GENERATE;
191 191 END GENERATE;
192 192
193 193 output_splitter: FOR CHAN IN 0 TO 5 GENERATE
194 194 bits_splitter: FOR BIT IN 0 TO 15 GENERATE
195 195 signal_f0_rec(CHAN,BIT) <= sample_f0_wdata((CHAN*16) + BIT);
196 196 signal_f1_rec(CHAN,BIT) <= sample_f1_wdata((CHAN*16) + BIT);
197 197 signal_f2_rec(CHAN,BIT) <= sample_f2_wdata((CHAN*16) + BIT);
198 198 signal_f3_rec(CHAN,BIT) <= sample_f3_wdata((CHAN*16) + BIT);
199 199 END GENERATE bits_splitter;
200 200 END GENERATE output_splitter;
201 201
202 202
203 203 -----------------------------------------------------------------------------
204 204 -- RECORD SIGNALS
205 205 -----------------------------------------------------------------------------
206 206
207 207 f0_rec : sig_recorder
208 208 GENERIC MAP(
209 209 FNAME => "output_f0.txt",
210 210 WIDTH => 6,
211 211 RESOLUTION => 16
212 212 )
213 213 PORT MAP(
214 214 clk => sample_f0_val,
215 215 end_of_simu => end_of_simu,
216 216 timestamp => TSTAMP,
217 217 input_signal => signal_f0_rec
218 218 );
219 219
220 220 f1_rec : sig_recorder
221 221 GENERIC MAP(
222 222 FNAME => "output_f1.txt",
223 223 WIDTH => 6,
224 224 RESOLUTION => 16
225 225 )
226 226 PORT MAP(
227 227 clk => sample_f1_val,
228 228 end_of_simu => end_of_simu,
229 229 timestamp => TSTAMP,
230 230 input_signal => signal_f1_rec
231 231 );
232 232
233 233 f2_rec : sig_recorder
234 234 GENERIC MAP(
235 235 FNAME => "output_f2.txt",
236 236 WIDTH => 6,
237 237 RESOLUTION => 16
238 238 )
239 239 PORT MAP(
240 240 clk => sample_f2_val,
241 241 end_of_simu => end_of_simu,
242 242 timestamp => TSTAMP,
243 243 input_signal => signal_f2_rec
244 244 );
245 245
246 246 f3_rec : sig_recorder
247 247 GENERIC MAP(
248 248 FNAME => "output_f3.txt",
249 249 WIDTH => 6,
250 250 RESOLUTION => 16
251 251 )
252 252 PORT MAP(
253 253 clk => sample_f3_val,
254 254 end_of_simu => end_of_simu,
255 255 timestamp => TSTAMP,
256 256 input_signal => signal_f3_rec
257 257 );
258 258
259 259 END;
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@@ -1,4 +1,6
1 1 include ../Validation_LFR_Filters/Makefile
2 2
3 3
4 4 test:test-common
5
6 test-vsim:test-vsim-common
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@@ -1,8 +1,13
1 1 import numpy as np
2 2 import random
3 3
4 W,H=8,100000
5 low,high=-1000,1000
4 W,H=8,6000000
5 low,high=-100,100
6 INPUT_F=98304
6 7 test = np.random.randint(low=low,high=high,size=(H,W))
8 test+=np.tile((3.*np.cos(np.arange(len(test)) *2.*np.pi * 3. /INPUT_F )).astype(int),(8,1)).transpose()
9 test+=np.tile((3.*np.cos(np.arange(len(test)) *2.*np.pi * 16. /INPUT_F )).astype(int),(8,1)).transpose()
10 test+=np.tile((3.*np.cos(np.arange(len(test)) *2.*np.pi * 256. /INPUT_F )).astype(int),(8,1)).transpose()
11 test+=np.tile((3.*np.cos(np.arange(len(test)) *2.*np.pi * 2048. /INPUT_F )).astype(int),(8,1)).transpose()
7 12 np.savetxt("input.txt", test,fmt="%d", delimiter=" ")
8 13
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@@ -1,4 +1,6
1 1 include ../Validation_LFR_Filters/Makefile
2 2
3 3
4 4 test:test-common
5
6 test-vsim:test-vsim-common
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