HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r248:d170a7fb48c0

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lib/lpp/lpp_cna/ReadFifo_GEN.vhd created 644 +67 0

@@ -0,0 +1,67
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	------------------------------------------------------------------------------
	19	-- Author : Martin Morlot
	20	-- Mail : martin.morlot@lpp.polytechnique.fr
	21	------------------------------------------------------------------------------
	22	library IEEE;
	23	use IEEE.numeric_std.all;
	24	use IEEE.std_logic_1164.all;
	25
	26	entity ReadFifo_GEN is
	27	port(
	28	clk,raz : in std_logic; --! Horloge et Reset du composant
	29	SYNC : in std_logic;
	30	Readn : out std_logic
	31	);
	32	end entity;
	33
	34
	35	architecture ar_ReadFifo_GEN of ReadFifo_GEN is
	36
	37	type etat is (eX,e0);
	38	signal ect : etat;
	39
	40	signal SYNC_reg : std_logic;
	41
	42	begin
	43	process(clk,raz)
	44	begin
	45	if(raz='0')then
	46	ect <= eX;
	47	Readn <= '1';
	48
	49	elsif(clk'event and clk='1')then
	50	SYNC_reg <= SYNC;
	51
	52	case ect is
	53	when eX =>
	54	if (SYNC_reg='0' and SYNC='1') then
	55	Readn <= '0';
	56	ect <= e0;
	57	end if;
	58
	59	when e0 =>
	60	Readn <= '1';
	61	ect <= eX;
	62
	63	end case;
	64	end if;
	65	end process;
	66
	67	end architecture; No newline at end of file

LPP_drivers/libsrc/FIFO/apb_fifo_Driver.c +1 -1

                 int i=0;
                 //int poub;
                 //printf("%x\n",dev->FIFOreg[(2*0)+FIFO_Ctrl]);
-                while(i<count)
+                while(i<=count)
                 //while((dev->FIFOreg[(2*ID)+FIFO_Ctrl] & FIFO_Full) != FIFO_Full)// TANT QUE  full a 0  ALORS
                 {
                     //printf("%x\n",dev->FIFOreg[(2*ID)+FIFO_Ctrl]);

lib/lpp/lpp_cna/APB_DAC.vhd +23 -18

                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
-                abits    : integer := 8);
+                abits    : integer := 8;
+                cpt_serial : integer := 6);
               port (
                 clk     : in  std_logic;           --! Horloge du composant
                 rst     : in  std_logic;           --! Reset general du composant
                 apbi    : in  apb_slv_in_type;     --! Registre de gestion des entr�es du bus
                 apbo    : out apb_slv_out_type;    --! Registre de gestion des sorties du bus
+                DataIN : in std_logic_vector(15 downto 0);
                 Cal_EN  : out std_logic;           --! Signal Enable du multiplex pour la CAL
+                Readn   : out std_logic;
                 SYNC    : out std_logic;           --! Signal de synchronisation du convertisseur
                 SCLK    : out std_logic;           --! Horloge systeme du convertisseur
                 DATA    : out std_logic            --! Donn�e num�rique s�rialis�
 => apb_iobar(paddr, pmask));
             signal enable   : std_logic;
-            signal flag_sd : std_logic;
+            --signal flag_sd : std_logic;
             type DAC_ctrlr_Reg is record
-                 DAC_Cfg  : std_logic_vector(1 downto 0);
+                 DAC_Enable  : std_logic_vector(0 downto 0);
-                 DAC_Data : std_logic_vector(15 downto 0);
+            --     DAC_Data : std_logic_vector(15 downto 0);
             end record;
             signal Rec : DAC_ctrlr_Reg;
             begin
-            enable <= Rec.DAC_Cfg(0);
+            enable <= Rec.DAC_Enable(0);
-            Rec.DAC_Cfg(1) <= flag_sd;
+            --Rec.DAC_Cfg(1) <= flag_sd;
                 CONV0 : DacDriver
-                    port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
+                    generic map(cpt_serial)
+                    port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Data);
                 process(rst,clk)
                 begin
                     if(rst='0')then
-                        Rec.DAC_Data <=  (others => '0');
+                        --Rec.DAC_Data <=  (others => '0');
+                        Rec.DAC_Enable(0) <= '0';
                     elsif(clk'event and clk='1')then
                         if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    Rec.DAC_Cfg(0) <= apbi.pwdata(0);
+                                    Rec.DAC_Enable(0) <= apbi.pwdata(0);
-                                when "000001" =>
+            --                    when "000001" =>
-                                    Rec.DAC_Data <= apbi.pwdata(15 downto 0);
+            --                        Rec.DAC_Data <= apbi.pwdata(15 downto 0);
                                 when others =>
                                     null;
                             end case;
                         if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
                             case apbi.paddr(abits-1 downto 2) is
                                 when "000000" =>
-                                    Rdata(31 downto 2) <= X"ABCDEF5" & "00";
+                                    Rdata(31 downto 1) <= (others => '0');--X"ABCDEF5" & "00";
-                                    Rdata(1 downto 0) <= Rec.DAC_Cfg;
+                                    Rdata(0 downto 0) <= Rec.DAC_Enable;
-                                when "000001" =>
+             --                   when "000001" =>
-                                    Rdata(31 downto 16) <= X"FD18";
+             --                       Rdata(31 downto 16) <= X"FD18";
-                                    Rdata(15 downto 0) <= Rec.DAC_Data;
+             --                       Rdata(15 downto 0) <= Rec.DAC_Data;
                                 when others =>
                                     Rdata <= (others => '0');
                             end case;
                 end process;
             apbo.prdata     <=   Rdata when apbi.penable = '1';
-            Cal_EN <= enable;
+            Cal_EN <= Rec.DAC_Enable(0);
-            end architecture;
+            end architecture;
  No newline at end of file

lib/lpp/lpp_cna/DacDriver.vhd +10 -7

             library IEEE;
             use IEEE.std_logic_1164.all;
             use IEEE.numeric_std.all;
-            use work.Convertisseur_config.all;
             use lpp.lpp_cna.all;
             --! Programme du Convertisseur Num�rique/Analogique
             entity DacDriver is
+              generic(cpt_serial : integer := 6);  --! G�n�rique contenant le r�sultat de la division clk/sclk  !!! clk=25Mhz
               port(
                 clk         : in std_logic;                        --! Horloge du composant
                 rst         : in std_logic;                        --! Reset general du composant
                 enable      : in std_logic;                        --! Autorise ou non l'utilisation du composant
-                Data_C      : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
+                Data_reg    : in std_logic_vector(15 downto 0);    --! Donn�e Num�rique d'entr�e sur 16 bits
                 SYNC        : out std_logic;                       --! Signal de synchronisation du convertisseur
                 SCLK        : out std_logic;                       --! Horloge systeme du convertisseur
-                flag_sd     : out std_logic;                       --! Flag, signale la fin de la s�rialisation d'une donn�e
+                Readn       : out std_logic;
                 Data        : out std_logic                        --! Donn�e num�rique s�rialis�
                 );
             end entity;
             architecture ar_DacDriver of DacDriver is
             signal s_SCLK      : std_logic;
-            signal OKAI_send    : std_logic;
+            signal s_SYNC    : std_logic;
             begin
             SystemCLK : Systeme_Clock
-                generic map (nb_serial)
+                generic map (cpt_serial)
                 port map (clk,rst,s_SCLK);
             Signal_sync : Gene_SYNC
-                port map (s_SCLK,rst,enable,OKAI_send,SYNC);
+                port map (s_SCLK,rst,enable,s_SYNC);
             Serial : serialize
-                port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
+                port map (clk,rst,s_SCLK,Data_reg,s_SYNC,Data);
+            RenGEN : ReadFifo_GEN
+                port map (clk,rst,s_SYNC,Readn);
             SCLK        <= s_SCLK;
+            SYNC        <= s_SYNC;
             end architecture;

lib/lpp/lpp_cna/Gene_SYNC.vhd +8 -7

               port(
                 SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
                 enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-                OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
+            --    OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
                 SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
                 );
             end Gene_SYNC;
                     if(raz='0')then
                         SYNC <= '0';
                         count <= 14;
-                        OKAI_send <= '0';
+            --            OKAI_send <= '0';
                     elsif(SCLK' event and SCLK='1')then
                         if(enable='1')then
                             if(count=15)then
                                 SYNC <= '1';
-                                count <= count+1;
+            --                    count <= count+1;
-                            elsif(count=16)then
+            --                elsif(count=16)then
                                 count <= 0;
-                                SYNC <= '0';
+            --                    SYNC <= '0';
-                                OKAI_send <= '1';
+            --                    OKAI_send <= '1';
                             else
                                 count <= count+1;
-                                OKAI_send <= '0';
+                                SYNC <= '0';
+            --                    OKAI_send <= '0';
                             end if;
                         end if;

lib/lpp/lpp_cna/Serialize.vhd +16 -7

                 sclk    : in std_logic;                      --! Horloge Systeme
                 vectin  : in std_logic_vector(15 downto 0);  --! Vecteur d'entr�e
                 send    : in std_logic;                      --! Flag, Une nouvelle donn�e est pr�sente
-                sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
+            --    sended  : out std_logic;                     --! Flag, La donn�e a �t� s�rialis�e
                 Data    : out std_logic                      --! Donn�e num�rique s�rialis�
                 );
             end Serialize;
             architecture ar_Serialize of Serialize is
-            type etat is (attente,serialize);
+            type etat is (attente,serialize,reg);
             signal ect      : etat;
             signal vector_int   : std_logic_vector(16 downto 0);
             signal load         : std_logic;
             signal N            : integer range 0 to 16;
             signal CPT_ended    : std_logic:='0';
+            signal i            : std_logic;
             begin
                 process(clk,raz)
                         ect         <= attente;
                         vectin_reg  <= (others=> '0');
                         load        <= '0';
-                        sended      <= '1';
+                        i <= '1';
+            --            sended      <= '1';
                     elsif(clk'event and clk='1')then
                         vectin_reg <= vectin;
                         case ect is
                             when attente =>
                                 if (send='1') then
-                                    sended  <= '0';
+            --                        sended  <= '0';
+                                    if(i='1')then
+                                        i <= '0';
+                                        ect <= reg;
+                                    else
                                         load    <= '1';
                                         ect     <= serialize;
-                                else
+                                    end if;
-                                    ect <= attente;
                                 end if;
+                            when reg =>
+                                load    <= '1';
+                                ect <= serialize;
                             when serialize =>
                                 load <= '0';
                                 if(CPT_ended='1')then
                                     ect     <= attente;
-                                    sended  <= '1';
+            --                        sended  <= '1';
                                 end if;
                         end case;

lib/lpp/lpp_cna/lpp_cna.vhd +21 -9

                 paddr    : integer := 0;
                 pmask    : integer := 16#fff#;
                 pirq     : integer := 0;
-                abits    : integer := 8);
+                abits    : integer := 8;
+                cpt_serial : integer := 6);
               port (
                 clk     : in  std_logic;
                 rst     : in  std_logic;
                 apbi    : in  apb_slv_in_type;
                 apbo    : out apb_slv_out_type;
+                DataIN : in std_logic_vector(15 downto 0);
                 Cal_EN  : out std_logic;
+                Readn   : out std_logic;
                 SYNC    : out std_logic;
                 SCLK    : out std_logic;
                 DATA    : out std_logic
             component DacDriver is
+                generic(cpt_serial : integer := 6);
                 port(
                     clk       : in std_logic;
                     rst         : in std_logic;
                     enable      : in std_logic;
-                    Data_C      : in std_logic_vector(15 downto 0);
+                    Data_reg      : in std_logic_vector(15 downto 0);
                     SYNC        : out std_logic;
                     SCLK        : out std_logic;
-                    flag_sd     : out std_logic;
+                    Readn     : out std_logic;
                     Data        : out std_logic
                     );
             end component;
             component Gene_SYNC is
               port(
-                    clk,raz     : in std_logic;
+                SCLK,raz : in std_logic;     --! Horloge systeme et Reset du composant
-                    send     : in std_logic;
+                enable : in std_logic;       --! Autorise ou non l'utilisation du composant
-                    Sysclk      : in std_logic;
+            --    OKAI_send : out std_logic;   --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
-                    OKAI_send   : out std_logic;
+                SYNC : out std_logic         --! Signal de synchronisation du convertisseur g�n�r�
-                    SYNC        : out std_logic);
+                );
             end component;
                 sclk    : in std_logic;
                 vectin  : in std_logic_vector(15 downto 0);
                 send    : in std_logic;
-                sended  : out std_logic;
+            --    sended  : out std_logic;
                 Data    : out std_logic);
             end component;
+            component ReadFifo_GEN is
+              port(
+                clk,raz : in std_logic;
+                SYNC : in std_logic;
+                Readn : out std_logic
+                );
+            end component;
             end;

lib/lpp/lpp_cna/Convertisseur_config.vhd removed 0 -34

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