HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r269:cda86f81a8b0

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Jeandet Alexis -

r269:cda86f81a8b0 alexis

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r269:cda86f81a8b0

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Makefile 0 -1

             link:
             	sh $(SCRIPTSDIR)/vhdlsynPatcher.sh
             	sh $(SCRIPTSDIR)/linklibs.sh $(GRLIB)
-            	sh $(SCRIPTSDIR)/patchboards.sh $(GRLIB)
             dist: init
             	tar -cvzf ./../lpp-lib.tgz ./../VHD_Lib/*

boards/BeagleSynth/default.ucf +2 -2

             NET "CLK"      CLOCK_DEDICATED_ROUTE = FALSE;
             NET "CLK"              LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
-            #NET "CLKM" TNM_NET = "clkm_net";
+            NET "CLKM" TNM_NET = "clkm_net";
-            #TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
+            TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
             NET "RESET"    CLOCK_DEDICATED_ROUTE = FALSE;
             NET "RESET"            LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;

designs/BeagleSynth/BeagleSynth.vhd +7 -5

             --sdclk <= sdclkl;
             sdclk <= sdclkl_DDR2;
+            LED(1)  <= not cgo.clklock;
+            LED(0)  <= cgo.clklock;
             ODDR2_inst : ODDR2
                generic map(
-                  DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
+                  DDR_ALIGNMENT => "NONE", -- Sets output alignment to "NONE", "C0", "C1"
                   INIT => '0', -- Sets initial state of the Q output to '0' or '1'
-                  SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
+                  SRTYPE => "SYNC") -- Specifies "SYNC" or "ASYNC" set/reset
                port map (
                   Q => sdclkl_DDR2, -- 1-bit output data
                   C0 => sdclkl, -- 1-bit clock input
                 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
                 ahbuarti.rxd  <= RXD;
                 TXD           <= ahbuarto.txd;
-                led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd;
               end generate;
               nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
             -- connect memory controller outputs to entity output signals
             Address <= sdo.address(13 downto 2);
-            sdba	  <= sdo.address(16 downto 15);
+            --sdba	  <= sdo.address(16 downto 15);
+            sdba	  <= "00";
             sdcke <= sdo.sdcke(0);
             sdwen <= sdo.sdwen;
             sdcsn <= sdo.sdcsn(0);
             sdrasn <= sdo.rasn;
             sdcasn <= sdo.casn;
             sddqm <= sdo.dqm(3 downto 0);
-            --sdi.data(31 downto 0) <= data(31 downto 0);

designs/BeagleSynth/Makefile +1 -1

             VHDLSYNFILES= \
-            	config.vhd  BeagleSynth.vhd
+            	config.vhd  BeagleSynth.vhd BeagleSynth_MCTRL.vhd
             #VHDLSIMFILES=testbench.vhd
             #SIMTOP=testbench
             #SDCFILE=$(GRLIB)/boards/$(BOARD)/default.sdc

designs/BeagleSynth/config.vhd +4 -3

               constant CFG_MEMTECH : integer := spartan6;
               constant CFG_PADTECH : integer := spartan6;
             -- Clock generator
+            --  ON Spartan 6 VCO freq must be between 400MHz and 1GHz
               constant CFG_CLKTECH : integer := spartan6;
-              constant CFG_CLKMUL : integer := (2);
+              constant CFG_CLKMUL : integer := (6);
-              constant CFG_CLKDIV : integer := (8);
+              constant CFG_CLKDIV : integer := (12);
               constant CFG_OCLKDIV : integer := (1);
               constant CFG_PCIDLL : integer := 0;
               constant CFG_PCISYSCLK: integer := 0;

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