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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39 ./dsp/lpp_fft_rtax \
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd \
46 lpp_lfr_apbreg.vhd \
47 CoreFFT.vhd
48
49 include $(GRLIB)/bin/Makefile
50 include $(GRLIB)/software/leon3/Makefile
51
52 ################## project specific targets ##########################
53
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1 NO CONTENT: new file 100644, binary diff hidden
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1 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/chirp/chirp_pkg.vhd
2 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/chirp/chirp.vhd
3 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd
4 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic.vhd
5 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_integrator.vhd
6 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_downsampler.vhd
7 vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_comb.vhd
8
9 vcom -quiet -93 -work work tb.vhd
10
11 vsim work.testbench
12
13 log -r *
14
15 do wave.do
16
17 run -all
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1
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
4 USE IEEE.MATH_REAL.ALL;
5 USE ieee.numeric_std.ALL;
6
7 LIBRARY lpp;
8 USE lpp.cic_pkg.ALL;
9 USE lpp.chirp_pkg.ALL;
10
11 ENTITY testbench IS
12 END;
13
14 ARCHITECTURE behav OF testbench IS
15
16 SIGNAL clk : STD_LOGIC := '0';
17 SIGNAL rstn : STD_LOGIC;
18 SIGNAL run : STD_LOGIC;
19 SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
20 SIGNAL data_in_valid : STD_LOGIC;
21 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
22 SIGNAL data_out_valid : STD_LOGIC;
23
24 BEGIN
25
26 clk <= NOT clk AFTER 5 ns;
27
28 PROCESS
29 BEGIN -- PROCESS
30 WAIT UNTIL clk = '1';
31 rstn <= '0';
32 run <= '0';
33 data_in_valid <= '0';
34
35 WAIT UNTIL clk = '1';
36 rstn <= '1';
37 WAIT UNTIL clk = '1';
38 WAIT UNTIL clk = '1';
39 run <= '1';
40 WAIT UNTIL clk = '1';
41 WAIT UNTIL clk = '1';
42 data_in_valid <= '1';
43 WAIT FOR 105 us;
44 REPORT "*** END simulation ***" SEVERITY failure;
45 WAIT;
46 END PROCESS;
47 -----------------------------------------------------------------------------
48 DUT_cic: cic
49 GENERIC MAP (
50 D_delay_number => 2,
51 S_stage_number => 3,
52 R_downsampling_decimation_factor => 16,
53 b_data_size => 16,
54 b_grow => 15)
55 PORT MAP (
56 clk => clk,
57 rstn => rstn,
58 run => run,
59 data_in => data_in,
60 data_in_valid => data_in_valid,
61 data_out => data_out,
62 data_out_valid => data_out_valid);
63 -----------------------------------------------------------------------------
64 chirp_gen: chirp
65 GENERIC MAP (
66 LOW_FREQUENCY_LIMIT => 0,
67 HIGH_FREQUENCY_LIMIT => 1000,
68 NB_POINT_TO_GEN => 10000,
69 AMPLITUDE => 200,
70 NB_BITS => 16)
71 PORT MAP (
72 clk => clk,
73 rstn => rstn,
74 run => run,
75 data_ack => data_in_valid,
76 data => data_in);
77
78 END;
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1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate /testbench/dut_cic/d_delay_number
4 add wave -noupdate /testbench/dut_cic/s_stage_number
5 add wave -noupdate /testbench/dut_cic/r_downsampling_decimation_factor
6 add wave -noupdate -format Analog-Step -height 74 -max 1999.9999999999998 /testbench/chirp_gen/freq_chirp
7 add wave -noupdate -format Analog-Step -height 74 -max 10000.0 /testbench/chirp_gen/n
8 add wave -noupdate -format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal /testbench/dut_cic/data_in
9 add wave -noupdate -format Analog-Step -height 74 -max 189.0 -min -172.0 -radix decimal /testbench/dut_cic/data_out
10 add wave -noupdate -divider COMB
11 add wave -noupdate -radix decimal -expand -subitemconfig {/testbench/dut_cic/c_data(3) {-format Analog-Step -height 74 -max 6208650.0000000009 -min -5630018.0 -radix decimal} /testbench/dut_cic/c_data(2) {-format Analog-Step -height 74 -max 22640530.0 -radix decimal} /testbench/dut_cic/c_data(1) {-format Analog-Step -height 74 -max 1067269590.0 -min -1072646474.0 -radix decimal} /testbench/dut_cic/c_data(0) {-format Analog-Step -height 74 -max 1071549238.9999998 -min -1068913901.0 -radix decimal}} /testbench/dut_cic/c_data
12 add wave -noupdate -divider INTEGRATOR
13 add wave -noupdate -radix decimal -expand -subitemconfig {/testbench/dut_cic/i_data(3) {-format Analog-Step -height 74 -max 1073731108.9999998 -min -1073537753.0 -radix decimal} /testbench/dut_cic/i_data(2) {-format Analog-Step -height 74 -max 164477947.0 -radix decimal} /testbench/dut_cic/i_data(1) {-format Analog-Step -height 74 -max 22580.0 -radix decimal} /testbench/dut_cic/i_data(0) {-format Analog-Step -height 74 -max 200.0 -min -200.0 -radix decimal}} /testbench/dut_cic/i_data
14 TreeUpdate [SetDefaultTree]
15 WaveRestoreCursors {{Cursor 1} {3685000 ps} 0}
16 configure wave -namecolwidth 370
17 configure wave -valuecolwidth 40
18 configure wave -justifyvalue left
19 configure wave -signalnamewidth 0
20 configure wave -snapdistance 10
21 configure wave -datasetprefix 0
22 configure wave -rowmargin 4
23 configure wave -childrowmargin 2
24 configure wave -gridoffset 0
25 configure wave -gridperiod 1
26 configure wave -griddelta 40
27 configure wave -timeline 0
28 configure wave -timelineunits ns
29 update
30 WaveRestoreZoom {0 ps} {110307750 ps}
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE IEEE.std_logic_arith.ALL;
27 USE IEEE.std_logic_signed.ALL;
28 USE IEEE.MATH_real.ALL;
29
30 ENTITY chirp IS
31
32 GENERIC (
33 LOW_FREQUENCY_LIMIT : INTEGER := 0;
34 HIGH_FREQUENCY_LIMIT : INTEGER := 2000;
35 NB_POINT_TO_GEN : INTEGER := 10000;
36 AMPLITUDE : INTEGER := 100;
37 NB_BITS : INTEGER := 16);
38
39 PORT (
40 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
42 run : IN STD_LOGIC;
43
44 data_ack : IN STD_LOGIC;
45 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
46 );
47
48 END chirp;
49
50 ARCHITECTURE beh OF chirp IS
51
52 SIGNAL reg : STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0);
53 SIGNAL n : INTEGER;
54 SIGNAL current_time : REAL := REAL(0);
55 SIGNAL freq_chirp : REAL := REAL(0);
56 BEGIN -- beh
57
58 current_time <= REAL(n) / REAL(NB_POINT_TO_GEN);
59 freq_chirp <= REAL(LOW_FREQUENCY_LIMIT) + (REAL(HIGH_FREQUENCY_LIMIT) - REAL(LOW_FREQUENCY_LIMIT))*current_time;
60
61 PROCESS (clk, rstn)
62 BEGIN -- PROCESS
63 IF rstn = '0' THEN -- asynchronous reset (active low)
64 reg <= (OTHERS => '0');
65 n <= 0;
66 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
67 IF run = '0' THEN
68 reg <= (OTHERS => '0');
69 n <= 0;
70 ELSE
71 IF data_ack = '1' THEN
72 IF n < NB_POINT_TO_GEN THEN
73 n <= n+1;
74 reg <= conv_std_logic_vector(INTEGER(REAL(AMPLITUDE) * SIN(MATH_2_PI*current_time*freq_chirp)),NB_BITS);
75 ELSE
76 reg <= (OTHERS => '0');
77 END IF;
78 END IF;
79 END IF;
80 END IF;
81 END PROCESS;
82
83 data <= reg;
84
85 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 PACKAGE chirp_pkg IS
28
29 COMPONENT chirp
30 GENERIC (
31 LOW_FREQUENCY_LIMIT : INTEGER;
32 HIGH_FREQUENCY_LIMIT : INTEGER;
33 NB_POINT_TO_GEN : INTEGER;
34 AMPLITUDE : INTEGER;
35 NB_BITS : INTEGER);
36 PORT (
37 clk : IN STD_LOGIC;
38 rstn : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40 data_ack : IN STD_LOGIC;
41 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0));
42 END COMPONENT;
43
44
45 END chirp_pkg;
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1 chirp_pkg.vhd
2 chirp.vhd
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 LIBRARY lpp;
28 USE lpp.cic_pkg.ALL;
29
30 ENTITY cic IS
31
32 GENERIC (
33 D_delay_number : INTEGER := 2;
34 S_stage_number : INTEGER := 3;
35 R_downsampling_decimation_factor : INTEGER := 16;
36
37 b_data_size : INTEGER := 16;
38 b_grow : INTEGER := 5 --
39 );
40
41 PORT (
42 clk : IN STD_LOGIC;
43 rstn : IN STD_LOGIC;
44 run : IN STD_LOGIC;
45
46 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
47 data_in_valid : IN STD_LOGIC;
48
49 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
50 data_out_valid : OUT STD_LOGIC
51 );
52
53 END cic;
54
55 ARCHITECTURE beh OF cic IS
56
57 TYPE data_vector IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(b_data_size + b_grow - 1 DOWNTO 0);
58
59 SIGNAL I_data : data_vector(S_stage_number DOWNTO 0);
60 SIGNAL I_valid : STD_LOGIC_VECTOR(S_stage_number DOWNTO 0);
61
62 SIGNAL C_data : data_vector(S_stage_number DOWNTO 0);
63 SIGNAL C_valid : STD_LOGIC_VECTOR(S_stage_number DOWNTO 0);
64
65 BEGIN -- beh
66 -----------------------------------------------------------------------------
67 I_valid(0) <= data_in_valid;
68 I_data(0)(b_data_size-1 DOWNTO 0) <= data_in;
69 all_bit_grow: FOR I IN 0 TO b_grow-1 GENERATE
70 I_data(0)(I+b_data_size) <= data_in(b_data_size-1);
71 END GENERATE all_bit_grow;
72 -----------------------------------------------------------------------------
73 all_I: FOR S_i IN 1 TO S_stage_number GENERATE
74 I_1: cic_integrator
75 GENERIC MAP (
76 b_data_size => b_data_size + b_grow)
77 PORT MAP (
78 clk => clk,
79 rstn => rstn,
80 run => run,
81
82 data_in => I_data(S_i-1),
83 data_in_valid => I_valid(S_i-1),
84 data_out => I_data(S_i),
85 data_out_valid => I_valid(S_i)
86 );
87 END GENERATE all_I;
88 -----------------------------------------------------------------------------
89 cic_downsampler_1: cic_downsampler
90 GENERIC MAP (
91 R_downsampling_decimation_factor => R_downsampling_decimation_factor,
92 b_data_size => b_data_size + b_grow)
93 PORT MAP (
94 clk => clk,
95 rstn => rstn,
96 run => run,
97 data_in => I_data(S_stage_number),
98 data_in_valid => I_valid(S_stage_number),
99 data_out => C_data(0),
100 data_out_valid => C_valid(0));
101 -----------------------------------------------------------------------------
102 all_C: FOR S_i IN 1 TO S_stage_number GENERATE
103 cic_comb_1: cic_comb
104 GENERIC MAP (
105 b_data_size => b_data_size + b_grow,
106 D_delay_number => D_delay_number)
107 PORT MAP (
108 clk => clk,
109 rstn => rstn,
110 run => run,
111
112 data_in => C_data(S_i-1),
113 data_in_valid => C_valid(S_i-1),
114 data_out => C_data(S_i),
115 data_out_valid => C_valid(S_i));
116 END GENERATE all_C;
117 -----------------------------------------------------------------------------
118 data_out <= C_data(S_stage_number)(b_data_size + b_grow - 1 DOWNTO b_grow);
119 data_out_valid <= C_valid(S_stage_number);
120 -----------------------------------------------------------------------------
121 END beh;
122
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.numeric_std.ALL;
26 USE IEEE.std_logic_1164.ALL;
27
28 ENTITY cic_comb IS
29
30 GENERIC (
31 b_data_size : INTEGER := 16;
32 D_delay_number : INTEGER := 2
33 );
34
35 PORT (
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 run : IN STD_LOGIC;
39
40 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
41 data_in_valid : IN STD_LOGIC;
42
43 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
44 data_out_valid : OUT STD_LOGIC
45 );
46
47 END cic_comb;
48
49 ARCHITECTURE beh OF cic_comb IS
50
51 TYPE data_vector IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(b_data_size - 1 DOWNTO 0);
52
53 SIGNAL data_reg : data_vector(D_delay_number DOWNTO 0);
54
55 BEGIN -- beh
56
57 data_reg(0) <= data_in;
58
59 all_D: FOR I IN D_delay_number DOWNTO 1 GENERATE
60 PROCESS (clk, rstn)
61 BEGIN
62 IF rstn = '0' THEN
63 data_reg(I) <= (OTHERS => '0');
64 ELSIF clk'event AND clk = '1' THEN
65 IF run = '0' THEN
66 data_reg(I) <= (OTHERS => '0');
67 ELSIF data_in_valid = '1' THEN
68 data_reg(I) <= data_reg(I-1);
69 END IF;
70 END IF;
71 END PROCESS;
72 END GENERATE all_D;
73
74 PROCESS (clk, rstn)
75 BEGIN
76 IF rstn = '0' THEN
77 data_out <= (OTHERS => '0');
78 data_out_valid <= '0';
79 ELSIF clk'event AND clk = '1' THEN
80 IF run = '0' THEN
81 data_out <= (OTHERS => '0');
82 data_out_valid <= '0';
83 ELSE
84 data_out_valid <= data_in_valid;
85 IF data_in_valid = '1' THEN
86 data_out <= STD_LOGIC_VECTOR(resize(SIGNED(data_reg(0))-SIGNED(data_reg(D_delay_number)),b_data_size));
87 END IF;
88 END IF;
89 END IF;
90 END PROCESS;
91
92
93 END beh;
94
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 ENTITY cic_downsampler IS
28
29 GENERIC (
30 R_downsampling_decimation_factor : INTEGER := 16;
31 b_data_size : INTEGER := 16
32 );
33
34 PORT (
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38
39 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
40 data_in_valid : IN STD_LOGIC;
41
42 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
43 data_out_valid : OUT STD_LOGIC
44 );
45
46 END cic_downsampler;
47
48 ARCHITECTURE beh OF cic_downsampler IS
49
50 SUBTYPE INTEGER_downsampler IS INTEGER RANGE 0 TO R_downsampling_decimation_factor-1;
51
52 SIGNAL counter_downsampler : INTEGER_downsampler;
53
54 BEGIN -- beh
55
56 PROCESS (clk, rstn)
57 BEGIN -- PROCESS
58 IF rstn = '0' THEN -- asynchronous reset (active low)
59 data_out <= (OTHERS => '0');
60 data_out_valid <= '0';
61 counter_downsampler <= 0;
62 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
63 IF run = '0' THEN
64 data_out <= (OTHERS => '0');
65 data_out_valid <= '0';
66 counter_downsampler <= 0;
67 ELSE
68 data_out_valid <= '0';
69 IF data_in_valid = '1' THEN
70 IF counter_downsampler = R_downsampling_decimation_factor-1 THEN
71 counter_downsampler <= 0;
72 ELSE
73 counter_downsampler <= counter_downsampler + 1;
74 END IF;
75
76 IF counter_downsampler = 0 THEN
77 data_out_valid <= '1';
78 data_out <= data_in;
79 END IF;
80
81 END IF;
82 END IF;
83 END IF;
84 END PROCESS;
85
86 END beh;
87
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@@ -0,0 +1,78
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY IEEE;
25 USE IEEE.numeric_std.ALL;
26 USE IEEE.std_logic_1164.ALL;
27
28 ENTITY cic_integrator IS
29
30 GENERIC (
31 b_data_size : INTEGER := 16
32 );
33
34 PORT (
35 clk : IN STD_LOGIC;
36 rstn : IN STD_LOGIC;
37 run : IN STD_LOGIC;
38
39 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
40 data_in_valid : IN STD_LOGIC;
41
42 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
43 data_out_valid : OUT STD_LOGIC
44 );
45
46 END cic_integrator;
47
48 ARCHITECTURE beh OF cic_integrator IS
49
50 SIGNAL data_reg : STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
51 SIGNAL data_add : STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
52
53 BEGIN -- beh
54
55 data_out <= data_reg;
56
57 data_add <= STD_LOGIC_VECTOR(resize(SIGNED(data_in)+SIGNED(data_reg),b_data_size));
58
59 PROCESS (clk, rstn)
60 BEGIN -- PROCESS
61 IF rstn = '0' THEN -- asynchronous reset (active low)
62 data_reg <= (OTHERS => '0');
63 data_out_valid <= '0';
64 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
65 IF run = '0' THEN
66 data_reg <= (OTHERS => '0');
67 data_out_valid <= '0';
68 ELSE
69 data_out_valid <= data_in_valid;
70 IF data_in_valid = '1' THEN
71 data_reg <= data_add;
72 END IF;
73 END IF;
74 END IF;
75 END PROCESS;
76
77 END beh;
78
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@@ -0,0 +1,55
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 LIBRARY lpp;
28 USE lpp.cic_pkg.ALL;
29 USE lpp.data_type_pkg.ALL;
30
31 ENTITY cic_lfr IS
32
33 PORT (
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
37
38 data_in : IN sample_vector(5 DOWNTO 0,15 DOWNTO 0);
39 data_in_valid : IN STD_LOGIC;
40
41 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
42 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
43 data_out_valid : OUT STD_LOGIC
44 );
45
46 END cic_lfr;
47
48 ARCHITECTURE beh OF cic_lfr IS
49
50 BEGIN
51
52
53
54 END beh;
55
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@@ -0,0 +1,89
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 PACKAGE cic_pkg IS
28
29 -----------------------------------------------------------------------------
30 COMPONENT cic
31 GENERIC (
32 D_delay_number : INTEGER;
33 S_stage_number : INTEGER;
34 R_downsampling_decimation_factor : INTEGER;
35 b_data_size : INTEGER;
36 b_grow : INTEGER);
37 PORT (
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 run : IN STD_LOGIC;
41 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
43 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
44 data_out_valid : OUT STD_LOGIC);
45 END COMPONENT;
46 -----------------------------------------------------------------------------
47 COMPONENT cic_integrator
48 GENERIC (
49 b_data_size : INTEGER);
50 PORT (
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53 run : IN STD_LOGIC;
54 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
55 data_in_valid : IN STD_LOGIC;
56 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
57 data_out_valid : OUT STD_LOGIC);
58 END COMPONENT;
59
60 COMPONENT cic_downsampler
61 GENERIC (
62 R_downsampling_decimation_factor : INTEGER;
63 b_data_size : INTEGER);
64 PORT (
65 clk : IN STD_LOGIC;
66 rstn : IN STD_LOGIC;
67 run : IN STD_LOGIC;
68 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
69 data_in_valid : IN STD_LOGIC;
70 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
71 data_out_valid : OUT STD_LOGIC);
72 END COMPONENT;
73
74 COMPONENT cic_comb
75 GENERIC (
76 b_data_size : INTEGER;
77 D_delay_number : INTEGER);
78 PORT (
79 clk : IN STD_LOGIC;
80 rstn : IN STD_LOGIC;
81 run : IN STD_LOGIC;
82 data_in : IN STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
83 data_in_valid : IN STD_LOGIC;
84 data_out : OUT STD_LOGIC_VECTOR(b_data_size-1 DOWNTO 0);
85 data_out_valid : OUT STD_LOGIC);
86 END COMPONENT;
87 -----------------------------------------------------------------------------
88
89 END cic_pkg;
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@@ -0,0 +1,6
1 cic_pkg.vhd
2 cic.vhd
3 cic_integrator.vhd
4 cic_downsampler.vhd
5 cic_comb.vhd
6 cic_lfr.vhd
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@@ -0,0 +1,31
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26
27 PACKAGE data_type_pkg IS
28
29 TYPE sample_vector IS ARRAY(NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
30
31 END data_type_pkg;
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@@ -4,6 +4,8
4 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
5 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
6 ./lpp_amba
7 ./dsp/chirp
8 ./dsp/cic
7 ./dsp/iir_filter
9 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
10 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft_rtax
11 ./dsp/lpp_fft_rtax
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@@ -1,3 +1,4
1 data_type_pkg.vhd
1 general_purpose.vhd
2 general_purpose.vhd
2 ADDRcntr.vhd
3 ADDRcntr.vhd
3 ALU.vhd
4 ALU.vhd
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