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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 library proasic3e;
49 use proasic3e.clkint;
50
48 ENTITY LFR_EQM IS
51 ENTITY LFR_EQM IS
49
52
50 PORT (
53 PORT (
51 clk50MHz : IN STD_ULOGIC;
54 clk50MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
55 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
56 reset : IN STD_ULOGIC;
54
57
55 -- TAG --------------------------------------------------------------------
58 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
59 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
60 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
61 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
62 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
63 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
64 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
65 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64
67
65 nSRAM_MBE : INOUT STD_LOGIC; -- new
68 nSRAM_MBE : INOUT STD_LOGIC; -- new
66 nSRAM_E1 : OUT STD_LOGIC; -- new
69 nSRAM_E1 : OUT STD_LOGIC; -- new
67 nSRAM_E2 : OUT STD_LOGIC; -- new
70 nSRAM_E2 : OUT STD_LOGIC; -- new
68 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
71 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
69 nSRAM_W : OUT STD_LOGIC; -- new
72 nSRAM_W : OUT STD_LOGIC; -- new
70 nSRAM_G : OUT STD_LOGIC; -- new
73 nSRAM_G : OUT STD_LOGIC; -- new
71 nSRAM_BUSY : IN STD_LOGIC; -- new
74 nSRAM_BUSY : IN STD_LOGIC; -- new
72 -- SPW --------------------------------------------------------------------
75 -- SPW --------------------------------------------------------------------
73 spw1_en : OUT STD_LOGIC; -- new
76 spw1_en : OUT STD_LOGIC; -- new
74 spw1_din : IN STD_LOGIC;
77 spw1_din : IN STD_LOGIC;
75 spw1_sin : IN STD_LOGIC;
78 spw1_sin : IN STD_LOGIC;
76 spw1_dout : OUT STD_LOGIC;
79 spw1_dout : OUT STD_LOGIC;
77 spw1_sout : OUT STD_LOGIC;
80 spw1_sout : OUT STD_LOGIC;
78 spw2_en : OUT STD_LOGIC; -- new
81 spw2_en : OUT STD_LOGIC; -- new
79 spw2_din : IN STD_LOGIC;
82 spw2_din : IN STD_LOGIC;
80 spw2_sin : IN STD_LOGIC;
83 spw2_sin : IN STD_LOGIC;
81 spw2_dout : OUT STD_LOGIC;
84 spw2_dout : OUT STD_LOGIC;
82 spw2_sout : OUT STD_LOGIC;
85 spw2_sout : OUT STD_LOGIC;
83 -- ADC --------------------------------------------------------------------
86 -- ADC --------------------------------------------------------------------
84 bias_fail_sw : OUT STD_LOGIC;
87 bias_fail_sw : OUT STD_LOGIC;
85 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
88 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
86 ADC_smpclk : OUT STD_LOGIC;
89 ADC_smpclk : OUT STD_LOGIC;
87 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
90 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
88 -- DAC --------------------------------------------------------------------
91 -- DAC --------------------------------------------------------------------
89 DAC_SDO : OUT STD_LOGIC;
92 DAC_SDO : OUT STD_LOGIC;
90 DAC_SCK : OUT STD_LOGIC;
93 DAC_SCK : OUT STD_LOGIC;
91 DAC_SYNC : OUT STD_LOGIC;
94 DAC_SYNC : OUT STD_LOGIC;
92 DAC_CAL_EN : OUT STD_LOGIC;
95 DAC_CAL_EN : OUT STD_LOGIC;
93 -- HK ---------------------------------------------------------------------
96 -- HK ---------------------------------------------------------------------
94 HK_smpclk : OUT STD_LOGIC;
97 HK_smpclk : OUT STD_LOGIC;
95 ADC_OEB_bar_HK : OUT STD_LOGIC;
98 ADC_OEB_bar_HK : OUT STD_LOGIC;
96 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
99 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
97 ---------------------------------------------------------------------------
100 ---------------------------------------------------------------------------
98 TAG8 : OUT STD_LOGIC
101 TAG8 : OUT STD_LOGIC
99 );
102 );
100
103
101 END LFR_EQM;
104 END LFR_EQM;
102
105
103
106
104 ARCHITECTURE beh OF LFR_EQM IS
107 ARCHITECTURE beh OF LFR_EQM IS
105
108
106 SIGNAL clk_25 : STD_LOGIC := '0';
109 SIGNAL clk_25 : STD_LOGIC := '0';
107 SIGNAL clk_24 : STD_LOGIC := '0';
110 SIGNAL clk_24 : STD_LOGIC := '0';
108 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
109 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
112 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
113 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
111
114
112 -- CONSTANTS
115 -- CONSTANTS
113 CONSTANT CFG_PADTECH : INTEGER := inferred;
116 CONSTANT CFG_PADTECH : INTEGER := inferred;
114 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
117 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
115 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
118 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
116 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
119 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
117
120
118 SIGNAL apbi_ext : apb_slv_in_type;
121 SIGNAL apbi_ext : apb_slv_in_type;
119 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
122 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
120 SIGNAL ahbi_s_ext : ahb_slv_in_type;
123 SIGNAL ahbi_s_ext : ahb_slv_in_type;
121 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
124 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
122 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
125 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
123 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
126 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
124
127
125 -- Spacewire signals
128 -- Spacewire signals
126 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
127 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL spw_rxtxclk : STD_ULOGIC;
132 SIGNAL spw_rxtxclk : STD_ULOGIC;
130 SIGNAL spw_rxclkn : STD_ULOGIC;
133 SIGNAL spw_rxclkn : STD_ULOGIC;
131 SIGNAL spw_clk : STD_LOGIC;
134 SIGNAL spw_clk : STD_LOGIC;
132 SIGNAL swni : grspw_in_type;
135 SIGNAL swni : grspw_in_type;
133 SIGNAL swno : grspw_out_type;
136 SIGNAL swno : grspw_out_type;
134
137
135 --GPIO
138 --GPIO
136 SIGNAL gpioi : gpio_in_type;
139 SIGNAL gpioi : gpio_in_type;
137 SIGNAL gpioo : gpio_out_type;
140 SIGNAL gpioo : gpio_out_type;
138
141
139 -- AD Converter ADS7886
142 -- AD Converter ADS7886
140 SIGNAL sample : Samples14v(8 DOWNTO 0);
143 SIGNAL sample : Samples14v(8 DOWNTO 0);
141 SIGNAL sample_s : Samples(8 DOWNTO 0);
144 SIGNAL sample_s : Samples(8 DOWNTO 0);
142 SIGNAL sample_val : STD_LOGIC;
145 SIGNAL sample_val : STD_LOGIC;
143 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
146 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
144
147
145 -----------------------------------------------------------------------------
148 -----------------------------------------------------------------------------
146 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
147
150
148 -----------------------------------------------------------------------------
151 -----------------------------------------------------------------------------
149 SIGNAL rstn_25 : STD_LOGIC;
152 SIGNAL rstn_25 : STD_LOGIC;
150 SIGNAL rstn_24 : STD_LOGIC;
153 SIGNAL rstn_24 : STD_LOGIC;
151
154
152 SIGNAL LFR_soft_rstn : STD_LOGIC;
155 SIGNAL LFR_soft_rstn : STD_LOGIC;
153 SIGNAL LFR_rstn : STD_LOGIC;
156 SIGNAL LFR_rstn : STD_LOGIC;
154
157
155 SIGNAL ADC_smpclk_s : STD_LOGIC;
158 SIGNAL ADC_smpclk_s : STD_LOGIC;
156
159
157 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
158
161
162 SIGNAL clk50MHz_int : STD_LOGIC := '0';
163
164 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
165
159 BEGIN -- beh
166 BEGIN -- beh
160
167
161 -----------------------------------------------------------------------------
168 -----------------------------------------------------------------------------
162 -- CLK
169 -- CLK
163 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
164 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
171 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
165 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
172 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
166
173
167 PROCESS(clk50MHz)
174 clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
175
176 PROCESS(clk50MHz_int)
168 BEGIN
177 BEGIN
169 IF clk50MHz'EVENT AND clk50MHz = '1' THEN
178 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
170 clk_25 <= NOT clk_25;
179 clk_25 <= NOT clk_25;
171 END IF;
180 END IF;
172 END PROCESS;
181 END PROCESS;
173
182
174 PROCESS(clk49_152MHz)
183 PROCESS(clk49_152MHz)
175 BEGIN
184 BEGIN
176 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
185 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
177 clk_24 <= NOT clk_24;
186 clk_24 <= NOT clk_24;
178 END IF;
187 END IF;
179 END PROCESS;
188 END PROCESS;
180
189
181 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
182 --
191 --
183 leon3_soc_1 : leon3_soc
192 leon3_soc_1 : leon3_soc
184 GENERIC MAP (
193 GENERIC MAP (
185 fabtech => apa3e,
194 fabtech => apa3e,
186 memtech => apa3e,
195 memtech => apa3e,
187 padtech => inferred,
196 padtech => inferred,
188 clktech => inferred,
197 clktech => inferred,
189 disas => 0,
198 disas => 0,
190 dbguart => 0,
199 dbguart => 0,
191 pclow => 2,
200 pclow => 2,
192 clk_freq => 25000,
201 clk_freq => 25000,
193 IS_RADHARD => 0,
202 IS_RADHARD => 0,
194 NB_CPU => 1,
203 NB_CPU => 1,
195 ENABLE_FPU => 1,
204 ENABLE_FPU => 1,
196 FPU_NETLIST => 0,
205 FPU_NETLIST => 0,
197 ENABLE_DSU => 1,
206 ENABLE_DSU => 1,
198 ENABLE_AHB_UART => 1,
207 ENABLE_AHB_UART => 1,
199 ENABLE_APB_UART => 1,
208 ENABLE_APB_UART => 1,
200 ENABLE_IRQMP => 1,
209 ENABLE_IRQMP => 1,
201 ENABLE_GPT => 1,
210 ENABLE_GPT => 1,
202 NB_AHB_MASTER => NB_AHB_MASTER,
211 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_SLAVE => NB_AHB_SLAVE,
212 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_APB_SLAVE => NB_APB_SLAVE,
213 NB_APB_SLAVE => NB_APB_SLAVE,
205 ADDRESS_SIZE => 19,
214 ADDRESS_SIZE => 19,
206 USES_IAP_MEMCTRLR => 1)
215 USES_IAP_MEMCTRLR => 1)
207 PORT MAP (
216 PORT MAP (
208 clk => clk_25,
217 clk => clk_25,
209 reset => rstn_25,
218 reset => rstn_25,
210 errorn => OPEN,
219 errorn => OPEN,
211
220
212 ahbrxd => TAG1,
221 ahbrxd => TAG1,
213 ahbtxd => TAG3,
222 ahbtxd => TAG3,
214 urxd1 => TAG2,
223 urxd1 => TAG2,
215 utxd1 => TAG4,
224 utxd1 => TAG4,
216
225
217 address => address,
226 address => address,
218 data => data,
227 data => data,
219 nSRAM_BE0 => OPEN,
228 nSRAM_BE0 => OPEN,
220 nSRAM_BE1 => OPEN,
229 nSRAM_BE1 => OPEN,
221 nSRAM_BE2 => OPEN,
230 nSRAM_BE2 => OPEN,
222 nSRAM_BE3 => OPEN,
231 nSRAM_BE3 => OPEN,
223 nSRAM_WE => nSRAM_W,
232 nSRAM_WE => nSRAM_W,
224 nSRAM_CE => nSRAM_CE,
233 nSRAM_CE => nSRAM_CE,
225 nSRAM_OE => nSRAM_G,
234 nSRAM_OE => nSRAM_G,
226 nSRAM_READY => nSRAM_BUSY,
235 nSRAM_READY => nSRAM_BUSY,
227 SRAM_MBE => nSRAM_MBE,
236 SRAM_MBE => nSRAM_MBE,
228
237
229 apbi_ext => apbi_ext,
238 apbi_ext => apbi_ext,
230 apbo_ext => apbo_ext,
239 apbo_ext => apbo_ext,
231 ahbi_s_ext => ahbi_s_ext,
240 ahbi_s_ext => ahbi_s_ext,
232 ahbo_s_ext => ahbo_s_ext,
241 ahbo_s_ext => ahbo_s_ext,
233 ahbi_m_ext => ahbi_m_ext,
242 ahbi_m_ext => ahbi_m_ext,
234 ahbo_m_ext => ahbo_m_ext);
243 ahbo_m_ext => ahbo_m_ext);
235
244
236
245
237 nSRAM_E1 <= nSRAM_CE(0);
246 nSRAM_E1 <= nSRAM_CE(0);
238 nSRAM_E2 <= nSRAM_CE(1);
247 nSRAM_E2 <= nSRAM_CE(1);
239
248
240 -------------------------------------------------------------------------------
249 -------------------------------------------------------------------------------
241 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
250 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
242 -------------------------------------------------------------------------------
251 -------------------------------------------------------------------------------
243 apb_lfr_management_1 : apb_lfr_management
252 apb_lfr_management_1 : apb_lfr_management
244 GENERIC MAP (
253 GENERIC MAP (
245 tech => apa3e,
254 tech => apa3e,
246 pindex => 6,
255 pindex => 6,
247 paddr => 6,
256 paddr => 6,
248 pmask => 16#fff#,
257 pmask => 16#fff#,
249 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
258 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
250 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
259 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
251 PORT MAP (
260 PORT MAP (
252 clk25MHz => clk_25,
261 clk25MHz => clk_25,
253 resetn_25MHz => rstn_25, -- TODO
262 resetn_25MHz => rstn_25, -- TODO
254 clk24_576MHz => clk_24, -- 49.152MHz/2
263 clk24_576MHz => clk_24, -- 49.152MHz/2
255 resetn_24_576MHz => rstn_24, -- TODO
264 resetn_24_576MHz => rstn_24, -- TODO
256
265
257 grspw_tick => swno.tickout,
266 grspw_tick => swno.tickout,
258 apbi => apbi_ext,
267 apbi => apbi_ext,
259 apbo => apbo_ext(6),
268 apbo => apbo_ext(6),
260
269
261 HK_sample => sample_s(8),
270 HK_sample => sample_s(8),
262 HK_val => sample_val,
271 HK_val => sample_val,
263 HK_sel => HK_SEL,
272 HK_sel => HK_SEL,
264
273
265 DAC_SDO => DAC_SDO,
274 DAC_SDO => DAC_SDO,
266 DAC_SCK => DAC_SCK,
275 DAC_SCK => DAC_SCK,
267 DAC_SYNC => DAC_SYNC,
276 DAC_SYNC => DAC_SYNC,
268 DAC_CAL_EN => DAC_CAL_EN,
277 DAC_CAL_EN => DAC_CAL_EN,
269
278
270 coarse_time => coarse_time,
279 coarse_time => coarse_time,
271 fine_time => fine_time,
280 fine_time => fine_time,
272 LFR_soft_rstn => LFR_soft_rstn
281 LFR_soft_rstn => LFR_soft_rstn
273 );
282 );
274
283
275 -----------------------------------------------------------------------
284 -----------------------------------------------------------------------
276 --- SpaceWire --------------------------------------------------------
285 --- SpaceWire --------------------------------------------------------
277 -----------------------------------------------------------------------
286 -----------------------------------------------------------------------
278
287
279 ------------------------------------------------------------------------------
288 ------------------------------------------------------------------------------
280 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
289 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
281 ------------------------------------------------------------------------------
290 ------------------------------------------------------------------------------
282 spw1_en <= '1';
291 spw1_en <= '1';
283 spw2_en <= '1';
292 spw2_en <= '1';
284 ------------------------------------------------------------------------------
293 ------------------------------------------------------------------------------
285 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
294 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
286 ------------------------------------------------------------------------------
295 ------------------------------------------------------------------------------
287
296
288 spw_clk <= clk50MHz;
297 --spw_clk <= clk50MHz;
289 spw_rxtxclk <= spw_clk;
298 --spw_rxtxclk <= spw_clk;
290 spw_rxclkn <= NOT spw_rxtxclk;
299 --spw_rxclkn <= NOT spw_rxtxclk;
291
300
292 -- PADS for SPW1
301 -- PADS for SPW1
293 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
302 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
294 PORT MAP (spw1_din, dtmp(0));
303 PORT MAP (spw1_din, dtmp(0));
295 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
304 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
296 PORT MAP (spw1_sin, stmp(0));
305 PORT MAP (spw1_sin, stmp(0));
297 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
306 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
298 PORT MAP (spw1_dout, swno.d(0));
307 PORT MAP (spw1_dout, swno.d(0));
299 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
308 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
300 PORT MAP (spw1_sout, swno.s(0));
309 PORT MAP (spw1_sout, swno.s(0));
301 -- PADS FOR SPW2
310 -- PADS FOR SPW2
302 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
311 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
303 PORT MAP (spw2_din, dtmp(1));
312 PORT MAP (spw2_din, dtmp(1));
304 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
313 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
305 PORT MAP (spw2_sin, stmp(1));
314 PORT MAP (spw2_sin, stmp(1));
306 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
315 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
307 PORT MAP (spw2_dout, swno.d(1));
316 PORT MAP (spw2_dout, swno.d(1));
308 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
317 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
309 PORT MAP (spw2_sout, swno.s(1));
318 PORT MAP (spw2_sout, swno.s(1));
310
319
311 -- GRSPW PHY
320 -- GRSPW PHY
312 --spw1_input: if CFG_SPW_GRSPW = 1 generate
321 --spw1_input: if CFG_SPW_GRSPW = 1 generate
313 spw_inputloop : FOR j IN 0 TO 1 GENERATE
322 spw_inputloop : FOR j IN 0 TO 1 GENERATE
314 spw_phy0 : grspw_phy
323 spw_phy0 : grspw_phy
315 GENERIC MAP(
324 GENERIC MAP(
316 tech => apa3e,
325 tech => apa3e,
317 rxclkbuftype => 1,
326 rxclkbuftype => 1,
318 scantest => 0)
327 scantest => 0)
319 PORT MAP(
328 PORT MAP(
320 rxrst => swno.rxrst,
329 rxrst => swno.rxrst,
321 di => dtmp(j),
330 di => dtmp(j),
322 si => stmp(j),
331 si => stmp(j),
323 rxclko => spw_rxclk(j),
332 rxclko => spw_rxclk(j),
324 do => swni.d(j),
333 do => swni.d(j),
325 ndo => swni.nd(j*5+4 DOWNTO j*5),
334 ndo => swni.nd(j*5+4 DOWNTO j*5),
326 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
335 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
327 END GENERATE spw_inputloop;
336 END GENERATE spw_inputloop;
328
337
329 -- SPW core
338 -- SPW core
330 sw0 : grspwm GENERIC MAP(
339 sw0 : grspwm GENERIC MAP(
331 tech => apa3e,
340 tech => apa3e,
332 hindex => 1,
341 hindex => 1,
333 pindex => 5,
342 pindex => 5,
334 paddr => 5,
343 paddr => 5,
335 pirq => 11,
344 pirq => 11,
336 sysfreq => 25000, -- CPU_FREQ
345 sysfreq => 25000, -- CPU_FREQ
337 rmap => 1,
346 rmap => 1,
338 rmapcrc => 1,
347 rmapcrc => 1,
339 fifosize1 => 16,
348 fifosize1 => 16,
340 fifosize2 => 16,
349 fifosize2 => 16,
341 rxclkbuftype => 1,
350 rxclkbuftype => 1,
342 rxunaligned => 0,
351 rxunaligned => 0,
343 rmapbufs => 4,
352 rmapbufs => 4,
344 ft => 0,
353 ft => 0,
345 netlist => 0,
354 netlist => 0,
346 ports => 2,
355 ports => 2,
347 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
356 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
348 memtech => apa3e,
357 memtech => apa3e,
349 destkey => 2,
358 destkey => 2,
350 spwcore => 1
359 spwcore => 1
351 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
360 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
352 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
361 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
353 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
362 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
354 )
363 )
355 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
364 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
356 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
365 spw_rxclk(1),
366 clk50MHz_int,
367 clk50MHz_int,
368 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
357 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
369 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
358 swni, swno);
370 swni, swno);
359
371
360 swni.tickin <= '0';
372 swni.tickin <= '0';
361 swni.rmapen <= '1';
373 swni.rmapen <= '1';
362 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
374 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
363 swni.tickinraw <= '0';
375 swni.tickinraw <= '0';
364 swni.timein <= (OTHERS => '0');
376 swni.timein <= (OTHERS => '0');
365 swni.dcrstval <= (OTHERS => '0');
377 swni.dcrstval <= (OTHERS => '0');
366 swni.timerrstval <= (OTHERS => '0');
378 swni.timerrstval <= (OTHERS => '0');
367
379
368 -------------------------------------------------------------------------------
380 -------------------------------------------------------------------------------
369 -- LFR ------------------------------------------------------------------------
381 -- LFR ------------------------------------------------------------------------
370 -------------------------------------------------------------------------------
382 -------------------------------------------------------------------------------
371 LFR_rstn <= LFR_soft_rstn AND rstn_25;
383 LFR_rstn <= LFR_soft_rstn AND rstn_25;
372
384
373 lpp_lfr_1 : lpp_lfr
385 lpp_lfr_1 : lpp_lfr
374 GENERIC MAP (
386 GENERIC MAP (
375 Mem_use => use_RAM,
387 Mem_use => use_RAM,
376 nb_data_by_buffer_size => 32,
388 nb_data_by_buffer_size => 32,
377 --nb_word_by_buffer_size => 30,
389 --nb_word_by_buffer_size => 30,
378 nb_snapshot_param_size => 32,
390 nb_snapshot_param_size => 32,
379 delta_vector_size => 32,
391 delta_vector_size => 32,
380 delta_vector_size_f0_2 => 7, -- log2(96)
392 delta_vector_size_f0_2 => 7, -- log2(96)
381 pindex => 15,
393 pindex => 15,
382 paddr => 15,
394 paddr => 15,
383 pmask => 16#fff#,
395 pmask => 16#fff#,
384 pirq_ms => 6,
396 pirq_ms => 6,
385 pirq_wfp => 14,
397 pirq_wfp => 14,
386 hindex => 2,
398 hindex => 2,
387 top_lfr_version => X"020144") -- aa.bb.cc version
399 top_lfr_version => X"020144") -- aa.bb.cc version
388 -- AA : BOARD NUMBER
400 -- AA : BOARD NUMBER
389 -- 0 => MINI_LFR
401 -- 0 => MINI_LFR
390 -- 1 => EM
402 -- 1 => EM
391 -- 1 => EQM (with A3PE3000)
403 -- 2 => EQM (with A3PE3000)
392 PORT MAP (
404 PORT MAP (
393 clk => clk_25,
405 clk => clk_25,
394 rstn => LFR_rstn,
406 rstn => LFR_rstn,
395 sample_B => sample_s(2 DOWNTO 0),
407 sample_B => sample_s(2 DOWNTO 0),
396 sample_E => sample_s(7 DOWNTO 3),
408 sample_E => sample_s(7 DOWNTO 3),
397 sample_val => sample_val,
409 sample_val => sample_val,
398 apbi => apbi_ext,
410 apbi => apbi_ext,
399 apbo => apbo_ext(15),
411 apbo => apbo_ext(15),
400 ahbi => ahbi_m_ext,
412 ahbi => ahbi_m_ext,
401 ahbo => ahbo_m_ext(2),
413 ahbo => ahbo_m_ext(2),
402 coarse_time => coarse_time,
414 coarse_time => coarse_time,
403 fine_time => fine_time,
415 fine_time => fine_time,
404 data_shaping_BW => bias_fail_sw,
416 data_shaping_BW => bias_fail_sw,
405 debug_vector => OPEN,
417 debug_vector => OPEN,
406 debug_vector_ms => OPEN); --,
418 debug_vector_ms => OPEN); --,
407 --observation_vector_0 => OPEN,
419 --observation_vector_0 => OPEN,
408 --observation_vector_1 => OPEN,
420 --observation_vector_1 => OPEN,
409 --observation_reg => observation_reg);
421 --observation_reg => observation_reg);
410
422
411
423
412 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
424 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
413 sample_s(I) <= sample(I) & '0' & '0';
425 sample_s(I) <= sample(I) & '0' & '0';
414 END GENERATE all_sample;
426 END GENERATE all_sample;
415 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
427 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
416
428
417 -----------------------------------------------------------------------------
429 -----------------------------------------------------------------------------
418 --
430 --
419 -----------------------------------------------------------------------------
431 -----------------------------------------------------------------------------
420 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
432 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
421 GENERIC MAP (
433 GENERIC MAP (
422 ChanelCount => 9,
434 ChanelCount => 9,
423 ncycle_cnv_high => 13,
435 ncycle_cnv_high => 13,
424 ncycle_cnv => 25,
436 ncycle_cnv => 25,
425 FILTER_ENABLED => 16#FF#)
437 FILTER_ENABLED => 16#FF#)
426 PORT MAP (
438 PORT MAP (
427 cnv_clk => clk_24,
439 cnv_clk => clk_24,
428 cnv_rstn => rstn_24,
440 cnv_rstn => rstn_24,
429 cnv => ADC_smpclk_s,
441 cnv => ADC_smpclk_s,
430 clk => clk_25,
442 clk => clk_25,
431 rstn => rstn_25,
443 rstn => rstn_25,
432 ADC_data => ADC_data,
444 ADC_data => ADC_data,
433 ADC_nOE => ADC_OEB_bar_CH_s,
445 ADC_nOE => ADC_OEB_bar_CH_s,
434 sample => sample,
446 sample => sample,
435 sample_val => sample_val);
447 sample_val => sample_val);
436
448
437 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
449 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
438
450
439 ADC_smpclk <= ADC_smpclk_s;
451 ADC_smpclk <= ADC_smpclk_s;
440 HK_smpclk <= ADC_smpclk_s;
452 HK_smpclk <= ADC_smpclk_s;
441
453
442 TAG8 <= ADC_smpclk_s;
454 TAG8 <='0';
443
455
444 -----------------------------------------------------------------------------
456 -----------------------------------------------------------------------------
445 -- HK
457 -- HK
446 -----------------------------------------------------------------------------
458 -----------------------------------------------------------------------------
447 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
459 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
448
460
449 END beh;
461 END beh;
Show file before | Show file after | Hide comments
@@ -1,54 +1,55
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=LFR_EQM
5 TOP=LFR_EQM
6 BOARD=LFR-EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
15 #VHDLSYNFILES=config.vhd leon3mp.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
16 VHDLSYNFILES=LFR-EQM.vhd
17 VHDLSIMFILES=testbench.vhd
17 VHDLSIMFILES=testbench.vhd
18 #SIMTOP=testbench
18 #SIMTOP=testbench
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_A3PE3000.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM.sdc
20 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_synthesis.sdc
21 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_place_and_route.sdc
21
22
22 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
23 CLEAN=soft-clean
24 CLEAN=soft-clean
24
25
25 TECHLIBS = proasic3e
26 TECHLIBS = proasic3e
26
27
27 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
28 tmtc openchip hynix ihp gleichmann micron usbhc
29 tmtc openchip hynix ihp gleichmann micron usbhc
29
30
30 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
31 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
32 ./amba_lcd_16x2_ctrlr \
33 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
36 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
37 ./lpp_bootloader \
37 ./dsp/lpp_fft_rtax \
38 ./dsp/lpp_fft_rtax \
38 ./lpp_uart \
39 ./lpp_uart \
39 ./lpp_usb \
40 ./lpp_usb \
40 ./lpp_sim/CY7C1061DV33 \
41 ./lpp_sim/CY7C1061DV33 \
41
42
42 FILESKIP = i2cmst.vhd \
43 FILESKIP = i2cmst.vhd \
43 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
44 APB_MULTI_DIODE.vhd \
45 APB_MULTI_DIODE.vhd \
45 Top_MatrixSpec.vhd \
46 Top_MatrixSpec.vhd \
46 APB_FFT.vhd\
47 APB_FFT.vhd\
47 CoreFFT_simu.vhd \
48 CoreFFT_simu.vhd \
48 lpp_lfr_apbreg_simu.vhd
49 lpp_lfr_apbreg_simu.vhd
49
50
50 include $(GRLIB)/bin/Makefile
51 include $(GRLIB)/bin/Makefile
51 include $(GRLIB)/software/leon3/Makefile
52 include $(GRLIB)/software/leon3/Makefile
52
53
53 ################## project specific targets ##########################
54 ################## project specific targets ##########################
54
55
Show file before | Show file after | Hide comments
@@ -1,218 +1,228
1
1
2 LIBRARY IEEE;
2 LIBRARY IEEE;
3 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.STD_LOGIC_1164.ALL;
4 USE IEEE.numeric_std.ALL;
4 USE IEEE.numeric_std.ALL;
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.general_purpose.SYNC_FF;
7 USE lpp.general_purpose.SYNC_FF;
8
8
9 ENTITY top_ad_conv_RHF1401_withFilter IS
9 ENTITY top_ad_conv_RHF1401_withFilter IS
10 GENERIC(
10 GENERIC(
11 ChanelCount : INTEGER := 8;
11 ChanelCount : INTEGER := 8;
12 ncycle_cnv_high : INTEGER := 13;
12 ncycle_cnv_high : INTEGER := 13;
13 ncycle_cnv : INTEGER := 25;
13 ncycle_cnv : INTEGER := 25;
14 FILTER_ENABLED : INTEGER := 16#FF#
14 FILTER_ENABLED : INTEGER := 16#FF#
15 );
15 );
16 PORT (
16 PORT (
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
17 cnv_clk : IN STD_LOGIC; -- 24Mhz
18 cnv_rstn : IN STD_LOGIC;
18 cnv_rstn : IN STD_LOGIC;
19
19
20 cnv : OUT STD_LOGIC;
20 cnv : OUT STD_LOGIC;
21
21
22 clk : IN STD_LOGIC; -- 25MHz
22 clk : IN STD_LOGIC; -- 25MHz
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24 ADC_data : IN Samples14;
24 ADC_data : IN Samples14;
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
25 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
26 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
27 sample_val : OUT STD_LOGIC
27 sample_val : OUT STD_LOGIC
28 );
28 );
29 END top_ad_conv_RHF1401_withFilter;
29 END top_ad_conv_RHF1401_withFilter;
30
30
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
31 ARCHITECTURE ar_top_ad_conv_RHF1401 OF top_ad_conv_RHF1401_withFilter IS
32
32
33 SIGNAL cnv_cycle_counter : INTEGER;
33 SIGNAL cnv_cycle_counter : INTEGER;
34 SIGNAL cnv_s : STD_LOGIC;
34 SIGNAL cnv_s : STD_LOGIC;
35 SIGNAL cnv_s_reg : STD_LOGIC;
35 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync : STD_LOGIC;
36 SIGNAL cnv_sync_pre : STD_LOGIC;
37 SIGNAL cnv_sync_pre : STD_LOGIC;
37
38
38 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
39 SIGNAL ADC_nOE_reg : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
39 SIGNAL enable_ADC : STD_LOGIC;
40 SIGNAL enable_ADC : STD_LOGIC;
40
41
41
42
42 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
43 SIGNAL sample_reg : Samples14v(ChanelCount-1 DOWNTO 0);
43
44
44 SIGNAL channel_counter : INTEGER;
45 SIGNAL channel_counter : INTEGER;
45 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
46 CONSTANT MAX_COUNTER : INTEGER := ChanelCount*2+1;
46
47
47 SIGNAL ADC_data_selected : Samples14;
48 SIGNAL ADC_data_selected : Samples14;
48 SIGNAL ADC_data_result : Samples15;
49 SIGNAL ADC_data_result : Samples15;
49
50
50 SIGNAL sample_counter : INTEGER;
51 SIGNAL sample_counter : INTEGER;
51 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
52 CONSTANT MAX_SAMPLE_COUNTER : INTEGER := 9;
52
53
53 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
54 CONSTANT FILTER_ENABLED_STDLOGIC : STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0) := STD_LOGIC_VECTOR(to_unsigned(FILTER_ENABLED,ChanelCount));
54
55
55 BEGIN
56 BEGIN
56
57
57
58
58 -----------------------------------------------------------------------------
59 -----------------------------------------------------------------------------
59 -- CNV GEN
60 -- CNV GEN
60 -----------------------------------------------------------------------------
61 -----------------------------------------------------------------------------
61 PROCESS (cnv_clk, cnv_rstn)
62 PROCESS (cnv_clk, cnv_rstn)
62 BEGIN -- PROCESS
63 BEGIN -- PROCESS
63 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
64 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
64 cnv_cycle_counter <= 0;
65 cnv_cycle_counter <= 0;
65 cnv_s <= '0';
66 cnv_s <= '0';
66 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
67 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
67 IF cnv_cycle_counter < ncycle_cnv-1 THEN
68 IF cnv_cycle_counter < ncycle_cnv-1 THEN
68 cnv_cycle_counter <= cnv_cycle_counter + 1;
69 cnv_cycle_counter <= cnv_cycle_counter + 1;
69 IF cnv_cycle_counter < ncycle_cnv_high THEN
70 IF cnv_cycle_counter < ncycle_cnv_high THEN
70 cnv_s <= '1';
71 cnv_s <= '1';
71 ELSE
72 ELSE
72 cnv_s <= '0';
73 cnv_s <= '0';
73 END IF;
74 END IF;
74 ELSE
75 ELSE
75 cnv_s <= '1';
76 cnv_s <= '1';
76 cnv_cycle_counter <= 0;
77 cnv_cycle_counter <= 0;
77 END IF;
78 END IF;
78 END IF;
79 END IF;
79 END PROCESS;
80 END PROCESS;
80
81
81 cnv <= cnv_s;
82 cnv <= cnv_s;
82
83
84 PROCESS (cnv_clk, cnv_rstn)
85 BEGIN -- PROCESS
86 IF cnv_rstn = '0' THEN -- asynchronous reset (active low)
87 cnv_s_reg <= '0';
88 ELSIF cnv_clk'EVENT AND cnv_clk = '1' THEN -- rising clock edge
89 cnv_s_reg <= cnv_s;
90 END IF;
91 END PROCESS;
92
83
93
84 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
85 -- SYNC CNV
95 -- SYNC CNV
86 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
87
97
88 SYNC_FF_cnv : SYNC_FF
98 SYNC_FF_cnv : SYNC_FF
89 GENERIC MAP (
99 GENERIC MAP (
90 NB_FF_OF_SYNC => 2)
100 NB_FF_OF_SYNC => 2)
91 PORT MAP (
101 PORT MAP (
92 clk => clk,
102 clk => clk,
93 rstn => rstn,
103 rstn => rstn,
94 A => cnv_s,
104 A => cnv_s_reg,
95 A_sync => cnv_sync);
105 A_sync => cnv_sync);
96
106
97
107
98 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
99 -- DATA GEN Output Enable
109 -- DATA GEN Output Enable
100 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
101 PROCESS (clk, rstn)
111 PROCESS (clk, rstn)
102 BEGIN -- PROCESS
112 BEGIN -- PROCESS
103 IF rstn = '0' THEN -- asynchronous reset (active low)
113 IF rstn = '0' THEN -- asynchronous reset (active low)
104 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
114 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= (OTHERS => '1');
105 cnv_sync_pre <= '0';
115 cnv_sync_pre <= '0';
106 enable_ADC <= '0';
116 enable_ADC <= '0';
107 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
108 cnv_sync_pre <= cnv_sync;
118 cnv_sync_pre <= cnv_sync;
109 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
119 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
110 enable_ADC <= '1';
120 enable_ADC <= '1';
111 ADC_nOE_reg(0) <= '0';
121 ADC_nOE_reg(0) <= '0';
112 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
122 ADC_nOE_reg(ChanelCount-1 DOWNTO 1) <= (OTHERS => '1');
113 ELSE
123 ELSE
114 enable_ADC <= NOT enable_ADC;
124 enable_ADC <= NOT enable_ADC;
115 IF enable_ADC = '0' THEN
125 IF enable_ADC = '0' THEN
116 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
126 ADC_nOE_reg(ChanelCount-1 DOWNTO 0) <= ADC_nOE_reg(ChanelCount-2 DOWNTO 0) & '1';
117 END IF;
127 END IF;
118 END IF;
128 END IF;
119
129
120 END IF;
130 END IF;
121 END PROCESS;
131 END PROCESS;
122
132
123 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
133 ADC_nOE <= (OTHERS => '1') WHEN enable_ADC = '0' ELSE ADC_nOE_reg;
124
134
125 -----------------------------------------------------------------------------
135 -----------------------------------------------------------------------------
126 -- ADC READ DATA
136 -- ADC READ DATA
127 -----------------------------------------------------------------------------
137 -----------------------------------------------------------------------------
128 PROCESS (clk, rstn)
138 PROCESS (clk, rstn)
129 BEGIN -- PROCESS
139 BEGIN -- PROCESS
130 IF rstn = '0' THEN -- asynchronous reset (active low)
140 IF rstn = '0' THEN -- asynchronous reset (active low)
131 channel_counter <= MAX_COUNTER;
141 channel_counter <= MAX_COUNTER;
132
142
133 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
143 all_sample_reg_init: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
134 sample_reg(I) <= (OTHERS => '0');
144 sample_reg(I) <= (OTHERS => '0');
135 END LOOP all_sample_reg_init;
145 END LOOP all_sample_reg_init;
136
146
137 sample_val <= '0';
147 sample_val <= '0';
138 sample_counter <= 0;
148 sample_counter <= 0;
139 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
149 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
140 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
150 IF cnv_sync = '1' AND cnv_sync_pre = '0' THEN
141 channel_counter <= 0;
151 channel_counter <= 0;
142 ELSE
152 ELSE
143 IF channel_counter < MAX_COUNTER THEN
153 IF channel_counter < MAX_COUNTER THEN
144 channel_counter <= channel_counter + 1;
154 channel_counter <= channel_counter + 1;
145 END IF;
155 END IF;
146 END IF;
156 END IF;
147 sample_val <= '0';
157 sample_val <= '0';
148
158
149 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
159 all_sample_reg: FOR I IN ChanelCount-1 DOWNTO 0 LOOP
150 IF channel_counter = I*2 THEN
160 IF channel_counter = I*2 THEN
151 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
161 IF FILTER_ENABLED_STDLOGIC(I) = '1' THEN
152 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
162 sample_reg(I) <= ADC_data_result(14 DOWNTO 1);
153 ELSE
163 ELSE
154 sample_reg(I) <= ADC_data;
164 sample_reg(I) <= ADC_data;
155 END IF;
165 END IF;
156 END IF;
166 END IF;
157 END LOOP all_sample_reg;
167 END LOOP all_sample_reg;
158
168
159 IF channel_counter = (ChanelCount-1)*2 THEN
169 IF channel_counter = (ChanelCount-1)*2 THEN
160
170
161 IF sample_counter = MAX_SAMPLE_COUNTER THEN
171 IF sample_counter = MAX_SAMPLE_COUNTER THEN
162 sample_counter <= 0 ;
172 sample_counter <= 0 ;
163 sample_val <= '1';
173 sample_val <= '1';
164 ELSE
174 ELSE
165 sample_counter <= sample_counter +1;
175 sample_counter <= sample_counter +1;
166 END IF;
176 END IF;
167
177
168 END IF;
178 END IF;
169 END IF;
179 END IF;
170 END PROCESS;
180 END PROCESS;
171
181
172 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
182 -- mux_adc: PROCESS (sample_reg)-- (channel_counter, sample_reg)
173 -- BEGIN -- PROCESS mux_adc
183 -- BEGIN -- PROCESS mux_adc
174 -- CASE channel_counter IS
184 -- CASE channel_counter IS
175 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
185 -- WHEN OTHERS => ADC_data_selected <= sample_reg(channel_counter/2);
176 -- END CASE;
186 -- END CASE;
177 -- END PROCESS mux_adc;
187 -- END PROCESS mux_adc;
178
188
179
189
180 -----------------------------------------------------------------------------
190 -----------------------------------------------------------------------------
181 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
191 -- \/\/\/\/\/\/\/ TODO : this part is not GENERIC !!! \/\/\/\/\/\/\/
182 -----------------------------------------------------------------------------
192 -----------------------------------------------------------------------------
183
193
184 WITH channel_counter SELECT
194 WITH channel_counter SELECT
185 ADC_data_selected <= sample_reg(0) WHEN 0*2,
195 ADC_data_selected <= sample_reg(0) WHEN 0*2,
186 sample_reg(1) WHEN 1*2,
196 sample_reg(1) WHEN 1*2,
187 sample_reg(2) WHEN 2*2,
197 sample_reg(2) WHEN 2*2,
188 sample_reg(3) WHEN 3*2,
198 sample_reg(3) WHEN 3*2,
189 sample_reg(4) WHEN 4*2,
199 sample_reg(4) WHEN 4*2,
190 sample_reg(5) WHEN 5*2,
200 sample_reg(5) WHEN 5*2,
191 sample_reg(6) WHEN 6*2,
201 sample_reg(6) WHEN 6*2,
192 sample_reg(7) WHEN 7*2,
202 sample_reg(7) WHEN 7*2,
193 sample_reg(8) WHEN OTHERS ;
203 sample_reg(8) WHEN OTHERS ;
194
204
195 -----------------------------------------------------------------------------
205 -----------------------------------------------------------------------------
196 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
206 -- /\/\/\/\/\/\/\ ----------------------------------- /\/\/\/\/\/\/\
197 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
198
208
199 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
209 ADC_data_result <= std_logic_vector( (signed( ADC_data_selected(13) & ADC_data_selected) + signed( ADC_data(13) & ADC_data)) );
200
210
201 sample <= sample_reg;
211 sample <= sample_reg;
202
212
203 END ar_top_ad_conv_RHF1401;
213 END ar_top_ad_conv_RHF1401;
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