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Added AdvancedTrigger IP....
Alexis Jeandet -
r653:c45d52d9ef54 default draft
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1 ################################################################################
2 # SDC WRITER VERSION "3.1";
3 # DESIGN "LFR_EQM";
4 # Timing constraints scenario: "Primary";
5 # DATE "Fri Apr 24 16:02:16 2015";
6 # VENDOR "Actel";
7 # PROGRAM "Actel Designer Software Release v9.1 SP5";
8 # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp.
9 ################################################################################
10
11
12 set sdc_version 1.7
13
14
15 ######## Clock Constraints ########
16
17 create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz }
18
19 create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz }
20
21 create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q }
22
23 create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q }
24
25 create_clock -name { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
26
27 create_clock -name { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y }
28
29
30
31 ######## Generated Clock Constraints ########
32
33
34
35 ######## Clock Source Latency Constraints #########
36
37
38
39 ######## Input Delay Constraints ########
40
41 set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
42 set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
43 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
44 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
45 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
46 set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \
47 data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \
48 data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \
49 data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}]
50
51 #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }]
52 #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
53 #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}]
54
55
56
57 ######## Output Delay Constraints ########
58
59 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
60 set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
61 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
62 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
63 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
64 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \
65 data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \
66 data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \
67 data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }]
68
69 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }]
70 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
71 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
72 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
73 address[7] SRAM_A[8] SRAM_A[9] }]
74 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \
75 address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \
76 address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \
77 address[7] SRAM_A[8] SRAM_A[9] }]
78
79 set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
80 set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
81 set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_nBE[0] SRAM_nBE[1] SRAM_nBE[2] SRAM_nBE[3] SRAM_nWE SRAM_CE SRAM_nOE }]
82
83
84 ######## Delay Constraints ########
85
86 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
87
88 set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}]
89
90
91 ######## Delay Constraints ########
92
93
94
95 ######## Multicycle Constraints ########
96
97
98
99 ######## False Path Constraints ########
100
101
102
103 ######## Output load Constraints ########
104
105
106
107 ######## Disable Timing Constraints #########
108
109
110
111 ######## Clock Uncertainty Constraints #########
112
113
114
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1 PACKAGE=\"\"
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 DESIGNER_PACKAGE=FBGA
12 DESIGNER_PINS=324
13
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
16 MGCPART=$(PART)
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19
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1 # Actel Physical design constraints file
2 # Generated file
3
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
7
8
9 #
10 # IO banks setting
11 #
12
13
14 #
15 # I/O constraints
16 #
17
18 set_io clk100MHz \
19 -pinname F7 \
20 -fixed yes \
21 -DIRECTION Inout
22
23 set_io clk49_152MHz \
24 -pinname F8 \
25 -fixed yes \
26 -DIRECTION Inout
27
28 set_io reset \
29 -pinname J12 \
30 -fixed yes \
31 -DIRECTION Inout
32 #====================================================================
33 # BPs
34 #====================================================================
35 set_io BP0 \
36 -pinname F16 \
37 -fixed yes \
38 -DIRECTION Inout
39
40 set_io BP1 \
41 -pinname F13 \
42 -fixed yes \
43 -DIRECTION Inout
44
45 #====================================================================
46 # LEDs
47 #====================================================================
48
49 set_io LED0 \
50 -pinname R13 \
51 -fixed yes \
52 -DIRECTION Inout
53
54 set_io LED1 \
55 -pinname P13 \
56 -fixed yes \
57 -DIRECTION Inout
58
59 set_io LED2 \
60 -pinname N11 \
61 -fixed yes \
62 -DIRECTION Inout
63
64 #====================================================================
65 # TRIGGERs
66 #====================================================================
67
68 set_io DISCO1_TRIG1 \
69 -pinname J15 \
70 -fixed yes \
71 -DIRECTION Inout
72
73 set_io DISCO2_TRIG1 \
74 -pinname H15 \
75 -fixed yes \
76 -DIRECTION Inout
77
78 set_io DISCO3_TRIG1 \
79 -pinname D14 \
80 -fixed yes \
81 -DIRECTION Inout
82
83 set_io DISCO4_TRIG1 \
84 -pinname A8 \
85 -fixed yes \
86 -DIRECTION Inout
87
88 #====================================================================
89 # UARTS
90 #====================================================================
91
92 set_io TXD1 \
93 -pinname N12 \
94 -fixed yes \
95 -DIRECTION Inout
96
97 set_io RXD1 \
98 -pinname N10 \
99 -fixed yes \
100 -DIRECTION Inout
101
102 set_io nCTS1 \
103 -pinname L13 \
104 -fixed yes \
105 -DIRECTION Inout
106
107 set_io nRTS1 \
108 -pinname M9 \
109 -fixed yes \
110 -DIRECTION Inout
111
112
113 set_io TXD2 \
114 -pinname G6 \
115 -fixed yes \
116 -DIRECTION Inout
117
118 set_io RXD2 \
119 -pinname F6 \
120 -fixed yes \
121 -DIRECTION Inout
122
123
124
125 #====================================================================
126 # SPACE WIRE
127 #====================================================================
128
129 set_io SPW_EN \
130 -pinname U9 \
131 -fixed yes \
132 -DIRECTION Inout
133
134 #================================
135 # NOMINAL LINK
136 #================================
137
138 set_io SPW_NOM_DIN \
139 -pinname T9 \
140 -fixed yes \
141 -DIRECTION Inout
142
143 set_io SPW_NOM_SIN \
144 -pinname T8 \
145 -fixed yes \
146 -DIRECTION Inout
147
148 set_io SPW_NOM_DOUT \
149 -pinname U7 \
150 -fixed yes \
151 -DIRECTION Inout
152
153 set_io SPW_NOM_SOUT \
154 -pinname U1 \
155 -fixed yes \
156 -DIRECTION Inout
157
158 #================================
159 # REDUNDANT LINK
160 #================================
161
162 set_io SPW_RED_DIN \
163 -pinname R10 \
164 -fixed yes \
165 -DIRECTION Inout
166
167 set_io SPW_RED_SIN \
168 -pinname T10 \
169 -fixed yes \
170 -DIRECTION Inout
171
172 set_io SPW_RED_DOUT \
173 -pinname V2 \
174 -fixed yes \
175 -DIRECTION Inout
176
177 set_io SPW_RED_SOUT \
178 -pinname T11 \
179 -fixed yes \
180 -DIRECTION Inout
181
182
183 #====================================================================
184 # SRAM
185 #====================================================================
186
187 #================================
188 # SRAM CTRL
189 #================================
190
191 set_io SRAM_nWE \
192 -pinname D4 \
193 -fixed yes \
194 -DIRECTION Inout
195
196 set_io SRAM_CE \
197 -pinname J6 \
198 -fixed yes \
199 -DIRECTION Inout
200
201 set_io SRAM_nOE \
202 -pinname J1 \
203 -fixed yes \
204 -DIRECTION Inout
205
206 set_io SRAM_nBE\[0\] \
207 -pinname N2 \
208 -fixed yes \
209 -DIRECTION Inout
210
211 set_io SRAM_nBE\[1\] \
212 -pinname K5 \
213 -fixed yes \
214 -DIRECTION Inout
215
216 set_io SRAM_nBE\[2\] \
217 -pinname G2 \
218 -fixed yes \
219 -DIRECTION Inout
220
221 set_io SRAM_nBE\[3\] \
222 -pinname J2 \
223 -fixed yes \
224 -DIRECTION Inout
225
226
227 #================================
228 # SRAM ADDRESS
229 #================================
230
231 set_io SRAM_A\[0\] \
232 -pinname A3 \
233 -fixed yes \
234 -DIRECTION Inout
235
236 set_io SRAM_A\[1\] \
237 -pinname A2 \
238 -fixed yes \
239 -DIRECTION Inout
240
241 set_io SRAM_A\[2\] \
242 -pinname B1 \
243 -fixed yes \
244 -DIRECTION Inout
245
246 set_io SRAM_A\[3\] \
247 -pinname C1 \
248 -fixed yes \
249 -DIRECTION Inout
250
251 set_io SRAM_A\[4\] \
252 -pinname D1 \
253 -fixed yes \
254 -DIRECTION Inout
255
256 set_io SRAM_A\[5\] \
257 -pinname B6 \
258 -fixed yes \
259 -DIRECTION Inout
260
261 set_io SRAM_A\[6\] \
262 -pinname F1 \
263 -fixed yes \
264 -DIRECTION Inout
265
266 set_io SRAM_A\[7\] \
267 -pinname C6 \
268 -fixed yes \
269 -DIRECTION Inout
270
271 set_io SRAM_A\[8\] \
272 -pinname H1 \
273 -fixed yes \
274 -DIRECTION Inout
275
276 set_io SRAM_A\[9\] \
277 -pinname A5 \
278 -fixed yes \
279 -DIRECTION Inout
280
281 set_io SRAM_A\[10\] \
282 -pinname D5 \
283 -fixed yes \
284 -DIRECTION Inout
285
286 set_io SRAM_A\[11\] \
287 -pinname K1 \
288 -fixed yes \
289 -DIRECTION Inout
290
291 set_io SRAM_A\[12\] \
292 -pinname A4 \
293 -fixed yes \
294 -DIRECTION Inout
295
296 set_io SRAM_A\[13\] \
297 -pinname E10 \
298 -fixed yes \
299 -DIRECTION Inout
300
301 set_io SRAM_A\[14\] \
302 -pinname C4 \
303 -fixed yes \
304 -DIRECTION Inout
305
306 set_io SRAM_A\[15\] \
307 -pinname G4 \
308 -fixed yes \
309 -DIRECTION Inout
310
311 set_io SRAM_A\[16\] \
312 -pinname K7 \
313 -fixed yes \
314 -DIRECTION Inout
315
316 set_io SRAM_A\[17\] \
317 -pinname F4 \
318 -fixed yes \
319 -DIRECTION Inout
320
321 set_io SRAM_A\[18\] \
322 -pinname K2 \
323 -fixed yes \
324 -DIRECTION Inout
325
326 set_io SRAM_A\[19\] \
327 -pinname E4 \
328 -fixed yes \
329 -DIRECTION Inout
330
331
332 #================================
333 # SRAM DATA
334 #================================
335
336 set_io SRAM_DQ\[0\] \
337 -pinname M3 \
338 -fixed yes \
339 -DIRECTION Inout
340
341 set_io SRAM_DQ\[1\] \
342 -pinname N8 \
343 -fixed yes \
344 -DIRECTION Inout
345
346 set_io SRAM_DQ\[2\] \
347 -pinname M2 \
348 -fixed yes \
349 -DIRECTION Inout
350
351 set_io SRAM_DQ\[3\] \
352 -pinname N9 \
353 -fixed yes \
354 -DIRECTION Inout
355
356 set_io SRAM_DQ\[4\] \
357 -pinname R11 \
358 -fixed yes \
359 -DIRECTION Inout
360
361 set_io SRAM_DQ\[5\] \
362 -pinname K12 \
363 -fixed yes \
364 -DIRECTION Inout
365
366 set_io SRAM_DQ\[6\] \
367 -pinname J4 \
368 -fixed yes \
369 -DIRECTION Inout
370
371 set_io SRAM_DQ\[7\] \
372 -pinname N3 \
373 -fixed yes \
374 -DIRECTION Inout
375
376 set_io SRAM_DQ\[8\] \
377 -pinname M6 \
378 -fixed yes \
379 -DIRECTION Inout
380
381 set_io SRAM_DQ\[9\] \
382 -pinname L3 \
383 -fixed yes \
384 -DIRECTION Inout
385
386 set_io SRAM_DQ\[10\] \
387 -pinname L6 \
388 -fixed yes \
389 -DIRECTION Inout
390
391 set_io SRAM_DQ\[11\] \
392 -pinname K4 \
393 -fixed yes \
394 -DIRECTION Inout
395
396 set_io SRAM_DQ\[12\] \
397 -pinname L4 \
398 -fixed yes \
399 -DIRECTION Inout
400
401 set_io SRAM_DQ\[13\] \
402 -pinname N7 \
403 -fixed yes \
404 -DIRECTION Inout
405
406 set_io SRAM_DQ\[14\] \
407 -pinname M7 \
408 -fixed yes \
409 -DIRECTION Inout
410
411 set_io SRAM_DQ\[15\] \
412 -pinname K6 \
413 -fixed yes \
414 -DIRECTION Inout
415
416 set_io SRAM_DQ\[16\] \
417 -pinname E1 \
418 -fixed yes \
419 -DIRECTION Inout
420
421 set_io SRAM_DQ\[17\] \
422 -pinname J7 \
423 -fixed yes \
424 -DIRECTION Inout
425
426 set_io SRAM_DQ\[18\] \
427 -pinname H4 \
428 -fixed yes \
429 -DIRECTION Inout
430
431 set_io SRAM_DQ\[19\] \
432 -pinname F10 \
433 -fixed yes \
434 -DIRECTION Inout
435
436 set_io SRAM_DQ\[20\] \
437 -pinname B3 \
438 -fixed yes \
439 -DIRECTION Inout
440
441 set_io SRAM_DQ\[21\] \
442 -pinname F3 \
443 -fixed yes \
444 -DIRECTION Inout
445
446 set_io SRAM_DQ\[22\] \
447 -pinname C3 \
448 -fixed yes \
449 -DIRECTION Inout
450
451 set_io SRAM_DQ\[23\] \
452 -pinname G3 \
453 -fixed yes \
454 -DIRECTION Inout
455
456 set_io SRAM_DQ\[24\] \
457 -pinname R6 \
458 -fixed yes \
459 -DIRECTION Inout
460
461 set_io SRAM_DQ\[25\] \
462 -pinname P4 \
463 -fixed yes \
464 -DIRECTION Inout
465
466 set_io SRAM_DQ\[26\] \
467 -pinname R4 \
468 -fixed yes \
469 -DIRECTION Inout
470
471 set_io SRAM_DQ\[27\] \
472 -pinname M4 \
473 -fixed yes \
474 -DIRECTION Inout
475
476 set_io SRAM_DQ\[28\] \
477 -pinname F9 \
478 -fixed yes \
479 -DIRECTION Inout
480
481 set_io SRAM_DQ\[29\] \
482 -pinname B2 \
483 -fixed yes \
484 -DIRECTION Inout
485
486 set_io SRAM_DQ\[30\] \
487 -pinname H3 \
488 -fixed yes \
489 -DIRECTION Inout
490
491 set_io SRAM_DQ\[31\] \
492 -pinname C2 \
493 -fixed yes \
494 -DIRECTION Inout
495
496
497
498
499
500
501
502
503
504
505
506
507
508
509
510
511
512
513
514
515
516
517
518
519
520
521
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_amba.all;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 ENTITY DISCOSPACE_top IS
50
51 PORT (
52 clk100MHz : IN STD_LOGIC;
53 clk49_152MHz : IN STD_LOGIC;
54 reset : IN STD_LOGIC;
55 --BPs
56 BP0 : IN STD_LOGIC;
57 BP1 : IN STD_LOGIC;
58 --LEDs
59 LED0 : OUT STD_LOGIC;
60 LED1 : OUT STD_LOGIC;
61 LED2 : OUT STD_LOGIC;
62 --UARTs
63 TXD1 : IN STD_LOGIC;
64 RXD1 : OUT STD_LOGIC;
65 nCTS1 : OUT STD_LOGIC;
66 nRTS1 : IN STD_LOGIC;
67
68 TXD2 : IN STD_LOGIC;
69 RXD2 : OUT STD_LOGIC;
70 nCTS2 : OUT STD_LOGIC;
71 nDTR2 : IN STD_LOGIC;
72 nRTS2 : IN STD_LOGIC;
73 nDCD2 : OUT STD_LOGIC;
74
75 --EXT CONNECTOR
76 DISCO1_TRIG1 : OUT STD_LOGIC;
77 DISCO2_TRIG1 : OUT STD_LOGIC;
78 DISCO3_TRIG1 : OUT STD_LOGIC;
79 DISCO4_TRIG1 : OUT STD_LOGIC;
80
81 -- MINI LFR ADC INPUTS
82 ADC_nCS : OUT STD_LOGIC;
83 ADC_CLK : OUT STD_LOGIC;
84 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
85 --SPACE WIRE
86 SPW_EN : OUT STD_LOGIC; -- 0 => off
87 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
88 SPW_NOM_SIN : IN STD_LOGIC;
89 SPW_NOM_DOUT : OUT STD_LOGIC;
90 SPW_NOM_SOUT : OUT STD_LOGIC;
91 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
92 SPW_RED_SIN : IN STD_LOGIC;
93 SPW_RED_DOUT : OUT STD_LOGIC;
94 SPW_RED_SOUT : OUT STD_LOGIC;
95
96 -- SRAM
97 SRAM_nWE : OUT STD_LOGIC;
98 SRAM_CE : OUT STD_LOGIC;
99 SRAM_nOE : OUT STD_LOGIC;
100 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
102 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 );
104
105 END DISCOSPACE_top;
106
107
108 ARCHITECTURE beh OF DISCOSPACE_top IS
109
110 --==========================================================================
111 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
112 -- when enabled, chip enable polarity should be reversed and bank size also
113 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
114 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
115 --==========================================================================
116 CONSTANT USE_IAP_MEMCTRL : integer := 1;
117 --==========================================================================
118
119 SIGNAL clk_50_s : STD_LOGIC := '0';
120 SIGNAL clk_25 : STD_LOGIC := '0';
121 SIGNAL clk_24 : STD_LOGIC := '0';
122 -----------------------------------------------------------------------------
123 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
125 --
126 SIGNAL errorn : STD_LOGIC;
127 --
128 SIGNAL I00_s : STD_LOGIC;
129
130 -- CONSTANTS
131 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
143
144 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153
154
155 -- AdvancedTrigger
156 SIGNAL Trigger : STD_LOGIC;
157
158 -- AD Converter ADS7886
159 SIGNAL sample : Samples14v(7 DOWNTO 0);
160 SIGNAL sample_s : Samples(7 DOWNTO 0);
161 SIGNAL sample_val : STD_LOGIC;
162 SIGNAL ADC_nCS_sig : STD_LOGIC;
163 SIGNAL ADC_CLK_sig : STD_LOGIC;
164 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
165
166 SIGNAL bias_fail_sw_sig : STD_LOGIC;
167
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL LFR_soft_rstn : STD_LOGIC;
172 SIGNAL LFR_rstn : STD_LOGIC;
173
174
175 SIGNAL rstn_25 : STD_LOGIC;
176 SIGNAL rstn_25_d1 : STD_LOGIC;
177 SIGNAL rstn_25_d2 : STD_LOGIC;
178 SIGNAL rstn_25_d3 : STD_LOGIC;
179
180 SIGNAL rstn_24 : STD_LOGIC;
181 SIGNAL rstn_24_d1 : STD_LOGIC;
182 SIGNAL rstn_24_d2 : STD_LOGIC;
183 SIGNAL rstn_24_d3 : STD_LOGIC;
184
185 SIGNAL rstn_50 : STD_LOGIC;
186 SIGNAL rstn_50_d1 : STD_LOGIC;
187 SIGNAL rstn_50_d2 : STD_LOGIC;
188 SIGNAL rstn_50_d3 : STD_LOGIC;
189 --
190 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
191
192 --
193 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
194 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
195
196 SIGNAL nSRAM_READY : STD_LOGIC;
197
198 BEGIN -- beh
199
200 -----------------------------------------------------------------------------
201 PROCESS (clk100MHz, reset)
202 BEGIN -- PROCESS
203 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
204 clk_50_s <= NOT clk_50_s;
205 END IF;
206 END PROCESS;
207 -----------------------------------------------------------------------------
208
209 PROCESS (clk_50_s, reset)
210 BEGIN -- PROCESS
211 IF reset = '0' THEN -- asynchronous reset (active low)
212 clk_25 <= '0';
213 rstn_25 <= '0';
214 rstn_25_d1 <= '0';
215 rstn_25_d2 <= '0';
216 rstn_25_d3 <= '0';
217 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
218 clk_25 <= NOT clk_25;
219 rstn_25_d1 <= '1';
220 rstn_25_d2 <= rstn_25_d1;
221 rstn_25_d3 <= rstn_25_d2;
222 rstn_25 <= rstn_25_d3;
223 END IF;
224 END PROCESS;
225
226 PROCESS (clk49_152MHz, reset)
227 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_24 <= '0';
230 rstn_24_d1 <= '0';
231 rstn_24_d2 <= '0';
232 rstn_24_d3 <= '0';
233 rstn_24 <= '0';
234 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
235 clk_24 <= NOT clk_24;
236 rstn_24_d1 <= '1';
237 rstn_24_d2 <= rstn_24_d1;
238 rstn_24_d3 <= rstn_24_d2;
239 rstn_24 <= rstn_24_d3;
240 END IF;
241 END PROCESS;
242
243 -----------------------------------------------------------------------------
244
245 PROCESS (clk_25, rstn_25)
246 BEGIN -- PROCESS
247 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
248 LED0 <= '0';
249 LED1 <= '0';
250 LED2 <= '0';
251 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
252 LED0 <= '0';
253 LED1 <= '1';
254 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
255 END IF;
256 END PROCESS;
257
258 PROCESS (clk49_152MHz, rstn_24)
259 BEGIN -- PROCESS
260 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
261 I00_s <= '0';
262 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
263 I00_s <= NOT I00_s;
264 END IF;
265 END PROCESS;
266
267 --UARTs
268 nCTS1 <= '1';
269 nCTS2 <= '1';
270 nDCD2 <= '1';
271 -- No AHB UART
272 RXD1 <= TXD1;
273
274 --
275
276 leon3_soc_1 : leon3_soc
277 GENERIC MAP (
278 fabtech => apa3e,
279 memtech => apa3e,
280 padtech => inferred,
281 clktech => inferred,
282 disas => 0,
283 dbguart => 0,
284 pclow => 2,
285 clk_freq => 25000,
286 IS_RADHARD => 0,
287 NB_CPU => 1,
288 ENABLE_FPU => 1,
289 FPU_NETLIST => 0,
290 ENABLE_DSU => 1,
291 ENABLE_AHB_UART => 0,
292 ENABLE_APB_UART => 1,
293 ENABLE_IRQMP => 1,
294 ENABLE_GPT => 1,
295 NB_AHB_MASTER => NB_AHB_MASTER,
296 NB_AHB_SLAVE => NB_AHB_SLAVE,
297 NB_APB_SLAVE => NB_APB_SLAVE,
298 ADDRESS_SIZE => 20,
299 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
300 BYPASS_EDAC_MEMCTRLR => '0',
301 SRBANKSZ => 9)
302 PORT MAP (
303 clk => clk_25,
304 reset => rstn_25,
305 errorn => errorn,
306 ahbrxd => OPEN,--TXD1,
307 ahbtxd => OPEN,--RXD1,
308 urxd1 => TXD2,
309 utxd1 => RXD2,
310 address => SRAM_A,
311 data => SRAM_DQ,
312 nSRAM_BE0 => SRAM_nBE(0),
313 nSRAM_BE1 => SRAM_nBE(1),
314 nSRAM_BE2 => SRAM_nBE(2),
315 nSRAM_BE3 => SRAM_nBE(3),
316 nSRAM_WE => SRAM_nWE,
317 nSRAM_CE => SRAM_CE_s,
318 nSRAM_OE => SRAM_nOE,
319 nSRAM_READY => nSRAM_READY,
320 SRAM_MBE => OPEN,
321 apbi_ext => apbi_ext,
322 apbo_ext => apbo_ext,
323 ahbi_s_ext => ahbi_s_ext,
324 ahbo_s_ext => ahbo_s_ext,
325 ahbi_m_ext => ahbi_m_ext,
326 ahbo_m_ext => ahbo_m_ext);
327
328 PROCESS (clk_25, rstn_25)
329 BEGIN -- PROCESS
330 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
331 nSRAM_READY <= '1';
332 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
333 nSRAM_READY <= '1';
334 END IF;
335 END PROCESS;
336
337
338
339 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
340 SRAM_CE <= not SRAM_CE_s(0);
341 END GENERATE;
342
343 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
344 SRAM_CE <= SRAM_CE_s(0);
345 END GENERATE;
346 -------------------------------------------------------------------------------
347 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
348 -------------------------------------------------------------------------------
349 apb_lfr_management_1 : apb_lfr_management
350 GENERIC MAP (
351 tech => apa3e,
352 pindex => 6,
353 paddr => 6,
354 pmask => 16#fff#,
355 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
356 PORT MAP (
357 clk25MHz => clk_25,
358 resetn_25MHz => rstn_25,
359 grspw_tick => swno.tickout,
360 apbi => apbi_ext,
361 apbo => apbo_ext(6),
362 HK_sample => sample_hk,
363 HK_val => sample_val,
364 HK_sel => HK_SEL,
365 DAC_SDO => OPEN,
366 DAC_SCK => OPEN,
367 DAC_SYNC => OPEN,
368 DAC_CAL_EN => OPEN,
369 coarse_time => coarse_time,
370 fine_time => fine_time,
371 LFR_soft_rstn => LFR_soft_rstn
372 );
373
374 -----------------------------------------------------------------------
375 --- SpaceWire --------------------------------------------------------
376 -----------------------------------------------------------------------
377
378 SPW_EN <= '1';
379
380 spw_clk <= clk_50_s;
381 spw_rxtxclk <= spw_clk;
382 spw_rxclkn <= NOT spw_rxtxclk;
383
384 -- PADS for SPW1
385 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
386 PORT MAP (SPW_NOM_DIN, dtmp(0));
387 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
388 PORT MAP (SPW_NOM_SIN, stmp(0));
389 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
390 PORT MAP (SPW_NOM_DOUT, swno.d(0));
391 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
392 PORT MAP (SPW_NOM_SOUT, swno.s(0));
393 -- PADS FOR SPW2
394 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
395 PORT MAP (SPW_RED_SIN, dtmp(1));
396 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
397 PORT MAP (SPW_RED_DIN, stmp(1));
398 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
399 PORT MAP (SPW_RED_DOUT, swno.d(1));
400 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
401 PORT MAP (SPW_RED_SOUT, swno.s(1));
402
403 -- GRSPW PHY
404 spw_inputloop : FOR j IN 0 TO 1 GENERATE
405 spw_phy0 : grspw_phy
406 GENERIC MAP(
407 tech => apa3e,
408 rxclkbuftype => 1,
409 scantest => 0)
410 PORT MAP(
411 rxrst => swno.rxrst,
412 di => dtmp(j),
413 si => stmp(j),
414 rxclko => spw_rxclk(j),
415 do => swni.d(j),
416 ndo => swni.nd(j*5+4 DOWNTO j*5),
417 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
418 END GENERATE spw_inputloop;
419
420 swni.rmapnodeaddr <= (OTHERS => '0');
421
422 -- SPW core
423 sw0 : grspwm GENERIC MAP(
424 tech => apa3e,
425 hindex => 1,
426 pindex => 5,
427 paddr => 5,
428 pirq => 11,
429 sysfreq => 25000, -- CPU_FREQ
430 rmap => 1,
431 rmapcrc => 1,
432 fifosize1 => 16,
433 fifosize2 => 16,
434 rxclkbuftype => 1,
435 rxunaligned => 0,
436 rmapbufs => 4,
437 ft => 0,
438 netlist => 0,
439 ports => 2,
440 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
441 memtech => apa3e,
442 destkey => 2,
443 spwcore => 1
444 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
445 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
446 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
447 )
448 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
449 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
450 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
451 swni, swno);
452
453 swni.tickin <= '0';
454 swni.rmapen <= '1';
455 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
456 swni.tickinraw <= '0';
457 swni.timein <= (OTHERS => '0');
458 swni.dcrstval <= (OTHERS => '0');
459 swni.timerrstval <= (OTHERS => '0');
460
461 -------------------------------------------------------------------------------
462 -- LFR ------------------------------------------------------------------------
463 -------------------------------------------------------------------------------
464
465
466 LFR_rstn <= LFR_soft_rstn AND rstn_25;
467
468 lpp_lfr_1 : lpp_lfr
469 GENERIC MAP (
470 Mem_use => use_RAM,
471 nb_data_by_buffer_size => 32,
472 nb_snapshot_param_size => 32,
473 delta_vector_size => 32,
474 delta_vector_size_f0_2 => 7, -- log2(96)
475 pindex => 15,
476 paddr => 15,
477 pmask => 16#fff#,
478 pirq_ms => 6,
479 pirq_wfp => 14,
480 hindex => 2,
481 top_lfr_version => X"000159") -- aa.bb.cc version
482 PORT MAP (
483 clk => clk_25,
484 rstn => LFR_rstn,
485 sample_B => sample_s(2 DOWNTO 0),
486 sample_E => sample_s(7 DOWNTO 3),
487 sample_val => sample_val,
488 apbi => apbi_ext,
489 apbo => apbo_ext(15),
490 ahbi => ahbi_m_ext,
491 ahbo => ahbo_m_ext(2),
492 coarse_time => coarse_time,
493 fine_time => fine_time,
494 data_shaping_BW => bias_fail_sw_sig,
495 debug_vector => open,
496 debug_vector_ms => open
497 );
498
499 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
500 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
501 END GENERATE all_sample;
502
503 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
504 GENERIC MAP(
505 ChannelCount => 8,
506 SampleNbBits => 14,
507 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
508 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
509 PORT MAP (
510 -- CONV
511 cnv_clk => clk_24,
512 cnv_rstn => rstn_24,
513 cnv => ADC_nCS_sig,
514 -- DATA
515 clk => clk_25,
516 rstn => rstn_25,
517 sck => ADC_CLK_sig,
518 sdo => ADC_SDO_sig,
519 -- SAMPLE
520 sample => sample,
521 sample_val => sample_val);
522
523 ADC_nCS <= ADC_nCS_sig;
524 ADC_CLK <= ADC_CLK_sig;
525 ADC_SDO_sig <= ADC_SDO;
526
527 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
528 "0010001000100010" WHEN HK_SEL = "01" ELSE
529 "0100010001000100" WHEN HK_SEL = "10" ELSE
530 (OTHERS => '0');
531
532
533
534 ----------------------------------------------------------------------
535 --- APB_ADVANCED_TRIGGER -----------------------------------------------------------
536 ----------------------------------------------------------------------
537 advtrig0: APB_ADVANCED_TRIGGER
538 generic map(
539 pindex => 12,
540 paddr => 12)
541 port map(
542 rstn => rstn_25,
543 clk => clk_25,
544 apbi => apbi_ext,
545 apbo => apbo_ext(12),
546
547 SPW_Tickout => swno.tickout,
548 CoarseTime => coarse_time,
549 FineTime => fine_time,
550
551 Trigger => Trigger
552 );
553
554
555 DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
556 PORT MAP (DISCO1_TRIG1, Trigger);
557 DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
558 PORT MAP (DISCO2_TRIG1, Trigger);
559 DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
560 PORT MAP (DISCO3_TRIG1, Trigger);
561 DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
562 PORT MAP (DISCO4_TRIG1, Trigger);
563
564 -----------------------------------------------------------------------------
565 --
566 -----------------------------------------------------------------------------
567 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
568 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE
569 apbo_ext(I) <= apb_none;
570 END GENERATE apbo_ext_not_used;
571 END GENERATE all_apbo_ext;
572
573
574 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
575 ahbo_s_ext(I) <= ahbs_none;
576 END GENERATE all_ahbo_ext;
577
578 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
579 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
580 ahbo_m_ext(I) <= ahbm_none;
581 END GENERATE ahbo_m_ext_not_used;
582 END GENERATE all_ahbo_m_ext;
583
584 END beh; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.lpp_top_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 use lpp.lpp_amba.all;
46 USE lpp.lpp_lfr_management.ALL;
47 USE lpp.lpp_leon3_soc_pkg.ALL;
48
49 ENTITY DISCOSPACE_top IS
50
51 PORT (
52 clk100MHz : IN STD_LOGIC;
53 clk49_152MHz : IN STD_LOGIC;
54 reset : IN STD_LOGIC;
55 --BPs
56 BP0 : IN STD_LOGIC;
57 BP1 : IN STD_LOGIC;
58 --LEDs
59 LED0 : OUT STD_LOGIC;
60 LED1 : OUT STD_LOGIC;
61 LED2 : OUT STD_LOGIC;
62 --UARTs
63 TXD1 : IN STD_LOGIC;
64 RXD1 : OUT STD_LOGIC;
65 nCTS1 : OUT STD_LOGIC;
66 nRTS1 : IN STD_LOGIC;
67
68 TXD2 : IN STD_LOGIC;
69 RXD2 : OUT STD_LOGIC;
70 nCTS2 : OUT STD_LOGIC;
71 nDTR2 : IN STD_LOGIC;
72 nRTS2 : IN STD_LOGIC;
73 nDCD2 : OUT STD_LOGIC;
74
75 --EXT CONNECTOR
76 DISCO1_TRIG1 : OUT STD_LOGIC;
77 DISCO2_TRIG1 : OUT STD_LOGIC;
78 DISCO3_TRIG1 : OUT STD_LOGIC;
79 DISCO4_TRIG1 : OUT STD_LOGIC;
80
81 -- MINI LFR ADC INPUTS
82 ADC_nCS : OUT STD_LOGIC;
83 ADC_CLK : OUT STD_LOGIC;
84 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
85 --SPACE WIRE
86 SPW_EN : OUT STD_LOGIC; -- 0 => off
87 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
88 SPW_NOM_SIN : IN STD_LOGIC;
89 SPW_NOM_DOUT : OUT STD_LOGIC;
90 SPW_NOM_SOUT : OUT STD_LOGIC;
91 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
92 SPW_RED_SIN : IN STD_LOGIC;
93 SPW_RED_DOUT : OUT STD_LOGIC;
94 SPW_RED_SOUT : OUT STD_LOGIC;
95
96 -- SRAM
97 SRAM_nWE : OUT STD_LOGIC;
98 SRAM_CE : OUT STD_LOGIC;
99 SRAM_nOE : OUT STD_LOGIC;
100 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
102 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 );
104
105 END DISCOSPACE_top;
106
107
108 ARCHITECTURE beh OF DISCOSPACE_top IS
109
110 --==========================================================================
111 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
112 -- when enabled, chip enable polarity should be reversed and bank size also
113 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
114 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
115 --==========================================================================
116 CONSTANT USE_IAP_MEMCTRL : integer := 1;
117 --==========================================================================
118
119 SIGNAL clk_50_s : STD_LOGIC := '0';
120 SIGNAL clk_25 : STD_LOGIC := '0';
121 SIGNAL clk_24 : STD_LOGIC := '0';
122 -----------------------------------------------------------------------------
123 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
125 --
126 SIGNAL errorn : STD_LOGIC;
127 --
128 SIGNAL I00_s : STD_LOGIC;
129
130 -- CONSTANTS
131 CONSTANT CFG_PADTECH : INTEGER := inferred;
132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
143
144 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153
154
155 -- AdvancedTrigger
156 SIGNAL Trigger : STD_LOGIC;
157
158 -- AD Converter ADS7886
159 SIGNAL sample : Samples14v(7 DOWNTO 0);
160 SIGNAL sample_s : Samples(7 DOWNTO 0);
161 SIGNAL sample_val : STD_LOGIC;
162 SIGNAL ADC_nCS_sig : STD_LOGIC;
163 SIGNAL ADC_CLK_sig : STD_LOGIC;
164 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
165
166 SIGNAL bias_fail_sw_sig : STD_LOGIC;
167
168
169 -----------------------------------------------------------------------------
170
171 SIGNAL LFR_soft_rstn : STD_LOGIC;
172 SIGNAL LFR_rstn : STD_LOGIC;
173
174
175 SIGNAL rstn_25 : STD_LOGIC;
176 SIGNAL rstn_25_d1 : STD_LOGIC;
177 SIGNAL rstn_25_d2 : STD_LOGIC;
178 SIGNAL rstn_25_d3 : STD_LOGIC;
179
180 SIGNAL rstn_24 : STD_LOGIC;
181 SIGNAL rstn_24_d1 : STD_LOGIC;
182 SIGNAL rstn_24_d2 : STD_LOGIC;
183 SIGNAL rstn_24_d3 : STD_LOGIC;
184
185 SIGNAL rstn_50 : STD_LOGIC;
186 SIGNAL rstn_50_d1 : STD_LOGIC;
187 SIGNAL rstn_50_d2 : STD_LOGIC;
188 SIGNAL rstn_50_d3 : STD_LOGIC;
189 --
190 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
191
192 --
193 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
194 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
195
196 SIGNAL nSRAM_READY : STD_LOGIC;
197
198 BEGIN -- beh
199
200 -----------------------------------------------------------------------------
201 PROCESS (clk100MHz, reset)
202 BEGIN -- PROCESS
203 IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge
204 clk_50_s <= NOT clk_50_s;
205 END IF;
206 END PROCESS;
207 -----------------------------------------------------------------------------
208
209 PROCESS (clk_50_s, reset)
210 BEGIN -- PROCESS
211 IF reset = '0' THEN -- asynchronous reset (active low)
212 clk_25 <= '0';
213 rstn_25 <= '0';
214 rstn_25_d1 <= '0';
215 rstn_25_d2 <= '0';
216 rstn_25_d3 <= '0';
217 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
218 clk_25 <= NOT clk_25;
219 rstn_25_d1 <= '1';
220 rstn_25_d2 <= rstn_25_d1;
221 rstn_25_d3 <= rstn_25_d2;
222 rstn_25 <= rstn_25_d3;
223 END IF;
224 END PROCESS;
225
226 PROCESS (clk49_152MHz, reset)
227 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_24 <= '0';
230 rstn_24_d1 <= '0';
231 rstn_24_d2 <= '0';
232 rstn_24_d3 <= '0';
233 rstn_24 <= '0';
234 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
235 clk_24 <= NOT clk_24;
236 rstn_24_d1 <= '1';
237 rstn_24_d2 <= rstn_24_d1;
238 rstn_24_d3 <= rstn_24_d2;
239 rstn_24 <= rstn_24_d3;
240 END IF;
241 END PROCESS;
242
243 -----------------------------------------------------------------------------
244
245 PROCESS (clk_25, rstn_25)
246 BEGIN -- PROCESS
247 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
248 LED0 <= '0';
249 LED1 <= '0';
250 LED2 <= '0';
251 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
252 LED0 <= '0';
253 LED1 <= '1';
254 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
255 END IF;
256 END PROCESS;
257
258 PROCESS (clk49_152MHz, rstn_24)
259 BEGIN -- PROCESS
260 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
261 I00_s <= '0';
262 ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge
263 I00_s <= NOT I00_s;
264 END IF;
265 END PROCESS;
266
267 --UARTs
268 nCTS1 <= '1';
269 nCTS2 <= '1';
270 nDCD2 <= '1';
271 -- No AHB UART
272 RXD1 <= TXD1;
273
274 --
275
276 leon3_soc_1 : leon3_soc
277 GENERIC MAP (
278 fabtech => apa3e,
279 memtech => apa3e,
280 padtech => inferred,
281 clktech => inferred,
282 disas => 0,
283 dbguart => 0,
284 pclow => 2,
285 clk_freq => 25000,
286 IS_RADHARD => 0,
287 NB_CPU => 1,
288 ENABLE_FPU => 1,
289 FPU_NETLIST => 0,
290 ENABLE_DSU => 1,
291 ENABLE_AHB_UART => 0,
292 ENABLE_APB_UART => 1,
293 ENABLE_IRQMP => 1,
294 ENABLE_GPT => 1,
295 NB_AHB_MASTER => NB_AHB_MASTER,
296 NB_AHB_SLAVE => NB_AHB_SLAVE,
297 NB_APB_SLAVE => NB_APB_SLAVE,
298 ADDRESS_SIZE => 20,
299 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
300 BYPASS_EDAC_MEMCTRLR => '0',
301 SRBANKSZ => 9)
302 PORT MAP (
303 clk => clk_25,
304 reset => rstn_25,
305 errorn => errorn,
306 ahbrxd => OPEN,--TXD1,
307 ahbtxd => OPEN,--RXD1,
308 urxd1 => TXD2,
309 utxd1 => RXD2,
310 address => SRAM_A,
311 data => SRAM_DQ,
312 nSRAM_BE0 => SRAM_nBE(0),
313 nSRAM_BE1 => SRAM_nBE(1),
314 nSRAM_BE2 => SRAM_nBE(2),
315 nSRAM_BE3 => SRAM_nBE(3),
316 nSRAM_WE => SRAM_nWE,
317 nSRAM_CE => SRAM_CE_s,
318 nSRAM_OE => SRAM_nOE,
319 nSRAM_READY => nSRAM_READY,
320 SRAM_MBE => OPEN,
321 apbi_ext => apbi_ext,
322 apbo_ext => apbo_ext,
323 ahbi_s_ext => ahbi_s_ext,
324 ahbo_s_ext => ahbo_s_ext,
325 ahbi_m_ext => ahbi_m_ext,
326 ahbo_m_ext => ahbo_m_ext);
327
328 PROCESS (clk_25, rstn_25)
329 BEGIN -- PROCESS
330 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
331 nSRAM_READY <= '1';
332 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
333 nSRAM_READY <= '1';
334 END IF;
335 END PROCESS;
336
337
338
339 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
340 SRAM_CE <= not SRAM_CE_s(0);
341 END GENERATE;
342
343 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
344 SRAM_CE <= SRAM_CE_s(0);
345 END GENERATE;
346 -------------------------------------------------------------------------------
347 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
348 -------------------------------------------------------------------------------
349 apb_lfr_management_1 : apb_lfr_management
350 GENERIC MAP (
351 tech => apa3e,
352 pindex => 6,
353 paddr => 6,
354 pmask => 16#fff#,
355 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
356 PORT MAP (
357 clk25MHz => clk_25,
358 resetn_25MHz => rstn_25,
359 grspw_tick => swno.tickout,
360 apbi => apbi_ext,
361 apbo => apbo_ext(6),
362 HK_sample => sample_hk,
363 HK_val => sample_val,
364 HK_sel => HK_SEL,
365 DAC_SDO => OPEN,
366 DAC_SCK => OPEN,
367 DAC_SYNC => OPEN,
368 DAC_CAL_EN => OPEN,
369 coarse_time => coarse_time,
370 fine_time => fine_time,
371 LFR_soft_rstn => LFR_soft_rstn
372 );
373
374 -----------------------------------------------------------------------
375 --- SpaceWire --------------------------------------------------------
376 -----------------------------------------------------------------------
377
378 SPW_EN <= '1';
379
380 spw_clk <= clk_50_s;
381 spw_rxtxclk <= spw_clk;
382 spw_rxclkn <= NOT spw_rxtxclk;
383
384 -- PADS for SPW1
385 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
386 PORT MAP (SPW_NOM_DIN, dtmp(0));
387 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
388 PORT MAP (SPW_NOM_SIN, stmp(0));
389 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
390 PORT MAP (SPW_NOM_DOUT, swno.d(0));
391 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
392 PORT MAP (SPW_NOM_SOUT, swno.s(0));
393 -- PADS FOR SPW2
394 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
395 PORT MAP (SPW_RED_SIN, dtmp(1));
396 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
397 PORT MAP (SPW_RED_DIN, stmp(1));
398 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
399 PORT MAP (SPW_RED_DOUT, swno.d(1));
400 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
401 PORT MAP (SPW_RED_SOUT, swno.s(1));
402
403 -- GRSPW PHY
404 spw_inputloop : FOR j IN 0 TO 1 GENERATE
405 spw_phy0 : grspw_phy
406 GENERIC MAP(
407 tech => apa3e,
408 rxclkbuftype => 1,
409 scantest => 0)
410 PORT MAP(
411 rxrst => swno.rxrst,
412 di => dtmp(j),
413 si => stmp(j),
414 rxclko => spw_rxclk(j),
415 do => swni.d(j),
416 ndo => swni.nd(j*5+4 DOWNTO j*5),
417 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
418 END GENERATE spw_inputloop;
419
420 swni.rmapnodeaddr <= (OTHERS => '0');
421
422 -- SPW core
423 sw0 : grspwm GENERIC MAP(
424 tech => apa3e,
425 hindex => 1,
426 pindex => 5,
427 paddr => 5,
428 pirq => 11,
429 sysfreq => 25000, -- CPU_FREQ
430 rmap => 1,
431 rmapcrc => 1,
432 fifosize1 => 16,
433 fifosize2 => 16,
434 rxclkbuftype => 1,
435 rxunaligned => 0,
436 rmapbufs => 4,
437 ft => 0,
438 netlist => 0,
439 ports => 2,
440 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
441 memtech => apa3e,
442 destkey => 2,
443 spwcore => 1
444 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
445 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
446 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
447 )
448 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
449 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
450 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
451 swni, swno);
452
453 swni.tickin <= '0';
454 swni.rmapen <= '1';
455 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
456 swni.tickinraw <= '0';
457 swni.timein <= (OTHERS => '0');
458 swni.dcrstval <= (OTHERS => '0');
459 swni.timerrstval <= (OTHERS => '0');
460
461 -------------------------------------------------------------------------------
462 -- LFR ------------------------------------------------------------------------
463 -------------------------------------------------------------------------------
464
465
466 LFR_rstn <= LFR_soft_rstn AND rstn_25;
467
468 lpp_lfr_1 : lpp_lfr
469 GENERIC MAP (
470 Mem_use => use_RAM,
471 nb_data_by_buffer_size => 32,
472 nb_snapshot_param_size => 32,
473 delta_vector_size => 32,
474 delta_vector_size_f0_2 => 7, -- log2(96)
475 pindex => 15,
476 paddr => 15,
477 pmask => 16#fff#,
478 pirq_ms => 6,
479 pirq_wfp => 14,
480 hindex => 2,
481 top_lfr_version => X"000159") -- aa.bb.cc version
482 PORT MAP (
483 clk => clk_25,
484 rstn => LFR_rstn,
485 sample_B => sample_s(2 DOWNTO 0),
486 sample_E => sample_s(7 DOWNTO 3),
487 sample_val => sample_val,
488 apbi => apbi_ext,
489 apbo => apbo_ext(15),
490 ahbi => ahbi_m_ext,
491 ahbo => ahbo_m_ext(2),
492 coarse_time => coarse_time,
493 fine_time => fine_time,
494 data_shaping_BW => bias_fail_sw_sig,
495 debug_vector => open,
496 debug_vector_ms => open
497 );
498
499 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
500 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
501 END GENERATE all_sample;
502
503 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
504 GENERIC MAP(
505 ChannelCount => 8,
506 SampleNbBits => 14,
507 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
508 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
509 PORT MAP (
510 -- CONV
511 cnv_clk => clk_24,
512 cnv_rstn => rstn_24,
513 cnv => ADC_nCS_sig,
514 -- DATA
515 clk => clk_25,
516 rstn => rstn_25,
517 sck => ADC_CLK_sig,
518 sdo => ADC_SDO_sig,
519 -- SAMPLE
520 sample => sample,
521 sample_val => sample_val);
522
523 ADC_nCS <= ADC_nCS_sig;
524 ADC_CLK <= ADC_CLK_sig;
525 ADC_SDO_sig <= ADC_SDO;
526
527 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
528 "0010001000100010" WHEN HK_SEL = "01" ELSE
529 "0100010001000100" WHEN HK_SEL = "10" ELSE
530 (OTHERS => '0');
531
532
533
534 ----------------------------------------------------------------------
535 --- APB_ADVANCED_TRIGGER -----------------------------------------------------------
536 ----------------------------------------------------------------------
537 advtrig0: APB_ADVANCED_TRIGGER
538 generic map(
539 pindex => 12,
540 paddr => 12)
541 port map(
542 rstn => rstn_25,
543 clk => clk_25,
544 apbi => apbi_ext,
545 apbo => apbo_ext(12),
546
547 SPW_Tickout => swno.tickout,
548 CoarseTime => coarse_time,
549 FineTime => fine_time,
550
551 Trigger => Trigger
552 );
553
554
555 DISCO1_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
556 PORT MAP (DISCO1_TRIG1, Trigger);
557 DISCO2_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
558 PORT MAP (DISCO2_TRIG1, Trigger);
559 DISCO3_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
560 PORT MAP (DISCO3_TRIG1, Trigger);
561 DISCO4_TRIG1_PAD : outpad GENERIC MAP (tech => inferred)
562 PORT MAP (DISCO4_TRIG1, Trigger);
563
564 -----------------------------------------------------------------------------
565 --
566 -----------------------------------------------------------------------------
567 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
568 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 12 AND I /= 15 GENERATE
569 apbo_ext(I) <= apb_none;
570 END GENERATE apbo_ext_not_used;
571 END GENERATE all_apbo_ext;
572
573
574 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
575 ahbo_s_ext(I) <= ahbs_none;
576 END GENERATE all_ahbo_ext;
577
578 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
579 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
580 ahbo_m_ext(I) <= ahbm_none;
581 END GENERATE ahbo_m_ext_not_used;
582 END GENERATE all_ahbo_m_ext;
583
584 END beh;
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1 KEY LIBERO "9.1"
2 KEY CAPTURE "9.1.5.1"
3 KEY DEFAULT_IMPORT_LOC "C:\opt\VHDLIB\tests\Validation_LFR_Filters"
4 KEY DEFAULT_OPEN_LOC ""
5 KEY ProjectID "2f64e589-285c-45b2-b6c4-709f59f83db9"
6 KEY HDLTechnology "VHDL"
7 KEY VendorTechnology_Family "ProASIC3E"
8 KEY VendorTechnology_Die "IT14X14M4"
9 KEY VendorTechnology_Package "fg324"
10 KEY ProjectLocation "C:\opt\VHDLIB\designs\TIMEGEN"
11 KEY SimulationType "VHDL"
12 KEY Vendor "Actel"
13 KEY ActiveRoot "DISCOSPACE_top::work"
14 LIST REVISIONS
15 VALUE="Impl1",NUM=1
16 VALUE="Impl2",NUM=2
17 CURREV=2
18 ENDLIST
19 LIST LIBRARIES
20 grlib
21 synplify
22 techmap
23 spw
24 eth
25 opencores
26 gaisler
27 esa
28 fmf
29 spansion
30 gsi
31 iap
32 lpp
33 cypress
34 ENDLIST
35 LIST LIBRARY_grlib
36 ALIAS=grlib
37 COMPILE_OPTION=COMPILE
38 ENDLIST
39 LIST LIBRARY_synplify
40 ALIAS=synplify
41 COMPILE_OPTION=COMPILE
42 ENDLIST
43 LIST LIBRARY_techmap
44 ALIAS=techmap
45 COMPILE_OPTION=COMPILE
46 ENDLIST
47 LIST LIBRARY_spw
48 ALIAS=spw
49 COMPILE_OPTION=COMPILE
50 ENDLIST
51 LIST LIBRARY_eth
52 ALIAS=eth
53 COMPILE_OPTION=COMPILE
54 ENDLIST
55 LIST LIBRARY_opencores
56 ALIAS=opencores
57 COMPILE_OPTION=COMPILE
58 ENDLIST
59 LIST LIBRARY_gaisler
60 ALIAS=gaisler
61 COMPILE_OPTION=COMPILE
62 ENDLIST
63 LIST LIBRARY_esa
64 ALIAS=esa
65 COMPILE_OPTION=COMPILE
66 ENDLIST
67 LIST LIBRARY_fmf
68 ALIAS=fmf
69 COMPILE_OPTION=COMPILE
70 ENDLIST
71 LIST LIBRARY_spansion
72 ALIAS=spansion
73 COMPILE_OPTION=COMPILE
74 ENDLIST
75 LIST LIBRARY_gsi
76 ALIAS=gsi
77 COMPILE_OPTION=COMPILE
78 ENDLIST
79 LIST LIBRARY_iap
80 ALIAS=iap
81 COMPILE_OPTION=COMPILE
82 ENDLIST
83 LIST LIBRARY_lpp
84 ALIAS=lpp
85 COMPILE_OPTION=COMPILE
86 ENDLIST
87 LIST LIBRARY_cypress
88 ALIAS=cypress
89 COMPILE_OPTION=COMPILE
90 ENDLIST
91 LIST FileManager
92 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp.vhd,hdl"
93 STATE="utd"
94 TIME="1472547172"
95 SIZE="3091"
96 LIBRARY="lpp"
97 ENDFILE
98 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\chirp\chirp_pkg.vhd,hdl"
99 STATE="utd"
100 TIME="1472547172"
101 SIZE="1890"
102 LIBRARY="lpp"
103 ENDFILE
104 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\cic\cic.vhd,hdl"
105 STATE="utd"
106 TIME="1472547172"
107 SIZE="4795"
108 LIBRARY="lpp"
109 ENDFILE
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3215 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Clk_divider.vhd,hdl"
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3223 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\general_purpose\Multiplier.vhd,hdl"
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3843 ENDLIST
3844 LIST Other_Association
3845 ENDLIST
3846 LIST SimulationOptions
3847 UseAutomaticDoFile=true
3848 IncludeWaveDo=true
3849 Type=max
3850 RunTime=1000ns
3851 Resolution=1ps
3852 VsimOpt=
3853 EntityName=testbench
3854 TopInstanceName=<top>_0
3855 DoFileName=
3856 DoFileName2=wave.do
3857 DoFileParams=
3858 DisplayDUTWave=false
3859 LogAllSignals=false
3860 DumpVCD=false
3861 VCDFileName=power.vcd
3862 ENDLIST
3863 LIST ModelSimLibPath
3864 UseCustomPath=FALSE
3865 LibraryPath=
3866 ENDLIST
3867 LIST GlobalFlowOptions
3868 GenerateHDLAfterSynthesis=FALSE
3869 GenerateHDLAfterPhySynthesis=FALSE
3870 RunDRCAfterSynthesis=FALSE
3871 AutoCheckConstraints=TRUE
3872 UpdateViewDrawIni=TRUE
3873 UpdateModelSimIni=TRUE
3874 EnableFileDetection=FALSE
3875 NoIOMode=FALSE
3876 GenerateHDLFromSchematic=TRUE
3877 FlashProInputFile=stp
3878 SmartGenCompileReport=T
3879 ENDLIST
3880 LIST PhySynthesisOptions
3881 ENDLIST
3882 LIST Profiles
3883 NAME="Synplify 2012-03A-SP1-2"
3884 FUNCTION="Synthesis"
3885 TOOL="Synplify"
3886 LOCATION="C:\Synopsys\synplify_F201203ASP1-2\bin\synplify_pro.exe"
3887 PARAM=""
3888 BATCH=0
3889 EndProfile
3890 NAME="Questa"
3891 FUNCTION="Simulation"
3892 TOOL="ModelSim"
3893 LOCATION="C:\questasim64_10.5c\win64\questasim.exe"
3894 PARAM=""
3895 BATCH=0
3896 EndProfile
3897 NAME="WFL"
3898 FUNCTION="Stimulus"
3899 TOOL="WFL"
3900 LOCATION="syncad.exe"
3901 PARAM="-pwflite"
3902 BATCH=0
3903 EndProfile
3904 NAME="FlashPro"
3905 FUNCTION="Program"
3906 TOOL="FlashPro"
3907 LOCATION="C:\Microsemi\Libero_v9.1\Designer\bin\FlashPro.exe"
3908 PARAM=""
3909 BATCH=0
3910 EndProfile
3911 ENDLIST
3912 LIST ProjectState5.1
3913 ENDLIST
3914 LIST ExcludePackageForSimulation
3915 ENDLIST
3916 LIST ExcludePackageForSynthesis
3917 LIST DISCOSPACE_top
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3981 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
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3984 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
3985 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
3986 ENDLIST
3987 ENDLIST
3988 LIST IncludeModuleForSimulation
3989 ENDLIST
3990 LIST CDBOrder
3991 ENDLIST
3992 LIST UserCustomizedFileList
3993 LIST "DISCOSPACE_top"
3994 LIST "ideSYNTHESIS"
3995 USE_LIST=TRUE
3996 FILELIST
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4000 VALUE "<project>\..\..\..\GRLIB\lib\grlib\stdlib\stdlib.vhd,hdl"
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4009 VALUE "<project>\..\..\..\GRLIB\lib\grlib\amba\ahbctrl.vhd,hdl"
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4020 VALUE "<project>\..\..\..\GRLIB\lib\techmap\inferred\ddrphy_datapath.vhd,hdl"
4021 VALUE "<project>\..\..\..\GRLIB\lib\techmap\proasic3e\buffer_apa3e.vhd,hdl"
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4029 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\allmem.vhd,hdl"
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4036 VALUE "<project>\..\..\..\GRLIB\lib\techmap\maps\clkand.vhd,hdl"
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4327 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
4328 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
4329 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\ADS7886_drvr_v2.vhd,hdl"
4330 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
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4333 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
4334 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
4335 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
4336 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
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4338 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
4339 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
4340 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
4341 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
4342 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
4343 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
4344 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
4345 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
4346 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
4347 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
4348 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
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4762 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\dsp\lpp_fft\Linker_FFT.vhd,hdl"
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4765 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_cna\RAM_READER.vhd,hdl"
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4771 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lpp_lfr_management_apbreg_pkg.vhd,hdl"
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4773 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lfr_management\lfr_time_management.vhd,hdl"
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4778 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\RHF1401.vhd,hdl"
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4780 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_RHF1401_withFilter.vhd,hdl"
4781 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\TestModule_RHF1401.vhd,hdl"
4782 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\top_ad_conv_ADS7886_v2.vhd,hdl"
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4784 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_ad_Conv\lpp_lfr_hk.vhd,hdl"
4785 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_package.vhd,hdl"
4786 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_calculation.vhd,hdl"
4787 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\MS_control.vhd,hdl"
4788 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_switch_f0.vhd,hdl"
4789 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_spectral_matrix\spectral_matrix_time_managment.vhd,hdl"
4790 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\DEMUX.vhd,hdl"
4791 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_demux\lpp_demux.vhd,hdl"
4792 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\lpp_Header.vhd,hdl"
4793 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_Header\HeaderBuilder.vhd,hdl"
4794 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\lpp_matrix.vhd,hdl"
4795 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ALU_Driver.vhd,hdl"
4796 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\ReUse_CTRLR.vhd,hdl"
4797 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Dispatch.vhd,hdl"
4798 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\DriveInputs.vhd,hdl"
4799 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\GetResult.vhd,hdl"
4800 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\MatriceSpectrale.vhd,hdl"
4801 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\Matrix.vhd,hdl"
4802 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\SpectralMatrix.vhd,hdl"
4803 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_matrix\TopSpecMatrix.vhd,hdl"
4804 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_pkg.vhd,hdl"
4805 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\fifo_latency_correction.vhd,hdl"
4806 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma.vhd,hdl"
4807 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_ip.vhd,hdl"
4808 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_16word.vhd,hdl"
4809 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_send_1word.vhd,hdl"
4810 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_singleOrBurst.vhd,hdl"
4811 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem.vhd,hdl"
4812 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_GestionBuffer.vhd,hdl"
4813 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_Arbiter.vhd,hdl"
4814 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\DMA_SubSystem_MUX.vhd,hdl"
4815 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_dma\lpp_dma_SEND16B_FIFO2DMA.vhd,hdl"
4816 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_pkg.vhd,hdl"
4817 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform.vhd,hdl"
4818 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_burst.vhd,hdl"
4819 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_withoutLatency.vhd,hdl"
4820 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_latencyCorrection.vhd,hdl"
4821 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo.vhd,hdl"
4822 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter.vhd,hdl"
4823 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_ctrl.vhd,hdl"
4824 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_headreg.vhd,hdl"
4825 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot.vhd,hdl"
4826 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_snapshot_controler.vhd,hdl"
4827 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_genaddress.vhd,hdl"
4828 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_dma_genvalid.vhd,hdl"
4829 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fifo_arbiter_reg.vhd,hdl"
4830 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_waveform\lpp_waveform_fsmdma.vhd,hdl"
4831 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_top_lfr_pkg.vhd,hdl"
4832 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_pkg.vhd,hdl"
4833 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_pkg.vhd,hdl"
4834 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter_coeff.vhd,hdl"
4835 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_filter.vhd,hdl"
4836 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg.vhd,hdl"
4837 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_apbreg_ms_pointer.vhd,hdl"
4838 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_fsmdma.vhd,hdl"
4839 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_FFT.vhd,hdl"
4840 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms.vhd,hdl"
4841 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr_ms_reg_head.vhd,hdl"
4842 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_top_lfr\lpp_lfr.vhd,hdl"
4843 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\lpp_leon3_soc_pkg.vhd,hdl"
4844 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_leon3_soc\leon3_soc.vhd,hdl"
4845 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_lfr_pkg.vhd,hdl"
4846 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_debug_lfr\lpp_debug_dma_singleOrBurst.vhd,hdl"
4847 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_reader.vhd,hdl"
4848 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\sig_recorder.vhd,hdl"
4849 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_sim_pkg.vhd,hdl"
4850 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_sim\lpp_lfr_sim_pkg.vhd,hdl"
4851 VALUE "<project>\..\..\..\GRLIB\lib\..\..\VHDLIB\lib\lpp\.\lpp_file\reader_pkg.vhd,hdl"
4852 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\components.vhd,hdl"
4853 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\package_utility.vhd,hdl"
4854 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1354b.vhd,hdl"
4855 VALUE "<project>\..\..\..\GRLIB\lib\cypress\ssram\cy7c1380d.vhd,hdl"
4856 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\debug.vhd,hdl"
4857 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\grtestmod.vhd,hdl"
4858 VALUE "<project>\..\..\..\GRLIB\lib\work\debug\cpu_disas.vhd,hdl"
4859 VALUE "<project>\DISCOSPACE_top.vhd,hdl"
4860 ENDFILELIST
4861 ENDLIST
4862 ENDLIST
4863 ENDLIST
4864 LIST OpenedFileList
4865 ENDLIST
Show file before | Show file after | Hide comments
@@ -0,0 +1,47
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=DISCOSPACE_top
5 BOARD=DISCOSPACE
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= DISCOSPACE_top.vhd
14 VHDLSIMFILES= testbench.vhd
15 SIMTOP=testbench
16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/DISCOSPACE.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/DISCOSPACE.sdc
19 CLEAN=soft-clean
20
21 TECHLIBS = proasic3e
22
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc ge_1000baseX
25
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./lpp_bootloader \
29 ./lpp_uart \
30 ./lpp_usb \
31 ./dsp/lpp_fft_rtax \
32 ./lpp_sim/CY7C1061DV33 \
33
34 FILESKIP =i2cmst.vhd \
35 APB_MULTI_DIODE.vhd \
36 APB_SIMPLE_DIODE.vhd \
37 Top_MatrixSpec.vhd \
38 APB_FFT.vhd \
39 CoreFFT_simu.vhd \
40 lpp_lfr_apbreg_simu.vhd \
41 sgmii.vhd
42
43 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
45
46 ################## project specific targets ##########################
47
Show file before | Show file after | Hide comments
@@ -0,0 +1,128
1 -- TimeGenAdvancedTrigger.vhd
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2016, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Alexis Jeandet
21 -- Mail : alexis.jeandet@lpp.polytechnique.fr
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 ENTITY TimeGenAdvancedTrigger IS
28 PORT(
29 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
31
32 SPW_Tickout : IN STD_LOGIC;
33
34 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
35 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
36
37 TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
38 TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
39 Restart : IN STD_LOGIC;
40 StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
41
42 BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
43 -- else Trigger output is driven by advanced trig
44 Trigger : OUT STD_LOGIC
45
46 );
47
48 END TimeGenAdvancedTrigger;
49
50
51 ARCHITECTURE beh OF TimeGenAdvancedTrigger IS
52
53 SIGNAL AdvancedTrigger : STD_LOGIC:='0';
54 SIGNAL AdvancedTrigger_l0 : STD_LOGIC:='0';
55 SIGNAL AdvancedTrigger_l1 : STD_LOGIC:='0';
56 SIGNAL started : STD_LOGIC:='0';
57 SIGNAL periodCntr : STD_LOGIC_VECTOR(3 DOWNTO 0):=(OTHERS=>'0');
58 SIGNAL coarseTime0 : STD_LOGIC:='0';
59
60
61 BEGIN
62
63 Trigger <= SPW_Tickout WHEN BypassTickout = '1' ELSE AdvancedTrigger;
64 AdvancedTrigger <= AdvancedTrigger_l0 AND AdvancedTrigger_l1;
65
66
67 PROCESS(clk,rstn)
68 BEGIN
69 IF rstn = '0' THEN
70 started <= '0';
71 AdvancedTrigger_l0 <='0';
72 AdvancedTrigger_l1 <='0';
73 coarseTime0 <= '0';
74 periodCntr <= (OTHERS => '0');
75
76 ELSIF clk'event AND clk = '1' THEN
77
78 coarseTime0 <= CoarseTime(0);
79
80 -- Detection of start date and handling of Restart
81 IF Restart = '1' THEN
82 started <= '0';
83 ELSIF StartDate = CoarseTime THEN
84 started <= '1';
85 END IF;
86
87 -- Fine time based comparator for phase shift
88 IF TrigShift = FineTime THEN
89 AdvancedTrigger_l0 <='1';
90 ELSE
91 AdvancedTrigger_l0 <='0';
92 END IF;
93
94 -- Second filter, generates a pulse for each N seconds since StartDate
95 IF started = '1' THEN
96 IF periodCntr = "0000" THEN
97 AdvancedTrigger_l1 <='1';
98 periodCntr <= TrigPeriod;
99 ELSIF CoarseTime(0) /= coarseTime0 THEN
100 periodCntr <= STD_LOGIC_VECTOR(SIGNED(periodCntr) - 1);
101 AdvancedTrigger_l1 <='0';
102 END IF;
103 ELSE
104 periodCntr <= (OTHERS => '0');
105 AdvancedTrigger_l1 <='0';
106 END IF;
107
108 END IF;
109 END PROCESS;
110
111 END beh;
112
113
114
115
116
117
118
119
120
121
122
123
124
125
126
127
128
Show file before | Show file after | Hide comments
@@ -0,0 +1,158
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2016, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Alexis Jeandet
20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 --use ieee.numeric_std.all;
25 library grlib;
26 use grlib.amba.all;
27 use grlib.stdlib.all;
28 use grlib.devices.all;
29 library lpp;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_amba.all;
32 use lpp.general_purpose.TimeGenAdvancedTrigger;
33
34
35 entity APB_ADVANCED_TRIGGER is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 rstn : in std_ulogic;
44 clk : in std_ulogic;
45 apbi : in apb_slv_in_type;
46 apbo : out apb_slv_out_type;
47
48 SPW_Tickout : IN STD_LOGIC;
49 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
51
52 Trigger : OUT STD_LOGIC
53 );
54 end;
55
56
57 architecture beh of APB_ADVANCED_TRIGGER is
58
59 constant REVISION : integer := 1;
60
61 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_APB_ADVANCED_TRIGGER, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask));
64
65
66
67 type adv_trig_type is record
68 TrigPeriod : STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
69 TrigShift : STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
70 Restart : STD_LOGIC;
71 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
72 BypassTickout : STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
73 end record;
74
75 type adv_trig_regs is record
76 CFG : STD_LOGIC_VECTOR(31 DOWNTO 0);
77 Restart : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 StartDate : STD_LOGIC_VECTOR(31 DOWNTO 0);
79 end record;
80
81 signal r : adv_trig_regs;
82 signal adv_trig : adv_trig_type;
83 signal Rdata : std_logic_vector(31 downto 0);
84
85
86 begin
87
88
89
90 adv_trig0: TimeGenAdvancedTrigger
91 PORT MAP(
92 clk => clk,
93 rstn => rstn,
94
95 SPW_Tickout => SPW_Tickout,
96
97 CoarseTime => CoarseTime,
98 FineTime => FineTime,
99
100 TrigPeriod => adv_trig.TrigPeriod,
101 TrigShift => adv_trig.TrigShift,
102 Restart => adv_trig.Restart,
103 StartDate => adv_trig.StartDate,
104
105 BypassTickout => adv_trig.BypassTickout,
106 Trigger => Trigger
107
108 );
109
110 adv_trig.BypassTickout <= r.CFG(0);
111 adv_trig.TrigPeriod <= r.CFG(7 downto 4);
112 adv_trig.TrigShift <= r.CFG(31 downto 16);
113 adv_trig.Restart <= r.Restart(0);
114 adv_trig.StartDate <= r.StartDate;
115
116
117 process(rstn,clk)
118 begin
119 if rstn = '0' then
120 r.CFG <= (others=>'0');
121 r.Restart <= (others=>'0');
122 r.StartDate <= (others=>'0');
123 elsif clk'event and clk = '1' then
124
125 --APB Write OP
126 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
127 case apbi.paddr(abits-1 downto 2) is
128 when "000000" =>
129 r.CFG <= apbi.pwdata;
130 when "000001" =>
131 r.Restart <= apbi.pwdata;
132 when "000010" =>
133 r.StartDate <= apbi.pwdata;
134 when others =>
135 null;
136 end case;
137 end if;
138
139 --APB READ OP
140 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
141 case apbi.paddr(abits-1 downto 2) is
142 when "000000" =>
143 Rdata <= r.CFG;
144 when "000001" =>
145 Rdata <= r.Restart;
146 when "000010" =>
147 Rdata <= r.StartDate;
148 when others =>
149 Rdata <= r.Restart;
150 end case;
151 end if;
152
153 end if;
154 apbo.pconfig <= pconfig;
155 end process;
156
157 apbo.prdata <= Rdata when apbi.penable = '1';
158 end beh; No newline at end of file
Show file before | Show file after | Hide comments
@@ -417,4 +417,26 PACKAGE general_purpose IS
417 417 output_data : OUT STD_LOGIC_VECTOR(DATA_SIZE-1 DOWNTO 0));
418 418 END COMPONENT;
419 419
420 COMPONENT TimeGenAdvancedTrigger
421 PORT(
422 clk : IN STD_LOGIC;
423 rstn : IN STD_LOGIC;
424
425 SPW_Tickout : IN STD_LOGIC;
426
427 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
428 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
429
430 TrigPeriod : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- In seconds 0 to 15
431 TrigShift : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- In FineTime steps
432 Restart : IN STD_LOGIC;
433 StartDate : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- Date in seconds since epoch
434
435 BypassTickout : IN STD_LOGIC; -- if set then Trigger output is driven by SPW tickout
436 -- else Trigger output is driven by advanced trig
437 Trigger : OUT STD_LOGIC
438
439 );
440 END COMPONENT;
441
420 442 END;
Show file before | Show file after | Hide comments
@@ -25,3 +25,4 SYNC_VALID_BIT.vhd
25 25 RR_Arbiter_4.vhd
26 26 general_counter.vhd
27 27 ramp_generator.vhd
28 TimeGenAdvancedTrigger.vhd
Show file before | Show file after | Hide comments
@@ -44,5 +44,6 PACKAGE apb_devices_list IS
44 44 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
45 45 constant APB_ADC_READER : amba_device_type := 16#F1#;
46 46 CONSTANT LPP_DEBUG_LFR_ID : amba_device_type := 16#A2#;
47 CONSTANT LPP_APB_ADVANCED_TRIGGER : amba_device_type := 16#A3#;
47 48
48 49 END;
Show file before | Show file after | Hide comments
@@ -29,7 +29,7 use std.textio.all;
29 29
30 30 package lpp_amba is
31 31
32 component APB_CHENILLARD is
32 component APB_ADVANCED_TRIGGER is
33 33 generic (
34 34 pindex : integer := 0;
35 35 paddr : integer := 0;
@@ -37,12 +37,16 component APB_CHENILLARD is
37 37 pirq : integer := 0;
38 38 abits : integer := 8);
39 39 port (
40 rst : in std_ulogic;
40 rstn : in std_ulogic;
41 41 clk : in std_ulogic;
42 RegLed : in std_logic_vector (7 downto 0);
43 42 apbi : in apb_slv_in_type;
44 43 apbo : out apb_slv_out_type;
45 Leds : out std_logic_vector (7 downto 0)
44
45 SPW_Tickout : IN STD_LOGIC;
46 CoarseTime : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 FineTime : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48
49 Trigger : OUT STD_LOGIC
46 50 );
47 51 end component;
48 52
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@@ -1,2 +1,3
1 1 apb_devices_list.vhd
2 2 lpp_amba.vhd
3 APB_ADVANCED_TRIGGER.vhd
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