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LFR-EQM et MINI-LFR x.1.70
pellion -
r577:bcb5a865d2bb (MINI-LFR) 0-1-70 (LFR-EQM) 2-1-70 JC
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
25 LIBRARY ieee;
26 USE ieee.std_logic_1164.ALL;
27 USE ieee.numeric_std.ALL;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
31 USE grlib.devices.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_amba.ALL;
35 USE lpp.apb_devices_list.ALL;
36 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_dma_pkg.ALL;
38 USE lpp.general_purpose.ALL;
39 --USE lpp.lpp_waveform_pkg.ALL;
40 LIBRARY techmap;
41 USE techmap.gencomp.ALL;
42
43
44 ENTITY lpp_dma_SEND16B_FIFO2DMA IS
45 GENERIC (
46 hindex : INTEGER := 2;
47 vendorid : IN INTEGER := 0;
48 deviceid : IN INTEGER := 0;
49 version : IN INTEGER := 0
50 );
51 PORT (
52 clk : IN STD_LOGIC;
53 rstn : IN STD_LOGIC;
54
55 -- AMBA AHB Master Interface
56 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58
59 -- FIFO Interface
60 ren : OUT STD_LOGIC;
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62
63 -- Controls
64 send : IN STD_LOGIC;
65 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
66 done : OUT STD_LOGIC;
67 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
68 );
69 END;
70
71 ARCHITECTURE Behavioral OF lpp_dma_SEND16B_FIFO2DMA IS
72
73 CONSTANT HConfig : AHB_Config_Type := (
74 0 => ahb_device_reg(vendorid, deviceid, 0, version, 0),
75 OTHERS => (OTHERS => '0'));
76
77 TYPE AHB_DMA_FSM_STATE IS (IDLE, s_ARBITER ,s_CTRL, s_CTRL_DATA, s_DATA);
78 SIGNAL state : AHB_DMA_FSM_STATE;
79
80 SIGNAL address_counter_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
81 SIGNAL address_counter : STD_LOGIC_VECTOR(3 DOWNTO 0);
82
83 SIGNAL data_window : STD_LOGIC;
84 SIGNAL ctrl_window : STD_LOGIC;
85
86 SIGNAL bus_request : STD_LOGIC;
87 SIGNAL bus_lock : STD_LOGIC;
88
89 BEGIN
90
91 -----------------------------------------------------------------------------
92 AHB_Master_Out.HCONFIG <= HConfig;
93 AHB_Master_Out.HSIZE <= "010"; --WORDS 32b
94 AHB_Master_Out.HINDEX <= hindex;
95 AHB_Master_Out.HPROT <= "0011"; --DATA ACCESS and PRIVILEDGED ACCESS
96 AHB_Master_Out.HIRQ <= (OTHERS => '0');
97 AHB_Master_Out.HBURST <= "111"; -- INCR --"111"; --INCR16
98 AHB_Master_Out.HWRITE <= '1';
99
100 --AHB_Master_Out.HTRANS <= HTRANS_NONSEQ WHEN ctrl_window = '1' OR data_window = '1' ELSE HTRANS_IDLE;
101
102 --AHB_Master_Out.HBUSREQ <= bus_request;
103 --AHB_Master_Out.HLOCK <= data_window;
104
105 --bus_request <= '0' WHEN address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' ELSE
106 -- '1' WHEN ctrl_window = '1' ELSE
107 -- '0';
108
109 --bus_lock <= '0' WHEN address_counter_reg = "1111" ELSE
110 -- '1' WHEN ctrl_window = '1' ELSE '0';
111
112 -----------------------------------------------------------------------------
113 AHB_Master_Out.HADDR <= address(31 DOWNTO 6) & address_counter_reg & "00";
114 AHB_Master_Out.HWDATA <= ahbdrivedata(data);
115
116 -----------------------------------------------------------------------------
117 --ren <= NOT ((AHB_Master_In.HGRANT(hindex) OR LAST_READ ) AND AHB_Master_In.HREADY );
118 --ren <= NOT beat;
119 -----------------------------------------------------------------------------
120 PROCESS (clk, rstn)
121 BEGIN -- PROCESS
122 IF rstn = '0' THEN -- asynchronous reset (active low)
123 state <= IDLE;
124 done <= '0';
125 address_counter_reg <= (OTHERS => '0');
126 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
127 AHB_Master_Out.HBUSREQ <= '0';
128 AHB_Master_Out.HLOCK <= '0';
129 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
130 done <= '0';
131 CASE state IS
132 WHEN IDLE =>
133 AHB_Master_Out.HBUSREQ <= '0';
134 AHB_Master_Out.HLOCK <= '0';
135 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
136 address_counter_reg <= (OTHERS => '0');
137 IF send = '1' THEN
138 AHB_Master_Out.HBUSREQ <= '1';
139 AHB_Master_Out.HLOCK <= '1';
140 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
141 state <= s_ARBITER;
142 END IF;
143
144 WHEN s_ARBITER =>
145 AHB_Master_Out.HBUSREQ <= '1';
146 AHB_Master_Out.HLOCK <= '1';
147 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
148 address_counter_reg <= (OTHERS => '0');
149
150 IF AHB_Master_In.HGRANT(hindex) = '1' THEN
151 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
152 state <= s_CTRL;
153 END IF;
154
155 WHEN s_CTRL =>
156 AHB_Master_Out.HBUSREQ <= '1';
157 AHB_Master_Out.HLOCK <= '1';
158 AHB_Master_Out.HTRANS <= HTRANS_NONSEQ;
159 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
160 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
161 state <= s_CTRL_DATA;
162 END IF;
163
164 WHEN s_CTRL_DATA =>
165 AHB_Master_Out.HBUSREQ <= '1';
166 AHB_Master_Out.HLOCK <= '1';
167 AHB_Master_Out.HTRANS <= HTRANS_SEQ;
168 IF AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' THEN
169 address_counter_reg <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1);
170 END IF;
171
172 IF address_counter_reg = "1111" AND AHB_Master_In.HREADY = '1' THEN
173 AHB_Master_Out.HBUSREQ <= '0';
174 AHB_Master_Out.HLOCK <= '1';--'0';
175 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
176 state <= s_DATA;
177 END IF;
178
179 WHEN s_DATA =>
180 AHB_Master_Out.HBUSREQ <= '0';
181 AHB_Master_Out.HLOCK <= '0';
182 AHB_Master_Out.HTRANS <= HTRANS_IDLE;
183 IF AHB_Master_In.HREADY = '1' THEN
184 state <= IDLE;
185 done <= '1';
186 END IF;
187
188 WHEN OTHERS => NULL;
189 END CASE;
190 END IF;
191 END PROCESS;
192
193 ctrl_window <= '1' WHEN state = s_CTRL OR state = s_CTRL_DATA ELSE '0';
194 data_window <= '1' WHEN state = s_CTRL_DATA OR state = s_DATA ELSE '0';
195 -----------------------------------------------------------------------------
196 ren <= NOT(AHB_Master_In.HREADY) WHEN state = s_CTRL_DATA ELSE '1';
197
198 -----------------------------------------------------------------------------
199 --PROCESS (clk, rstn)
200 --BEGIN -- PROCESS
201 -- IF rstn = '0' THEN -- asynchronous reset (active low)
202 -- address_counter_reg <= (OTHERS => '0');
203 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
204 -- address_counter_reg <= address_counter;
205 -- END IF;
206 --END PROCESS;
207
208 --address_counter <= STD_LOGIC_VECTOR(UNSIGNED(address_counter_reg) + 1) WHEN data_window = '1' AND AHB_Master_In.HREADY = '1' AND AHB_Master_In.HGRANT(hindex) = '1' ELSE
209 -- address_counter_reg;
210 -----------------------------------------------------------------------------
211
212
213 END Behavioral;
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@@ -1,469 +1,469
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 --library proasic3l;
48 --library proasic3l;
49 --use proasic3l.all;
49 --use proasic3l.all;
50
50
51 ENTITY LFR_EQM IS
51 ENTITY LFR_EQM IS
52 --GENERIC (
52 --GENERIC (
53 -- Mem_use : INTEGER := use_RAM);
53 -- Mem_use : INTEGER := use_RAM);
54
54
55 PORT (
55 PORT (
56 clk50MHz : IN STD_ULOGIC;
56 clk50MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
59
60 -- TAG --------------------------------------------------------------------
60 -- TAG --------------------------------------------------------------------
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 -- UART APB ---------------------------------------------------------------
63 -- UART APB ---------------------------------------------------------------
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 -- RAM --------------------------------------------------------------------
66 -- RAM --------------------------------------------------------------------
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69
69
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
74 nSRAM_W : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
75 nSRAM_G : OUT STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 -- SPW --------------------------------------------------------------------
77 -- SPW --------------------------------------------------------------------
78 spw1_en : OUT STD_LOGIC; -- new
78 spw1_en : OUT STD_LOGIC; -- new
79 spw1_din : IN STD_LOGIC;
79 spw1_din : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
80 spw1_sin : IN STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
81 spw1_dout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
82 spw1_sout : OUT STD_LOGIC;
83 spw2_en : OUT STD_LOGIC; -- new
83 spw2_en : OUT STD_LOGIC; -- new
84 spw2_din : IN STD_LOGIC;
84 spw2_din : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
85 spw2_sin : IN STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
86 spw2_dout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
87 spw2_sout : OUT STD_LOGIC;
88 -- ADC --------------------------------------------------------------------
88 -- ADC --------------------------------------------------------------------
89 bias_fail_sw : OUT STD_LOGIC;
89 bias_fail_sw : OUT STD_LOGIC;
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 ADC_smpclk : OUT STD_LOGIC;
91 ADC_smpclk : OUT STD_LOGIC;
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 -- DAC --------------------------------------------------------------------
93 -- DAC --------------------------------------------------------------------
94 DAC_SDO : OUT STD_LOGIC;
94 DAC_SDO : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
95 DAC_SCK : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
96 DAC_SYNC : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
97 DAC_CAL_EN : OUT STD_LOGIC;
98 -- HK ---------------------------------------------------------------------
98 -- HK ---------------------------------------------------------------------
99 HK_smpclk : OUT STD_LOGIC;
99 HK_smpclk : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 ---------------------------------------------------------------------------
102 ---------------------------------------------------------------------------
103 TAG8 : OUT STD_LOGIC
103 TAG8 : OUT STD_LOGIC
104 );
104 );
105
105
106 END LFR_EQM;
106 END LFR_EQM;
107
107
108
108
109 ARCHITECTURE beh OF LFR_EQM IS
109 ARCHITECTURE beh OF LFR_EQM IS
110
110
111 SIGNAL clk_25 : STD_LOGIC := '0';
111 SIGNAL clk_25 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
112 SIGNAL clk_24 : STD_LOGIC := '0';
113 -----------------------------------------------------------------------------
113 -----------------------------------------------------------------------------
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116
116
117 -- CONSTANTS
117 -- CONSTANTS
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122
122
123 SIGNAL apbi_ext : apb_slv_in_type;
123 SIGNAL apbi_ext : apb_slv_in_type;
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129
129
130 -- Spacewire signals
130 -- Spacewire signals
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
136 SIGNAL spw_clk : STD_LOGIC;
137 SIGNAL swni : grspw_in_type;
137 SIGNAL swni : grspw_in_type;
138 SIGNAL swno : grspw_out_type;
138 SIGNAL swno : grspw_out_type;
139
139
140 --GPIO
140 --GPIO
141 SIGNAL gpioi : gpio_in_type;
141 SIGNAL gpioi : gpio_in_type;
142 SIGNAL gpioo : gpio_out_type;
142 SIGNAL gpioo : gpio_out_type;
143
143
144 -- AD Converter ADS7886
144 -- AD Converter ADS7886
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 SIGNAL sample_val : STD_LOGIC;
147 SIGNAL sample_val : STD_LOGIC;
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149
149
150 -----------------------------------------------------------------------------
150 -----------------------------------------------------------------------------
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152
152
153 -----------------------------------------------------------------------------
153 -----------------------------------------------------------------------------
154 SIGNAL rstn_25 : STD_LOGIC;
154 SIGNAL rstn_25 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
155 SIGNAL rstn_24 : STD_LOGIC;
156
156
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
158 SIGNAL LFR_rstn : STD_LOGIC;
159
159
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161
161
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163
163
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
165 SIGNAL clk_25_int : STD_LOGIC := '0';
166
166
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168
168
169 BEGIN -- beh
169 BEGIN -- beh
170
170
171 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
172 -- CLK
172 -- CLK
173 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176
176
177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 clk50MHz_int <= clk50MHz;
178 clk50MHz_int <= clk50MHz;
179
179
180 PROCESS(clk50MHz_int)
180 PROCESS(clk50MHz_int)
181 BEGIN
181 BEGIN
182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 --clk_25_int <= NOT clk_25_int;
183 --clk_25_int <= NOT clk_25_int;
184 clk_25 <= NOT clk_25;
184 clk_25 <= NOT clk_25;
185 END IF;
185 END IF;
186 END PROCESS;
186 END PROCESS;
187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188
188
189 PROCESS(clk49_152MHz)
189 PROCESS(clk49_152MHz)
190 BEGIN
190 BEGIN
191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 clk_24 <= NOT clk_24;
192 clk_24 <= NOT clk_24;
193 END IF;
193 END IF;
194 END PROCESS;
194 END PROCESS;
195
195
196 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
197 --
197 --
198 leon3_soc_1 : leon3_soc
198 leon3_soc_1 : leon3_soc
199 GENERIC MAP (
199 GENERIC MAP (
200 fabtech => apa3l,
200 fabtech => apa3l,
201 memtech => apa3l,
201 memtech => apa3l,
202 padtech => inferred,
202 padtech => inferred,
203 clktech => inferred,
203 clktech => inferred,
204 disas => 0,
204 disas => 0,
205 dbguart => 0,
205 dbguart => 0,
206 pclow => 2,
206 pclow => 2,
207 clk_freq => 25000,
207 clk_freq => 25000,
208 IS_RADHARD => 0,
208 IS_RADHARD => 0,
209 NB_CPU => 1,
209 NB_CPU => 1,
210 ENABLE_FPU => 1,
210 ENABLE_FPU => 1,
211 FPU_NETLIST => 0,
211 FPU_NETLIST => 0,
212 ENABLE_DSU => 1,
212 ENABLE_DSU => 1,
213 ENABLE_AHB_UART => 1,
213 ENABLE_AHB_UART => 1,
214 ENABLE_APB_UART => 1,
214 ENABLE_APB_UART => 1,
215 ENABLE_IRQMP => 1,
215 ENABLE_IRQMP => 1,
216 ENABLE_GPT => 1,
216 ENABLE_GPT => 1,
217 NB_AHB_MASTER => NB_AHB_MASTER,
217 NB_AHB_MASTER => NB_AHB_MASTER,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
218 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
219 NB_APB_SLAVE => NB_APB_SLAVE,
220 ADDRESS_SIZE => 19,
220 ADDRESS_SIZE => 19,
221 USES_IAP_MEMCTRLR => 1,
221 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '0',
222 BYPASS_EDAC_MEMCTRLR => '0',
223 SRBANKSZ => 8)
223 SRBANKSZ => 8)
224 PORT MAP (
224 PORT MAP (
225 clk => clk_25,
225 clk => clk_25,
226 reset => rstn_25,
226 reset => rstn_25,
227 errorn => OPEN,
227 errorn => OPEN,
228
228
229 ahbrxd => TAG1,
229 ahbrxd => TAG1,
230 ahbtxd => TAG3,
230 ahbtxd => TAG3,
231 urxd1 => TAG2,
231 urxd1 => TAG2,
232 utxd1 => TAG4,
232 utxd1 => TAG4,
233
233
234 address => address,
234 address => address,
235 data => data,
235 data => data,
236 nSRAM_BE0 => OPEN,
236 nSRAM_BE0 => OPEN,
237 nSRAM_BE1 => OPEN,
237 nSRAM_BE1 => OPEN,
238 nSRAM_BE2 => OPEN,
238 nSRAM_BE2 => OPEN,
239 nSRAM_BE3 => OPEN,
239 nSRAM_BE3 => OPEN,
240 nSRAM_WE => nSRAM_W,
240 nSRAM_WE => nSRAM_W,
241 nSRAM_CE => nSRAM_CE,
241 nSRAM_CE => nSRAM_CE,
242 nSRAM_OE => nSRAM_G,
242 nSRAM_OE => nSRAM_G,
243 nSRAM_READY => nSRAM_BUSY,
243 nSRAM_READY => nSRAM_BUSY,
244 SRAM_MBE => nSRAM_MBE,
244 SRAM_MBE => nSRAM_MBE,
245
245
246 apbi_ext => apbi_ext,
246 apbi_ext => apbi_ext,
247 apbo_ext => apbo_ext,
247 apbo_ext => apbo_ext,
248 ahbi_s_ext => ahbi_s_ext,
248 ahbi_s_ext => ahbi_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
249 ahbo_s_ext => ahbo_s_ext,
250 ahbi_m_ext => ahbi_m_ext,
250 ahbi_m_ext => ahbi_m_ext,
251 ahbo_m_ext => ahbo_m_ext);
251 ahbo_m_ext => ahbo_m_ext);
252
252
253
253
254 nSRAM_E1 <= nSRAM_CE(0);
254 nSRAM_E1 <= nSRAM_CE(0);
255 nSRAM_E2 <= nSRAM_CE(1);
255 nSRAM_E2 <= nSRAM_CE(1);
256
256
257 -------------------------------------------------------------------------------
257 -------------------------------------------------------------------------------
258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
259 -------------------------------------------------------------------------------
259 -------------------------------------------------------------------------------
260 apb_lfr_management_1 : apb_lfr_management
260 apb_lfr_management_1 : apb_lfr_management
261 GENERIC MAP (
261 GENERIC MAP (
262 tech => apa3l,
262 tech => apa3l,
263 pindex => 6,
263 pindex => 6,
264 paddr => 6,
264 paddr => 6,
265 pmask => 16#fff#,
265 pmask => 16#fff#,
266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
268 PORT MAP (
268 PORT MAP (
269 clk25MHz => clk_25,
269 clk25MHz => clk_25,
270 resetn_25MHz => rstn_25, -- TODO
270 resetn_25MHz => rstn_25, -- TODO
271 --clk24_576MHz => clk_24, -- 49.152MHz/2
271 --clk24_576MHz => clk_24, -- 49.152MHz/2
272 --resetn_24_576MHz => rstn_24, -- TODO
272 --resetn_24_576MHz => rstn_24, -- TODO
273
273
274 grspw_tick => swno.tickout,
274 grspw_tick => swno.tickout,
275 apbi => apbi_ext,
275 apbi => apbi_ext,
276 apbo => apbo_ext(6),
276 apbo => apbo_ext(6),
277
277
278 HK_sample => sample_s(8),
278 HK_sample => sample_s(8),
279 HK_val => sample_val,
279 HK_val => sample_val,
280 HK_sel => HK_SEL,
280 HK_sel => HK_SEL,
281
281
282 DAC_SDO => DAC_SDO,
282 DAC_SDO => DAC_SDO,
283 DAC_SCK => DAC_SCK,
283 DAC_SCK => DAC_SCK,
284 DAC_SYNC => DAC_SYNC,
284 DAC_SYNC => DAC_SYNC,
285 DAC_CAL_EN => DAC_CAL_EN,
285 DAC_CAL_EN => DAC_CAL_EN,
286
286
287 coarse_time => coarse_time,
287 coarse_time => coarse_time,
288 fine_time => fine_time,
288 fine_time => fine_time,
289 LFR_soft_rstn => LFR_soft_rstn
289 LFR_soft_rstn => LFR_soft_rstn
290 );
290 );
291
291
292 -----------------------------------------------------------------------
292 -----------------------------------------------------------------------
293 --- SpaceWire --------------------------------------------------------
293 --- SpaceWire --------------------------------------------------------
294 -----------------------------------------------------------------------
294 -----------------------------------------------------------------------
295
295
296 ------------------------------------------------------------------------------
296 ------------------------------------------------------------------------------
297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
298 ------------------------------------------------------------------------------
298 ------------------------------------------------------------------------------
299 spw1_en <= '1';
299 spw1_en <= '1';
300 spw2_en <= '1';
300 spw2_en <= '1';
301 ------------------------------------------------------------------------------
301 ------------------------------------------------------------------------------
302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
303 ------------------------------------------------------------------------------
303 ------------------------------------------------------------------------------
304
304
305 --spw_clk <= clk50MHz;
305 --spw_clk <= clk50MHz;
306 --spw_rxtxclk <= spw_clk;
306 --spw_rxtxclk <= spw_clk;
307 --spw_rxclkn <= NOT spw_rxtxclk;
307 --spw_rxclkn <= NOT spw_rxtxclk;
308
308
309 -- PADS for SPW1
309 -- PADS for SPW1
310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
311 PORT MAP (spw1_din, dtmp(0));
311 PORT MAP (spw1_din, dtmp(0));
312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
313 PORT MAP (spw1_sin, stmp(0));
313 PORT MAP (spw1_sin, stmp(0));
314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
315 PORT MAP (spw1_dout, swno.d(0));
315 PORT MAP (spw1_dout, swno.d(0));
316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
317 PORT MAP (spw1_sout, swno.s(0));
317 PORT MAP (spw1_sout, swno.s(0));
318 -- PADS FOR SPW2
318 -- PADS FOR SPW2
319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
320 PORT MAP (spw2_din, dtmp(1));
320 PORT MAP (spw2_din, dtmp(1));
321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
322 PORT MAP (spw2_sin, stmp(1));
322 PORT MAP (spw2_sin, stmp(1));
323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
324 PORT MAP (spw2_dout, swno.d(1));
324 PORT MAP (spw2_dout, swno.d(1));
325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
326 PORT MAP (spw2_sout, swno.s(1));
326 PORT MAP (spw2_sout, swno.s(1));
327
327
328 -- GRSPW PHY
328 -- GRSPW PHY
329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
331 spw_phy0 : grspw_phy
331 spw_phy0 : grspw_phy
332 GENERIC MAP(
332 GENERIC MAP(
333 tech => apa3l,
333 tech => apa3l,
334 rxclkbuftype => 1,
334 rxclkbuftype => 1,
335 scantest => 0)
335 scantest => 0)
336 PORT MAP(
336 PORT MAP(
337 rxrst => swno.rxrst,
337 rxrst => swno.rxrst,
338 di => dtmp(j),
338 di => dtmp(j),
339 si => stmp(j),
339 si => stmp(j),
340 rxclko => spw_rxclk(j),
340 rxclko => spw_rxclk(j),
341 do => swni.d(j),
341 do => swni.d(j),
342 ndo => swni.nd(j*5+4 DOWNTO j*5),
342 ndo => swni.nd(j*5+4 DOWNTO j*5),
343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
344 END GENERATE spw_inputloop;
344 END GENERATE spw_inputloop;
345
345
346 -- SPW core
346 -- SPW core
347 sw0 : grspwm GENERIC MAP(
347 sw0 : grspwm GENERIC MAP(
348 tech => apa3l,
348 tech => apa3l,
349 hindex => 1,
349 hindex => 1,
350 pindex => 5,
350 pindex => 5,
351 paddr => 5,
351 paddr => 5,
352 pirq => 11,
352 pirq => 11,
353 sysfreq => 25000, -- CPU_FREQ
353 sysfreq => 25000, -- CPU_FREQ
354 rmap => 1,
354 rmap => 1,
355 rmapcrc => 1,
355 rmapcrc => 1,
356 fifosize1 => 16,
356 fifosize1 => 16,
357 fifosize2 => 16,
357 fifosize2 => 16,
358 rxclkbuftype => 1,
358 rxclkbuftype => 1,
359 rxunaligned => 0,
359 rxunaligned => 0,
360 rmapbufs => 4,
360 rmapbufs => 4,
361 ft => 0,
361 ft => 0,
362 netlist => 0,
362 netlist => 0,
363 ports => 2,
363 ports => 2,
364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
365 memtech => apa3l,
365 memtech => apa3l,
366 destkey => 2,
366 destkey => 2,
367 spwcore => 1
367 spwcore => 1
368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
371 )
371 )
372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
373 spw_rxclk(1),
373 spw_rxclk(1),
374 clk50MHz_int,
374 clk50MHz_int,
375 clk50MHz_int,
375 clk50MHz_int,
376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
378 swni, swno);
378 swni, swno);
379
379
380 swni.tickin <= '0';
380 swni.tickin <= '0';
381 swni.rmapen <= '1';
381 swni.rmapen <= '1';
382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
383 swni.tickinraw <= '0';
383 swni.tickinraw <= '0';
384 swni.timein <= (OTHERS => '0');
384 swni.timein <= (OTHERS => '0');
385 swni.dcrstval <= (OTHERS => '0');
385 swni.dcrstval <= (OTHERS => '0');
386 swni.timerrstval <= (OTHERS => '0');
386 swni.timerrstval <= (OTHERS => '0');
387
387
388 -------------------------------------------------------------------------------
388 -------------------------------------------------------------------------------
389 -- LFR ------------------------------------------------------------------------
389 -- LFR ------------------------------------------------------------------------
390 -------------------------------------------------------------------------------
390 -------------------------------------------------------------------------------
391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
392
392
393 lpp_lfr_1 : lpp_lfr
393 lpp_lfr_1 : lpp_lfr
394 GENERIC MAP (
394 GENERIC MAP (
395 Mem_use => use_RAM,
395 Mem_use => use_RAM,
396 nb_data_by_buffer_size => 32,
396 nb_data_by_buffer_size => 32,
397 --nb_word_by_buffer_size => 30,
397 --nb_word_by_buffer_size => 30,
398 nb_snapshot_param_size => 32,
398 nb_snapshot_param_size => 32,
399 delta_vector_size => 32,
399 delta_vector_size => 32,
400 delta_vector_size_f0_2 => 7, -- log2(96)
400 delta_vector_size_f0_2 => 7, -- log2(96)
401 pindex => 15,
401 pindex => 15,
402 paddr => 15,
402 paddr => 15,
403 pmask => 16#fff#,
403 pmask => 16#fff#,
404 pirq_ms => 6,
404 pirq_ms => 6,
405 pirq_wfp => 14,
405 pirq_wfp => 14,
406 hindex => 2,
406 hindex => 2,
407 top_lfr_version => X"020145") -- aa.bb.cc version
407 top_lfr_version => X"020146") -- aa.bb.cc version
408 -- AA : BOARD NUMBER
408 -- AA : BOARD NUMBER
409 -- 0 => MINI_LFR
409 -- 0 => MINI_LFR
410 -- 1 => EM
410 -- 1 => EM
411 -- 2 => EQM (with A3PE3000)
411 -- 2 => EQM (with A3PE3000)
412 PORT MAP (
412 PORT MAP (
413 clk => clk_25,
413 clk => clk_25,
414 rstn => LFR_rstn,
414 rstn => LFR_rstn,
415 sample_B => sample_s(2 DOWNTO 0),
415 sample_B => sample_s(2 DOWNTO 0),
416 sample_E => sample_s(7 DOWNTO 3),
416 sample_E => sample_s(7 DOWNTO 3),
417 sample_val => sample_val,
417 sample_val => sample_val,
418 apbi => apbi_ext,
418 apbi => apbi_ext,
419 apbo => apbo_ext(15),
419 apbo => apbo_ext(15),
420 ahbi => ahbi_m_ext,
420 ahbi => ahbi_m_ext,
421 ahbo => ahbo_m_ext(2),
421 ahbo => ahbo_m_ext(2),
422 coarse_time => coarse_time,
422 coarse_time => coarse_time,
423 fine_time => fine_time,
423 fine_time => fine_time,
424 data_shaping_BW => bias_fail_sw,
424 data_shaping_BW => bias_fail_sw,
425 debug_vector => OPEN,
425 debug_vector => OPEN,
426 debug_vector_ms => OPEN); --,
426 debug_vector_ms => OPEN); --,
427 --observation_vector_0 => OPEN,
427 --observation_vector_0 => OPEN,
428 --observation_vector_1 => OPEN,
428 --observation_vector_1 => OPEN,
429 --observation_reg => observation_reg);
429 --observation_reg => observation_reg);
430
430
431
431
432 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
432 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
433 sample_s(I) <= sample(I) & '0' & '0';
433 sample_s(I) <= sample(I) & '0' & '0';
434 END GENERATE all_sample;
434 END GENERATE all_sample;
435 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
435 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
436
436
437 -----------------------------------------------------------------------------
437 -----------------------------------------------------------------------------
438 --
438 --
439 -----------------------------------------------------------------------------
439 -----------------------------------------------------------------------------
440 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
440 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
441 GENERIC MAP (
441 GENERIC MAP (
442 ChanelCount => 9,
442 ChanelCount => 9,
443 ncycle_cnv_high => 13,
443 ncycle_cnv_high => 13,
444 ncycle_cnv => 25,
444 ncycle_cnv => 25,
445 FILTER_ENABLED => 16#FF#)
445 FILTER_ENABLED => 16#FF#)
446 PORT MAP (
446 PORT MAP (
447 cnv_clk => clk_24,
447 cnv_clk => clk_24,
448 cnv_rstn => rstn_24,
448 cnv_rstn => rstn_24,
449 cnv => ADC_smpclk_s,
449 cnv => ADC_smpclk_s,
450 clk => clk_25,
450 clk => clk_25,
451 rstn => rstn_25,
451 rstn => rstn_25,
452 ADC_data => ADC_data,
452 ADC_data => ADC_data,
453 ADC_nOE => ADC_OEB_bar_CH_s,
453 ADC_nOE => ADC_OEB_bar_CH_s,
454 sample => sample,
454 sample => sample,
455 sample_val => sample_val);
455 sample_val => sample_val);
456
456
457 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
457 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
458
458
459 ADC_smpclk <= ADC_smpclk_s;
459 ADC_smpclk <= ADC_smpclk_s;
460 HK_smpclk <= ADC_smpclk_s;
460 HK_smpclk <= ADC_smpclk_s;
461
461
462 TAG8 <= nSRAM_BUSY;
462 TAG8 <= nSRAM_BUSY;
463
463
464 -----------------------------------------------------------------------------
464 -----------------------------------------------------------------------------
465 -- HK
465 -- HK
466 -----------------------------------------------------------------------------
466 -----------------------------------------------------------------------------
467 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
467 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
468
468
469 END beh;
469 END beh;
Show file before | Show file after | Hide comments
@@ -1,758 +1,774
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_management.ALL;
45 USE lpp.lpp_lfr_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116
116
117 --==========================================================================
117 --==========================================================================
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 -- when enabled, chip enable polarity should be reversed and bank size also
119 -- when enabled, chip enable polarity should be reversed and bank size also
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 --==========================================================================
122 --==========================================================================
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 --==========================================================================
124 --==========================================================================
125
125
126 SIGNAL clk_50_s : STD_LOGIC := '0';
126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
127 SIGNAL clk_25 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
128 SIGNAL clk_24 : STD_LOGIC := '0';
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 --
132 --
133 SIGNAL errorn : STD_LOGIC;
133 SIGNAL errorn : STD_LOGIC;
134 -- UART AHB ---------------------------------------------------------------
134 -- UART AHB ---------------------------------------------------------------
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
137
137
138 -- UART APB ---------------------------------------------------------------
138 -- UART APB ---------------------------------------------------------------
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
141 --
141 --
142 SIGNAL I00_s : STD_LOGIC;
142 SIGNAL I00_s : STD_LOGIC;
143
143
144 -- CONSTANTS
144 -- CONSTANTS
145 CONSTANT CFG_PADTECH : INTEGER := inferred;
145 CONSTANT CFG_PADTECH : INTEGER := inferred;
146 --
146 --
147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
150
150
151 SIGNAL apbi_ext : apb_slv_in_type;
151 SIGNAL apbi_ext : apb_slv_in_type;
152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
157
157
158 -- Spacewire signals
158 -- Spacewire signals
159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 SIGNAL spw_rxtxclk : STD_ULOGIC;
162 SIGNAL spw_rxtxclk : STD_ULOGIC;
163 SIGNAL spw_rxclkn : STD_ULOGIC;
163 SIGNAL spw_rxclkn : STD_ULOGIC;
164 SIGNAL spw_clk : STD_LOGIC;
164 SIGNAL spw_clk : STD_LOGIC;
165 SIGNAL swni : grspw_in_type;
165 SIGNAL swni : grspw_in_type;
166 SIGNAL swno : grspw_out_type;
166 SIGNAL swno : grspw_out_type;
167 -- SIGNAL clkmn : STD_ULOGIC;
167 -- SIGNAL clkmn : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
168 -- SIGNAL txclk : STD_ULOGIC;
169
169
170 --GPIO
170 --GPIO
171 SIGNAL gpioi : gpio_in_type;
171 SIGNAL gpioi : gpio_in_type;
172 SIGNAL gpioo : gpio_out_type;
172 SIGNAL gpioo : gpio_out_type;
173
173
174 -- AD Converter ADS7886
174 -- AD Converter ADS7886
175 SIGNAL sample : Samples14v(7 DOWNTO 0);
175 SIGNAL sample : Samples14v(7 DOWNTO 0);
176 SIGNAL sample_s : Samples(7 DOWNTO 0);
176 SIGNAL sample_s : Samples(7 DOWNTO 0);
177 SIGNAL sample_val : STD_LOGIC;
177 SIGNAL sample_val : STD_LOGIC;
178 SIGNAL ADC_nCS_sig : STD_LOGIC;
178 SIGNAL ADC_nCS_sig : STD_LOGIC;
179 SIGNAL ADC_CLK_sig : STD_LOGIC;
179 SIGNAL ADC_CLK_sig : STD_LOGIC;
180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
181
181
182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
183
183
184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
187 -----------------------------------------------------------------------------
187 -----------------------------------------------------------------------------
188
188
189 SIGNAL LFR_soft_rstn : STD_LOGIC;
189 SIGNAL LFR_soft_rstn : STD_LOGIC;
190 SIGNAL LFR_rstn : STD_LOGIC;
190 SIGNAL LFR_rstn : STD_LOGIC;
191
191
192
192
193 SIGNAL rstn_25 : STD_LOGIC;
193 SIGNAL rstn_25 : STD_LOGIC;
194 SIGNAL rstn_25_d1 : STD_LOGIC;
194 SIGNAL rstn_25_d1 : STD_LOGIC;
195 SIGNAL rstn_25_d2 : STD_LOGIC;
195 SIGNAL rstn_25_d2 : STD_LOGIC;
196 SIGNAL rstn_25_d3 : STD_LOGIC;
196 SIGNAL rstn_25_d3 : STD_LOGIC;
197
197
198 SIGNAL rstn_24 : STD_LOGIC;
198 SIGNAL rstn_24 : STD_LOGIC;
199 SIGNAL rstn_24_d1 : STD_LOGIC;
199 SIGNAL rstn_24_d1 : STD_LOGIC;
200 SIGNAL rstn_24_d2 : STD_LOGIC;
200 SIGNAL rstn_24_d2 : STD_LOGIC;
201 SIGNAL rstn_24_d3 : STD_LOGIC;
201 SIGNAL rstn_24_d3 : STD_LOGIC;
202
202
203 SIGNAL rstn_50 : STD_LOGIC;
203 SIGNAL rstn_50 : STD_LOGIC;
204 SIGNAL rstn_50_d1 : STD_LOGIC;
204 SIGNAL rstn_50_d1 : STD_LOGIC;
205 SIGNAL rstn_50_d2 : STD_LOGIC;
205 SIGNAL rstn_50_d2 : STD_LOGIC;
206 SIGNAL rstn_50_d3 : STD_LOGIC;
206 SIGNAL rstn_50_d3 : STD_LOGIC;
207
207
208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
210
210
211 --
211 --
212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
213
213
214 --
214 --
215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
217
218 SIGNAL nSRAM_READY : STD_LOGIC;
217
219
218 BEGIN -- beh
220 BEGIN -- beh
219
221
220 -----------------------------------------------------------------------------
222 -----------------------------------------------------------------------------
221 -- CLK
223 -- CLK
222 -----------------------------------------------------------------------------
224 -----------------------------------------------------------------------------
223
225
224 --PROCESS(clk_50)
226 --PROCESS(clk_50)
225 --BEGIN
227 --BEGIN
226 -- IF clk_50'EVENT AND clk_50 = '1' THEN
228 -- IF clk_50'EVENT AND clk_50 = '1' THEN
227 -- clk_50_s <= NOT clk_50_s;
229 -- clk_50_s <= NOT clk_50_s;
228 -- END IF;
230 -- END IF;
229 --END PROCESS;
231 --END PROCESS;
230
232
231 --PROCESS(clk_50_s)
233 --PROCESS(clk_50_s)
232 --BEGIN
234 --BEGIN
233 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
235 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
234 -- clk_25 <= NOT clk_25;
236 -- clk_25 <= NOT clk_25;
235 -- END IF;
237 -- END IF;
236 --END PROCESS;
238 --END PROCESS;
237
239
238 --PROCESS(clk_49)
240 --PROCESS(clk_49)
239 --BEGIN
241 --BEGIN
240 -- IF clk_49'EVENT AND clk_49 = '1' THEN
242 -- IF clk_49'EVENT AND clk_49 = '1' THEN
241 -- clk_24 <= NOT clk_24;
243 -- clk_24 <= NOT clk_24;
242 -- END IF;
244 -- END IF;
243 --END PROCESS;
245 --END PROCESS;
244
246
245 --PROCESS(clk_25)
247 --PROCESS(clk_25)
246 --BEGIN
248 --BEGIN
247 -- IF clk_25'EVENT AND clk_25 = '1' THEN
249 -- IF clk_25'EVENT AND clk_25 = '1' THEN
248 -- rstn_25 <= reset;
250 -- rstn_25 <= reset;
249 -- END IF;
251 -- END IF;
250 --END PROCESS;
252 --END PROCESS;
251
253
252 PROCESS (clk_50, reset)
254 PROCESS (clk_50, reset)
253 BEGIN -- PROCESS
255 BEGIN -- PROCESS
254 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
256 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
255 clk_50_s <= NOT clk_50_s;
257 clk_50_s <= NOT clk_50_s;
256 END IF;
258 END IF;
257 END PROCESS;
259 END PROCESS;
258
260
259 PROCESS (clk_50_s, reset)
261 PROCESS (clk_50_s, reset)
260 BEGIN -- PROCESS
262 BEGIN -- PROCESS
261 IF reset = '0' THEN -- asynchronous reset (active low)
263 IF reset = '0' THEN -- asynchronous reset (active low)
262 clk_25 <= '0';
264 clk_25 <= '0';
263 rstn_25 <= '0';
265 rstn_25 <= '0';
264 rstn_25_d1 <= '0';
266 rstn_25_d1 <= '0';
265 rstn_25_d2 <= '0';
267 rstn_25_d2 <= '0';
266 rstn_25_d3 <= '0';
268 rstn_25_d3 <= '0';
267 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
269 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
268 clk_25 <= NOT clk_25;
270 clk_25 <= NOT clk_25;
269 rstn_25_d1 <= '1';
271 rstn_25_d1 <= '1';
270 rstn_25_d2 <= rstn_25_d1;
272 rstn_25_d2 <= rstn_25_d1;
271 rstn_25_d3 <= rstn_25_d2;
273 rstn_25_d3 <= rstn_25_d2;
272 rstn_25 <= rstn_25_d3;
274 rstn_25 <= rstn_25_d3;
273 END IF;
275 END IF;
274 END PROCESS;
276 END PROCESS;
275
277
276 PROCESS (clk_49, reset)
278 PROCESS (clk_49, reset)
277 BEGIN -- PROCESS
279 BEGIN -- PROCESS
278 IF reset = '0' THEN -- asynchronous reset (active low)
280 IF reset = '0' THEN -- asynchronous reset (active low)
279 clk_24 <= '0';
281 clk_24 <= '0';
280 rstn_24_d1 <= '0';
282 rstn_24_d1 <= '0';
281 rstn_24_d2 <= '0';
283 rstn_24_d2 <= '0';
282 rstn_24_d3 <= '0';
284 rstn_24_d3 <= '0';
283 rstn_24 <= '0';
285 rstn_24 <= '0';
284 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
286 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
285 clk_24 <= NOT clk_24;
287 clk_24 <= NOT clk_24;
286 rstn_24_d1 <= '1';
288 rstn_24_d1 <= '1';
287 rstn_24_d2 <= rstn_24_d1;
289 rstn_24_d2 <= rstn_24_d1;
288 rstn_24_d3 <= rstn_24_d2;
290 rstn_24_d3 <= rstn_24_d2;
289 rstn_24 <= rstn_24_d3;
291 rstn_24 <= rstn_24_d3;
290 END IF;
292 END IF;
291 END PROCESS;
293 END PROCESS;
292
294
293 -----------------------------------------------------------------------------
295 -----------------------------------------------------------------------------
294
296
295 PROCESS (clk_25, rstn_25)
297 PROCESS (clk_25, rstn_25)
296 BEGIN -- PROCESS
298 BEGIN -- PROCESS
297 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
299 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
298 LED0 <= '0';
300 LED0 <= '0';
299 LED1 <= '0';
301 LED1 <= '0';
300 LED2 <= '0';
302 LED2 <= '0';
301 --IO1 <= '0';
303 --IO1 <= '0';
302 --IO2 <= '1';
304 --IO2 <= '1';
303 --IO3 <= '0';
305 --IO3 <= '0';
304 --IO4 <= '0';
306 --IO4 <= '0';
305 --IO5 <= '0';
307 --IO5 <= '0';
306 --IO6 <= '0';
308 --IO6 <= '0';
307 --IO7 <= '0';
309 --IO7 <= '0';
308 --IO8 <= '0';
310 --IO8 <= '0';
309 --IO9 <= '0';
311 --IO9 <= '0';
310 --IO10 <= '0';
312 --IO10 <= '0';
311 --IO11 <= '0';
313 --IO11 <= '0';
312 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
314 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
313 LED0 <= '0';
315 LED0 <= '0';
314 LED1 <= '1';
316 LED1 <= '1';
315 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
317 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
316 --IO1 <= '1';
318 --IO1 <= '1';
317 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
319 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
318 --IO3 <= ADC_SDO(0);
320 --IO3 <= ADC_SDO(0);
319 --IO4 <= ADC_SDO(1);
321 --IO4 <= ADC_SDO(1);
320 --IO5 <= ADC_SDO(2);
322 --IO5 <= ADC_SDO(2);
321 --IO6 <= ADC_SDO(3);
323 --IO6 <= ADC_SDO(3);
322 --IO7 <= ADC_SDO(4);
324 --IO7 <= ADC_SDO(4);
323 --IO8 <= ADC_SDO(5);
325 --IO8 <= ADC_SDO(5);
324 --IO9 <= ADC_SDO(6);
326 --IO9 <= ADC_SDO(6);
325 --IO10 <= ADC_SDO(7);
327 --IO10 <= ADC_SDO(7);
326 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
328 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
327 END IF;
329 END IF;
328 END PROCESS;
330 END PROCESS;
329
331
330 PROCESS (clk_24, rstn_24)
332 PROCESS (clk_24, rstn_24)
331 BEGIN -- PROCESS
333 BEGIN -- PROCESS
332 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
334 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
333 I00_s <= '0';
335 I00_s <= '0';
334 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
336 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
335 I00_s <= NOT I00_s;
337 I00_s <= NOT I00_s;
336 END IF;
338 END IF;
337 END PROCESS;
339 END PROCESS;
338 -- IO0 <= I00_s;
340 -- IO0 <= I00_s;
339
341
340 --UARTs
342 --UARTs
341 nCTS1 <= '1';
343 nCTS1 <= '1';
342 nCTS2 <= '1';
344 nCTS2 <= '1';
343 nDCD2 <= '1';
345 nDCD2 <= '1';
344
346
345 --
347 --
346
348
347 leon3_soc_1 : leon3_soc
349 leon3_soc_1 : leon3_soc
348 GENERIC MAP (
350 GENERIC MAP (
349 fabtech => apa3e,
351 fabtech => apa3e,
350 memtech => apa3e,
352 memtech => apa3e,
351 padtech => inferred,
353 padtech => inferred,
352 clktech => inferred,
354 clktech => inferred,
353 disas => 0,
355 disas => 0,
354 dbguart => 0,
356 dbguart => 0,
355 pclow => 2,
357 pclow => 2,
356 clk_freq => 25000,
358 clk_freq => 25000,
357 IS_RADHARD => 0,
359 IS_RADHARD => 0,
358 NB_CPU => 1,
360 NB_CPU => 1,
359 ENABLE_FPU => 1,
361 ENABLE_FPU => 1,
360 FPU_NETLIST => 0,
362 FPU_NETLIST => 0,
361 ENABLE_DSU => 1,
363 ENABLE_DSU => 1,
362 ENABLE_AHB_UART => 1,
364 ENABLE_AHB_UART => 1,
363 ENABLE_APB_UART => 1,
365 ENABLE_APB_UART => 1,
364 ENABLE_IRQMP => 1,
366 ENABLE_IRQMP => 1,
365 ENABLE_GPT => 1,
367 ENABLE_GPT => 1,
366 NB_AHB_MASTER => NB_AHB_MASTER,
368 NB_AHB_MASTER => NB_AHB_MASTER,
367 NB_AHB_SLAVE => NB_AHB_SLAVE,
369 NB_AHB_SLAVE => NB_AHB_SLAVE,
368 NB_APB_SLAVE => NB_APB_SLAVE,
370 NB_APB_SLAVE => NB_APB_SLAVE,
369 ADDRESS_SIZE => 20,
371 ADDRESS_SIZE => 20,
370 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
372 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
371 BYPASS_EDAC_MEMCTRLR => '1',
373 BYPASS_EDAC_MEMCTRLR => '0',
372 SRBANKSZ => 9)
374 SRBANKSZ => 9)
373 PORT MAP (
375 PORT MAP (
374 clk => clk_25,
376 clk => clk_25,
375 reset => rstn_25,
377 reset => rstn_25,
376 errorn => errorn,
378 errorn => errorn,
377 ahbrxd => TXD1,
379 ahbrxd => TXD1,
378 ahbtxd => RXD1,
380 ahbtxd => RXD1,
379 urxd1 => TXD2,
381 urxd1 => TXD2,
380 utxd1 => RXD2,
382 utxd1 => RXD2,
381 address => SRAM_A,
383 address => SRAM_A,
382 data => SRAM_DQ,
384 data => SRAM_DQ,
383 nSRAM_BE0 => SRAM_nBE(0),
385 nSRAM_BE0 => SRAM_nBE(0),
384 nSRAM_BE1 => SRAM_nBE(1),
386 nSRAM_BE1 => SRAM_nBE(1),
385 nSRAM_BE2 => SRAM_nBE(2),
387 nSRAM_BE2 => SRAM_nBE(2),
386 nSRAM_BE3 => SRAM_nBE(3),
388 nSRAM_BE3 => SRAM_nBE(3),
387 nSRAM_WE => SRAM_nWE,
389 nSRAM_WE => SRAM_nWE,
388 nSRAM_CE => SRAM_CE_s,
390 nSRAM_CE => SRAM_CE_s,
389 nSRAM_OE => SRAM_nOE,
391 nSRAM_OE => SRAM_nOE,
390 nSRAM_READY => '1',
392 nSRAM_READY => nSRAM_READY,
391 SRAM_MBE => OPEN,
393 SRAM_MBE => OPEN,
392 apbi_ext => apbi_ext,
394 apbi_ext => apbi_ext,
393 apbo_ext => apbo_ext,
395 apbo_ext => apbo_ext,
394 ahbi_s_ext => ahbi_s_ext,
396 ahbi_s_ext => ahbi_s_ext,
395 ahbo_s_ext => ahbo_s_ext,
397 ahbo_s_ext => ahbo_s_ext,
396 ahbi_m_ext => ahbi_m_ext,
398 ahbi_m_ext => ahbi_m_ext,
397 ahbo_m_ext => ahbo_m_ext);
399 ahbo_m_ext => ahbo_m_ext);
398
400
399 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
401 PROCESS (clk_25, rstn_25)
400 SRAM_CE <= not SRAM_CE_s(0);
402 BEGIN -- PROCESS
401 END GENERATE;
403 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
404 nSRAM_READY <= '1';
405 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
406 nSRAM_READY <= '1';
407 IF IO0 = '1' THEN
408 nSRAM_READY <= '0';
409 END IF;
410 END IF;
411 END PROCESS;
412
413
402
414
403 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
415 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
404 SRAM_CE <= SRAM_CE_s(0);
416 SRAM_CE <= not SRAM_CE_s(0);
405 END GENERATE;
417 END GENERATE;
418
419 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
420 SRAM_CE <= SRAM_CE_s(0);
421 END GENERATE;
406 -------------------------------------------------------------------------------
422 -------------------------------------------------------------------------------
407 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
423 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
408 -------------------------------------------------------------------------------
424 -------------------------------------------------------------------------------
409 apb_lfr_management_1 : apb_lfr_management
425 apb_lfr_management_1 : apb_lfr_management
410 GENERIC MAP (
426 GENERIC MAP (
411 tech => apa3e,
427 tech => apa3e,
412 pindex => 6,
428 pindex => 6,
413 paddr => 6,
429 paddr => 6,
414 pmask => 16#fff#,
430 pmask => 16#fff#,
415 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
431 -- FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
416 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
432 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
417 PORT MAP (
433 PORT MAP (
418 clk25MHz => clk_25,
434 clk25MHz => clk_25,
419 resetn_25MHz => rstn_25, -- TODO
435 resetn_25MHz => rstn_25, -- TODO
420 clk24_576MHz => clk_24, -- 49.152MHz/2
436 -- clk24_576MHz => clk_24, -- 49.152MHz/2
421 resetn_24_576MHz => rstn_24, -- TODO
437 -- resetn_24_576MHz => rstn_24, -- TODO
422 grspw_tick => swno.tickout,
438 grspw_tick => swno.tickout,
423 apbi => apbi_ext,
439 apbi => apbi_ext,
424 apbo => apbo_ext(6),
440 apbo => apbo_ext(6),
425 HK_sample => sample_hk,
441 HK_sample => sample_hk,
426 HK_val => sample_val,
442 HK_val => sample_val,
427 HK_sel => HK_SEL,
443 HK_sel => HK_SEL,
428 DAC_SDO => OPEN,
444 DAC_SDO => OPEN,
429 DAC_SCK => OPEN,
445 DAC_SCK => OPEN,
430 DAC_SYNC => OPEN,
446 DAC_SYNC => OPEN,
431 DAC_CAL_EN => OPEN,
447 DAC_CAL_EN => OPEN,
432 coarse_time => coarse_time,
448 coarse_time => coarse_time,
433 fine_time => fine_time,
449 fine_time => fine_time,
434 LFR_soft_rstn => LFR_soft_rstn
450 LFR_soft_rstn => LFR_soft_rstn
435 );
451 );
436
452
437 -----------------------------------------------------------------------
453 -----------------------------------------------------------------------
438 --- SpaceWire --------------------------------------------------------
454 --- SpaceWire --------------------------------------------------------
439 -----------------------------------------------------------------------
455 -----------------------------------------------------------------------
440
456
441 SPW_EN <= '1';
457 SPW_EN <= '1';
442
458
443 spw_clk <= clk_50_s;
459 spw_clk <= clk_50_s;
444 spw_rxtxclk <= spw_clk;
460 spw_rxtxclk <= spw_clk;
445 spw_rxclkn <= NOT spw_rxtxclk;
461 spw_rxclkn <= NOT spw_rxtxclk;
446
462
447 -- PADS for SPW1
463 -- PADS for SPW1
448 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
464 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
449 PORT MAP (SPW_NOM_DIN, dtmp(0));
465 PORT MAP (SPW_NOM_DIN, dtmp(0));
450 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
466 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
451 PORT MAP (SPW_NOM_SIN, stmp(0));
467 PORT MAP (SPW_NOM_SIN, stmp(0));
452 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
468 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
453 PORT MAP (SPW_NOM_DOUT, swno.d(0));
469 PORT MAP (SPW_NOM_DOUT, swno.d(0));
454 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
470 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
455 PORT MAP (SPW_NOM_SOUT, swno.s(0));
471 PORT MAP (SPW_NOM_SOUT, swno.s(0));
456 -- PADS FOR SPW2
472 -- PADS FOR SPW2
457 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
473 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
458 PORT MAP (SPW_RED_SIN, dtmp(1));
474 PORT MAP (SPW_RED_SIN, dtmp(1));
459 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
475 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
460 PORT MAP (SPW_RED_DIN, stmp(1));
476 PORT MAP (SPW_RED_DIN, stmp(1));
461 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
477 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
462 PORT MAP (SPW_RED_DOUT, swno.d(1));
478 PORT MAP (SPW_RED_DOUT, swno.d(1));
463 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
479 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
464 PORT MAP (SPW_RED_SOUT, swno.s(1));
480 PORT MAP (SPW_RED_SOUT, swno.s(1));
465
481
466 -- GRSPW PHY
482 -- GRSPW PHY
467 --spw1_input: if CFG_SPW_GRSPW = 1 generate
483 --spw1_input: if CFG_SPW_GRSPW = 1 generate
468 spw_inputloop : FOR j IN 0 TO 1 GENERATE
484 spw_inputloop : FOR j IN 0 TO 1 GENERATE
469 spw_phy0 : grspw_phy
485 spw_phy0 : grspw_phy
470 GENERIC MAP(
486 GENERIC MAP(
471 tech => apa3e,
487 tech => apa3e,
472 rxclkbuftype => 1,
488 rxclkbuftype => 1,
473 scantest => 0)
489 scantest => 0)
474 PORT MAP(
490 PORT MAP(
475 rxrst => swno.rxrst,
491 rxrst => swno.rxrst,
476 di => dtmp(j),
492 di => dtmp(j),
477 si => stmp(j),
493 si => stmp(j),
478 rxclko => spw_rxclk(j),
494 rxclko => spw_rxclk(j),
479 do => swni.d(j),
495 do => swni.d(j),
480 ndo => swni.nd(j*5+4 DOWNTO j*5),
496 ndo => swni.nd(j*5+4 DOWNTO j*5),
481 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
497 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
482 END GENERATE spw_inputloop;
498 END GENERATE spw_inputloop;
483
499
484 swni.rmapnodeaddr <= (OTHERS => '0');
500 swni.rmapnodeaddr <= (OTHERS => '0');
485
501
486 -- SPW core
502 -- SPW core
487 sw0 : grspwm GENERIC MAP(
503 sw0 : grspwm GENERIC MAP(
488 tech => apa3e,
504 tech => apa3e,
489 hindex => 1,
505 hindex => 1,
490 pindex => 5,
506 pindex => 5,
491 paddr => 5,
507 paddr => 5,
492 pirq => 11,
508 pirq => 11,
493 sysfreq => 25000, -- CPU_FREQ
509 sysfreq => 25000, -- CPU_FREQ
494 rmap => 1,
510 rmap => 1,
495 rmapcrc => 1,
511 rmapcrc => 1,
496 fifosize1 => 16,
512 fifosize1 => 16,
497 fifosize2 => 16,
513 fifosize2 => 16,
498 rxclkbuftype => 1,
514 rxclkbuftype => 1,
499 rxunaligned => 0,
515 rxunaligned => 0,
500 rmapbufs => 4,
516 rmapbufs => 4,
501 ft => 0,
517 ft => 0,
502 netlist => 0,
518 netlist => 0,
503 ports => 2,
519 ports => 2,
504 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
520 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
505 memtech => apa3e,
521 memtech => apa3e,
506 destkey => 2,
522 destkey => 2,
507 spwcore => 1
523 spwcore => 1
508 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
524 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
509 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
525 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
510 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
526 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
511 )
527 )
512 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
528 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
513 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
529 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
514 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
530 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
515 swni, swno);
531 swni, swno);
516
532
517 swni.tickin <= '0';
533 swni.tickin <= '0';
518 swni.rmapen <= '1';
534 swni.rmapen <= '1';
519 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
535 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
520 swni.tickinraw <= '0';
536 swni.tickinraw <= '0';
521 swni.timein <= (OTHERS => '0');
537 swni.timein <= (OTHERS => '0');
522 swni.dcrstval <= (OTHERS => '0');
538 swni.dcrstval <= (OTHERS => '0');
523 swni.timerrstval <= (OTHERS => '0');
539 swni.timerrstval <= (OTHERS => '0');
524
540
525 -------------------------------------------------------------------------------
541 -------------------------------------------------------------------------------
526 -- LFR ------------------------------------------------------------------------
542 -- LFR ------------------------------------------------------------------------
527 -------------------------------------------------------------------------------
543 -------------------------------------------------------------------------------
528
544
529
545
530 LFR_rstn <= LFR_soft_rstn AND rstn_25;
546 LFR_rstn <= LFR_soft_rstn AND rstn_25;
531 --LFR_rstn <= rstn_25;
547 --LFR_rstn <= rstn_25;
532
548
533 lpp_lfr_1 : lpp_lfr
549 lpp_lfr_1 : lpp_lfr
534 GENERIC MAP (
550 GENERIC MAP (
535 Mem_use => use_RAM,
551 Mem_use => use_RAM,
536 nb_data_by_buffer_size => 32,
552 nb_data_by_buffer_size => 32,
537 nb_snapshot_param_size => 32,
553 nb_snapshot_param_size => 32,
538 delta_vector_size => 32,
554 delta_vector_size => 32,
539 delta_vector_size_f0_2 => 7, -- log2(96)
555 delta_vector_size_f0_2 => 7, -- log2(96)
540 pindex => 15,
556 pindex => 15,
541 paddr => 15,
557 paddr => 15,
542 pmask => 16#fff#,
558 pmask => 16#fff#,
543 pirq_ms => 6,
559 pirq_ms => 6,
544 pirq_wfp => 14,
560 pirq_wfp => 14,
545 hindex => 2,
561 hindex => 2,
546 top_lfr_version => X"000144") -- aa.bb.cc version
562 top_lfr_version => X"000146") -- aa.bb.cc version
547 PORT MAP (
563 PORT MAP (
548 clk => clk_25,
564 clk => clk_25,
549 rstn => LFR_rstn,
565 rstn => LFR_rstn,
550 sample_B => sample_s(2 DOWNTO 0),
566 sample_B => sample_s(2 DOWNTO 0),
551 sample_E => sample_s(7 DOWNTO 3),
567 sample_E => sample_s(7 DOWNTO 3),
552 sample_val => sample_val,
568 sample_val => sample_val,
553 apbi => apbi_ext,
569 apbi => apbi_ext,
554 apbo => apbo_ext(15),
570 apbo => apbo_ext(15),
555 ahbi => ahbi_m_ext,
571 ahbi => ahbi_m_ext,
556 ahbo => ahbo_m_ext(2),
572 ahbo => ahbo_m_ext(2),
557 coarse_time => coarse_time,
573 coarse_time => coarse_time,
558 fine_time => fine_time,
574 fine_time => fine_time,
559 data_shaping_BW => bias_fail_sw_sig,
575 data_shaping_BW => bias_fail_sw_sig,
560 debug_vector => lfr_debug_vector,
576 debug_vector => lfr_debug_vector,
561 debug_vector_ms => lfr_debug_vector_ms
577 debug_vector_ms => lfr_debug_vector_ms
562 );
578 );
563
579
564 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
580 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
565 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
581 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
566 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
582 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
567 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
583 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
568 IO0 <= rstn_25;
584 -- IO0 <= rstn_25;
569 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
585 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
570 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
586 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
571 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
587 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
572 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
588 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
573 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
589 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
574 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
590 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
575 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
591 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
576
592
577 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
593 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
578 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
594 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
579 END GENERATE all_sample;
595 END GENERATE all_sample;
580
596
581 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
597 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
582 GENERIC MAP(
598 GENERIC MAP(
583 ChannelCount => 8,
599 ChannelCount => 8,
584 SampleNbBits => 14,
600 SampleNbBits => 14,
585 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
601 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
586 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
602 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
587 PORT MAP (
603 PORT MAP (
588 -- CONV
604 -- CONV
589 cnv_clk => clk_24,
605 cnv_clk => clk_24,
590 cnv_rstn => rstn_24,
606 cnv_rstn => rstn_24,
591 cnv => ADC_nCS_sig,
607 cnv => ADC_nCS_sig,
592 -- DATA
608 -- DATA
593 clk => clk_25,
609 clk => clk_25,
594 rstn => rstn_25,
610 rstn => rstn_25,
595 sck => ADC_CLK_sig,
611 sck => ADC_CLK_sig,
596 sdo => ADC_SDO_sig,
612 sdo => ADC_SDO_sig,
597 -- SAMPLE
613 -- SAMPLE
598 sample => sample,
614 sample => sample,
599 sample_val => sample_val);
615 sample_val => sample_val);
600
616
601 --IO10 <= ADC_SDO_sig(5);
617 --IO10 <= ADC_SDO_sig(5);
602 --IO9 <= ADC_SDO_sig(4);
618 --IO9 <= ADC_SDO_sig(4);
603 --IO8 <= ADC_SDO_sig(3);
619 --IO8 <= ADC_SDO_sig(3);
604
620
605 ADC_nCS <= ADC_nCS_sig;
621 ADC_nCS <= ADC_nCS_sig;
606 ADC_CLK <= ADC_CLK_sig;
622 ADC_CLK <= ADC_CLK_sig;
607 ADC_SDO_sig <= ADC_SDO;
623 ADC_SDO_sig <= ADC_SDO;
608
624
609 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
625 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
610 "0010001000100010" WHEN HK_SEL = "01" ELSE
626 "0010001000100010" WHEN HK_SEL = "01" ELSE
611 "0100010001000100" WHEN HK_SEL = "10" ELSE
627 "0100010001000100" WHEN HK_SEL = "10" ELSE
612 (OTHERS => '0');
628 (OTHERS => '0');
613
629
614
630
615 ----------------------------------------------------------------------
631 ----------------------------------------------------------------------
616 --- GPIO -----------------------------------------------------------
632 --- GPIO -----------------------------------------------------------
617 ----------------------------------------------------------------------
633 ----------------------------------------------------------------------
618
634
619 grgpio0 : grgpio
635 grgpio0 : grgpio
620 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
636 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
621 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
637 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
622
638
623 gpioi.sig_en <= (OTHERS => '0');
639 gpioi.sig_en <= (OTHERS => '0');
624 gpioi.sig_in <= (OTHERS => '0');
640 gpioi.sig_in <= (OTHERS => '0');
625 gpioi.din <= (OTHERS => '0');
641 gpioi.din <= (OTHERS => '0');
626 --pio_pad_0 : iopad
642 --pio_pad_0 : iopad
627 -- GENERIC MAP (tech => CFG_PADTECH)
643 -- GENERIC MAP (tech => CFG_PADTECH)
628 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
644 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
629 --pio_pad_1 : iopad
645 --pio_pad_1 : iopad
630 -- GENERIC MAP (tech => CFG_PADTECH)
646 -- GENERIC MAP (tech => CFG_PADTECH)
631 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
647 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
632 --pio_pad_2 : iopad
648 --pio_pad_2 : iopad
633 -- GENERIC MAP (tech => CFG_PADTECH)
649 -- GENERIC MAP (tech => CFG_PADTECH)
634 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
650 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
635 --pio_pad_3 : iopad
651 --pio_pad_3 : iopad
636 -- GENERIC MAP (tech => CFG_PADTECH)
652 -- GENERIC MAP (tech => CFG_PADTECH)
637 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
653 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
638 --pio_pad_4 : iopad
654 --pio_pad_4 : iopad
639 -- GENERIC MAP (tech => CFG_PADTECH)
655 -- GENERIC MAP (tech => CFG_PADTECH)
640 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
656 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
641 --pio_pad_5 : iopad
657 --pio_pad_5 : iopad
642 -- GENERIC MAP (tech => CFG_PADTECH)
658 -- GENERIC MAP (tech => CFG_PADTECH)
643 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
659 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
644 --pio_pad_6 : iopad
660 --pio_pad_6 : iopad
645 -- GENERIC MAP (tech => CFG_PADTECH)
661 -- GENERIC MAP (tech => CFG_PADTECH)
646 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
662 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
647 --pio_pad_7 : iopad
663 --pio_pad_7 : iopad
648 -- GENERIC MAP (tech => CFG_PADTECH)
664 -- GENERIC MAP (tech => CFG_PADTECH)
649 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
665 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
650
666
651 PROCESS (clk_25, rstn_25)
667 PROCESS (clk_25, rstn_25)
652 BEGIN -- PROCESS
668 BEGIN -- PROCESS
653 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
669 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
654 -- --IO0 <= '0';
670 -- --IO0 <= '0';
655 -- IO1 <= '0';
671 -- IO1 <= '0';
656 -- IO2 <= '0';
672 -- IO2 <= '0';
657 -- IO3 <= '0';
673 -- IO3 <= '0';
658 -- IO4 <= '0';
674 -- IO4 <= '0';
659 -- IO5 <= '0';
675 -- IO5 <= '0';
660 -- IO6 <= '0';
676 -- IO6 <= '0';
661 -- IO7 <= '0';
677 -- IO7 <= '0';
662 IO8 <= '0';
678 IO8 <= '0';
663 IO9 <= '0';
679 IO9 <= '0';
664 IO10 <= '0';
680 IO10 <= '0';
665 IO11 <= '0';
681 IO11 <= '0';
666 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
682 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
667 CASE gpioo.dout(2 DOWNTO 0) IS
683 CASE gpioo.dout(2 DOWNTO 0) IS
668 WHEN "011" =>
684 WHEN "011" =>
669 -- --IO0 <= observation_reg(0 );
685 -- --IO0 <= observation_reg(0 );
670 -- IO1 <= observation_reg(1 );
686 -- IO1 <= observation_reg(1 );
671 -- IO2 <= observation_reg(2 );
687 -- IO2 <= observation_reg(2 );
672 -- IO3 <= observation_reg(3 );
688 -- IO3 <= observation_reg(3 );
673 -- IO4 <= observation_reg(4 );
689 -- IO4 <= observation_reg(4 );
674 -- IO5 <= observation_reg(5 );
690 -- IO5 <= observation_reg(5 );
675 -- IO6 <= observation_reg(6 );
691 -- IO6 <= observation_reg(6 );
676 -- IO7 <= observation_reg(7 );
692 -- IO7 <= observation_reg(7 );
677 IO8 <= observation_reg(8);
693 IO8 <= observation_reg(8);
678 IO9 <= observation_reg(9);
694 IO9 <= observation_reg(9);
679 IO10 <= observation_reg(10);
695 IO10 <= observation_reg(10);
680 IO11 <= observation_reg(11);
696 IO11 <= observation_reg(11);
681 WHEN "001" =>
697 WHEN "001" =>
682 -- --IO0 <= observation_reg(0 + 12);
698 -- --IO0 <= observation_reg(0 + 12);
683 -- IO1 <= observation_reg(1 + 12);
699 -- IO1 <= observation_reg(1 + 12);
684 -- IO2 <= observation_reg(2 + 12);
700 -- IO2 <= observation_reg(2 + 12);
685 -- IO3 <= observation_reg(3 + 12);
701 -- IO3 <= observation_reg(3 + 12);
686 -- IO4 <= observation_reg(4 + 12);
702 -- IO4 <= observation_reg(4 + 12);
687 -- IO5 <= observation_reg(5 + 12);
703 -- IO5 <= observation_reg(5 + 12);
688 -- IO6 <= observation_reg(6 + 12);
704 -- IO6 <= observation_reg(6 + 12);
689 -- IO7 <= observation_reg(7 + 12);
705 -- IO7 <= observation_reg(7 + 12);
690 IO8 <= observation_reg(8 + 12);
706 IO8 <= observation_reg(8 + 12);
691 IO9 <= observation_reg(9 + 12);
707 IO9 <= observation_reg(9 + 12);
692 IO10 <= observation_reg(10 + 12);
708 IO10 <= observation_reg(10 + 12);
693 IO11 <= observation_reg(11 + 12);
709 IO11 <= observation_reg(11 + 12);
694 WHEN "010" =>
710 WHEN "010" =>
695 -- --IO0 <= observation_reg(0 + 12 + 12);
711 -- --IO0 <= observation_reg(0 + 12 + 12);
696 -- IO1 <= observation_reg(1 + 12 + 12);
712 -- IO1 <= observation_reg(1 + 12 + 12);
697 -- IO2 <= observation_reg(2 + 12 + 12);
713 -- IO2 <= observation_reg(2 + 12 + 12);
698 -- IO3 <= observation_reg(3 + 12 + 12);
714 -- IO3 <= observation_reg(3 + 12 + 12);
699 -- IO4 <= observation_reg(4 + 12 + 12);
715 -- IO4 <= observation_reg(4 + 12 + 12);
700 -- IO5 <= observation_reg(5 + 12 + 12);
716 -- IO5 <= observation_reg(5 + 12 + 12);
701 -- IO6 <= observation_reg(6 + 12 + 12);
717 -- IO6 <= observation_reg(6 + 12 + 12);
702 -- IO7 <= observation_reg(7 + 12 + 12);
718 -- IO7 <= observation_reg(7 + 12 + 12);
703 IO8 <= '0';
719 IO8 <= '0';
704 IO9 <= '0';
720 IO9 <= '0';
705 IO10 <= '0';
721 IO10 <= '0';
706 IO11 <= '0';
722 IO11 <= '0';
707 WHEN "000" =>
723 WHEN "000" =>
708 -- --IO0 <= observation_vector_0(0 );
724 -- --IO0 <= observation_vector_0(0 );
709 -- IO1 <= observation_vector_0(1 );
725 -- IO1 <= observation_vector_0(1 );
710 -- IO2 <= observation_vector_0(2 );
726 -- IO2 <= observation_vector_0(2 );
711 -- IO3 <= observation_vector_0(3 );
727 -- IO3 <= observation_vector_0(3 );
712 -- IO4 <= observation_vector_0(4 );
728 -- IO4 <= observation_vector_0(4 );
713 -- IO5 <= observation_vector_0(5 );
729 -- IO5 <= observation_vector_0(5 );
714 -- IO6 <= observation_vector_0(6 );
730 -- IO6 <= observation_vector_0(6 );
715 -- IO7 <= observation_vector_0(7 );
731 -- IO7 <= observation_vector_0(7 );
716 IO8 <= observation_vector_0(8);
732 IO8 <= observation_vector_0(8);
717 IO9 <= observation_vector_0(9);
733 IO9 <= observation_vector_0(9);
718 IO10 <= observation_vector_0(10);
734 IO10 <= observation_vector_0(10);
719 IO11 <= observation_vector_0(11);
735 IO11 <= observation_vector_0(11);
720 WHEN "100" =>
736 WHEN "100" =>
721 -- --IO0 <= observation_vector_1(0 );
737 -- --IO0 <= observation_vector_1(0 );
722 -- IO1 <= observation_vector_1(1 );
738 -- IO1 <= observation_vector_1(1 );
723 -- IO2 <= observation_vector_1(2 );
739 -- IO2 <= observation_vector_1(2 );
724 -- IO3 <= observation_vector_1(3 );
740 -- IO3 <= observation_vector_1(3 );
725 -- IO4 <= observation_vector_1(4 );
741 -- IO4 <= observation_vector_1(4 );
726 -- IO5 <= observation_vector_1(5 );
742 -- IO5 <= observation_vector_1(5 );
727 -- IO6 <= observation_vector_1(6 );
743 -- IO6 <= observation_vector_1(6 );
728 -- IO7 <= observation_vector_1(7 );
744 -- IO7 <= observation_vector_1(7 );
729 IO8 <= observation_vector_1(8);
745 IO8 <= observation_vector_1(8);
730 IO9 <= observation_vector_1(9);
746 IO9 <= observation_vector_1(9);
731 IO10 <= observation_vector_1(10);
747 IO10 <= observation_vector_1(10);
732 IO11 <= observation_vector_1(11);
748 IO11 <= observation_vector_1(11);
733 WHEN OTHERS => NULL;
749 WHEN OTHERS => NULL;
734 END CASE;
750 END CASE;
735
751
736 END IF;
752 END IF;
737 END PROCESS;
753 END PROCESS;
738 -----------------------------------------------------------------------------
754 -----------------------------------------------------------------------------
739 --
755 --
740 -----------------------------------------------------------------------------
756 -----------------------------------------------------------------------------
741 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
757 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
742 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
758 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
743 apbo_ext(I) <= apb_none;
759 apbo_ext(I) <= apb_none;
744 END GENERATE apbo_ext_not_used;
760 END GENERATE apbo_ext_not_used;
745 END GENERATE all_apbo_ext;
761 END GENERATE all_apbo_ext;
746
762
747
763
748 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
764 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
749 ahbo_s_ext(I) <= ahbs_none;
765 ahbo_s_ext(I) <= ahbs_none;
750 END GENERATE all_ahbo_ext;
766 END GENERATE all_ahbo_ext;
751
767
752 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
768 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
753 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
769 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
754 ahbo_m_ext(I) <= ahbm_none;
770 ahbo_m_ext(I) <= ahbm_none;
755 END GENERATE ahbo_m_ext_not_used;
771 END GENERATE ahbo_m_ext_not_used;
756 END GENERATE all_ahbo_m_ext;
772 END GENERATE all_ahbo_m_ext;
757
773
758 END beh;
774 END beh;
Show file before | Show file after | Hide comments
@@ -1,201 +1,226
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.apb_devices_list.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_memory.ALL;
10 --USE lpp.lpp_waveform_pkg.ALL;
11 --USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_dma_pkg.ALL;
12 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_top_lfr_pkg.ALL;
13 --USE lpp.lpp_lfr_pkg.ALL;
14 --USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.general_purpose.ALL;
15
16
16 LIBRARY techmap;
17 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
18 USE techmap.gencomp.ALL;
18
19
19 LIBRARY grlib;
20 LIBRARY grlib;
20 USE grlib.amba.ALL;
21 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
23 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24 USE GRLIB.DMA2AHB_Package.ALL;
24
25
25 ENTITY DMA_SubSystem IS
26 ENTITY DMA_SubSystem IS
26
27
27 GENERIC (
28 GENERIC (
28 hindex : INTEGER := 2);
29 hindex : INTEGER := 2;
30 CUSTOM_DMA : INTEGER := 1);
29
31
30 PORT (
32 PORT (
31 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
32 rstn : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
33 run : IN STD_LOGIC;
35 run : IN STD_LOGIC;
34 -- AHB
36 -- AHB
35 ahbi : IN AHB_Mst_In_Type;
37 ahbi : IN AHB_Mst_In_Type;
36 ahbo : OUT AHB_Mst_Out_Type;
38 ahbo : OUT AHB_Mst_Out_Type;
37 ---------------------------------------------------------------------------
39 ---------------------------------------------------------------------------
38 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
41 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
40 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
42 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
42 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
45 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
44 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
46 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
45 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
48 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
47 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
48 grant_error : OUT STD_LOGIC --
50 grant_error : OUT STD_LOGIC --
49
51
50 );
52 );
51
53
52 END DMA_SubSystem;
54 END DMA_SubSystem;
53
55
54
56
55 ARCHITECTURE beh OF DMA_SubSystem IS
57 ARCHITECTURE beh OF DMA_SubSystem IS
56
58
57 COMPONENT DMA_SubSystem_GestionBuffer
59 COMPONENT DMA_SubSystem_GestionBuffer
58 GENERIC (
60 GENERIC (
59 BUFFER_ADDR_SIZE : INTEGER;
61 BUFFER_ADDR_SIZE : INTEGER;
60 BUFFER_LENGTH_SIZE : INTEGER);
62 BUFFER_LENGTH_SIZE : INTEGER);
61 PORT (
63 PORT (
62 clk : IN STD_LOGIC;
64 clk : IN STD_LOGIC;
63 rstn : IN STD_LOGIC;
65 rstn : IN STD_LOGIC;
64 run : IN STD_LOGIC;
66 run : IN STD_LOGIC;
65 buffer_new : IN STD_LOGIC;
67 buffer_new : IN STD_LOGIC;
66 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
68 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
67 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
69 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
68 buffer_full : OUT STD_LOGIC;
70 buffer_full : OUT STD_LOGIC;
69 buffer_full_err : OUT STD_LOGIC;
71 buffer_full_err : OUT STD_LOGIC;
70 burst_send : IN STD_LOGIC;
72 burst_send : IN STD_LOGIC;
71 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
73 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
72 END COMPONENT;
74 END COMPONENT;
73
75
74 COMPONENT DMA_SubSystem_Arbiter
76 COMPONENT DMA_SubSystem_Arbiter
75 PORT (
77 PORT (
76 clk : IN STD_LOGIC;
78 clk : IN STD_LOGIC;
77 rstn : IN STD_LOGIC;
79 rstn : IN STD_LOGIC;
78 run : IN STD_LOGIC;
80 run : IN STD_LOGIC;
79 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
80 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
82 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
81 END COMPONENT;
83 END COMPONENT;
82
84
83 COMPONENT DMA_SubSystem_MUX
85 COMPONENT DMA_SubSystem_MUX
84 PORT (
86 PORT (
85 clk : IN STD_LOGIC;
87 clk : IN STD_LOGIC;
86 rstn : IN STD_LOGIC;
88 rstn : IN STD_LOGIC;
87 run : IN STD_LOGIC;
89 run : IN STD_LOGIC;
88 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
90 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
89 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
91 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
90 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
92 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
91 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
93 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
92 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
94 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
93 dma_send : OUT STD_LOGIC;
95 dma_send : OUT STD_LOGIC;
94 dma_valid_burst : OUT STD_LOGIC;
96 dma_valid_burst : OUT STD_LOGIC;
95 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 dma_ren : IN STD_LOGIC;
99 dma_ren : IN STD_LOGIC;
98 dma_done : IN STD_LOGIC;
100 dma_done : IN STD_LOGIC;
99 grant_error : OUT STD_LOGIC);
101 grant_error : OUT STD_LOGIC);
100 END COMPONENT;
102 END COMPONENT;
101
103
102 -----------------------------------------------------------------------------
104 -----------------------------------------------------------------------------
103 SIGNAL dma_send : STD_LOGIC;
105 SIGNAL dma_send : STD_LOGIC;
104 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
106 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
105 SIGNAL dma_done : STD_LOGIC;
107 SIGNAL dma_done : STD_LOGIC;
106 SIGNAL dma_ren : STD_LOGIC;
108 SIGNAL dma_ren : STD_LOGIC;
107 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL burst_send : STD_LOGIC_VECTOR(4 DOWNTO 0);
110 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
112 SIGNAL fifo_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
111 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
113 SIGNAL fifo_address : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0); --
112
114
113
115
114 BEGIN -- beh
116 BEGIN -- beh
115
117
116 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
117 -- DMA
119 -- DMA
118 -----------------------------------------------------------------------------
120 -----------------------------------------------------------------------------
119 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
121 GR_DMA : IF CUSTOM_DMA = 0 GENERATE
120 GENERIC MAP (
122 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
121 tech => inferred,
123 GENERIC MAP (
122 hindex => hindex)
124 tech => inferred,
123 PORT MAP (
125 hindex => hindex)
124 HCLK => clk,
126 PORT MAP (
125 HRESETn => rstn,
127 HCLK => clk,
126 run => run,
128 HRESETn => rstn,
127 AHB_Master_In => ahbi,
129 run => run,
128 AHB_Master_Out => ahbo,
130 AHB_Master_In => ahbi,
131 AHB_Master_Out => ahbo,
132
133 send => dma_send,
134 valid_burst => dma_valid_burst,
135 done => dma_done,
136 ren => dma_ren,
137 address => dma_address,
138 data => dma_data);
139 END GENERATE GR_DMA;
129
140
130 send => dma_send,
141 LPP_DMA_IP : IF CUSTOM_DMA = 1 GENERATE
131 valid_burst => dma_valid_burst,
142 lpp_dma_SEND16B_FIFO2DMA_1 : lpp_dma_SEND16B_FIFO2DMA
132 done => dma_done,
143 GENERIC MAP (
133 ren => dma_ren,
144 hindex => hindex,
134 address => dma_address,
145 vendorid => VENDOR_LPP,
135 data => dma_data);
146 deviceid => 10,
147 version => 0)
148 PORT MAP (
149 clk => clk,
150 rstn => rstn,
151 AHB_Master_In => ahbi,
152 AHB_Master_Out => ahbo,
136
153
137
154 ren => dma_ren,
155 data => dma_data,
156 send => dma_send,
157 valid_burst => dma_valid_burst,
158 done => dma_done,
159 address => dma_address);
160 END GENERATE LPP_DMA_IP;
161
162
138 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
139 -- RoundRobin Selection Channel For DMA
164 -- RoundRobin Selection Channel For DMA
140 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
141 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
166 DMA_SubSystem_Arbiter_1: DMA_SubSystem_Arbiter
142 PORT MAP (
167 PORT MAP (
143 clk => clk,
168 clk => clk,
144 rstn => rstn,
169 rstn => rstn,
145 run => run,
170 run => run,
146 data_burst_valid => fifo_burst_valid,
171 data_burst_valid => fifo_burst_valid,
147 data_burst_valid_grant => fifo_grant);
172 data_burst_valid_grant => fifo_grant);
148
173
149
174
150 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
151 -- Mux between the channel from Waveform Picker and Spectral Matrix
176 -- Mux between the channel from Waveform Picker and Spectral Matrix
152 -----------------------------------------------------------------------------
177 -----------------------------------------------------------------------------
153 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
178 DMA_SubSystem_MUX_1: DMA_SubSystem_MUX
154 PORT MAP (
179 PORT MAP (
155 clk => clk,
180 clk => clk,
156 rstn => rstn,
181 rstn => rstn,
157 run => run,
182 run => run,
158
183
159 fifo_grant => fifo_grant,
184 fifo_grant => fifo_grant,
160 fifo_data => fifo_data,
185 fifo_data => fifo_data,
161 fifo_address => fifo_address,
186 fifo_address => fifo_address,
162 fifo_ren => fifo_ren,
187 fifo_ren => fifo_ren,
163 fifo_burst_done => burst_send,
188 fifo_burst_done => burst_send,
164
189
165 dma_send => dma_send,
190 dma_send => dma_send,
166 dma_valid_burst => dma_valid_burst,
191 dma_valid_burst => dma_valid_burst,
167 dma_address => dma_address,
192 dma_address => dma_address,
168 dma_data => dma_data,
193 dma_data => dma_data,
169 dma_ren => dma_ren,
194 dma_ren => dma_ren,
170 dma_done => dma_done,
195 dma_done => dma_done,
171
196
172 grant_error => grant_error);
197 grant_error => grant_error);
173
198
174
199
175 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
176 -- GEN ADDR
201 -- GEN ADDR
177 -----------------------------------------------------------------------------
202 -----------------------------------------------------------------------------
178 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
203 all_buffer : FOR I IN 4 DOWNTO 0 GENERATE
179 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
204 DMA_SubSystem_GestionBuffer_I : DMA_SubSystem_GestionBuffer
180 GENERIC MAP (
205 GENERIC MAP (
181 BUFFER_ADDR_SIZE => 32,
206 BUFFER_ADDR_SIZE => 32,
182 BUFFER_LENGTH_SIZE => 26)
207 BUFFER_LENGTH_SIZE => 26)
183 PORT MAP (
208 PORT MAP (
184 clk => clk,
209 clk => clk,
185 rstn => rstn,
210 rstn => rstn,
186 run => run,
211 run => run,
187
212
188 buffer_new => buffer_new(I),
213 buffer_new => buffer_new(I),
189 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
214 buffer_addr => buffer_addr(32*(I+1)-1 DOWNTO I*32),
190 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
215 buffer_length => buffer_length(26*(I+1)-1 DOWNTO I*26),
191 buffer_full => buffer_full(I),
216 buffer_full => buffer_full(I),
192 buffer_full_err => buffer_full_err(I),
217 buffer_full_err => buffer_full_err(I),
193
218
194 burst_send => burst_send(I),
219 burst_send => burst_send(I),
195 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
220 burst_addr => fifo_address(32*(I+1)-1 DOWNTO 32*I)
196 );
221 );
197 END GENERATE all_buffer;
222 END GENERATE all_buffer;
198
223
199
224
200
225
201 END beh;
226 END beh;
Show file before | Show file after | Hide comments
@@ -1,289 +1,309
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE std.textio.ALL;
27 USE std.textio.ALL;
28 LIBRARY grlib;
28 LIBRARY grlib;
29 USE grlib.amba.ALL;
29 USE grlib.amba.ALL;
30 USE grlib.stdlib.ALL;
30 USE grlib.stdlib.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34 --LIBRARY lpp;
34 --LIBRARY lpp;
35 --USE lpp.lpp_amba.ALL;
35 --USE lpp.lpp_amba.ALL;
36 --USE lpp.apb_devices_list.ALL;
36 --USE lpp.apb_devices_list.ALL;
37 --USE lpp.lpp_memory.ALL;
37 --USE lpp.lpp_memory.ALL;
38
38
39 PACKAGE lpp_dma_pkg IS
39 PACKAGE lpp_dma_pkg IS
40
40
41 COMPONENT lpp_dma
41 COMPONENT lpp_dma
42 GENERIC (
42 GENERIC (
43 tech : INTEGER;
43 tech : INTEGER;
44 hindex : INTEGER;
44 hindex : INTEGER;
45 pindex : INTEGER;
45 pindex : INTEGER;
46 paddr : INTEGER;
46 paddr : INTEGER;
47 pmask : INTEGER;
47 pmask : INTEGER;
48 pirq : INTEGER);
48 pirq : INTEGER);
49 PORT (
49 PORT (
50 HCLK : IN STD_ULOGIC;
50 HCLK : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
51 HRESETn : IN STD_ULOGIC;
52 apbi : IN apb_slv_in_type;
52 apbi : IN apb_slv_in_type;
53 apbo : OUT apb_slv_out_type;
53 apbo : OUT apb_slv_out_type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 -- fifo interface
56 -- fifo interface
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
57 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
58 fifo_empty : IN STD_LOGIC;
58 fifo_empty : IN STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
59 fifo_ren : OUT STD_LOGIC;
60 -- header
60 -- header
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
61 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
62 header_val : IN STD_LOGIC;
62 header_val : IN STD_LOGIC;
63 header_ack : OUT STD_LOGIC);
63 header_ack : OUT STD_LOGIC);
64 END COMPONENT;
64 END COMPONENT;
65
65
66 COMPONENT fifo_test_dma
66 COMPONENT fifo_test_dma
67 GENERIC (
67 GENERIC (
68 tech : INTEGER;
68 tech : INTEGER;
69 pindex : INTEGER;
69 pindex : INTEGER;
70 paddr : INTEGER;
70 paddr : INTEGER;
71 pmask : INTEGER);
71 pmask : INTEGER);
72 PORT (
72 PORT (
73 HCLK : IN STD_ULOGIC;
73 HCLK : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
74 HRESETn : IN STD_ULOGIC;
75 apbi : IN apb_slv_in_type;
75 apbi : IN apb_slv_in_type;
76 apbo : OUT apb_slv_out_type;
76 apbo : OUT apb_slv_out_type;
77 -- fifo interface
77 -- fifo interface
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 fifo_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
79 fifo_empty : OUT STD_LOGIC;
79 fifo_empty : OUT STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
80 fifo_ren : IN STD_LOGIC;
81 -- header
81 -- header
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 header : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 header_val : OUT STD_LOGIC;
83 header_val : OUT STD_LOGIC;
84 header_ack : IN STD_LOGIC
84 header_ack : IN STD_LOGIC
85 );
85 );
86 END COMPONENT;
86 END COMPONENT;
87
87
88 COMPONENT lpp_dma_apbreg
88 COMPONENT lpp_dma_apbreg
89 GENERIC (
89 GENERIC (
90 pindex : INTEGER;
90 pindex : INTEGER;
91 paddr : INTEGER;
91 paddr : INTEGER;
92 pmask : INTEGER;
92 pmask : INTEGER;
93 pirq : INTEGER);
93 pirq : INTEGER);
94 PORT (
94 PORT (
95 HCLK : IN STD_ULOGIC;
95 HCLK : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
96 HRESETn : IN STD_ULOGIC;
97 apbi : IN apb_slv_in_type;
97 apbi : IN apb_slv_in_type;
98 apbo : OUT apb_slv_out_type;
98 apbo : OUT apb_slv_out_type;
99 -- IN
99 -- IN
100 ready_matrix_f0_0 : IN STD_LOGIC;
100 ready_matrix_f0_0 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
101 ready_matrix_f0_1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
102 ready_matrix_f1 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
103 ready_matrix_f2 : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
104 error_anticipating_empty_fifo : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
105 error_bad_component_error : IN STD_LOGIC;
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
106 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
107
107
108 -- OUT
108 -- OUT
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
109 status_ready_matrix_f0_0 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
110 status_ready_matrix_f0_1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
111 status_ready_matrix_f1 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
112 status_ready_matrix_f2 : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
113 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
114 status_error_bad_component_error : OUT STD_LOGIC;
115
115
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
116 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
117 config_active_interruption_onError : OUT STD_LOGIC;
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
119 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
121 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
122 );
122 );
123 END COMPONENT;
123 END COMPONENT;
124
124
125 COMPONENT lpp_dma_send_1word
125 COMPONENT lpp_dma_send_1word
126 PORT (
126 PORT (
127 HCLK : IN STD_ULOGIC;
127 HCLK : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
129 DMAIn : OUT DMA_In_Type;
129 DMAIn : OUT DMA_In_Type;
130 DMAOut : IN DMA_OUt_Type;
130 DMAOut : IN DMA_OUt_Type;
131 send : IN STD_LOGIC;
131 send : IN STD_LOGIC;
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 ren : OUT STD_LOGIC;
134 ren : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
136 send_ko : OUT STD_LOGIC);
136 send_ko : OUT STD_LOGIC);
137 END COMPONENT;
137 END COMPONENT;
138
138
139 COMPONENT lpp_dma_send_16word
139 COMPONENT lpp_dma_send_16word
140 PORT (
140 PORT (
141 HCLK : IN STD_ULOGIC;
141 HCLK : IN STD_ULOGIC;
142 HRESETn : IN STD_ULOGIC;
142 HRESETn : IN STD_ULOGIC;
143 DMAIn : OUT DMA_In_Type;
143 DMAIn : OUT DMA_In_Type;
144 DMAOut : IN DMA_OUt_Type;
144 DMAOut : IN DMA_OUt_Type;
145 send : IN STD_LOGIC;
145 send : IN STD_LOGIC;
146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
146 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 ren : OUT STD_LOGIC;
148 ren : OUT STD_LOGIC;
149 send_ok : OUT STD_LOGIC;
149 send_ok : OUT STD_LOGIC;
150 send_ko : OUT STD_LOGIC);
150 send_ko : OUT STD_LOGIC);
151 END COMPONENT;
151 END COMPONENT;
152
152
153 COMPONENT fifo_latency_correction
153 COMPONENT fifo_latency_correction
154 PORT (
154 PORT (
155 HCLK : IN STD_ULOGIC;
155 HCLK : IN STD_ULOGIC;
156 HRESETn : IN STD_ULOGIC;
156 HRESETn : IN STD_ULOGIC;
157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
158 fifo_empty : IN STD_LOGIC;
158 fifo_empty : IN STD_LOGIC;
159 fifo_ren : OUT STD_LOGIC;
159 fifo_ren : OUT STD_LOGIC;
160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 dma_empty : OUT STD_LOGIC;
161 dma_empty : OUT STD_LOGIC;
162 dma_ren : IN STD_LOGIC);
162 dma_ren : IN STD_LOGIC);
163 END COMPONENT;
163 END COMPONENT;
164
164
165 COMPONENT lpp_dma_ip
165 COMPONENT lpp_dma_ip
166 GENERIC (
166 GENERIC (
167 tech : INTEGER;
167 tech : INTEGER;
168 hindex : INTEGER);
168 hindex : INTEGER);
169 PORT (
169 PORT (
170 HCLK : IN STD_ULOGIC;
170 HCLK : IN STD_ULOGIC;
171 HRESETn : IN STD_ULOGIC;
171 HRESETn : IN STD_ULOGIC;
172 AHB_Master_In : IN AHB_Mst_In_Type;
172 AHB_Master_In : IN AHB_Mst_In_Type;
173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
173 AHB_Master_Out : OUT AHB_Mst_Out_Type;
174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
174 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
175 fifo_empty : IN STD_LOGIC;
175 fifo_empty : IN STD_LOGIC;
176 fifo_ren : OUT STD_LOGIC;
176 fifo_ren : OUT STD_LOGIC;
177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
177 header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
178 header_val : IN STD_LOGIC;
178 header_val : IN STD_LOGIC;
179 header_ack : OUT STD_LOGIC;
179 header_ack : OUT STD_LOGIC;
180 ready_matrix_f0_0 : OUT STD_LOGIC;
180 ready_matrix_f0_0 : OUT STD_LOGIC;
181 ready_matrix_f0_1 : OUT STD_LOGIC;
181 ready_matrix_f0_1 : OUT STD_LOGIC;
182 ready_matrix_f1 : OUT STD_LOGIC;
182 ready_matrix_f1 : OUT STD_LOGIC;
183 ready_matrix_f2 : OUT STD_LOGIC;
183 ready_matrix_f2 : OUT STD_LOGIC;
184 error_anticipating_empty_fifo : OUT STD_LOGIC;
184 error_anticipating_empty_fifo : OUT STD_LOGIC;
185 error_bad_component_error : OUT STD_LOGIC;
185 error_bad_component_error : OUT STD_LOGIC;
186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 status_ready_matrix_f0_0 : IN STD_LOGIC;
187 status_ready_matrix_f0_0 : IN STD_LOGIC;
188 status_ready_matrix_f0_1 : IN STD_LOGIC;
188 status_ready_matrix_f0_1 : IN STD_LOGIC;
189 status_ready_matrix_f1 : IN STD_LOGIC;
189 status_ready_matrix_f1 : IN STD_LOGIC;
190 status_ready_matrix_f2 : IN STD_LOGIC;
190 status_ready_matrix_f2 : IN STD_LOGIC;
191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
191 status_error_anticipating_empty_fifo : IN STD_LOGIC;
192 status_error_bad_component_error : IN STD_LOGIC;
192 status_error_bad_component_error : IN STD_LOGIC;
193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
193 config_active_interruption_onNewMatrix : IN STD_LOGIC;
194 config_active_interruption_onError : IN STD_LOGIC;
194 config_active_interruption_onError : IN STD_LOGIC;
195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
195 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
196 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
199 END COMPONENT;
199 END COMPONENT;
200
200
201 COMPONENT lpp_dma_singleOrBurst
201 COMPONENT lpp_dma_singleOrBurst
202 GENERIC (
202 GENERIC (
203 tech : INTEGER;
203 tech : INTEGER;
204 hindex : INTEGER);
204 hindex : INTEGER);
205 PORT (
205 PORT (
206 HCLK : IN STD_ULOGIC;
206 HCLK : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
208 run : IN STD_LOGIC;
208 run : IN STD_LOGIC;
209 AHB_Master_In : IN AHB_Mst_In_Type;
209 AHB_Master_In : IN AHB_Mst_In_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 send : IN STD_LOGIC;
211 send : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
213 done : OUT STD_LOGIC;
213 done : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_dmaout_okay : OUT STD_LOGIC);
217 debug_dmaout_okay : OUT STD_LOGIC);
218 END COMPONENT;
218 END COMPONENT;
219
219
220
220
221 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
222 -- DMA_SubSystem
222 -- DMA_SubSystem
223 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
224 COMPONENT DMA_SubSystem
224 COMPONENT DMA_SubSystem
225 GENERIC (
225 GENERIC (
226 hindex : INTEGER);
226 hindex : INTEGER;
227 CUSTOM_DMA : INTEGER := 1);
227 PORT (
228 PORT (
228 clk : IN STD_LOGIC;
229 clk : IN STD_LOGIC;
229 rstn : IN STD_LOGIC;
230 rstn : IN STD_LOGIC;
230 run : IN STD_LOGIC;
231 run : IN STD_LOGIC;
231 ahbi : IN AHB_Mst_In_Type;
232 ahbi : IN AHB_Mst_In_Type;
232 ahbo : OUT AHB_Mst_Out_Type;
233 ahbo : OUT AHB_Mst_Out_Type;
233 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
234 fifo_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
234 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
235 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
236 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
236 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
237 buffer_new : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
237 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 buffer_addr : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
238 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 buffer_length : IN STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
239 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
240 buffer_full : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
240 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 buffer_full_err : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
241 grant_error : OUT STD_LOGIC);
242 grant_error : OUT STD_LOGIC);
242 END COMPONENT;
243 END COMPONENT;
243
244
244 COMPONENT DMA_SubSystem_GestionBuffer
245 COMPONENT DMA_SubSystem_GestionBuffer
245 GENERIC (
246 GENERIC (
246 BUFFER_ADDR_SIZE : INTEGER;
247 BUFFER_ADDR_SIZE : INTEGER;
247 BUFFER_LENGTH_SIZE : INTEGER);
248 BUFFER_LENGTH_SIZE : INTEGER);
248 PORT (
249 PORT (
249 clk : IN STD_LOGIC;
250 clk : IN STD_LOGIC;
250 rstn : IN STD_LOGIC;
251 rstn : IN STD_LOGIC;
251 run : IN STD_LOGIC;
252 run : IN STD_LOGIC;
252 buffer_new : IN STD_LOGIC;
253 buffer_new : IN STD_LOGIC;
253 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
254 buffer_addr : IN STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0);
254 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
255 buffer_length : IN STD_LOGIC_VECTOR(BUFFER_LENGTH_SIZE-1 DOWNTO 0);
255 buffer_full : OUT STD_LOGIC;
256 buffer_full : OUT STD_LOGIC;
256 buffer_full_err : OUT STD_LOGIC;
257 buffer_full_err : OUT STD_LOGIC;
257 burst_send : IN STD_LOGIC;
258 burst_send : IN STD_LOGIC;
258 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
259 burst_addr : OUT STD_LOGIC_VECTOR(BUFFER_ADDR_SIZE-1 DOWNTO 0));
259 END COMPONENT;
260 END COMPONENT;
260
261
261 COMPONENT DMA_SubSystem_Arbiter
262 COMPONENT DMA_SubSystem_Arbiter
262 PORT (
263 PORT (
263 clk : IN STD_LOGIC;
264 clk : IN STD_LOGIC;
264 rstn : IN STD_LOGIC;
265 rstn : IN STD_LOGIC;
265 run : IN STD_LOGIC;
266 run : IN STD_LOGIC;
266 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
267 data_burst_valid : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
267 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
268 data_burst_valid_grant : OUT STD_LOGIC_VECTOR(4 DOWNTO 0));
268 END COMPONENT;
269 END COMPONENT;
269
270
270 COMPONENT DMA_SubSystem_MUX
271 COMPONENT DMA_SubSystem_MUX
271 PORT (
272 PORT (
272 clk : IN STD_LOGIC;
273 clk : IN STD_LOGIC;
273 rstn : IN STD_LOGIC;
274 rstn : IN STD_LOGIC;
274 run : IN STD_LOGIC;
275 run : IN STD_LOGIC;
275 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
276 fifo_grant : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
276 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
277 fifo_data : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
277 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 fifo_address : IN STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
278 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
279 fifo_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
279 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
280 fifo_burst_done : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
280 dma_send : OUT STD_LOGIC;
281 dma_send : OUT STD_LOGIC;
281 dma_valid_burst : OUT STD_LOGIC;
282 dma_valid_burst : OUT STD_LOGIC;
282 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 dma_address : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 dma_ren : IN STD_LOGIC;
285 dma_ren : IN STD_LOGIC;
285 dma_done : IN STD_LOGIC;
286 dma_done : IN STD_LOGIC;
286 grant_error : OUT STD_LOGIC);
287 grant_error : OUT STD_LOGIC);
287 END COMPONENT;
288 END COMPONENT;
289
290 COMPONENT lpp_dma_SEND16B_FIFO2DMA
291 GENERIC (
292 hindex : INTEGER;
293 vendorid : in Integer;
294 deviceid : in Integer;
295 version : in Integer);
296 PORT (
297 clk : IN STD_LOGIC;
298 rstn : IN STD_LOGIC;
299 AHB_Master_In : IN AHB_Mst_In_Type;
300 AHB_Master_Out : OUT AHB_Mst_Out_Type;
301 ren : OUT STD_LOGIC;
302 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 send : IN STD_LOGIC;
304 valid_burst : IN STD_LOGIC;
305 done : OUT STD_LOGIC;
306 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
307 END COMPONENT;
288
308
289 END;
309 END;
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@@ -1,11 +1,12
1 lpp_dma_pkg.vhd
1 lpp_dma_pkg.vhd
2 fifo_latency_correction.vhd
2 fifo_latency_correction.vhd
3 lpp_dma.vhd
3 lpp_dma.vhd
4 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
6 lpp_dma_send_1word.vhd
6 lpp_dma_send_1word.vhd
7 lpp_dma_singleOrBurst.vhd
7 lpp_dma_singleOrBurst.vhd
8 DMA_SubSystem.vhd
8 DMA_SubSystem.vhd
9 DMA_SubSystem_GestionBuffer.vhd
9 DMA_SubSystem_GestionBuffer.vhd
10 DMA_SubSystem_Arbiter.vhd
10 DMA_SubSystem_Arbiter.vhd
11 DMA_SubSystem_MUX.vhd
11 DMA_SubSystem_MUX.vhd
12 lpp_dma_SEND16B_FIFO2DMA.vhd
Show file before | Show file after | Hide comments
@@ -1,572 +1,572
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
42 USE lpp.lpp_leon3_soc_pkg.ALL;
43 LIBRARY iap;
43 LIBRARY iap;
44 USE iap.memctrl.ALL;
44 USE iap.memctrl.ALL;
45
45
46
46
47 ENTITY leon3_soc IS
47 ENTITY leon3_soc IS
48 GENERIC (
48 GENERIC (
49 fabtech : INTEGER := apa3e;
49 fabtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
50 memtech : INTEGER := apa3e;
51 padtech : INTEGER := inferred;
51 padtech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
52 clktech : INTEGER := inferred;
53 disas : INTEGER := 0; -- Enable disassembly to console
53 disas : INTEGER := 0; -- Enable disassembly to console
54 dbguart : INTEGER := 0; -- Print UART on console
54 dbguart : INTEGER := 0; -- Print UART on console
55 pclow : INTEGER := 2;
55 pclow : INTEGER := 2;
56 --
56 --
57 clk_freq : INTEGER := 25000; --kHz
57 clk_freq : INTEGER := 25000; --kHz
58 --
58 --
59 IS_RADHARD : INTEGER := 0;
59 IS_RADHARD : INTEGER := 0;
60 --
60 --
61 NB_CPU : INTEGER := 1;
61 NB_CPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
62 ENABLE_FPU : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
63 FPU_NETLIST : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
64 ENABLE_DSU : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
65 ENABLE_AHB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
66 ENABLE_APB_UART : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
67 ENABLE_IRQMP : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
68 ENABLE_GPT : INTEGER := 1;
69 --
69 --
70 NB_AHB_MASTER : INTEGER := 1;
70 NB_AHB_MASTER : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
71 NB_AHB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
72 NB_APB_SLAVE : INTEGER := 1;
73 --
73 --
74 ADDRESS_SIZE : INTEGER := 20;
74 ADDRESS_SIZE : INTEGER := 20;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
75 USES_IAP_MEMCTRLR : INTEGER := 0;
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
76 BYPASS_EDAC_MEMCTRLR : STD_LOGIC := '0';
77 SRBANKSZ : INTEGER := 8
77 SRBANKSZ : INTEGER := 8
78
78
79 );
79 );
80 PORT (
80 PORT (
81 clk : IN STD_ULOGIC;
81 clk : IN STD_ULOGIC;
82 reset : IN STD_ULOGIC;
82 reset : IN STD_ULOGIC;
83
83
84 errorn : OUT STD_ULOGIC;
84 errorn : OUT STD_ULOGIC;
85
85
86 -- UART AHB ---------------------------------------------------------------
86 -- UART AHB ---------------------------------------------------------------
87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
87 ahbrxd : IN STD_ULOGIC; -- DSU rx data
88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
88 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
89
89
90 -- UART APB ---------------------------------------------------------------
90 -- UART APB ---------------------------------------------------------------
91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
91 urxd1 : IN STD_ULOGIC; -- UART1 rx data
92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
92 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
93
93
94 -- RAM --------------------------------------------------------------------
94 -- RAM --------------------------------------------------------------------
95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
95 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 nSRAM_BE0 : OUT STD_LOGIC;
97 nSRAM_BE0 : OUT STD_LOGIC;
98 nSRAM_BE1 : OUT STD_LOGIC;
98 nSRAM_BE1 : OUT STD_LOGIC;
99 nSRAM_BE2 : OUT STD_LOGIC;
99 nSRAM_BE2 : OUT STD_LOGIC;
100 nSRAM_BE3 : OUT STD_LOGIC;
100 nSRAM_BE3 : OUT STD_LOGIC;
101 nSRAM_WE : OUT STD_LOGIC;
101 nSRAM_WE : OUT STD_LOGIC;
102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 nSRAM_CE : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
103 nSRAM_OE : OUT STD_LOGIC;
103 nSRAM_OE : OUT STD_LOGIC;
104 nSRAM_READY : IN STD_LOGIC;
104 nSRAM_READY : IN STD_LOGIC;
105 SRAM_MBE : INOUT STD_LOGIC;
105 SRAM_MBE : INOUT STD_LOGIC;
106 -- APB --------------------------------------------------------------------
106 -- APB --------------------------------------------------------------------
107 apbi_ext : OUT apb_slv_in_type;
107 apbi_ext : OUT apb_slv_in_type;
108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
108 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
109 -- AHB_Slave --------------------------------------------------------------
109 -- AHB_Slave --------------------------------------------------------------
110 ahbi_s_ext : OUT ahb_slv_in_type;
110 ahbi_s_ext : OUT ahb_slv_in_type;
111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
111 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
112 -- AHB_Master -------------------------------------------------------------
112 -- AHB_Master -------------------------------------------------------------
113 ahbi_m_ext : OUT AHB_Mst_In_Type;
113 ahbi_m_ext : OUT AHB_Mst_In_Type;
114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
114 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
115
115
116 );
116 );
117 END;
117 END;
118
118
119 ARCHITECTURE Behavioral OF leon3_soc IS
119 ARCHITECTURE Behavioral OF leon3_soc IS
120
120
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 -- CONFIG -------------------------------------------------------------------
122 -- CONFIG -------------------------------------------------------------------
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
124
125 -- Clock generator
125 -- Clock generator
126 CONSTANT CFG_CLKMUL : INTEGER := (1);
126 CONSTANT CFG_CLKMUL : INTEGER := (1);
127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
127 CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz
128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
128 CONSTANT CFG_OCLKDIV : INTEGER := (1);
129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
129 CONSTANT CFG_CLK_NOFB : INTEGER := 0;
130 -- LEON3 processor core
130 -- LEON3 processor core
131 CONSTANT CFG_LEON3 : INTEGER := 1;
131 CONSTANT CFG_LEON3 : INTEGER := 1;
132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
132 CONSTANT CFG_NCPU : INTEGER := NB_CPU;
133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
133 CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC
134 CONSTANT CFG_V8 : INTEGER := 0;
134 CONSTANT CFG_V8 : INTEGER := 0;
135 CONSTANT CFG_MAC : INTEGER := 0;
135 CONSTANT CFG_MAC : INTEGER := 0;
136 CONSTANT CFG_SVT : INTEGER := 0;
136 CONSTANT CFG_SVT : INTEGER := 0;
137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
137 CONSTANT CFG_RSTADDR : INTEGER := 16#00000#;
138 CONSTANT CFG_LDDEL : INTEGER := (1);
138 CONSTANT CFG_LDDEL : INTEGER := (1);
139 CONSTANT CFG_NWP : INTEGER := (0);
139 CONSTANT CFG_NWP : INTEGER := (0);
140 CONSTANT CFG_PWD : INTEGER := 1*2;
140 CONSTANT CFG_PWD : INTEGER := 1*2;
141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
141 CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
142 -- 1*(8 + 16 * 0) => grfpu-light
142 -- 1*(8 + 16 * 0) => grfpu-light
143 -- 1*(8 + 16 * 1) => netlist
143 -- 1*(8 + 16 * 1) => netlist
144 -- 0*(8 + 16 * 0) => No FPU
144 -- 0*(8 + 16 * 0) => No FPU
145 -- 0*(8 + 16 * 1) => No FPU;
145 -- 0*(8 + 16 * 1) => No FPU;
146 CONSTANT CFG_ICEN : INTEGER := 1;
146 CONSTANT CFG_ICEN : INTEGER := 1;
147 CONSTANT CFG_ISETS : INTEGER := 1;
147 CONSTANT CFG_ISETS : INTEGER := 1;
148 CONSTANT CFG_ISETSZ : INTEGER := 4;
148 CONSTANT CFG_ISETSZ : INTEGER := 4;
149 CONSTANT CFG_ILINE : INTEGER := 4;
149 CONSTANT CFG_ILINE : INTEGER := 4;
150 CONSTANT CFG_IREPL : INTEGER := 0;
150 CONSTANT CFG_IREPL : INTEGER := 0;
151 CONSTANT CFG_ILOCK : INTEGER := 0;
151 CONSTANT CFG_ILOCK : INTEGER := 0;
152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
152 CONSTANT CFG_ILRAMEN : INTEGER := 0;
153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
153 CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#;
154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
154 CONSTANT CFG_ILRAMSZ : INTEGER := 1;
155 CONSTANT CFG_DCEN : INTEGER := 1;
155 CONSTANT CFG_DCEN : INTEGER := 1;
156 CONSTANT CFG_DSETS : INTEGER := 1;
156 CONSTANT CFG_DSETS : INTEGER := 1;
157 CONSTANT CFG_DSETSZ : INTEGER := 4;
157 CONSTANT CFG_DSETSZ : INTEGER := 4;
158 CONSTANT CFG_DLINE : INTEGER := 4;
158 CONSTANT CFG_DLINE : INTEGER := 4;
159 CONSTANT CFG_DREPL : INTEGER := 0;
159 CONSTANT CFG_DREPL : INTEGER := 0;
160 CONSTANT CFG_DLOCK : INTEGER := 0;
160 CONSTANT CFG_DLOCK : INTEGER := 0;
161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
161 CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0;
162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
162 CONSTANT CFG_DLRAMEN : INTEGER := 0;
163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
163 CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#;
164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
164 CONSTANT CFG_DLRAMSZ : INTEGER := 1;
165 CONSTANT CFG_MMUEN : INTEGER := 0;
165 CONSTANT CFG_MMUEN : INTEGER := 0;
166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
166 CONSTANT CFG_ITLBNUM : INTEGER := 2;
167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
167 CONSTANT CFG_DTLBNUM : INTEGER := 2;
168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
168 CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2;
169 CONSTANT CFG_TLB_REP : INTEGER := 1;
169 CONSTANT CFG_TLB_REP : INTEGER := 1;
170
170
171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
171 CONSTANT CFG_DSU : INTEGER := ENABLE_DSU;
172 CONSTANT CFG_ITBSZ : INTEGER := 0;
172 CONSTANT CFG_ITBSZ : INTEGER := 0;
173 CONSTANT CFG_ATBSZ : INTEGER := 0;
173 CONSTANT CFG_ATBSZ : INTEGER := 0;
174
174
175 -- AMBA settings
175 -- AMBA settings
176 CONSTANT CFG_DEFMST : INTEGER := (0);
176 CONSTANT CFG_DEFMST : INTEGER := (0);
177 CONSTANT CFG_RROBIN : INTEGER := 1;
177 CONSTANT CFG_RROBIN : INTEGER := 1;
178 CONSTANT CFG_SPLIT : INTEGER := 0;
178 CONSTANT CFG_SPLIT : INTEGER := 0;
179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
179 CONSTANT CFG_AHBIO : INTEGER := 16#FFF#;
180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
180 CONSTANT CFG_APBADDR : INTEGER := 16#800#;
181
181
182 -- DSU UART
182 -- DSU UART
183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
183 CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART;
184
184
185 -- LEON2 memory controller
185 -- LEON2 memory controller
186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
186 CONSTANT CFG_MCTRL_SDEN : INTEGER := 0;
187
187
188 -- UART 1
188 -- UART 1
189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
189 CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART;
190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
190 CONSTANT CFG_UART1_FIFO : INTEGER := 1;
191
191
192 -- LEON3 interrupt controller
192 -- LEON3 interrupt controller
193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
193 CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP;
194
194
195 -- Modular timer
195 -- Modular timer
196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
196 CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT;
197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
197 CONSTANT CFG_GPT_NTIM : INTEGER := (2);
198 CONSTANT CFG_GPT_SW : INTEGER := (8);
198 CONSTANT CFG_GPT_SW : INTEGER := (8);
199 CONSTANT CFG_GPT_TW : INTEGER := (32);
199 CONSTANT CFG_GPT_TW : INTEGER := (32);
200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
200 CONSTANT CFG_GPT_IRQ : INTEGER := (8);
201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
201 CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1;
202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
202 CONSTANT CFG_GPT_WDOGEN : INTEGER := 0;
203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
203 CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#;
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205
205
206 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
207 -- SIGNALs
207 -- SIGNALs
208 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
209 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
210 -- CLK & RST --
210 -- CLK & RST --
211 SIGNAL clk2x : STD_ULOGIC;
211 SIGNAL clk2x : STD_ULOGIC;
212 SIGNAL clkmn : STD_ULOGIC;
212 SIGNAL clkmn : STD_ULOGIC;
213 SIGNAL clkm : STD_ULOGIC;
213 SIGNAL clkm : STD_ULOGIC;
214 SIGNAL rstn : STD_ULOGIC;
214 SIGNAL rstn : STD_ULOGIC;
215 SIGNAL rstraw : STD_ULOGIC;
215 SIGNAL rstraw : STD_ULOGIC;
216 SIGNAL pciclk : STD_ULOGIC;
216 SIGNAL pciclk : STD_ULOGIC;
217 SIGNAL sdclkl : STD_ULOGIC;
217 SIGNAL sdclkl : STD_ULOGIC;
218 SIGNAL cgi : clkgen_in_type;
218 SIGNAL cgi : clkgen_in_type;
219 SIGNAL cgo : clkgen_out_type;
219 SIGNAL cgo : clkgen_out_type;
220 --- AHB / APB
220 --- AHB / APB
221 SIGNAL apbi : apb_slv_in_type;
221 SIGNAL apbi : apb_slv_in_type;
222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
222 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
223 SIGNAL ahbsi : ahb_slv_in_type;
223 SIGNAL ahbsi : ahb_slv_in_type;
224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
224 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
225 SIGNAL ahbmi : ahb_mst_in_type;
225 SIGNAL ahbmi : ahb_mst_in_type;
226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
226 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
227 --UART
227 --UART
228 SIGNAL ahbuarti : uart_in_type;
228 SIGNAL ahbuarti : uart_in_type;
229 SIGNAL ahbuarto : uart_out_type;
229 SIGNAL ahbuarto : uart_out_type;
230 SIGNAL apbuarti : uart_in_type;
230 SIGNAL apbuarti : uart_in_type;
231 SIGNAL apbuarto : uart_out_type;
231 SIGNAL apbuarto : uart_out_type;
232 --MEM CTRLR
232 --MEM CTRLR
233 SIGNAL memi : memory_in_type;
233 SIGNAL memi : memory_in_type;
234 SIGNAL memo : memory_out_type;
234 SIGNAL memo : memory_out_type;
235 SIGNAL wpo : wprot_out_type;
235 SIGNAL wpo : wprot_out_type;
236 SIGNAL sdo : sdram_out_type;
236 SIGNAL sdo : sdram_out_type;
237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
237 SIGNAL mbe : STD_LOGIC; -- enable memory programming
238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
238 SIGNAL mbe_drive : STD_LOGIC; -- drive the MBE memory signal
239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
239 SIGNAL nSRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
240 SIGNAL nSRAM_OE_s : STD_LOGIC;
240 SIGNAL nSRAM_OE_s : STD_LOGIC;
241 --IRQ
241 --IRQ
242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
242 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
243 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
244 --Timer
244 --Timer
245 SIGNAL gpti : gptimer_in_type;
245 SIGNAL gpti : gptimer_in_type;
246 SIGNAL gpto : gptimer_out_type;
246 SIGNAL gpto : gptimer_out_type;
247 --DSU
247 --DSU
248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
248 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
249 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
250 SIGNAL dsui : dsu_in_type;
250 SIGNAL dsui : dsu_in_type;
251 SIGNAL dsuo : dsu_out_type;
251 SIGNAL dsuo : dsu_out_type;
252 -----------------------------------------------------------------------------
252 -----------------------------------------------------------------------------
253
253
254
254
255 BEGIN
255 BEGIN
256
256
257
257
258 ----------------------------------------------------------------------
258 ----------------------------------------------------------------------
259 --- Reset and Clock generation -------------------------------------
259 --- Reset and Clock generation -------------------------------------
260 ----------------------------------------------------------------------
260 ----------------------------------------------------------------------
261
261
262 cgi.pllctrl <= "00";
262 cgi.pllctrl <= "00";
263 cgi.pllrst <= rstraw;
263 cgi.pllrst <= rstraw;
264
264
265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
265 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
266
266
267 clkgen0 : clkgen -- clock generator
267 clkgen0 : clkgen -- clock generator
268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
268 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
269 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
270 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
271
271
272 ----------------------------------------------------------------------
272 ----------------------------------------------------------------------
273 --- LEON3 processor / DSU / IRQ ------------------------------------
273 --- LEON3 processor / DSU / IRQ ------------------------------------
274 ----------------------------------------------------------------------
274 ----------------------------------------------------------------------
275
275
276 l3 : IF CFG_LEON3 = 1 GENERATE
276 l3 : IF CFG_LEON3 = 1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
277 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
278 leon3_non_radhard : IF IS_RADHARD = 0 GENERATE
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
279 u0 : ENTITY gaisler.leon3s -- LEON3 processor
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
280 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
281 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
282 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
283 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
284 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
285 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
286 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
287 irqi(i), irqo(i), dbgi(i), dbgo(i));
287 irqi(i), irqo(i), dbgi(i), dbgo(i));
288 END GENERATE leon3_non_radhard;
288 END GENERATE leon3_non_radhard;
289
289
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
290 leon3_radhard_i : IF IS_RADHARD = 1 GENERATE
291 cpu : ENTITY gaisler.leon3ft
291 cpu : ENTITY gaisler.leon3ft
292 GENERIC MAP (
292 GENERIC MAP (
293 HINDEX => i, --: integer; --CPU_HINDEX,
293 HINDEX => i, --: integer; --CPU_HINDEX,
294 FABTECH => fabtech, --CFG_TECH,
294 FABTECH => fabtech, --CFG_TECH,
295 MEMTECH => memtech, --CFG_TECH,
295 MEMTECH => memtech, --CFG_TECH,
296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
296 NWINDOWS => CFG_NWIN, --CFG_NWIN,
297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
297 DSU => CFG_DSU, --condSel (HAS_DEBUG, 1, 0),
298 FPU => CFG_FPU, --CFG_FPU,
298 FPU => CFG_FPU, --CFG_FPU,
299 V8 => CFG_V8, --CFG_V8,
299 V8 => CFG_V8, --CFG_V8,
300 CP => 0, --CFG_CP,
300 CP => 0, --CFG_CP,
301 MAC => CFG_MAC, --CFG_MAC,
301 MAC => CFG_MAC, --CFG_MAC,
302 PCLOW => pclow, --CFG_PCLOW,
302 PCLOW => pclow, --CFG_PCLOW,
303 NOTAG => 0, --CFG_NOTAG,
303 NOTAG => 0, --CFG_NOTAG,
304 NWP => CFG_NWP, --CFG_NWP,
304 NWP => CFG_NWP, --CFG_NWP,
305 ICEN => CFG_ICEN, --CFG_ICEN,
305 ICEN => CFG_ICEN, --CFG_ICEN,
306 IREPL => CFG_IREPL, --CFG_IREPL,
306 IREPL => CFG_IREPL, --CFG_IREPL,
307 ISETS => CFG_ISETS, --CFG_ISETS,
307 ISETS => CFG_ISETS, --CFG_ISETS,
308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
308 ILINESIZE => CFG_ILINE, --CFG_ILINE,
309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
309 ISETSIZE => CFG_ISETSZ, --CFG_ISETSZ,
310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
310 ISETLOCK => CFG_ILOCK, --CFG_ILOCK,
311 DCEN => CFG_DCEN, --CFG_DCEN,
311 DCEN => CFG_DCEN, --CFG_DCEN,
312 DREPL => CFG_DREPL, --CFG_DREPL,
312 DREPL => CFG_DREPL, --CFG_DREPL,
313 DSETS => CFG_DSETS, --CFG_DSETS,
313 DSETS => CFG_DSETS, --CFG_DSETS,
314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
314 DLINESIZE => CFG_DLINE, --CFG_DLINE,
315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
315 DSETSIZE => CFG_DSETSZ, --CFG_DSETSZ,
316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
316 DSETLOCK => CFG_DLOCK, --CFG_DLOCK,
317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
317 DSNOOP => CFG_DSNOOP, --CFG_DSNOOP,
318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
318 ILRAM => CFG_ILRAMEN, --CFG_ILRAMEN,
319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
319 ILRAMSIZE => CFG_ILRAMSZ, --CFG_ILRAMSZ,
320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
320 ILRAMSTART => CFG_ILRAMADDR, --CFG_ILRAMADDR,
321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
321 DLRAM => CFG_DLRAMEN, --CFG_DLRAMEN,
322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
322 DLRAMSIZE => CFG_DLRAMSZ, --CFG_DLRAMSZ,
323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
323 DLRAMSTART => CFG_DLRAMADDR, --CFG_DLRAMADDR,
324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
324 MMUEN => CFG_MMUEN, --CFG_MMUEN,
325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
325 ITLBNUM => CFG_ITLBNUM, --CFG_ITLBNUM,
326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
326 DTLBNUM => CFG_DTLBNUM, --CFG_DTLBNUM,
327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
327 TLB_TYPE => CFG_TLB_TYPE, --CFG_TLB_TYPE,
328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
328 TLB_REP => CFG_TLB_REP, --CFG_TLB_REP,
329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
329 LDDEL => CFG_LDDEL, --CFG_LDDEL,
330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
330 DISAS => disas, --condSel (SIM_ENABLED, 1, 0),
331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
331 TBUF => CFG_ITBSZ, --CFG_ITBSZ,
332 PWD => CFG_PWD, --CFG_PWD,
332 PWD => CFG_PWD, --CFG_PWD,
333 SVT => CFG_SVT, --CFG_SVT,
333 SVT => CFG_SVT, --CFG_SVT,
334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
334 RSTADDR => CFG_RSTADDR, --CFG_RSTADDR,
335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
335 SMP => CFG_NCPU-1, --CFG_NCPU-1,
336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
336 IUFT => 2, --: integer range 0 to 4;--CFG_IUFT_EN,
337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
337 FPFT => 1, --: integer range 0 to 4;--CFG_FPUFT_EN,
338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
338 CMFT => 1, --: integer range 0 to 1;--CFG_CACHE_FT_EN,
339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
339 IUINJ => 0, --: integer; --CFG_RF_ERRINJ,
340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
340 CEINJ => 0, --: integer range 0 to 3;--CFG_CACHE_ERRINJ,
341 CACHED => 0, --: integer; --CFG_DFIXED,
341 CACHED => 0, --: integer; --CFG_DFIXED,
342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
342 NETLIST => 0, --: integer; --CFG_LEON3_NETLIST,
343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
343 SCANTEST => 0, --: integer; --CFG_SCANTEST,
344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
344 MMUPGSZ => 0, --: integer range 0 to 5;--CFG_MMU_PAGE,
345 BP => 1) --CFG_BP
345 BP => 1) --CFG_BP
346 PORT MAP ( --
346 PORT MAP ( --
347 rstn => rstn, --rst_n,
347 rstn => rstn, --rst_n,
348 clk => clkm, --clk,
348 clk => clkm, --clk,
349 ahbi => ahbmi, --ahbmi,
349 ahbi => ahbmi, --ahbmi,
350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
350 ahbo => ahbmo(i), --ahbmo(CPU_HINDEX),
351 ahbsi => ahbsi, --ahbsi,
351 ahbsi => ahbsi, --ahbsi,
352 ahbso => ahbso, --ahbso,
352 ahbso => ahbso, --ahbso,
353 irqi => irqi(i), --irqi(CPU_HINDEX),
353 irqi => irqi(i), --irqi(CPU_HINDEX),
354 irqo => irqo(i), --irqo(CPU_HINDEX),
354 irqo => irqo(i), --irqo(CPU_HINDEX),
355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
355 dbgi => dbgi(i), --dbgi(CPU_HINDEX),
356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
356 dbgo => dbgo(i), --dbgo(CPU_HINDEX),
357 gclk => clkm --clk
357 gclk => clkm --clk
358 );
358 );
359 END GENERATE leon3_radhard_i;
359 END GENERATE leon3_radhard_i;
360
360
361 END GENERATE;
361 END GENERATE;
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
362 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
363
363
364 dsugen : IF CFG_DSU = 1 GENERATE
364 dsugen : IF CFG_DSU = 1 GENERATE
365 dsu0 : dsu3 -- LEON3 Debug Support Unit
365 dsu0 : dsu3 -- LEON3 Debug Support Unit
366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
366 GENERIC MAP (hindex => 0, -- TODO : hindex => 2
367 haddr => 16#900#, hmask => 16#F00#,
367 haddr => 16#900#, hmask => 16#F00#,
368 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
368 ncpu => CFG_NCPU, tbits => 30, tech => memtech,
369 irq => 0, kbytes => CFG_ATBSZ)
369 irq => 0, kbytes => CFG_ATBSZ)
370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
370 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(0),-- TODO :ahbso(2)
371 dbgo, dbgi, dsui, dsuo);
371 dbgo, dbgi, dsui, dsuo);
372 dsui.enable <= '1';
372 dsui.enable <= '1';
373 dsui.break <= '0';
373 dsui.break <= '0';
374 END GENERATE;
374 END GENERATE;
375 END GENERATE;
375 END GENERATE;
376
376
377 nodsu : IF CFG_DSU = 0 GENERATE
377 nodsu : IF CFG_DSU = 0 GENERATE
378 ahbso(2) <= ahbs_none;
378 ahbso(0) <= ahbs_none;
379 dsuo.tstop <= '0';
379 dsuo.tstop <= '0';
380 dsuo.active <= '0';
380 dsuo.active <= '0';
381 END GENERATE;
381 END GENERATE;
382
382
383 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
383 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
384 irqctrl0 : irqmp -- interrupt controller
384 irqctrl0 : irqmp -- interrupt controller
385 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
385 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
386 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
386 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
387 END GENERATE;
387 END GENERATE;
388 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
388 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
389 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
389 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
390 irqi(i).irl <= "0000";
390 irqi(i).irl <= "0000";
391 END GENERATE;
391 END GENERATE;
392 apbo(2) <= apb_none;
392 apbo(2) <= apb_none;
393 END GENERATE;
393 END GENERATE;
394
394
395 ----------------------------------------------------------------------
395 ----------------------------------------------------------------------
396 --- Memory controllers ---------------------------------------------
396 --- Memory controllers ---------------------------------------------
397 ----------------------------------------------------------------------
397 ----------------------------------------------------------------------
398 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
398 ESAMEMCT : IF USES_IAP_MEMCTRLR = 0 GENERATE
399 memctrlr : mctrl GENERIC MAP (
399 memctrlr : mctrl GENERIC MAP (
400 hindex => 0,
400 hindex => 2,
401 pindex => 0,
401 pindex => 0,
402 paddr => 0,
402 paddr => 0,
403 srbanks => 1
403 srbanks => 1
404 )
404 )
405 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
405 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(2), apbi, apbo(0), wpo, sdo);
406 memi.bexcn <= '1';
406 memi.bexcn <= '1';
407 memi.brdyn <= '1';
407 memi.brdyn <= '1';
408
408
409 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
409 nSRAM_CE_s <= NOT (memo.ramsn(1 DOWNTO 0));
410 nSRAM_OE_s <= memo.ramoen(0);
410 nSRAM_OE_s <= memo.ramoen(0);
411 END GENERATE;
411 END GENERATE;
412
412
413 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
413 IAPMEMCT : IF USES_IAP_MEMCTRLR = 1 GENERATE
414 memctrlr : srctrle_0ws
414 memctrlr : srctrle_0ws
415 GENERIC MAP(
415 GENERIC MAP(
416 hindex => 2, -- TODO : hindex => 0
416 hindex => 2, -- TODO : hindex => 0
417 pindex => 0,
417 pindex => 0,
418 paddr => 0,
418 paddr => 0,
419 srbanks => 2,
419 srbanks => 2,
420 banksz => SRBANKSZ, --512k * 32
420 banksz => SRBANKSZ, --512k * 32
421 rmw => 1,
421 rmw => 1,
422 --Aeroflex memory generics:
422 --Aeroflex memory generics:
423 mbpedac => BYPASS_EDAC_MEMCTRLR,
423 mbpedac => BYPASS_EDAC_MEMCTRLR,
424 mprog => 1, -- program memory by default values after reset
424 mprog => 1, -- program memory by default values after reset
425 mpsrate => 15, -- default scrub rate period
425 mpsrate => 15, -- default scrub rate period
426 mpb2s => 14, -- default busy to scrub delay
426 mpb2s => 14, -- default busy to scrub delay
427 mpapb => 1, -- instantiate apb register
427 mpapb => 1, -- instantiate apb register
428 mchipcnt => 2,
428 mchipcnt => 2,
429 mpenall => 1 -- when 0 program only E1 chip, else program all dies
429 mpenall => 1 -- when 0 program only E1 chip, else program all dies
430 )
430 )
431 PORT MAP (
431 PORT MAP (
432 rst => rstn,
432 rst => rstn,
433 clk => clkm,
433 clk => clkm,
434 ahbsi => ahbsi,
434 ahbsi => ahbsi,
435 ahbso => ahbso(2), -- TODO :ahbso(0),
435 ahbso => ahbso(2), -- TODO :ahbso(0),
436 apbi => apbi,
436 apbi => apbi,
437 apbo => apbo(0),
437 apbo => apbo(0),
438 sri => memi,
438 sri => memi,
439 sro => memo,
439 sro => memo,
440 --Aeroflex memory signals:
440 --Aeroflex memory signals:
441 ucerr => OPEN, -- uncorrectable error signal
441 ucerr => OPEN, -- uncorrectable error signal
442 mbe => mbe, -- enable memory programming
442 mbe => mbe, -- enable memory programming
443 mbe_drive => mbe_drive -- drive the MBE memory signal
443 mbe_drive => mbe_drive -- drive the MBE memory signal
444 );
444 );
445
445
446 memi.brdyn <= nSRAM_READY;
446 memi.brdyn <= nSRAM_READY;
447
447
448 mbe_pad : iopad
448 mbe_pad : iopad
449 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
449 GENERIC MAP(tech => padtech, oepol => USES_IAP_MEMCTRLR)
450 PORT MAP(pad => SRAM_MBE,
450 PORT MAP(pad => SRAM_MBE,
451 i => mbe,
451 i => mbe,
452 en => mbe_drive,
452 en => mbe_drive,
453 o => memi.bexcn);
453 o => memi.bexcn);
454
454
455 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
455 nSRAM_CE_s <= (memo.ramsn(1 DOWNTO 0));
456 nSRAM_OE_s <= memo.oen;
456 nSRAM_OE_s <= memo.oen;
457
457
458 END GENERATE;
458 END GENERATE;
459
459
460
460
461 memi.writen <= '1';
461 memi.writen <= '1';
462 memi.wrn <= "1111";
462 memi.wrn <= "1111";
463 memi.bwidth <= "10";
463 memi.bwidth <= "10";
464
464
465 bdr : FOR i IN 0 TO 3 GENERATE
465 bdr : FOR i IN 0 TO 3 GENERATE
466 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
466 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8, oepol => USES_IAP_MEMCTRLR)
467 PORT MAP (
467 PORT MAP (
468 data(31-i*8 DOWNTO 24-i*8),
468 data(31-i*8 DOWNTO 24-i*8),
469 memo.data(31-i*8 DOWNTO 24-i*8),
469 memo.data(31-i*8 DOWNTO 24-i*8),
470 memo.bdrive(i),
470 memo.bdrive(i),
471 memi.data(31-i*8 DOWNTO 24-i*8));
471 memi.data(31-i*8 DOWNTO 24-i*8));
472 END GENERATE;
472 END GENERATE;
473
473
474 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
474 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
475 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
475 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
476 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
476 rams_pad : outpadv GENERIC MAP (tech => padtech, width => 2) PORT MAP (nSRAM_CE, nSRAM_CE_s);
477 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
477 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, nSRAM_OE_s);
478 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
478 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
479 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
479 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
480 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
480 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
481 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
481 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
482 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
482 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
483
483
484
484
485
485
486 ----------------------------------------------------------------------
486 ----------------------------------------------------------------------
487 --- AHB CONTROLLER -------------------------------------------------
487 --- AHB CONTROLLER -------------------------------------------------
488 ----------------------------------------------------------------------
488 ----------------------------------------------------------------------
489 ahb0 : ahbctrl -- AHB arbiter/multiplexer
489 ahb0 : ahbctrl -- AHB arbiter/multiplexer
490 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
490 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
491 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
491 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
492 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
492 ioen => 0, nahbm => maxahbmsp, nahbs => 8, fixbrst => 0)
493 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
493 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
494
494
495 ----------------------------------------------------------------------
495 ----------------------------------------------------------------------
496 --- AHB UART -------------------------------------------------------
496 --- AHB UART -------------------------------------------------------
497 ----------------------------------------------------------------------
497 ----------------------------------------------------------------------
498 dcomgen : IF CFG_AHB_UART = 1 GENERATE
498 dcomgen : IF CFG_AHB_UART = 1 GENERATE
499 dcom0 : ahbuart
499 dcom0 : ahbuart
500 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
500 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
501 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
501 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
502 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
502 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
503 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
503 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
504 END GENERATE;
504 END GENERATE;
505 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
505 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
506
506
507 ----------------------------------------------------------------------
507 ----------------------------------------------------------------------
508 --- APB Bridge -----------------------------------------------------
508 --- APB Bridge -----------------------------------------------------
509 ----------------------------------------------------------------------
509 ----------------------------------------------------------------------
510 apb0 : apbctrl -- AHB/APB bridge
510 apb0 : apbctrl -- AHB/APB bridge
511 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
511 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
512 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
512 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
513
513
514 ----------------------------------------------------------------------
514 ----------------------------------------------------------------------
515 --- GPT Timer ------------------------------------------------------
515 --- GPT Timer ------------------------------------------------------
516 ----------------------------------------------------------------------
516 ----------------------------------------------------------------------
517 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
517 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
518 timer0 : gptimer -- timer unit
518 timer0 : gptimer -- timer unit
519 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
519 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
520 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
520 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
521 nbits => CFG_GPT_TW)
521 nbits => CFG_GPT_TW)
522 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
522 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
523 gpti.dhalt <= dsuo.tstop;
523 gpti.dhalt <= dsuo.tstop;
524 gpti.extclk <= '0';
524 gpti.extclk <= '0';
525 END GENERATE;
525 END GENERATE;
526 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
526 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
527
527
528
528
529 ----------------------------------------------------------------------
529 ----------------------------------------------------------------------
530 --- APB UART -------------------------------------------------------
530 --- APB UART -------------------------------------------------------
531 ----------------------------------------------------------------------
531 ----------------------------------------------------------------------
532 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
532 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
533 uart1 : apbuart -- UART 1
533 uart1 : apbuart -- UART 1
534 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
534 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
535 fifosize => CFG_UART1_FIFO)
535 fifosize => CFG_UART1_FIFO)
536 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
536 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
537 apbuarti.rxd <= urxd1;
537 apbuarti.rxd <= urxd1;
538 apbuarti.extclk <= '0';
538 apbuarti.extclk <= '0';
539 utxd1 <= apbuarto.txd;
539 utxd1 <= apbuarto.txd;
540 apbuarti.ctsn <= '0';
540 apbuarti.ctsn <= '0';
541 END GENERATE;
541 END GENERATE;
542 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
542 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
543
543
544 -------------------------------------------------------------------------------
544 -------------------------------------------------------------------------------
545 -- AMBA BUS -------------------------------------------------------------------
545 -- AMBA BUS -------------------------------------------------------------------
546 -------------------------------------------------------------------------------
546 -------------------------------------------------------------------------------
547
547
548 -- APB --------------------------------------------------------------------
548 -- APB --------------------------------------------------------------------
549 apbi_ext <= apbi;
549 apbi_ext <= apbi;
550 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
550 all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
551 max_16_apb : IF I + 5 < 16 GENERATE
551 max_16_apb : IF I + 5 < 16 GENERATE
552 apbo(I+5) <= apbo_ext(I+5);
552 apbo(I+5) <= apbo_ext(I+5);
553 END GENERATE max_16_apb;
553 END GENERATE max_16_apb;
554 END GENERATE all_apb;
554 END GENERATE all_apb;
555 -- AHB_Slave --------------------------------------------------------------
555 -- AHB_Slave --------------------------------------------------------------
556 ahbi_s_ext <= ahbsi;
556 ahbi_s_ext <= ahbsi;
557 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
557 all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
558 max_16_ahbs : IF I + 3 < 16 GENERATE
558 max_16_ahbs : IF I + 3 < 16 GENERATE
559 ahbso(I+3) <= ahbo_s_ext(I+3);
559 ahbso(I+3) <= ahbo_s_ext(I+3);
560 END GENERATE max_16_ahbs;
560 END GENERATE max_16_ahbs;
561 END GENERATE all_ahbs;
561 END GENERATE all_ahbs;
562 -- AHB_Master -------------------------------------------------------------
562 -- AHB_Master -------------------------------------------------------------
563 ahbi_m_ext <= ahbmi;
563 ahbi_m_ext <= ahbmi;
564 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
564 all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
565 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
565 max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
566 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
566 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
567 END GENERATE max_16_ahbm;
567 END GENERATE max_16_ahbm;
568 END GENERATE all_ahbm;
568 END GENERATE all_ahbm;
569
569
570
570
571
571
572 END Behavioral; No newline at end of file
572 END Behavioral;
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