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DAC CAL input data via fifo
martin -
r262:b51052768d7e martin
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@@ -0,0 +1,67
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.numeric_std.all;
24 use IEEE.std_logic_1164.all;
25
26 entity ReadFifo_GEN is
27 port(
28 clk,raz : in std_logic; --! Horloge et Reset du composant
29 SYNC : in std_logic;
30 Readn : out std_logic
31 );
32 end entity;
33
34
35 architecture ar_ReadFifo_GEN of ReadFifo_GEN is
36
37 type etat is (eX,e0);
38 signal ect : etat;
39
40 signal SYNC_reg : std_logic;
41
42 begin
43 process(clk,raz)
44 begin
45 if(raz='0')then
46 ect <= eX;
47 Readn <= '1';
48
49 elsif(clk'event and clk='1')then
50 SYNC_reg <= SYNC;
51
52 case ect is
53 when eX =>
54 if (SYNC_reg='0' and SYNC='1') then
55 Readn <= '0';
56 ect <= e0;
57 end if;
58
59 when e0 =>
60 Readn <= '1';
61 ect <= eX;
62
63 end case;
64 end if;
65 end process;
66
67 end architecture; No newline at end of file
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@@ -45,7 +45,9 entity APB_DAC is
45 45 rst : in std_logic; --! Reset general du composant
46 46 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
47 47 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
48 DataIN : in std_logic_vector(15 downto 0);
48 49 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
50 Readn : out std_logic;
49 51 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
50 52 SCLK : out std_logic; --! Horloge systeme du convertisseur
51 53 DATA : out std_logic --! Donn�e num�rique s�rialis�
@@ -68,7 +70,7 signal Ready : std_logic;
68 70
69 71 type DAC_ctrlr_Reg is record
70 72 DAC_Cfg : std_logic_vector(1 downto 0);
71 DAC_Data : std_logic_vector(15 downto 0);
73 -- DAC_Data : std_logic_vector(15 downto 0);
72 74 end record;
73 75
74 76 signal Rec : DAC_ctrlr_Reg;
@@ -81,13 +83,14 Rec.DAC_Cfg(1) <= Ready;
81 83
82 84 CONV0 : DacDriver
83 85 generic map (cpt_serial)
84 port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
86 port map(clk,rst,enable,DataIN,SYNC,SCLK,Readn,Ready,Data);
87 -- port map(clk,rst,enable,Rec.DAC_Data,SYNC,SCLK,Ready,Data);
85 88
86 89
87 90 process(rst,clk)
88 91 begin
89 92 if(rst='0')then
90 Rec.DAC_Data <= (others => '0');
93 -- Rec.DAC_Data <= (others => '0');
91 94
92 95 elsif(clk'event and clk='1')then
93 96
@@ -97,8 +100,8 Rec.DAC_Cfg(1) <= Ready;
97 100 case apbi.paddr(abits-1 downto 2) is
98 101 when "000000" =>
99 102 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
100 when "000001" =>
101 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
103 -- when "000001" =>
104 -- Rec.DAC_Data <= apbi.pwdata(15 downto 0);
102 105 when others =>
103 106 null;
104 107 end case;
@@ -110,9 +113,9 Rec.DAC_Cfg(1) <= Ready;
110 113 when "000000" =>
111 114 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
112 115 Rdata(1 downto 0) <= Rec.DAC_Cfg;
113 when "000001" =>
114 Rdata(31 downto 16) <= X"FD18";
115 Rdata(15 downto 0) <= Rec.DAC_Data;
116 -- when "000001" =>
117 -- Rdata(31 downto 16) <= X"FD18";
118 -- Rdata(15 downto 0) <= Rec.DAC_Data;
116 119 when others =>
117 120 Rdata <= (others => '0');
118 121 end case;
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@@ -32,9 +32,10 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
32 32 clk : in std_logic; --! Horloge du composant
33 33 rst : in std_logic; --! Reset general du composant
34 34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
35 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 Readn : out std_logic;
38 39 Ready : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
39 40 Data : out std_logic --! Donn�e num�rique s�rialis�
40 41 );
@@ -46,7 +47,7 end entity;
46 47 architecture ar_DacDriver of DacDriver is
47 48
48 49 signal s_SCLK : std_logic;
49 signal Sended : std_logic;
50 signal Send : std_logic;
50 51
51 52 begin
52 53
@@ -56,12 +57,14 SystemCLK : Systeme_Clock
56 57
57 58
58 59 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,Sended,SYNC);
60 port map (s_SCLK,rst,enable,Send,SYNC);
60 61
61 62
62 63 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_C,Sended,Ready,Data);
64 port map (clk,rst,s_SCLK,Data_IN,Send,Ready,Data);
64 65
66 RenGEN : ReadFifo_GEN
67 port map (clk,rst,Send,Readn);
65 68
66 69 SCLK <= s_SCLK;
67 70
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@@ -29,7 +29,7 entity Gene_SYNC is
29 29 port(
30 30 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
31 31 enable : in std_logic; --! Autorise ou non l'utilisation du composant
32 Sended : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
32 Send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
33 33 SYNC : out std_logic --! Signal de synchronisation du convertisseur g�n�r�
34 34 );
35 35 end Gene_SYNC;
@@ -46,7 +46,7 begin
46 46 if(raz='0')then
47 47 SYNC <= '0';
48 48 count <= 14;
49 Sended <= '0';
49 Send <= '0';
50 50
51 51 elsif(SCLK' event and SCLK='1')then
52 52 if(enable='1')then
@@ -57,10 +57,10 begin
57 57 elsif(count=16)then
58 58 count <= 0;
59 59 SYNC <= '0';
60 Sended <= '1';
60 Send <= '1';
61 61 else
62 62 count <= count+1;
63 Sended <= '0';
63 Send <= '0';
64 64 end if;
65 65
66 66 end if;
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@@ -37,15 +37,18 component APB_DAC is
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 abits : integer := 8);
40 abits : integer := 8;
41 cpt_serial : integer := 6);
41 42 port (
42 43 clk : in std_logic;
43 44 rst : in std_logic;
44 45 apbi : in apb_slv_in_type;
45 46 apbo : out apb_slv_out_type;
46 Cal_EN : out std_logic;
47 SYNC : out std_logic;
48 SCLK : out std_logic;
47 DataIN : in std_logic_vector(15 downto 0);
48 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
49 Readn : out std_logic;
50 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
51 SCLK : out std_logic; --! Horloge systeme du convertisseur
49 52 DATA : out std_logic
50 53 );
51 54 end component;
@@ -57,9 +60,10 generic(cpt_serial : integer := 6); --! G�n�rique contenant le r�sultat de la division clk/sclk !!! clk=25Mhz
57 60 clk : in std_logic;
58 61 rst : in std_logic;
59 62 enable : in std_logic;
60 Data_C : in std_logic_vector(15 downto 0);
61 SYNC : out std_logic;
62 SCLK : out std_logic;
63 Data_IN : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
64 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
65 SCLK : out std_logic; --! Horloge systeme du convertisseur
66 Readn : out std_logic;
63 67 Ready : out std_logic;
64 68 Data : out std_logic
65 69 );
@@ -78,7 +82,7 component Gene_SYNC is
78 82 port(
79 83 SCLK,raz : in std_logic; --! Horloge systeme et Reset du composant
80 84 enable : in std_logic; --! Autorise ou non l'utilisation du composant
81 Sended : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
85 Send : out std_logic; --! Flag, Autorise l'envoi (s�rialisation) d'une nouvelle donn�e
82 86 SYNC : out std_logic); --! Signal de synchronisation du convertisseur g�n�r�
83 87 end component;
84 88
@@ -93,4 +97,12 port(
93 97 Data : out std_logic);
94 98 end component;
95 99
100 component ReadFifo_GEN is
101 port(
102 clk,raz : in std_logic; --! Horloge et Reset du composant
103 SYNC : in std_logic;
104 Readn : out std_logic
105 );
106 end component;
107
96 108 end; No newline at end of file
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