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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Fixed bug, now minor and major frame pulses have the good width....
Alexis Jeandet -
r222:b37e19fe4c0b alexis
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@@ -1,289 +1,292
1 1 -- TOP_GSE.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5 library lpp;
6 6 use lpp.lpp_usb.all;
7 7 use lpp.Rocket_PCM_Encoder.all;
8 8 use lpp.iir_filter.all;
9 9 use lpp.general_purpose.all;
10 10 library techmap;
11 11 use techmap.gencomp.all;
12 12 use work.config.all;
13 13
14 14
15 15 entity TOP_EGSE2 is
16 16 generic(WordSize : integer := 8; WordCnt : integer := 144;MinFCount : integer := 64;Simu : integer :=0);
17 17 port(
18 18 Clock : in std_logic;
19 19 reset : in std_logic;
20 20 DataRTX : in std_logic;
21 21 DataRTX_echo : out std_logic;
22 22 SCLK : out std_logic;
23 23 Gate : out std_logic;
24 24 Major_Frame : out std_logic;
25 25 Minor_Frame : out std_logic;
26 26 if_clk : out STD_LOGIC;
27 27 flagb : in STD_LOGIC;
28 28 slwr : out STD_LOGIC;
29 29 slrd : out std_logic;
30 30 pktend : out STD_LOGIC;
31 31 sloe : out STD_LOGIC;
32 32 fdbusw : out std_logic_vector (7 downto 0);
33 33 fifoadr : out std_logic_vector (1 downto 0);
34 34 BUS0 : out std_logic;
35 35 BUS12 : out std_logic;
36 36 BUS13 : out std_logic;
37 37 BUS14 : out std_logic
38 38 );
39 39 end TOP_EGSE2;
40 40
41 41
42 42
43 43 architecture ar_TOP_EGSE2 of TOP_EGSE2 is
44 44
45 45 component CLKINT
46 46 port( A : in std_logic := 'U';
47 47 Y : out std_logic
48 48 );
49 49 end component;
50 50
51 51 signal clk : std_logic;
52 52 signal clk_48 : std_logic;
53 53 signal sclkint : std_logic;
54 54 signal RaZ : std_logic;
55 55 signal rstn : std_logic;
56 56 signal WordCount : integer range 0 to WordCnt-1;
57 57 signal WordClk : std_logic;
58 58 signal MinFCnt : integer range 0 to MinFCount-1;
59 59 signal MinF : std_logic;
60 60 signal MinFclk : std_logic;
61 61 signal MajF : std_logic;
62 62 signal GateLF : std_logic;
63 63 signal GateHF : std_logic;
64 64 signal GateDC : std_logic;
65 65 signal GateR : std_logic;
66 66 signal Gateint : std_logic;
67 67 signal NwDat : std_logic;
68 68 signal NwDatR : std_logic;
69 69 signal DATA : std_logic_vector(WordSize-1 downto 0);
70 70 signal MinFVector : std_logic_vector(WordSize-1 downto 0);
71 71
72 72 Signal PROTO_WEN : std_logic;
73 73 Signal PROTO_DATAIN : std_logic_vector (WordSize-1 downto 0);
74 74 Signal PROTO_FULL : std_logic;
75 75 Signal PROTO_WR : std_logic;
76 76 Signal PROTO_DATAOUT : std_logic_vector (WordSize-1 downto 0);
77 77
78 78 Signal clk80 : std_logic;
79 79
80 80 signal cgi : clkgen_in_type;
81 81 signal cgo : clkgen_out_type;
82 82
83 83
84 84 begin
85 85
86 86
87 87 DataRTX_echo <= DataRTX; --P48
88 88
89 89
90 90 ck_int0 : CLKINT
91 91 port map(Clock,clk_48);
92 92
93 93 RaZ <= cgo.clklock;
94 94
95 95 CLKGEN : entity clkgen
96 96 generic map(
97 97 tech => CFG_CLKTECH,
98 98 clk_mul => CFG_CLKMUL,
99 99 clk_div => CFG_CLKDIV,
100 100 freq => BOARDFREQ, -- clock frequency in KHz
101 101 clk_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkA
102 102 clkb_odiv => CFG_OCLKDIV, -- Proasic3/Fusion output divider clkB
103 103 clkc_odiv => CFG_OCLKDIV) -- Proasic3/Fusion output divider clkC
104 104 port map(
105 105 clkin => clk_48,
106 106 pciclkin => '0',
107 107 clk => clk, -- main clock
108 108 clkn => open, -- inverted main clock
109 109 clk2x => open, -- 2x clock
110 110 sdclk => open, -- SDRAM clock
111 111 pciclk => open, -- PCI clock
112 112 cgi => cgi,
113 113 cgo => cgo,
114 114 clk4x => open, -- 4x clock
115 115 clk1xu => open, -- unscaled 1X clock
116 116 clk2xu => open, -- unscaled 2X clock
117 117 clkb => clk80, -- Proasic3/Fusion clkB
118 118 clkc => open); -- Proasic3/Fusion clkC
119 119
120 120
121 121
122 122 gene3_3M : entity Clk_Divider2
123 123 generic map(N => 10)
124 124 port map(
125 125 clk_in => clk,
126 126 clk_out => sclkint
127 127 );
128 128
129 129 Wcounter : entity Word_Cntr
130 130 generic map(WordSize => WordSize ,N => WordCnt)
131 131 port map(
132 132 Sclk => Sclkint,
133 133 reset => rstn,
134 134 WordClk => WordClk,
135 135 Cnt_out => WordCount
136 136 );
137 137
138 138 MFGEN0 : entity work.MinF_Gen
139 139 generic map(WordCnt => WordCnt)
140 140 port map(
141 141 clk => Sclkint,
142 142 reset => rstn,
143 143 WordCnt_in => WordCount,
144 144 WordClk => WordClk,
145 145 MinF_Clk => MinF
146 146 );
147 147
148 148 MinFcounter : entity Word_Cntr
149 149 generic map(WordSize => WordCnt ,N => MinFCount)
150 150 port map(
151 151 Sclk => WordClk,
152 152 reset => rstn,
153 153 WordClk => MinFclk,
154 154 Cnt_out => MinFCnt
155 155 );
156 156
157 157 MFGEN1 : entity work.MajF_Gen
158 158 generic map(WordCnt => WordCnt,MinFCount => MinFCount)
159 159 port map(
160 160 clk => Sclkint,
161 161 reset => rstn,
162 162 WordCnt_in => WordCount,
163 163 MinfCnt_in => MinFCnt,
164 164 WordClk => WordClk,
165 165 MajF_Clk => MajF
166 166 );
167 167
168 168 LFGATEGEN0 : entity work.LF_GATE_GEN
169 169 generic map(WordCnt => WordCnt)
170 170 port map(
171 171 clk => Sclkint,
172 172 Wcount => WordCount,
173 173 Gate => GateLF
174 174 );
175 175
176 176 DCGATEGEN0 : entity work.DC_GATE_GEN
177 177 generic map(WordCnt => WordCnt)
178 178 port map(
179 179 clk => Sclkint,
180 180 Wcount => WordCount,
181 181 Gate => GateDC
182 182 );
183 183
184 184 --GateDC <= '0';
185 185 --GateLF <= '0';
186 186
187 187 HFGATEGEN0 :
188 188 GateHF <= '1' when WordCount = 120 else
189 189 '1' when WordCount = 121 else '0';
190 190
191 191
192 192
193 193 SD0 : entity Serial_driver2
194 194 generic map(Sz => WordSize)
195 195 port map(
196 196 Sclk => Sclkint,
197 197 rstn => rstn,
198 198 Sdata => DataRTX,
199 199 Gate => GateR,
200 200 NwDat => NwDat,
201 201 Data => DATA
202 202 );
203 203
204 204
205 205
206 206 proto: entity work.ICI_EGSE_PROTOCOL
207 207 generic map(WordSize => WordSize,WordCnt => WordCnt,MinFCount => MinFCount,Simu => 0)
208 208 port map(
209 209 clk => clk,
210 210 -- reset => not MinF,
211 211 reset => rstn,
212 212 WEN => PROTO_WEN,
213 213 MinfCnt_in => MinfCnt,
214 214 WordCnt_in => WordCount,
215 215 DATAIN => PROTO_DATAIN,
216 216 FULL => PROTO_FULL,
217 217 WR => PROTO_WR,
218 218 DATAOUT => PROTO_DATAOUT
219 219 );
220 220
221 221
222 222
223 223 USB2: entity work.FX2_WithFIFO
224 224 generic map(CFG_MEMTECH,use_RAM)
225 225 port map(
226 226 clk => clk,
227 227 if_clk => if_clk,
228 228 reset => rstn,
229 229 flagb => flagb,
230 230 slwr => slwr,
231 231 slrd => slrd,
232 232 pktend => pktend,
233 233 sloe => sloe,
234 234 fdbusw => fdbusw,
235 235 fifoadr => fifoadr,
236 236 FULL => PROTO_FULL,
237 237 wen => PROTO_WR,
238 238 Data => PROTO_DATAOUT
239 239 );
240 240
241 241
242 242 rstn <= reset and RaZ;
243 243 SCLK <= Sclkint;
244 244
245 245 Major_Frame <= MajF;
246 --Minor_Frame <= MinF;
247 Minor_Frame <= MinFclk;
246 Minor_Frame <= MinF;
247 --Minor_Frame <= MinFclk;
248 248 gateint <= GateDC or GateLF or GateHF;
249 249 Gate <= gateint;
250 250
251 251 process(Sclkint,rstn)
252 252 begin
253 253 if rstn = '0' then
254 254 GateR <= '0';
255 255 elsif Sclkint'event and Sclkint = '0' then
256 256 GateR <= Gateint;
257 257 end if;
258 258 end process;
259 259
260 260 BUS0 <= WordClk;
261 261 BUS12 <= MinFVector(0);
262 BUS13 <= MinFclk;
263 BUS14 <= '1' when WordCount = 0 else '0';
262 --BUS13 <= MinFclk;
263 --BUS14 <= '1' when WordCount = 0 else '0';
264 BUS13 <= MinF;
265 BUS14 <= MajF;
266
264 267
265 268 MinFVector <= std_logic_vector(TO_UNSIGNED(MinfCnt,WordSize));
266 269
267 270
268 271 process(clk,rstn)
269 272 begin
270 273 if rstn = '0' then
271 274 PROTO_DATAIN <= (others => '0');
272 275 PROTO_WEN <= '1';
273 276 elsif clk'event and clk = '1' then
274 277 NwDatR <= NwDat;
275 278 if NwDat = '1' and NwDatR = '0' then
276 279 -- PROTO_DATAIN <= std_logic_vector(unsigned(PROTO_DATAIN) + 1 );
277 280 PROTO_DATAIN <= DATA;
278 281 PROTO_WEN <= '0';
279 282 else
280 283 PROTO_WEN <= '1';
281 284 end if;
282 285 end if;
283 286 end process;
284 287
285 288 end ar_TOP_EGSE2;
286 289
287 290
288 291
289 292
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@@ -1,42 +1,49
1 1 -- MajF_Gen.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5
6 6
7 7
8 8 entity MajF_Gen is
9 9 generic(WordCnt : integer :=144;MinFCount : integer := 64);
10 10 port(
11 11 clk : in std_logic;
12 12 reset : in std_logic;
13 13 WordCnt_in : in integer range 0 to WordCnt-1;
14 14 MinfCnt_in : in integer range 0 to MinFCount-1;
15 15 WordClk : in std_logic;
16 16 MajF_Clk : out std_logic
17 17 );
18 18 end entity;
19 19
20 20
21 21
22 22
23 23
24 24
25 25 architecture arMajF_Gen of MajF_Gen is
26 signal monostable : std_logic := '0';
26 27
27 28 begin
28 29
29 30 process(clk)
30 31 begin
31 32 if reset = '0' then
32 33 MajF_Clk <= '0';
34 monostable <= '1';
33 35 elsif clk'event and clk = '0' then
34 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' then
36 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
35 37 MajF_Clk <= '1';
36 38 else
37 39 MajF_Clk <= '0';
38 40 end if;
41 if WordCnt_in = 0 and MinfCnt_in = 0 and WordClk = '1' and monostable = '1' then
42 monostable <= '0';
43 elsif WordCnt_in /= 0 and monostable = '0' then
44 monostable <= '1';
45 end if;
39 46 end if;
40 47 end process;
41 48
42 49 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,41 +1,47
1 1 -- MinF_Gen.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5
6 6
7 7
8 8 entity MinF_Gen is
9 9 generic(WordCnt : integer :=144);
10 10 port(
11 11 clk : in std_logic;
12 12 reset : in std_logic;
13 13 WordCnt_in : in integer range 0 to WordCnt-1;
14 14 WordClk : in std_logic;
15 15 MinF_Clk : out std_logic
16 16 );
17 17 end entity;
18 18
19 19
20 20
21 21
22 22
23 23
24 24 architecture arMinF_Gen of MinF_Gen is
25
25 signal monostable : std_logic := '0';
26 26 begin
27 27
28 28 process(clk)
29 29 begin
30 30 if reset = '0' then
31 31 MinF_Clk <= '0';
32 monostable <= '1';
32 33 elsif clk'event and clk = '0' then
33 if WordCnt_in = 0 and WordClk = '1' then
34 if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
34 35 MinF_Clk <= '1';
35 36 else
36 37 MinF_Clk <= '0';
37 38 end if;
39 if WordCnt_in = 0 and WordClk = '1' and monostable = '1' then
40 monostable <= '0';
41 elsif WordCnt_in /= 0 and monostable = '0' then
42 monostable <= '1';
43 end if;
38 44 end if;
39 45 end process;
40 46
41 47 end architecture; No newline at end of file
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