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LFR-em
pellion -
r460:afe9a0bfb35f (LFR-EM) WFP_MS_1-1-33 JC
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@@ -0,0 +1,69
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.all;
27
28 LIBRARY lpp;
29 USE lpp.cic_pkg.ALL;
30 USE lpp.data_type_pkg.ALL;
31
32 ENTITY cic_lfr_address_gen IS
33 PORT (
34 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 run : IN STD_LOGIC;
37
38 addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
39 addr_init : IN STD_LOGIC;
40 addr_add_1 : IN STD_LOGIC;
41
42 addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
43 );
44 END cic_lfr_address_gen;
45
46 ARCHITECTURE beh OF cic_lfr_address_gen IS
47 SIGNAL address_reg_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
48 SIGNAL address_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
49 BEGIN
50
51 PROCESS (clk, rstn)
52 BEGIN -- PROCESS
53 IF rstn = '0' THEN -- asynchronous reset (active low)
54 address_reg <= (OTHERS => '0');
55 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
56 address_reg <= address_reg_s;
57 END IF;
58 END PROCESS;
59
60 address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE
61 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE
62 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE
63 addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE
64 address_reg;
65
66 addr <= address_reg WHEN addr_init = '0' ELSE addr_base;
67
68 END beh;
69
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@@ -347,7 +347,7 BEGIN -- beh
347 347 GENERIC MAP (
348 348 Mem_use => use_RAM,
349 349 nb_data_by_buffer_size => 32,
350 nb_word_by_buffer_size => 30,
350 --nb_word_by_buffer_size => 30,
351 351 nb_snapshot_param_size => 32,
352 352 delta_vector_size => 32,
353 353 delta_vector_size_f0_2 => 7, -- log2(96)
@@ -357,7 +357,7 BEGIN -- beh
357 357 pirq_ms => 6,
358 358 pirq_wfp => 14,
359 359 hindex => 2,
360 top_lfr_version => X"01011A") -- aa.bb.cc version
360 top_lfr_version => X"010121") -- aa.bb.cc version
361 361 -- AA : BOARD NUMBER
362 362 -- 0 => MINI_LFR
363 363 -- 1 => EM
@@ -373,10 +373,10 BEGIN -- beh
373 373 ahbo => ahbo_m_ext(2),
374 374 coarse_time => coarse_time,
375 375 fine_time => fine_time,
376 data_shaping_BW => bias_fail_sw,
377 observation_vector_0 => OPEN,
378 observation_vector_1 => OPEN,
379 observation_reg => observation_reg);
376 data_shaping_BW => bias_fail_sw);--,
377 --observation_vector_0 => OPEN,
378 --observation_vector_1 => OPEN,
379 --observation_reg => observation_reg);
380 380
381 381
382 382 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
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@@ -20,7 +20,7 VHDLSYNFILES=LFR-em.vhd
20 20 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
21 21 PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
22 22
23 SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
23 #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
24 24 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
25 25
26 26 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
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@@ -178,39 +178,100 ARCHITECTURE beh OF MINI_LFR_top IS
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181
182
183 SIGNAL rstn_25 : STD_LOGIC;
184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 SIGNAL rstn_25_d3 : STD_LOGIC;
181 187
188 SIGNAL rstn_50 : STD_LOGIC;
189 SIGNAL rstn_50_d1 : STD_LOGIC;
190 SIGNAL rstn_50_d2 : STD_LOGIC;
191 SIGNAL rstn_50_d3 : STD_LOGIC;
182 192 BEGIN -- beh
183 193
184 194 -----------------------------------------------------------------------------
185 195 -- CLK
186 196 -----------------------------------------------------------------------------
187 197
188 PROCESS(clk_50)
189 BEGIN
190 IF clk_50'EVENT AND clk_50 = '1' THEN
191 clk_50_s <= NOT clk_50_s;
198 --PROCESS(clk_50)
199 --BEGIN
200 -- IF clk_50'EVENT AND clk_50 = '1' THEN
201 -- clk_50_s <= NOT clk_50_s;
202 -- END IF;
203 --END PROCESS;
204
205 --PROCESS(clk_50_s)
206 --BEGIN
207 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
208 -- clk_25 <= NOT clk_25;
209 -- END IF;
210 --END PROCESS;
211
212 --PROCESS(clk_49)
213 --BEGIN
214 -- IF clk_49'EVENT AND clk_49 = '1' THEN
215 -- clk_24 <= NOT clk_24;
216 -- END IF;
217 --END PROCESS;
218
219 --PROCESS(clk_25)
220 --BEGIN
221 -- IF clk_25'EVENT AND clk_25 = '1' THEN
222 -- rstn_25 <= reset;
223 -- END IF;
224 --END PROCESS;
225
226 PROCESS (clk_50, reset)
227 BEGIN -- PROCESS
228 IF reset = '0' THEN -- asynchronous reset (active low)
229 clk_50_s <= '0';
230 rstn_50 <= '0';
231 rstn_50_d1 <= '0';
232 rstn_50_d2 <= '0';
233 rstn_50_d3 <= '0';
234
235 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
236 clk_50_s <= NOT clk_50_s;
237 rstn_50_d1 <= '1';
238 rstn_50_d2 <= rstn_50_d1;
239 rstn_50_d3 <= rstn_50_d2;
240 rstn_50 <= rstn_50_d3;
192 241 END IF;
193 242 END PROCESS;
194 243
195 PROCESS(clk_50_s)
196 BEGIN
197 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
198 clk_25 <= NOT clk_25;
244 PROCESS (clk_50_s, rstn_50)
245 BEGIN -- PROCESS
246 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
247 clk_25 <= '0';
248 rstn_25 <= '0';
249 rstn_25_d1 <= '0';
250 rstn_25_d2 <= '0';
251 rstn_25_d3 <= '0';
252 ELSIF clk_50_s'event AND clk_50_s = '1' THEN -- rising clock edge
253 clk_25 <= NOT clk_25;
254 rstn_25_d1 <= '1';
255 rstn_25_d2 <= rstn_25_d1;
256 rstn_25_d3 <= rstn_25_d2;
257 rstn_25 <= rstn_25_d3;
199 258 END IF;
200 259 END PROCESS;
201 260
202 PROCESS(clk_49)
203 BEGIN
204 IF clk_49'EVENT AND clk_49 = '1' THEN
205 clk_24 <= NOT clk_24;
261 PROCESS (clk_49, reset)
262 BEGIN -- PROCESS
263 IF reset = '0' THEN -- asynchronous reset (active low)
264 clk_24 <= '0';
265 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
266 clk_24 <= NOT clk_24;
206 267 END IF;
207 268 END PROCESS;
208
269
209 270 -----------------------------------------------------------------------------
210 271
211 PROCESS (clk_25, reset)
272 PROCESS (clk_25, rstn_25)
212 273 BEGIN -- PROCESS
213 IF reset = '0' THEN -- asynchronous reset (active low)
274 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
214 275 LED0 <= '0';
215 276 LED1 <= '0';
216 277 LED2 <= '0';
@@ -243,9 +304,9 BEGIN -- beh
243 304 END IF;
244 305 END PROCESS;
245 306
246 PROCESS (clk_24, reset)
307 PROCESS (clk_24, rstn_25)
247 308 BEGIN -- PROCESS
248 IF reset = '0' THEN -- asynchronous reset (active low)
309 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
249 310 I00_s <= '0';
250 311 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
251 312 I00_s <= NOT I00_s ;
@@ -286,7 +347,7 BEGIN -- beh
286 347 ADDRESS_SIZE => 20)
287 348 PORT MAP (
288 349 clk => clk_25,
289 reset => reset,
350 reset => rstn_25,
290 351 errorn => errorn,
291 352 ahbrxd => TXD1,
292 353 ahbtxd => RXD1,
@@ -322,7 +383,7 BEGIN -- beh
322 383 PORT MAP (
323 384 clk25MHz => clk_25,
324 385 clk24_576MHz => clk_24, -- 49.152MHz/2
325 resetn => reset,
386 resetn => rstn_25,
326 387 grspw_tick => swno.tickout,
327 388 apbi => apbi_ext,
328 389 apbo => apbo_ext(6),
@@ -404,7 +465,7 BEGIN -- beh
404 465 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
405 466 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
406 467 )
407 PORT MAP(reset, clk_25, spw_rxclk(0),
468 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
408 469 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
409 470 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
410 471 swni, swno);
@@ -422,7 +483,8 BEGIN -- beh
422 483 -------------------------------------------------------------------------------
423 484
424 485
425 LFR_rstn <= LFR_soft_rstn AND reset;
486 --LFR_rstn <= LFR_soft_rstn AND rstn_25;
487 LFR_rstn <= rstn_25;
426 488
427 489 lpp_lfr_1 : lpp_lfr
428 490 GENERIC MAP (
@@ -437,7 +499,7 BEGIN -- beh
437 499 pirq_ms => 6,
438 500 pirq_wfp => 14,
439 501 hindex => 2,
440 top_lfr_version => X"000121") -- aa.bb.cc version
502 top_lfr_version => X"000122") -- aa.bb.cc version
441 503 PORT MAP (
442 504 clk => clk_25,
443 505 rstn => LFR_rstn,
@@ -467,11 +529,11 BEGIN -- beh
467 529 PORT MAP (
468 530 -- CONV
469 531 cnv_clk => clk_24,
470 cnv_rstn => reset,
532 cnv_rstn => rstn_25,
471 533 cnv => ADC_nCS_sig,
472 534 -- DATA
473 535 clk => clk_25,
474 rstn => reset,
536 rstn => rstn_25,
475 537 sck => ADC_CLK_sig,
476 538 sdo => ADC_SDO_sig,
477 539 -- SAMPLE
@@ -492,7 +554,7 BEGIN -- beh
492 554
493 555 grgpio0 : grgpio
494 556 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
495 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
557 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
496 558
497 559 --pio_pad_0 : iopad
498 560 -- GENERIC MAP (tech => CFG_PADTECH)
@@ -519,9 +581,9 BEGIN -- beh
519 581 -- GENERIC MAP (tech => CFG_PADTECH)
520 582 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
521 583
522 PROCESS (clk_25, reset)
584 PROCESS (clk_25, rstn_25)
523 585 BEGIN -- PROCESS
524 IF reset = '0' THEN -- asynchronous reset (active low)
586 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
525 587 IO0 <= '0';
526 588 IO1 <= '0';
527 589 IO2 <= '0';
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@@ -43,7 +43,8 FILESKIP =i2cmst.vhd \
43 43 APB_SIMPLE_DIODE.vhd \
44 44 Top_MatrixSpec.vhd \
45 45 APB_FFT.vhd \
46 CoreFFT_simu.vhd
46 CoreFFT_simu.vhd \
47 lpp_lfr_apbreg_simu.vhd
47 48
48 49 include $(GRLIB)/bin/Makefile
49 50 include $(GRLIB)/software/leon3/Makefile
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@@ -191,6 +191,18 BEGIN
191 191 ADC_SDO <= x"AA";
192 192
193 193 SRAM_DQ <= (OTHERS => 'Z');
194 IO0 <= 'Z';
195 IO1 <= 'Z';
196 IO2 <= 'Z';
197 IO3 <= 'Z';
198 IO4 <= 'Z';
199 IO5 <= 'Z';
200 IO6 <= 'Z';
201 IO7 <= 'Z';
202 IO8 <= 'Z';
203 IO9 <= 'Z';
204 IO10 <= 'Z';
205 IO11 <= 'Z';
194 206
195 207 -----------------------------------------------------------------------------
196 208 -- DUT
@@ -249,7 +261,7 BEGIN
249 261
250 262 SRAM_nWE => SRAM_nWE,
251 263 SRAM_CE => SRAM_CE,
252 SRAM_nOE => SRAM_nOE,ddr_buffer_f
264 SRAM_nOE => SRAM_nOE,
253 265 SRAM_nBE => SRAM_nBE,
254 266 SRAM_A => SRAM_A,
255 267 SRAM_DQ => SRAM_DQ);
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@@ -26,7 +26,6 ENTITY lpp_lfr IS
26 26 GENERIC (
27 27 Mem_use : INTEGER := use_RAM;
28 28 nb_data_by_buffer_size : INTEGER := 11;
29 -- nb_word_by_buffer_size : INTEGER := 11; -- TODO
30 29 nb_snapshot_param_size : INTEGER := 11;
31 30 delta_vector_size : INTEGER := 20;
32 31 delta_vector_size_f0_2 : INTEGER := 7;
@@ -60,57 +59,10 ENTITY lpp_lfr IS
60 59 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 60 --
62 61 data_shaping_BW : OUT STD_LOGIC
63 --
64 --
65 -- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 -- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
68 -- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
70 --debug
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f0_data_valid : OUT STD_LOGIC;
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f1_data_valid : OUT STD_LOGIC;
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76 --debug_f2_data_valid : OUT STD_LOGIC;
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78 --debug_f3_data_valid : OUT STD_LOGIC;
79
80 ---- debug FIFO_IN
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
90 ----debug FIFO OUT
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
100 ----debug DMA IN
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
109 62 );
110 63 END lpp_lfr;
111 64
112 65 ARCHITECTURE beh OF lpp_lfr IS
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
114 66 SIGNAL sample_s : Samples(7 DOWNTO 0);
115 67 --
116 68 SIGNAL data_shaping_SP0 : STD_LOGIC;
@@ -142,17 +94,10 ARCHITECTURE beh OF lpp_lfr IS
142 94 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143 95 SIGNAL ready_matrix_f1 : STD_LOGIC;
144 96 SIGNAL ready_matrix_f2 : STD_LOGIC;
145 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146 -- SIGNAL error_bad_component_error : STD_LOGIC;
147 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 97 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149 98 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150 99 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151 100 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
154 --SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155 -- SIGNAL config_active_interruption_onError : STD_LOGIC;
156 101 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 102 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 103 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -161,9 +106,6 ARCHITECTURE beh OF lpp_lfr IS
161 106 SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
162 107
163 108 -- WFP
164 --SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 --SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 --SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 109 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 110 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 111 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
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