HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r460:afe9a0bfb35f

LFR-em

pellion -

r460:afe9a0bfb35f (LFR-EM) WFP_MS_1-1-33 JC

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r460:afe9a0bfb35f

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lib/lpp/dsp/cic/cic_lfr_address_gen.vhd created 644 +69 0

@@ -0,0 +1,69
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-- jean-christophe.pellion@easii-ic.com
	22	----------------------------------------------------------------------------
	23
	24	LIBRARY ieee;
	25	USE ieee.std_logic_1164.ALL;
	26	USE ieee.numeric_std.all;
	27
	28	LIBRARY lpp;
	29	USE lpp.cic_pkg.ALL;
	30	USE lpp.data_type_pkg.ALL;
	31
	32	ENTITY cic_lfr_address_gen IS
	33	PORT (
	34	clk : IN STD_LOGIC;
	35	rstn : IN STD_LOGIC;
	36	run : IN STD_LOGIC;
	37
	38	addr_base : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	39	addr_init : IN STD_LOGIC;
	40	addr_add_1 : IN STD_LOGIC;
	41
	42	addr : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
	43	);
	44	END cic_lfr_address_gen;
	45
	46	ARCHITECTURE beh OF cic_lfr_address_gen IS
	47	SIGNAL address_reg_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
	48	SIGNAL address_reg : STD_LOGIC_VECTOR(7 DOWNTO 0);
	49	BEGIN
	50
	51	PROCESS (clk, rstn)
	52	BEGIN -- PROCESS
	53	IF rstn = '0' THEN -- asynchronous reset (active low)
	54	address_reg <= (OTHERS => '0');
	55	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	56	address_reg <= address_reg_s;
	57	END IF;
	58	END PROCESS;
	59
	60	address_reg_s <= (OTHERS => '0') WHEN run = '0' ELSE
	61	STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(address_reg)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '0' ELSE
	62	STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base)) + 1,8)) WHEN addr_add_1 = '1' AND addr_init = '1' ELSE
	63	addr_base WHEN addr_add_1 = '0' AND addr_init = '1' ELSE
	64	address_reg;
	65
	66	addr <= address_reg WHEN addr_init = '0' ELSE addr_base;
	67
	68	END beh;
	69

designs/LFR-em-WFP_MS/LFR-em.vhd +6 -6

                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
-                  nb_word_by_buffer_size => 30,
+                  --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,      -- log2(96)
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"01011A")  -- aa.bb.cc version
+                  top_lfr_version        => X"010121")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
-                  data_shaping_BW => bias_fail_sw,
+                  data_shaping_BW => bias_fail_sw);--,
-                  observation_vector_0 => OPEN,
+              --observation_vector_0 => OPEN,
-                  observation_vector_1 => OPEN,
+              --observation_vector_1 => OPEN,
-                  observation_reg => observation_reg);
+              --observation_reg => observation_reg);
               all_sample: FOR I IN 7 DOWNTO 0 GENERATE

designs/LFR-em-WFP_MS/Makefile +1 -1

             #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
             PDC=$(VHDLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
-            SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
+            #SDCFILE=$(VHDLIB)/boards/$(BOARD)/LFR_EM_synthesis.sdc
             SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EM_place_and_route.sdc
             BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +89 -27

               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn : STD_LOGIC;
+              SIGNAL rstn_25    : STD_LOGIC;
+              SIGNAL rstn_25_d1 : STD_LOGIC;
+              SIGNAL rstn_25_d2 : STD_LOGIC;
+              SIGNAL rstn_25_d3 : STD_LOGIC;
+              SIGNAL rstn_50    : STD_LOGIC;
+              SIGNAL rstn_50_d1 : STD_LOGIC;
+              SIGNAL rstn_50_d2 : STD_LOGIC;
+              SIGNAL rstn_50_d3 : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
-              PROCESS(clk_50)
+              --PROCESS(clk_50)
-              BEGIN
+              --BEGIN
-                IF clk_50'EVENT AND clk_50 = '1' THEN
+              --  IF clk_50'EVENT AND clk_50 = '1' THEN
-                  clk_50_s <= NOT clk_50_s;
+              --    clk_50_s <= NOT clk_50_s;
+              --  END IF;
+              --END PROCESS;
+              --PROCESS(clk_50_s)
+              --BEGIN
+              --  IF clk_50_s'EVENT AND clk_50_s = '1' THEN
+              --    clk_25 <= NOT clk_25;
+              --  END IF;
+              --END PROCESS;
+              --PROCESS(clk_49)
+              --BEGIN
+              --  IF clk_49'EVENT AND clk_49 = '1' THEN
+              --    clk_24 <= NOT clk_24;
+              --  END IF;
+              --END PROCESS;
+              --PROCESS(clk_25)
+              --BEGIN
+              --  IF clk_25'EVENT AND clk_25 = '1' THEN
+              --    rstn_25 <= reset;
+              --  END IF;
+              --END PROCESS;
+              PROCESS (clk_50, reset)
+              BEGIN  -- PROCESS
+                IF reset = '0' THEN                 -- asynchronous reset (active low)
+                  clk_50_s   <= '0';
+                  rstn_50    <= '0';
+                  rstn_50_d1 <= '0';
+                  rstn_50_d2 <= '0';
+                  rstn_50_d3 <= '0';
+                ELSIF clk_50'event AND clk_50 = '1' THEN  -- rising clock edge
+                  clk_50_s  <= NOT clk_50_s;
+                  rstn_50_d1 <= '1';
+                  rstn_50_d2 <= rstn_50_d1;
+                  rstn_50_d3 <= rstn_50_d2;
+                  rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
-              PROCESS(clk_50_s)
+              PROCESS (clk_50_s, rstn_50)
-              BEGIN
+              BEGIN  -- PROCESS
-                IF clk_50_s'EVENT AND clk_50_s = '1' THEN
+                IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
-                  clk_25 <= NOT clk_25;
+                  clk_25   <= '0';
+                  rstn_25    <= '0';
+                  rstn_25_d1 <= '0';
+                  rstn_25_d2 <= '0';
+                  rstn_25_d3 <= '0';
+                ELSIF clk_50_s'event AND clk_50_s = '1' THEN  -- rising clock edge
+                  clk_25     <= NOT clk_25;
+                  rstn_25_d1 <= '1';
+                  rstn_25_d2 <= rstn_25_d1;
+                  rstn_25_d3 <= rstn_25_d2;
+                  rstn_25    <= rstn_25_d3;
                 END IF;
               END PROCESS;
-              PROCESS(clk_49)
+              PROCESS (clk_49, reset)
-              BEGIN
+              BEGIN  -- PROCESS
-                IF clk_49'EVENT AND clk_49 = '1' THEN
+                IF reset = '0' THEN                 -- asynchronous reset (active low)
-                  clk_24 <= NOT clk_24;
+                  clk_24 <= '0';
+                ELSIF clk_49'event AND clk_49 = '1' THEN  -- rising clock edge
+                  clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
-              PROCESS (clk_25, reset)
+              PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+                IF rstn_25 = '0' THEN                 -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                 END IF;
               END PROCESS;
-              PROCESS (clk_24, reset)
+              PROCESS (clk_24, rstn_25)
               BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+                IF rstn_25 = '0' THEN                 -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s ;
                   ADDRESS_SIZE    => 20)
                 PORT MAP (
                   clk       => clk_25,
-                  reset     => reset,
+                  reset     => rstn_25,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                 PORT MAP (
                   clk25MHz     => clk_25,
                   clk24_576MHz => clk_24,           -- 49.152MHz/2
-                  resetn       => reset,
+                  resetn       => rstn_25,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
-                PORT MAP(reset, clk_25, spw_rxclk(0),
+                PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
             -------------------------------------------------------------------------------
-              LFR_rstn <= LFR_soft_rstn AND reset;
+              --LFR_rstn <= LFR_soft_rstn AND rstn_25;
+              LFR_rstn <= rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"000121")  -- aa.bb.cc version
+                  top_lfr_version        => X"000122")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
-                  cnv_rstn   => reset,
+                  cnv_rstn   => rstn_25,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
-                  rstn       => reset,
+                  rstn       => rstn_25,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
-                PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
+                PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
-              PROCESS (clk_25, reset)
+              PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
-                IF reset = '0' THEN                  -- asynchronous reset (active low)
+                IF rstn_25 = '0' THEN                  -- asynchronous reset (active low)
                   IO0  <= '0';
                   IO1  <= '0';
                   IO2  <= '0';

designs/MINI-LFR_WFP_MS/Makefile +2 -1

             	APB_SIMPLE_DIODE.vhd \
             	Top_MatrixSpec.vhd \
             	APB_FFT.vhd \
-            	CoreFFT_simu.vhd
+            	CoreFFT_simu.vhd \
+            	lpp_lfr_apbreg_simu.vhd
             include $(GRLIB)/bin/Makefile
             include $(GRLIB)/software/leon3/Makefile

designs/MINI-LFR_WFP_MS/testbench.vhd +13 -1

               ADC_SDO      <= x"AA";
               SRAM_DQ      <= (OTHERS => 'Z');
+              IO0          <= 'Z';
+              IO1          <= 'Z';
+              IO2          <= 'Z';
+              IO3          <= 'Z';
+              IO4          <= 'Z';
+              IO5          <= 'Z';
+              IO6          <= 'Z';
+              IO7          <= 'Z';
+              IO8          <= 'Z';
+              IO9          <= 'Z';
+              IO10         <= 'Z';
+              IO11         <= 'Z';
               -----------------------------------------------------------------------------
               -- DUT
                   SRAM_nWE     => SRAM_nWE,
                   SRAM_CE      => SRAM_CE,
-                  SRAM_nOE     => SRAM_nOE,ddr_buffer_f
+                  SRAM_nOE     => SRAM_nOE,
                   SRAM_nBE     => SRAM_nBE,
                   SRAM_A       => SRAM_A,
                   SRAM_DQ      => SRAM_DQ);

lib/lpp/lpp_top_lfr/lpp_lfr.vhd 0 -58

@@ -26,7 +26,6 ENTITY lpp_lfr IS
26	GENERIC (	26	GENERIC (
27	Mem_use : INTEGER := use_RAM;	27	Mem_use : INTEGER := use_RAM;
28	nb_data_by_buffer_size : INTEGER := 11;	28	nb_data_by_buffer_size : INTEGER := 11;
29	-- nb_word_by_buffer_size : INTEGER := 11; -- TODO
30	nb_snapshot_param_size : INTEGER := 11;	29	nb_snapshot_param_size : INTEGER := 11;
31	delta_vector_size : INTEGER := 20;	30	delta_vector_size : INTEGER := 20;
32	delta_vector_size_f0_2 : INTEGER := 7;	31	delta_vector_size_f0_2 : INTEGER := 7;
@@ -60,57 +59,10 ENTITY lpp_lfr IS
60	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo	59	fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61	--	60	--
62	data_shaping_BW : OUT STD_LOGIC	61	data_shaping_BW : OUT STD_LOGIC
63	--
64	--
65	-- observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66	-- observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
68	-- observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
69
70	--debug
71	--debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72	--debug_f0_data_valid : OUT STD_LOGIC;
73	--debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74	--debug_f1_data_valid : OUT STD_LOGIC;
75	--debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
76	--debug_f2_data_valid : OUT STD_LOGIC;
77	--debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
78	--debug_f3_data_valid : OUT STD_LOGIC;
79
80	---- debug FIFO_IN
81	--debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82	--debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
83	--debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84	--debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
85	--debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86	--debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
87	--debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88	--debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
89
90	----debug FIFO OUT
91	--debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92	--debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
93	--debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94	--debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
95	--debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96	--debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
97	--debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98	--debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
99
100	----debug DMA IN
101	--debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102	--debug_f0_data_dma_in_valid : OUT STD_LOGIC;
103	--debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104	--debug_f1_data_dma_in_valid : OUT STD_LOGIC;
105	--debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106	--debug_f2_data_dma_in_valid : OUT STD_LOGIC;
107	--debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108	--debug_f3_data_dma_in_valid : OUT STD_LOGIC
109	);	62	);
110	END lpp_lfr;	63	END lpp_lfr;
111		64
112	ARCHITECTURE beh OF lpp_lfr IS	65	ARCHITECTURE beh OF lpp_lfr IS
113	--SIGNAL sample : Samples14v(7 DOWNTO 0);
114	SIGNAL sample_s : Samples(7 DOWNTO 0);	66	SIGNAL sample_s : Samples(7 DOWNTO 0);
115	--	67	--
116	SIGNAL data_shaping_SP0 : STD_LOGIC;	68	SIGNAL data_shaping_SP0 : STD_LOGIC;
@@ -142,17 +94,10 ARCHITECTURE beh OF lpp_lfr IS
142	SIGNAL ready_matrix_f0_1 : STD_LOGIC;	94	SIGNAL ready_matrix_f0_1 : STD_LOGIC;
143	SIGNAL ready_matrix_f1 : STD_LOGIC;	95	SIGNAL ready_matrix_f1 : STD_LOGIC;
144	SIGNAL ready_matrix_f2 : STD_LOGIC;	96	SIGNAL ready_matrix_f2 : STD_LOGIC;
145	-- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
146	-- SIGNAL error_bad_component_error : STD_LOGIC;
147	-- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
148	SIGNAL status_ready_matrix_f0 : STD_LOGIC;	97	SIGNAL status_ready_matrix_f0 : STD_LOGIC;
149	SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;	98	SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
150	SIGNAL status_ready_matrix_f1 : STD_LOGIC;	99	SIGNAL status_ready_matrix_f1 : STD_LOGIC;
151	SIGNAL status_ready_matrix_f2 : STD_LOGIC;	100	SIGNAL status_ready_matrix_f2 : STD_LOGIC;
152	-- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
153	-- SIGNAL status_error_bad_component_error : STD_LOGIC;
154	--SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
155	-- SIGNAL config_active_interruption_onError : STD_LOGIC;
156	SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);	101	SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157	SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);	102	SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158	SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);	103	SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
@@ -161,9 +106,6 ARCHITECTURE beh OF lpp_lfr IS
161	SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);	106	SIGNAL length_matrix_f2 : STD_LOGIC_VECTOR(25 DOWNTO 0);
162		107
163	-- WFP	108	-- WFP
164	--SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165	--SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
166	--SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167	SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);	109	SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168	SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	110	SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169	SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);	111	SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);

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