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Modif demux + Partage pour recherche de bug
martin -
r157:afd41c98ea9b martin
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@@ -22,9 +22,10
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 use work.fft_components.all;
26 use lpp.lpp_fft.all;
26 use lpp.lpp_fft.all;
27 use work.fft_components.all;
27
28 -- Update possible lecture (ren) de fifo en continu, pendant un Load, au lieu d'une lecture "cr�neau"
28
29
29 entity FFT is
30 entity FFT is
30 generic(
31 generic(
@@ -36,6 +37,7 entity FFT is
36 FifoIN_Empty : in std_logic_vector(4 downto 0);
37 FifoIN_Empty : in std_logic_vector(4 downto 0);
37 FifoIN_Data : in std_logic_vector(79 downto 0);
38 FifoIN_Data : in std_logic_vector(79 downto 0);
38 FifoOUT_Full : in std_logic_vector(4 downto 0);
39 FifoOUT_Full : in std_logic_vector(4 downto 0);
40 Load : out std_logic;
39 Read : out std_logic_vector(4 downto 0);
41 Read : out std_logic_vector(4 downto 0);
40 Write : out std_logic_vector(4 downto 0);
42 Write : out std_logic_vector(4 downto 0);
41 ReUse : out std_logic_vector(4 downto 0);
43 ReUse : out std_logic_vector(4 downto 0);
@@ -62,6 +64,7 signal Link_Read : std_logic;
62 begin
64 begin
63
65
64 Start <= '0';
66 Start <= '0';
67 Load <= FFT_Load;
65
68
66 DRIVE : Driver_FFT
69 DRIVE : Driver_FFT
67 generic map(Data_sz,NbData)
70 generic map(Data_sz,NbData)
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@@ -84,6 +84,7 component FFT is
84 FifoIN_Empty : in std_logic_vector(4 downto 0);
84 FifoIN_Empty : in std_logic_vector(4 downto 0);
85 FifoIN_Data : in std_logic_vector(79 downto 0);
85 FifoIN_Data : in std_logic_vector(79 downto 0);
86 FifoOUT_Full : in std_logic_vector(4 downto 0);
86 FifoOUT_Full : in std_logic_vector(4 downto 0);
87 Load : out std_logic;
87 Read : out std_logic_vector(4 downto 0);
88 Read : out std_logic_vector(4 downto 0);
88 Write : out std_logic_vector(4 downto 0);
89 Write : out std_logic_vector(4 downto 0);
89 ReUse : out std_logic_vector(4 downto 0);
90 ReUse : out std_logic_vector(4 downto 0);
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@@ -98,14 +98,14 entity leon3mp is
98 UART_RXD : in std_logic;
98 UART_RXD : in std_logic;
99 UART_TXD : out std_logic;
99 UART_TXD : out std_logic;
100 -- ACQ
100 -- ACQ
101 Clk_49Mhz : IN STD_LOGIC;
102 CNV_CH1 : OUT STD_LOGIC;
101 CNV_CH1 : OUT STD_LOGIC;
103 SCK_CH1 : OUT STD_LOGIC;
102 SCK_CH1 : OUT STD_LOGIC;
104 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
103 SDO_CH1 : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
104 Bias_Fails : out std_logic;
105 -- ADC
105 -- ADC
106 -- ADC_in : in AD7688_in(4 downto 0);
106 -- ADC_in : in AD7688_in(4 downto 0);
107 -- ADC_out : out AD7688_out;
107 -- ADC_out : out AD7688_out;
108 -- Bias_Fails : out std_logic;
108
109 -- CNA
109 -- CNA
110 -- DAC_SYNC : out std_logic;
110 -- DAC_SYNC : out std_logic;
111 -- DAC_SCLK : out std_logic;
111 -- DAC_SCLK : out std_logic;
@@ -177,25 +177,17 signal dsuo : dsu_out_type;
177 --- AJOUT TEST ------------------------Signaux----------------------
177 --- AJOUT TEST ------------------------Signaux----------------------
178 ---------------------------------------------------------------------
178 ---------------------------------------------------------------------
179 -- FIFOs
179 -- FIFOs
180 signal FifoF0a_Full : std_logic_vector(4 downto 0);
180 signal FifoF0_Empty : std_logic_vector(4 downto 0);
181 signal FifoF0a_Empty : std_logic_vector(4 downto 0);
181 signal FifoF0_Data : std_logic_vector(79 downto 0);
182 signal FifoF0a_Data : std_logic_vector(79 downto 0);
183 signal FifoF0b_Full : std_logic_vector(4 downto 0);
184 signal FifoF0b_Empty : std_logic_vector(4 downto 0);
185 signal FifoF0b_Data : std_logic_vector(79 downto 0);
186 signal FifoF1_Full : std_logic_vector(4 downto 0);
187 signal FifoF1_Empty : std_logic_vector(4 downto 0);
182 signal FifoF1_Empty : std_logic_vector(4 downto 0);
188 signal FifoF1_Data : std_logic_vector(79 downto 0);
183 signal FifoF1_Data : std_logic_vector(79 downto 0);
189 signal FifoF3_Full : std_logic_vector(4 downto 0);
190 signal FifoF3_Empty : std_logic_vector(4 downto 0);
184 signal FifoF3_Empty : std_logic_vector(4 downto 0);
191 signal FifoF3_Data : std_logic_vector(79 downto 0);
185 signal FifoF3_Data : std_logic_vector(79 downto 0);
192
186
193 signal FifoINT_Full : std_logic_vector(4 downto 0);
187 signal FifoINT_Full : std_logic_vector(4 downto 0);
194 signal FifoINT_Data : std_logic_vector(79 downto 0);
188 signal FifoINT_Data : std_logic_vector(79 downto 0);
195
189
196 --signal FifoOUT_FullV : std_logic;
197 signal FifoOUT_Full : std_logic_vector(1 downto 0);
190 signal FifoOUT_Full : std_logic_vector(1 downto 0);
198 --signal Matrix_WriteV : std_logic_vector(0 downto 0);
199
191
200 -- MATRICE SPECTRALE
192 -- MATRICE SPECTRALE
201 signal SM_FlagError : std_logic;
193 signal SM_FlagError : std_logic;
@@ -207,19 +199,23 signal SM_Data : std_logic_vector(6
207 signal Dma_acq : std_logic;
199 signal Dma_acq : std_logic;
208
200
209 -- FFT
201 -- FFT
202 signal FFT_Load : std_logic;
210 signal FFT_Read : std_logic_vector(4 downto 0);
203 signal FFT_Read : std_logic_vector(4 downto 0);
211 signal FFT_Write : std_logic_vector(4 downto 0);
204 signal FFT_Write : std_logic_vector(4 downto 0);
212 signal FFT_ReUse : std_logic_vector(4 downto 0);
205 signal FFT_ReUse : std_logic_vector(4 downto 0);
213 signal FFT_Data : std_logic_vector(79 downto 0);
206 signal FFT_Data : std_logic_vector(79 downto 0);
214
207
215 -- DEMUX
208 -- DEMUX
216 signal DEMU_Read : std_logic_vector(19 downto 0);
209 signal DEMU_Read : std_logic_vector(14 downto 0);
217 signal DEMU_Empty : std_logic_vector(4 downto 0);
210 signal DEMU_Empty : std_logic_vector(4 downto 0);
218 signal DEMU_Data : std_logic_vector(79 downto 0);
211 signal DEMU_Data : std_logic_vector(79 downto 0);
219
212
220 -- ACQ
213 -- ACQ
221 signal TopACQ_WenF0a : STD_LOGIC_VECTOR(4 DOWNTO 0);
214
222 signal TopACQ_WenF0b : STD_LOGIC_VECTOR(4 DOWNTO 0);
215 signal sample_val : STD_LOGIC;
216 signal sample : Samples(8-1 DOWNTO 0);
217
218 signal TopACQ_WenF0 : STD_LOGIC_VECTOR(4 DOWNTO 0);
223 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
219 signal TopACQ_DataF0 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
224 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
220 signal TopACQ_WenF1 : STD_LOGIC_VECTOR(4 DOWNTO 0);
225 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
221 signal TopACQ_DataF1 : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
@@ -311,7 +307,7 led(1 downto 0) <= gpio(1 downto 0);
311 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
307 -- port map (clkm,rstn,SmplClk,ADC_DataReady,Fuller,WG_ReUse,WG_Write);
312 --
308 --
313 --enableADC <= gpio(0);
309 --enableADC <= gpio(0);
314 --Bias_Fails <= '0';
310
315 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
311 --WG_DATA <= ADC_SmplOut(4) & ADC_SmplOut(3) & ADC_SmplOut(2) & ADC_SmplOut(1) & ADC_SmplOut(0);
316 --
312 --
317 --
313 --
@@ -319,32 +315,68 led(1 downto 0) <= gpio(1 downto 0);
319 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
315 -- generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
320 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
316 -- port map (clkm,rstn,clkm,clkm,WG_ReUse,(others => '1'),WG_Write,open,Fuller,open,WG_DATA,open,open,apbi,apbo(6));
321
317
322 TopACQ : lpp_top_acq
318 DIGITAL_acquisition : ADS7886_drvr
323 port map('1',CNV_CH1,SCK_CH1,SDO_CH1,Clk_49Mhz,rstn,clkm,rstn,TopACQ_WenF0a,TopACQ_WenF0b,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
319 GENERIC MAP (
320 ChanelCount => 8,
321 ncycle_cnv_high => 79,
322 ncycle_cnv => 500)
323 PORT MAP (
324 cnv_clk => clk50MHz, --
325 cnv_rstn => rstn, --
326 cnv_run => '1', --
327 cnv => CNV_CH1, --
328 clk => clkm, --
329 rstn => rstn, --
330 sck => SCK_CH1, --
331 sdo => SDO_CH1, --
332 sample => sample,
333 sample_val => sample_val);
334 --
335 TopACQ_WenF0 <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
336 TopACQ_DataF0 <= sample(4) & sample(3) & sample(2) & sample(1) & sample(0);
337 --
338 TEST(0) <= TopACQ_WenF0(1);
339 TEST(1) <= SDO_CH1(1);
340 --
341 --
342 --
343 --process(clkm,rstn)
344 --begin
345 -- if(rstn='0')then
346 -- TopACQ_WenF0a <= (others => '1');
347 --
348 -- elsif(clkm'event and clkm='1')then
349 -- TopACQ_WenF0a <= not sample_val & not sample_val & not sample_val & not sample_val & not sample_val;
350 --
351 -- end if;
352 --end process;
324
353
354 -- TopACQ : lpp_top_acq
355 -- port map('1',CNV_CH1,SCK_CH1,SDO_CH1,clk50MHz,rstn,clkm,rstn,TopACQ_WenF0,TopACQ_DataF0,TopACQ_WenF1,TopACQ_DataF1,open,open,TopACQ_WenF3,TopACQ_DataF3);
356
357 Bias_Fails <= '0';
325 --- FIFO IN -------------------------------------------------------------
358 --- FIFO IN -------------------------------------------------------------
326
359
327 Memf0a : lppFIFOxN
360 MemOut : APB_FIFO
328 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
361 generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 9, Enable_ReUse => '0', R => 1, W => 0)
329 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0a,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0a_Data,FifoF0a_Full,FifoF0a_Empty);
362 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),TopACQ_WenF0,FifoF0_Empty,open,open,TopACQ_DataF0,open,open,apbi,apbo(9));
363 -- Memf0 : lppFIFOxN
364 -- generic map(Data_sz => 16, Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
365 -- port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0,DEMU_Read(4 downto 0),TopACQ_DataF0,FifoF0_Data,open,FifoF0_Empty);
330
366
331 Memf0b : lppFIFOxN
332 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
333 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF0b,DEMU_Read(9 downto 5),TopACQ_DataF0,FifoF0b_Data,FifoF0b_Full,FifoF0b_Empty);
334
335 Memf1 : lppFIFOxN
367 Memf1 : lppFIFOxN
336 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
368 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
337 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(14 downto 10),TopACQ_DataF1,FifoF1_Data,FifoF1_Full,FifoF1_Empty);
369 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF1,DEMU_Read(9 downto 5),TopACQ_DataF1,FifoF1_Data,open,FifoF1_Empty);
338
370
339 Memf3 : lppFIFOxN
371 Memf3 : lppFIFOxN
340 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '0')
372 generic map(Data_sz => 16, Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
341 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(19 downto 15),TopACQ_DataF3,FifoF3_Data,FifoF3_Full,FifoF3_Empty);
373 port map(rstn,clkm,clkm,(others => '0'),TopACQ_WenF3,DEMU_Read(14 downto 10),TopACQ_DataF3,FifoF3_Data,open,FifoF3_Empty);
342
374
343 --- DEMUX -------------------------------------------------------------
375 --- DEMUX -------------------------------------------------------------
344
376
345 DEMUX0 : Demultiplex
377 DEMU0 : DEMUX
346 generic map(Data_sz => 16)
378 generic map(Data_sz => 16)
347 port map(clkm,rstn,FFT_Read,FifoF0a_Empty,FifoF0b_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0a_Data,FifoF0b_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
379 port map(clkm,rstn,FFT_Read,FFT_Load,FifoF0_Empty,FifoF1_Empty,FifoF3_Empty,FifoF0_Data,FifoF1_Data,FifoF3_Data,DEMU_Read,DEMU_Empty,DEMU_Data);
348
380
349 --- FFT -------------------------------------------------------------
381 --- FFT -------------------------------------------------------------
350
382
@@ -354,18 +386,18 led(1 downto 0) <= gpio(1 downto 0);
354
386
355 FFT0 : FFT
387 FFT0 : FFT
356 generic map(Data_sz => 16,NbData => 256)
388 generic map(Data_sz => 16,NbData => 256)
357 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
389 port map(clkm,rstn,DEMU_Empty,DEMU_Data,FifoINT_Full,FFT_Load,FFT_Read,FFT_Write,FFT_ReUse,FFT_Data);
358
390
359 ----- LINK MEMORY -------------------------------------------------------
391 ----- LINK MEMORY -------------------------------------------------------
360
392
361 -- MemOut : APB_FIFO
393 -- MemOut : APB_FIFO
362 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
394 -- generic map (pindex => 9, paddr => 9, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 0)
363 -- port map (clkm,rstn,clkm,clkm,Link_ReUse,(others =>'1'),Link_Write,Ept,FifoOUT_Full,open,Link_Data,open,open,apbi,apbo(9));
395 -- port map (clkm,rstn,clkm,clkm,FFT_ReUse,(others =>'1'),FFT_Write,open,FifoINT_Full,open,FFT_Data,open,open,apbi,apbo(9));
364
396
365 MemInt : lppFIFOxN
397 MemInt : lppFIFOxN
366 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
398 generic map(Data_sz => 16, FifoCnt => 5, Enable_ReUse => '1')
367 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
399 port map(rstn,clkm,clkm,FFT_ReUse,FFT_Write,SM_Read,FFT_Data,FifoINT_Data,FifoINT_Full,open);
368
400 --
369 -- MemIn : APB_FIFO
401 -- MemIn : APB_FIFO
370 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
402 -- generic map (pindex => 8, paddr => 8, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 0, W => 1)
371 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
403 -- port map (clkm,rstn,clkm,clkm,(others => '0'),TopSM_Read,(others => '1'),open,FifoINT_Full,FifoINT_Data,(others => '0'),open,open,apbi,apbo(8));
@@ -378,9 +410,9 led(1 downto 0) <= gpio(1 downto 0);
378
410
379 Dma_acq <= '1';
411 Dma_acq <= '1';
380
412
381 MemOut : APB_FIFO
413 -- MemOut : APB_FIFO
382 generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
414 -- generic map (pindex => 9, paddr => 9, FifoCnt => 2, Data_sz => 32, Addr_sz => 8, Enable_ReUse => '0', R => 1, W => 0)
383 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
415 -- port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),SM_Write,open,FifoOUT_Full,open,SM_Data,open,open,apbi,apbo(9));
384
416
385 ----- FIFO -------------------------------------------------------------
417 ----- FIFO -------------------------------------------------------------
386
418
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@@ -31,19 +31,17 port(
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 Read : in std_logic_vector(4 downto 0);
33 Read : in std_logic_vector(4 downto 0);
34 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
34 Load : in std_logic;
35
35
36 EmptyF0a : in std_logic_vector(4 downto 0);
36 EmptyF0 : in std_logic_vector(4 downto 0);
37 EmptyF0b : in std_logic_vector(4 downto 0);
38 EmptyF1 : in std_logic_vector(4 downto 0);
37 EmptyF1 : in std_logic_vector(4 downto 0);
39 EmptyF2 : in std_logic_vector(4 downto 0);
38 EmptyF2 : in std_logic_vector(4 downto 0);
40
39
41 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
40 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
43 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
41 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
44 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
42 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
45
43
46 Read_DEMUX : out std_logic_vector(19 downto 0);
44 Read_DEMUX : out std_logic_vector(14 downto 0);
47 Empty : out std_logic_vector(4 downto 0);
45 Empty : out std_logic_vector(4 downto 0);
48 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
46 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
49 );
47 );
@@ -55,9 +53,8 architecture ar_DEMUX of DEMUX is
55 type etat is (eX,e0,e1,e2,e3);
53 type etat is (eX,e0,e1,e2,e3);
56 signal ect : etat;
54 signal ect : etat;
57
55
58 signal pong : std_logic;
59
56
60 signal DataCpt_reg : std_logic_vector(3 downto 0);
57 signal load_reg : std_logic;
61 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
58 constant Dummy_Read : std_logic_vector(4 downto 0) := (others => '1');
62
59
63 signal Countf0 : integer;
60 signal Countf0 : integer;
@@ -68,61 +65,40 begin
68 begin
65 begin
69 if(rstn='0')then
66 if(rstn='0')then
70 ect <= e0;
67 ect <= e0;
71 pong <= '0';
68 load_reg <= '0';
72 Countf0 <= 1;
69 Countf0 <= 5;
73 Countf1 <= 0;
70 Countf1 <= 0;
74
71
75 elsif(clk'event and clk='1')then
72 elsif(clk'event and clk='1')then
76 DataCpt_reg <= DataCpt;
73 load_reg <= Load;
77
74
78 case ect is
75 case ect is
79
76
80 when e0 =>
77 when e0 =>
81 if(DataCpt_reg(0) = '1' and DataCpt(0) = '0')then
78 if(load_reg = '1' and Load = '0')then
82 pong <= not pong;
79 if(Countf0 = 24)then
83 if(Countf0 = 5)then
84 Countf0 <= 0;
80 Countf0 <= 0;
85 ect <= e2;
81 ect <= e1;
86 else
82 else
87 Countf0 <= Countf0 + 1;
83 Countf0 <= Countf0 + 1;
88 ect <= e1;
84 ect <= e0;
89 end if;
85 end if;
90 end if;
86 end if;
91
87
92 when e1 =>
88 when e1 =>
93 if(DataCpt_reg(1) = '1' and DataCpt(1) = '0')then
89 if(load_reg = '1' and Load = '0')then
94 pong <= not pong;
90 if(Countf1 = 74)then
95 if(Countf0 = 5)then
91 Countf1 <= 0;
96 Countf0 <= 0;
97 ect <= e2;
92 ect <= e2;
98 else
93 else
99 Countf0 <= Countf0 + 1;
94 Countf1 <= Countf1 + 1;
100 ect <= e0;
95 ect <= e0;
101 end if;
96 end if;
102 end if;
97 end if;
103
98
104 when e2 =>
99 when e2 =>
105 if(DataCpt_reg(2) = '1' and DataCpt(2) = '0')then
100 if(load_reg = '1' and Load = '0')then
106 if(Countf1 = 15)then
101 ect <= e0;
107 Countf1 <= 0;
108 ect <= e3;
109 else
110 Countf1 <= Countf1 + 1;
111 if(pong = '0')then
112 ect <= e0;
113 else
114 ect <= e1;
115 end if;
116 end if;
117 end if;
118
119 when e3 =>
120 if(DataCpt_reg(3) = '1' and DataCpt(3) = '0')then
121 if(pong = '0')then
122 ect <= e0;
123 else
124 ect <= e1;
125 end if;
126 end if;
102 end if;
127
103
128 when others =>
104 when others =>
@@ -133,29 +109,23 begin
133 end process;
109 end process;
134
110
135 with ect select
111 with ect select
136 Empty <= EmptyF0a when e0,
112 Empty <= EmptyF0 when e0,
137 EmptyF0b when e1,
113 EmptyF1 when e1,
138 EmptyF1 when e2,
114 EmptyF2 when e2,
139 EmptyF2 when e3,
140 (others => '1') when others;
115 (others => '1') when others;
141
116
142 with ect select
117 with ect select
143 Data <= DataF0a when e0,
118 Data <= DataF0 when e0,
144 DataF0b when e1,
119 DataF1 when e1,
145 DataF1 when e2,
120 DataF2 when e2,
146 DataF2 when e3,
147 (others => '0') when others;
121 (others => '0') when others;
148
122
149 with ect select
123 with ect select
150 Read_DEMUX <= Dummy_Read & Dummy_Read & Dummy_Read & Read when e0,
124 Read_DEMUX <= Dummy_Read & Dummy_Read & Read when e0,
151 Dummy_Read & Dummy_Read & Read & Dummy_Read when e1,
125 Dummy_Read & Read & Dummy_Read when e1,
152 Dummy_Read & Read & Dummy_Read & Dummy_Read when e2,
126 Read & Dummy_Read & Dummy_Read when e2,
153 Read & Dummy_Read & Dummy_Read & Dummy_Read when e3,
154 (others => '1') when others;
127 (others => '1') when others;
155
128
156
157
158
159 end architecture;
129 end architecture;
160
130
161
131
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@@ -29,34 +29,7 use lpp.lpp_amba.all;
29
29
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
30 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
31
31
32 package lpp_demux is
32 package lpp_demux is
33
34
35 component Demultiplex is
36 generic(
37 Data_sz : integer range 1 to 32 := 16);
38 port(
39 clk : in std_logic;
40 rstn : in std_logic;
41
42 Read : in std_logic_vector(4 downto 0);
43
44 EmptyF0a : in std_logic_vector(4 downto 0);
45 EmptyF0b : in std_logic_vector(4 downto 0);
46 EmptyF1 : in std_logic_vector(4 downto 0);
47 EmptyF2 : in std_logic_vector(4 downto 0);
48
49 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
51 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
52 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
53
54 Read_DEMUX : out std_logic_vector(19 downto 0);
55 Empty : out std_logic_vector(4 downto 0);
56 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
57 );
58 end component;
59
60
33
61 component DEMUX is
34 component DEMUX is
62 generic(
35 generic(
@@ -66,38 +39,20 port(
66 rstn : in std_logic;
39 rstn : in std_logic;
67
40
68 Read : in std_logic_vector(4 downto 0);
41 Read : in std_logic_vector(4 downto 0);
69 DataCpt : in std_logic_vector(3 downto 0); -- f2 f1 f0b f0a
42 Load : in std_logic;
70
43
71 EmptyF0a : in std_logic_vector(4 downto 0);
44 EmptyF0 : in std_logic_vector(4 downto 0);
72 EmptyF0b : in std_logic_vector(4 downto 0);
73 EmptyF1 : in std_logic_vector(4 downto 0);
45 EmptyF1 : in std_logic_vector(4 downto 0);
74 EmptyF2 : in std_logic_vector(4 downto 0);
46 EmptyF2 : in std_logic_vector(4 downto 0);
75
47
76 DataF0a : in std_logic_vector((5*Data_sz)-1 downto 0);
48 DataF0 : in std_logic_vector((5*Data_sz)-1 downto 0);
77 DataF0b : in std_logic_vector((5*Data_sz)-1 downto 0);
78 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
49 DataF1 : in std_logic_vector((5*Data_sz)-1 downto 0);
79 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
50 DataF2 : in std_logic_vector((5*Data_sz)-1 downto 0);
80
51
81 Read_DEMUX : out std_logic_vector(19 downto 0);
52 Read_DEMUX : out std_logic_vector(14 downto 0);
82 Empty : out std_logic_vector(4 downto 0);
53 Empty : out std_logic_vector(4 downto 0);
83 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
54 Data : out std_logic_vector((5*Data_sz)-1 downto 0)
84 );
55 );
85 end component;
56 end component;
86
57
87
88 component WatchFlag is
89 port(
90 clk : in std_logic;
91 rstn : in std_logic;
92
93 EmptyF0a : in std_logic_vector(4 downto 0);
94 EmptyF0b : in std_logic_vector(4 downto 0);
95 EmptyF1 : in std_logic_vector(4 downto 0);
96 EmptyF2 : in std_logic_vector(4 downto 0);
97
98 DataCpt : out std_logic_vector(3 downto 0) -- f2 f1 f0b f0a
99 );
100 end component;
101
102
103 end; No newline at end of file
58 end;
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@@ -31,6 +31,7 entity lppFIFOxN is
31 generic(
31 generic(
32 tech : integer := 0;
32 tech : integer := 0;
33 Data_sz : integer range 1 to 32 := 8;
33 Data_sz : integer range 1 to 32 := 8;
34 Addr_sz : integer range 1 to 32 := 8;
34 FifoCnt : integer := 1;
35 FifoCnt : integer := 1;
35 Enable_ReUse : std_logic := '0'
36 Enable_ReUse : std_logic := '0'
36 );
37 );
@@ -55,32 +56,9 begin
55
56
56 fifos: for i in 0 to FifoCnt-1 generate
57 fifos: for i in 0 to FifoCnt-1 generate
57 FIFO0 : lpp_fifo
58 FIFO0 : lpp_fifo
58 generic map (tech,Enable_ReUse,Data_sz,8)
59 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
59 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
60 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
60 end generate;
61 end generate;
61
62
62
63
64 -- fifoB1 : entity work.lpp_fifo
65 -- generic map (tech,Enable_ReUse,Data_sz,8)
66 -- port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
67 --
68 -- fifoB2 : entity work.lpp_fifo
69 -- generic map (tech,Enable_ReUse,Data_sz,8)
70 -- port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
71 --
72 -- fifoB3 : entity work.lpp_fifo
73 -- generic map (tech,Enable_ReUse,Data_sz,8)
74 -- port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
75 --
76 -- fifoE1 : entity work.lpp_fifo
77 -- generic map (tech,Enable_ReUse,Data_sz,8)
78 -- port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
79 --
80 -- fifoE2 : entity work.lpp_fifo
81 -- generic map (tech,Enable_ReUse,Data_sz,8)
82 -- port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
83
84
85 end architecture;
63 end architecture;
86
64
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@@ -99,6 +99,7 component lppFIFOxN is
99 generic(
99 generic(
100 tech : integer := 0;
100 tech : integer := 0;
101 Data_sz : integer range 1 to 32 := 8;
101 Data_sz : integer range 1 to 32 := 8;
102 Addr_sz : integer range 1 to 32 := 8;
102 FifoCnt : integer := 1;
103 FifoCnt : integer := 1;
103 Enable_ReUse : std_logic := '0'
104 Enable_ReUse : std_logic := '0'
104 );
105 );
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@@ -26,8 +26,7 ENTITY lpp_top_acq IS
26 clk : IN STD_LOGIC; -- 25 MHz
26 clk : IN STD_LOGIC; -- 25 MHz
27 rstn : IN STD_LOGIC;
27 rstn : IN STD_LOGIC;
28 --
28 --
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
30 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
31 --
33 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
@@ -86,11 +85,7 ARCHITECTURE tb OF lpp_top_acq IS
86 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
85 SIGNAL sample_downsampling_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
87 --
86 --
88 SIGNAL sample_f0_val : STD_LOGIC;
87 SIGNAL sample_f0_val : STD_LOGIC;
89 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
88 SIGNAL sample_f0 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
90 --
91 SIGNAL sample_f0_0_val : STD_LOGIC;
92 SIGNAL sample_f0_1_val : STD_LOGIC;
93 SIGNAL counter_f0 : INTEGER;
94 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
95 SIGNAL sample_f1_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
96 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
91 SIGNAL sample_f1 : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -207,35 +202,11 BEGIN
207 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
202 sample_f0_wdata(16*4+I) <= sample_f0(7, I);
208 END GENERATE all_bit_sample_f0;
203 END GENERATE all_bit_sample_f0;
209
204
210 PROCESS (clk, rstn)
205 sample_f0_wen <= NOT(sample_f0_val) &
211 BEGIN -- PROCESS
206 NOT(sample_f0_val) &
212 IF rstn = '0' THEN -- asynchronous reset (active low)
207 NOT(sample_f0_val) &
213 counter_f0 <= 0;
208 NOT(sample_f0_val) &
214 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
209 NOT(sample_f0_val);
215 IF sample_f0_val = '1' THEN
216 IF counter_f0 = 511 THEN
217 counter_f0 <= 0;
218 ELSE
219 counter_f0 <= counter_f0 + 1;
220 END IF;
221 END IF;
222 END IF;
223 END PROCESS;
224
225 sample_f0_0_val <= sample_f0_val WHEN counter_f0 < 256 ELSE '0';
226 sample_f0_0_wen <= NOT(sample_f0_0_val) &
227 NOT(sample_f0_0_val) &
228 NOT(sample_f0_0_val) &
229 NOT(sample_f0_0_val) &
230 NOT(sample_f0_0_val);
231
232 sample_f0_1_val <= sample_f0_val WHEN counter_f0 > 255 ELSE '0';
233 sample_f0_1_wen <= NOT(sample_f0_1_val) &
234 NOT(sample_f0_1_val) &
235 NOT(sample_f0_1_val) &
236 NOT(sample_f0_1_val) &
237 NOT(sample_f0_1_val);
238
239
210
240 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
241 -- F1 -- @4096 Hz
212 -- F1 -- @4096 Hz
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@@ -15,26 +15,34 USE techmap.gencomp.ALL;
15 PACKAGE lpp_top_lfr_pkg IS
15 PACKAGE lpp_top_lfr_pkg IS
16
16
17 COMPONENT lpp_top_acq
17 COMPONENT lpp_top_acq
18 GENERIC (
18 GENERIC(
19 tech : integer);
19 tech : INTEGER := 0
20 PORT (
20 );
21 cnv_run : IN STD_LOGIC;
21 PORT (
22 cnv : OUT STD_LOGIC;
22 -- ADS7886
23 sck : OUT STD_LOGIC;
23 cnv_run : IN STD_LOGIC;
24 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
24 cnv : OUT STD_LOGIC;
25 cnv_clk : IN STD_LOGIC;
25 sck : OUT STD_LOGIC;
26 cnv_rstn : IN STD_LOGIC;
26 sdo : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
27 clk : IN STD_LOGIC;
27 --
28 rstn : IN STD_LOGIC;
28 cnv_clk : IN STD_LOGIC; -- 49 MHz
29 sample_f0_0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
29 cnv_rstn : IN STD_LOGIC;
30 sample_f0_1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
30 --
31 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 clk : IN STD_LOGIC; -- 25 MHz
32 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
32 rstn : IN STD_LOGIC;
33 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 --
34 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f0_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 sample_f0_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
36 --
37 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0));
37 sample_f1_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f1_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 --
40 sample_f2_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f2_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 --
43 sample_f3_wen : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 );
38 END COMPONENT;
46 END COMPONENT;
39
47
40 COMPONENT lpp_top_apbreg
48 COMPONENT lpp_top_apbreg
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