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pellion
- Fri, 19 Jul 2013 10:53:46
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boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc
boards/em-LeonLPP-A3PE3kL-v2/em-LeonLPP-A3PE3kL.pdc
+5
0
@@
-69,6
+69,11
set_io spw1_sin -pinname C6 -fixed yes -
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set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
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set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
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set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
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set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
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set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
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set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
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set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
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set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
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set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
0
lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
lib/lpp/lpp_top_lfr/lpp_top_lfr_pkg.vhd
+3
-2
@@
-263,7
+263,8
PACKAGE lpp_top_lfr_pkg IS
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PORT (
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cnv_clk : IN STD_LOGIC ;
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cnv_rstn : IN STD_LOGIC ;
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sample : IN Samples14v ( 7 DOWNTO 0 );
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sample_B : IN Samples14v ( 2 DOWNTO 0 );
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sample_E : IN Samples14v ( 4 DOWNTO 0 );
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sample_val : IN STD_LOGIC ;
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HCLK : IN STD_ULOGIC ;
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HRESETn : IN STD_ULOGIC ;
@@
-275,4
+276,4
PACKAGE lpp_top_lfr_pkg IS
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data_shaping_BW : OUT STD_LOGIC );
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END COMPONENT ;
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END lpp_top_lfr_pkg ;
No newline at end of file
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END lpp_top_lfr_pkg ;
0
lib/lpp/lpp_top_lfr/top_wf_picker.vhd
lib/lpp/lpp_top_lfr/top_wf_picker.vhd
+8
-2
@@
-38,7
+38,8
ENTITY top_wf_picker IS
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cnv_clk : IN STD_LOGIC ;
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cnv_rstn : IN STD_LOGIC ;
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--
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sample : IN Samples14v ( 7 DOWNTO 0 );
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sample_B : IN Samples14v ( 2 DOWNTO 0 );
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sample_E : IN Samples14v ( 4 DOWNTO 0 );
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sample_val : IN STD_LOGIC ;
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-- AMBA AHB system signals
@@
-121,10
+122,15
ARCHITECTURE tb OF top_wf_picker IS
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CONSTANT ncycle_cnv_high : INTEGER := 40 ;
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CONSTANT ncycle_cnv : INTEGER := 250 ;
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SIGNAL sample_s : Samples ( ChanelCount - 1 DOWNTO 0 );
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SIGNAL sample_s : Samples ( ChanelCount - 1 DOWNTO 0 );
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SIGNAL sample : Samples14v ( 7 DOWNTO 0 );
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BEGIN
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sample ( 4 DOWNTO 0 ) <= sample_E ( 4 DOWNTO 0 );
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sample ( 7 DOWNTO 5 ) <= sample_B ( 2 DOWNTO 0 );
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ready_matrix_f0_0 <= '0' ;
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ready_matrix_f0_1 <= '0' ;
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ready_matrix_f1 <= '0' ;
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