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HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

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pellion -
r196:ac9b8685732d JC
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@@ -69,6 +69,11 set_io spw1_sin -pinname C6 -fixed yes -
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
69 set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
70 set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
71
71
72 set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
73 set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
74 set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
75 set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
76
72 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
77 set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
73 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
78 set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
74 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
79 set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
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@@ -263,7 +263,8 PACKAGE lpp_top_lfr_pkg IS
263 PORT (
263 PORT (
264 cnv_clk : IN STD_LOGIC;
264 cnv_clk : IN STD_LOGIC;
265 cnv_rstn : IN STD_LOGIC;
265 cnv_rstn : IN STD_LOGIC;
266 sample : IN Samples14v(7 DOWNTO 0);
266 sample_B : IN Samples14v(2 DOWNTO 0);
267 sample_E : IN Samples14v(4 DOWNTO 0);
267 sample_val : IN STD_LOGIC;
268 sample_val : IN STD_LOGIC;
268 HCLK : IN STD_ULOGIC;
269 HCLK : IN STD_ULOGIC;
269 HRESETn : IN STD_ULOGIC;
270 HRESETn : IN STD_ULOGIC;
@@ -275,4 +276,4 PACKAGE lpp_top_lfr_pkg IS
275 data_shaping_BW : OUT STD_LOGIC);
276 data_shaping_BW : OUT STD_LOGIC);
276 END COMPONENT;
277 END COMPONENT;
277
278
278 END lpp_top_lfr_pkg; No newline at end of file
279 END lpp_top_lfr_pkg;
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@@ -38,7 +38,8 ENTITY top_wf_picker IS
38 cnv_clk : IN STD_LOGIC;
38 cnv_clk : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
39 cnv_rstn : IN STD_LOGIC;
40 --
40 --
41 sample : IN Samples14v(7 DOWNTO 0);
41 sample_B : IN Samples14v(2 DOWNTO 0);
42 sample_E : IN Samples14v(4 DOWNTO 0);
42 sample_val : IN STD_LOGIC;
43 sample_val : IN STD_LOGIC;
43
44
44 -- AMBA AHB system signals
45 -- AMBA AHB system signals
@@ -121,10 +122,15 ARCHITECTURE tb OF top_wf_picker IS
121 CONSTANT ncycle_cnv_high : INTEGER := 40;
122 CONSTANT ncycle_cnv_high : INTEGER := 40;
122 CONSTANT ncycle_cnv : INTEGER := 250;
123 CONSTANT ncycle_cnv : INTEGER := 250;
123
124
124 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
125 SIGNAL sample_s : Samples(ChanelCount-1 DOWNTO 0);
126 SIGNAL sample : Samples14v(7 DOWNTO 0);
125
127
126 BEGIN
128 BEGIN
127
129
130 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
131 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
132
133
128 ready_matrix_f0_0 <= '0';
134 ready_matrix_f0_0 <= '0';
129 ready_matrix_f0_1 <= '0';
135 ready_matrix_f0_1 <= '0';
130 ready_matrix_f1 <= '0';
136 ready_matrix_f1 <= '0';
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