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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19 FILE = apb_dac_Driver
20 LIB = liblpp_dac_Driver.a
21
22 include ../../rules.mk
23
24 all: $(FILE).a
25 @echo $(FILE)".a created"
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@@ -0,0 +1,68
1 #include "apb_dac_Driver.h"
2 #include "lpp_apb_functions.h"
3 #include <stdio.h>
4
5
6 DAC_Device* DacOpen(int count)
7 {
8 DAC_Device* dac0;
9 dac0 = (DAC_Device*) apbgetdevice(LPP_DAC_CTRLR,VENDOR_LPP,count);
10 dac0->configReg = DAC_enable;
11 return dac0;
12 }
13
14 /*
15 DAC_Device* DacClose(int count)
16 {
17 DAC_Device* dac1;
18 dac1 = (DAC_Device*) apbgetdevice(LPP_DAC_CTRLR,VENDOR_LPP,count);
19 dac1->configReg = DAC_disable;
20 return dac1;
21 }
22 */
23
24
25 int DacTable()
26 {
27 int i;
28 DAC_Device* dac2;
29 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
30 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
31 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
32 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
33 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
34 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
35 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
36 dac2 = (DAC_Device*)0x80000800;
37 dac2->configReg = DAC_enable;
38 dac2->dataReg = tablo[0];
39
40 while(1)
41 {
42 for (i = 0 ; i < 251 ; i++)
43 {
44 while(!((dac2->configReg & DAC_ready) == DAC_ready));
45 dac2->dataReg = tablo[i];
46 while((dac2->configReg & DAC_ready) == DAC_ready);
47 }
48 }
49 return 0;
50 }
51
52
53
54 int DacConst()
55 {
56 DAC_Device* dac3;
57 int Value = 0x1FFF;
58 dac3 = (DAC_Device*)0x80000800;
59 dac3->configReg = DAC_enable;
60 while(1)
61 {
62 printf("\nEntrer une valeur entre 4096 et 8191 : ");
63 scanf("%d",&Value);
64 dac3->dataReg = Value;
65 }
66 return 0;
67 }
68
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@@ -0,0 +1,35
1 #ifndef APB_CNA_DRIVER_H
2 #define APB_CNA_DRIVER_H
3
4 #define DAC_ready 3
5 #define DAC_enable 1
6 #define DAC_disable 0
7
8
9 /*===================================================
10 T Y P E S D E F
11 ====================================================*/
12
13 struct DAC_Driver
14 {
15 int configReg;
16 int dataReg;
17 };
18
19 typedef struct DAC_Driver DAC_Device;
20
21 /*===================================================
22 F U N C T I O N S
23 ====================================================*/
24
25 DAC_Device* DacOpen(int count);
26
27 //DAC_Device* DacClose(int count);
28
29 int DacTable();
30
31 int DacConst();
32
33
34
35 #endif
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@@ -0,0 +1,40
1 -- Systeme_Clock.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
7
8 entity Systeme_Clock is
9 generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
10 port(
11 clk, raz : in std_logic; --! Horloge et Reset globale
12 sclk : out std_logic --! Horloge Systeme g�n�r�e
13 );
14 end Systeme_Clock;
15
16 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
17 architecture ar_Systeme_Clock of Systeme_Clock is
18
19 signal clockint : std_logic;
20 signal countint : integer range 0 to N/2-1;
21
22 begin
23 process (clk,raz)
24 begin
25 if(raz = '0') then
26 countint <= 0;
27 clockint <= '0';
28 elsif (clk' event and clk='1') then
29 if (countint = N/2-1) then
30 countint <= 0;
31 clockint <= not clockint;
32 else
33 countint <= countint+1;
34 end if;
35 end if;
36 end process;
37
38 sclk <= clockint;
39
40 end ar_Systeme_Clock; No newline at end of file
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@@ -20,6 +20,7 syntax: glob
20 *doc*
20 *doc*
21 *Doc*
21 *Doc*
22 *vhdlsyn.txt
22 *vhdlsyn.txt
23 *dirs.txt
23 *.orig
24 *.orig
24 *.o
25 *.o
25 *.a
26 *.a
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@@ -30,6 +30,8
30 #define LPP_SIMPLE_DIODE 0x003
30 #define LPP_SIMPLE_DIODE 0x003
31 #define LPP_MULTI_DIODE 0x004
31 #define LPP_MULTI_DIODE 0x004
32 #define LPP_LCD_CTRLR 0x005
32 #define LPP_LCD_CTRLR 0x005
33 #define LPP_UART_CTRLR 0x006
34 #define LPP_DAC_CTRLR 0x007
33
35
34 /** @todo implemente a descriptor structure for any APB device */
36 /** @todo implemente a descriptor structure for any APB device */
35
37
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@@ -1,3 +1,36
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../rules.mk
21
22
23
24 all:
25 make all -C AMBA
26 make all -C LCD
27 make all -C DAC
28
29
30 cleanall:
31 make clean -C AMBA
32 make clean -C LCD
33 make clean -C DAC
1 #------------------------------------------------------------------------------
34 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
35 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
36 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
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@@ -1,5 +1,3
1 amba_lcd_16x2_ctrlr.vhd
2 apb_lcd_ctrlr.vhd
3 FRAME_CLK.vhd
1 FRAME_CLK.vhd
4 LCD_16x2_CFG.vhd
2 LCD_16x2_CFG.vhd
5 LCD_16x2_DRVR.vhd
3 LCD_16x2_DRVR.vhd
@@ -7,3 +5,5 LCD_16x2_ENGINE.vhd
7 LCD_2x16_DRIVER.vhd
5 LCD_2x16_DRIVER.vhd
8 LCD_CLK_GENERATOR.vhd
6 LCD_CLK_GENERATOR.vhd
9 Top_LCD.vhd
7 Top_LCD.vhd
8 amba_lcd_16x2_ctrlr.vhd
9 apb_lcd_ctrlr.vhd
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@@ -1,12 +1,12
1 APB_IIR_CEL.vhd
1 APB_IIR_CEL.vhd
2 FILTER.vhd
3 FILTER_RAM_CTRLR.vhd
2 FILTERcfg.vhd
4 FILTERcfg.vhd
3 FilterCTRLR.vhd
5 FilterCTRLR.vhd
4 FILTER_RAM_CTRLR.vhd
5 FILTER.vhd
6 IIR_CEL_CTRLR.vhd
6 IIR_CEL_CTRLR.vhd
7 IIR_CEL_FILTER.vhd
7 IIR_CEL_FILTER.vhd
8 iir_filter.vhd
8 RAM.vhd
9 RAM_CEL.vhd
9 RAM_CEL.vhd
10 RAM_CTRLR2.vhd
10 RAM_CTRLR2.vhd
11 RAM.vhd
12 Top_Filtre_IIR.vhd
11 Top_Filtre_IIR.vhd
12 iir_filter.vhd
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@@ -1,14 +1,14
1 Adder.vhd
2 ADDRcntr.vhd
1 ADDRcntr.vhd
3 ALU.vhd
2 ALU.vhd
3 Adder.vhd
4 Clk_divider.vhd
4 Clk_divider.vhd
5 general_purpose.vhd
5 MAC.vhd
6 MAC_CONTROLER.vhd
6 MAC_CONTROLER.vhd
7 MAC_MUX2.vhd
8 MAC_MUX.vhd
7 MAC_MUX.vhd
8 MAC_MUX2.vhd
9 MAC_REG.vhd
9 MAC_REG.vhd
10 MAC.vhd
10 MUX2.vhd
11 Multiplier.vhd
11 Multiplier.vhd
12 MUX2.vhd
13 REG.vhd
12 REG.vhd
14 Shifter.vhd
13 Shifter.vhd
14 general_purpose.vhd
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@@ -60,6 +60,7 type LEDregs is record
60 end record;
60 end record;
61
61
62 signal r : LEDregs;
62 signal r : LEDregs;
63 signal Rdata : std_logic_vector(31 downto 0);
63
64
64
65
65 begin
66 begin
@@ -71,7 +72,7 begin
71 if rst = '0' then
72 if rst = '0' then
72 LED <= "000";
73 LED <= "000";
73 r.DATAin <= (others => '0');
74 r.DATAin <= (others => '0');
74 apbo.prdata <= (others => '0');
75
75 elsif clk'event and clk = '1' then
76 elsif clk'event and clk = '1' then
76
77
77 LED <= r.DATAin(2 downto 0);
78 LED <= r.DATAin(2 downto 0);
@@ -87,12 +88,12 begin
87 end if;
88 end if;
88
89
89 --APB READ OP
90 --APB READ OP
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
91 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 case apbi.paddr(abits-1 downto 2) is
92 case apbi.paddr(abits-1 downto 2) is
92 when "000000" =>
93 when "000000" =>
93 apbo.prdata <= r.DATAin;
94 Rdata <= r.DATAin;
94 when others =>
95 when others =>
95 apbo.prdata <= r.DATAout;
96 Rdata <= r.DATAout;
96 end case;
97 end case;
97 end if;
98 end if;
98
99
@@ -100,5 +101,5 begin
100 apbo.pconfig <= pconfig;
101 apbo.pconfig <= pconfig;
101 end process;
102 end process;
102
103
103
104 apbo.prdata <= Rdata when apbi.penable = '1';
104 end ar_APB_MULTI_DIODE;
105 end ar_APB_MULTI_DIODE;
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@@ -60,7 +60,7 type LEDregs is record
60 end record;
60 end record;
61
61
62 signal r : LEDregs;
62 signal r : LEDregs;
63
63 signal Rdata : std_logic_vector(31 downto 0);
64
64
65 begin
65 begin
66
66
@@ -71,7 +71,7 begin
71 if rst = '0' then
71 if rst = '0' then
72 LED <= '0';
72 LED <= '0';
73 r.DATAin <= (others => '0');
73 r.DATAin <= (others => '0');
74 apbo.prdata <= (others => '0');
74
75 elsif clk'event and clk = '1' then
75 elsif clk'event and clk = '1' then
76
76
77 LED <= r.DATAin(0);
77 LED <= r.DATAin(0);
@@ -87,12 +87,12 begin
87 end if;
87 end if;
88
88
89 --APB READ OP
89 --APB READ OP
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
90 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 case apbi.paddr(abits-1 downto 2) is
91 case apbi.paddr(abits-1 downto 2) is
92 when "000000" =>
92 when "000000" =>
93 apbo.prdata <= r.DATAin;
93 Rdata <= r.DATAin;
94 when others =>
94 when others =>
95 apbo.prdata <= r.DATAout;
95 Rdata <= r.DATAout;
96 end case;
96 end case;
97 end if;
97 end if;
98
98
@@ -100,7 +100,7 begin
100 apbo.pconfig <= pconfig;
100 apbo.pconfig <= pconfig;
101 end process;
101 end process;
102
102
103
103 apbo.prdata <= Rdata when apbi.penable = '1';
104
104
105 -- pragma translate_off
105 -- pragma translate_off
106 -- bootmsg : report_version
106 -- bootmsg : report_version
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@@ -44,7 +44,7 CLKINT_1 : CLKINT
44 port map(A => rst, Y => raz);
44 port map(A => rst, Y => raz);
45
45
46
46
47 SystemCLK : entity work.Clock_Serie
47 SystemCLK : entity work.Systeme_Clock
48 generic map (nb_serial)
48 generic map (nb_serial)
49 port map (clk,raz,s_SCLK);
49 port map (clk,raz,s_SCLK);
50
50
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@@ -46,7 +46,7 component CNA_TabloC is
46 end component;
46 end component;
47
47
48
48
49 component Clock_Serie is
49 component Systeme_Clock is
50 generic(N :integer := 695);
50 generic(N :integer := 695);
51 port(
51 port(
52 clk, raz : in std_logic ;
52 clk, raz : in std_logic ;
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@@ -67,6 +67,7 type UART_ctrlr_Reg is record
67 end record;
67 end record;
68
68
69 signal Rec : UART_ctrlr_Reg;
69 signal Rec : UART_ctrlr_Reg;
70 signal Rdata : std_logic_vector(31 downto 0);
70
71
71 begin
72 begin
72
73
@@ -86,7 +87,7 Rec.UART_Cfg(4) <= NwData;
86 begin
87 begin
87 if(rst='0')then
88 if(rst='0')then
88 Rec.UART_Wdata <= (others => '0');
89 Rec.UART_Wdata <= (others => '0');
89 apbo.prdata <= (others => '0');
90
90
91
91 elsif(clk'event and clk='1')then
92 elsif(clk'event and clk='1')then
92
93
@@ -104,18 +105,18 Rec.UART_Cfg(4) <= NwData;
104 end if;
105 end if;
105
106
106 --APB READ OP
107 --APB READ OP
107 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 case apbi.paddr(abits-1 downto 2) is
109 case apbi.paddr(abits-1 downto 2) is
109 when "000000" =>
110 when "000000" =>
110 apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
111 Rdata(31 downto 27) <= Rec.UART_Cfg;
111 apbo.prdata(26 downto 12) <= (others => '0');
112 Rdata(26 downto 12) <= (others => '0');
112 apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
113 Rdata(11 downto 0) <= Rec.UART_BTrig;
113 when "000001" =>
114 when "000001" =>
114 apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
115 Rdata(7 downto 0) <= Rec.UART_Wdata;
115 when "000010" =>
116 when "000010" =>
116 apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
117 Rdata(7 downto 0) <= Rec.UART_Rdata;
117 when others =>
118 when others =>
118 apbo.prdata <= (others => '0');
119 Rdata <= (others => '0');
119 end case;
120 end case;
120 end if;
121 end if;
121
122
@@ -123,4 +124,6 Rec.UART_Cfg(4) <= NwData;
123 apbo.pconfig <= pconfig;
124 apbo.pconfig <= pconfig;
124 end process;
125 end process;
125
126
127 apbo.prdata <= Rdata when apbi.penable = '1';
128
126 end ar_APB_UART;
129 end ar_APB_UART;
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