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Alexis Jeandet -
r433:a787767be54c JC
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1 PACKAGE=\"\"
2 SPEED=Std
3 SYNFREQ=50
4
5 TECHNOLOGY=ProASIC3E
6 LIBERO_DIE=IT14X14M4
7 PART=A3PE3000
8
9 DESIGNER_VOLTAGE=COM
10 DESIGNER_TEMP=COM
11 DESIGNER_PACKAGE=FBGA
12 DESIGNER_PINS=324
13
14 MANUFACTURER=Actel
15 MGCTECHNOLOGY=Proasic3
16 MGCPART=$(PART)
17 MGCPACKAGE= {$(DESIGNER_PINS) $(DESIGNER_PACKAGE)}
18 LIBERO_PACKAGE=fg$(DESIGNER_PINS)
19
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1 # Actel Physical design constraints file
2 # Generated file
3
4 # Version: 9.1 SP3 9.1.3.4
5 # Family: ProASIC3L , Die: A3PE3000L , Package: 324 FBGA
6 # Date generated: Tue Oct 18 08:21:45 2011
7
8
9 #
10 # IO banks setting
11 #
12
13
14 #
15 # I/O constraints
16 #
17
18 set_io clk_50 \
19 -pinname F7 \
20 -fixed yes \
21 -DIRECTION Inout
22
23 set_io clk_49 \
24 -pinname F8 \
25 -fixed yes \
26 -DIRECTION Inout
27
28 set_io reset \
29 -pinname J12 \
30 -fixed yes \
31 -DIRECTION Inout
32 #====================================================================
33 # BPs
34 #====================================================================
35 set_io BP0 \
36 -pinname F16 \
37 -fixed yes \
38 -DIRECTION Inout
39
40 set_io BP1 \
41 -pinname F13 \
42 -fixed yes \
43 -DIRECTION Inout
44
45 #====================================================================
46 # LEDs
47 #====================================================================
48
49 set_io LED0 \
50 -pinname R13 \
51 -fixed yes \
52 -DIRECTION Inout
53
54 set_io LED1 \
55 -pinname P13 \
56 -fixed yes \
57 -DIRECTION Inout
58
59 set_io LED2 \
60 -pinname N11 \
61 -fixed yes \
62 -DIRECTION Inout
63
64 #====================================================================
65 # UARTS
66 #====================================================================
67
68 set_io TXD1 \
69 -pinname N12 \
70 -fixed yes \
71 -DIRECTION Inout
72
73 set_io RXD1 \
74 -pinname N10 \
75 -fixed yes \
76 -DIRECTION Inout
77
78 set_io nCTS1 \
79 -pinname L13 \
80 -fixed yes \
81 -DIRECTION Inout
82
83 set_io nRTS1 \
84 -pinname M9 \
85 -fixed yes \
86 -DIRECTION Inout
87
88
89 set_io TXD2 \
90 -pinname G6 \
91 -fixed yes \
92 -DIRECTION Inout
93
94 set_io RXD2 \
95 -pinname F6 \
96 -fixed yes \
97 -DIRECTION Inout
98
99
100 #====================================================================
101 # SRAM
102 #====================================================================
103
104 #================================
105 # SRAM CTRL
106 #================================
107
108 set_io SRAM_nWE \
109 -pinname B16 \
110 -fixed yes \
111 -DIRECTION Inout
112
113 set_io SRAM_nCE1 \
114 -pinname C17 \
115 -fixed yes \
116 -DIRECTION Inout
117
118 set_io SRAM_nCE2 \
119 -pinname B17 \
120 -fixed yes \
121 -DIRECTION Inout
122
123 set_io SRAM_nOE \
124 -pinname J14 \
125 -fixed yes \
126 -DIRECTION Inout
127
128 set_io SRAM_MBE \
129 -pinname D13 \
130 -fixed yes \
131 -DIRECTION Inout
132
133 set_io SRAM_nSCRUB \
134 -pinname E13 \
135 -fixed yes \
136 -DIRECTION Inout
137
138 set_io SRAM_nBUSY \
139 -pinname D12 \
140 -fixed yes \
141 -DIRECTION Inout
142
143
144
145
146 #================================
147 # SRAM ADDRESS
148 #================================
149
150 set_io SRAM_A\[0\] \
151 -pinname T12 \
152 -fixed yes \
153 -DIRECTION Inout
154
155 set_io SRAM_A\[1\] \
156 -pinname U13 \
157 -fixed yes \
158 -DIRECTION Inout
159
160 set_io SRAM_A\[2\] \
161 -pinname T13 \
162 -fixed yes \
163 -DIRECTION Inout
164
165 set_io SRAM_A\[3\] \
166 -pinname N15 \
167 -fixed yes \
168 -DIRECTION Inout
169
170 set_io SRAM_A\[4\] \
171 -pinname P17 \
172 -fixed yes \
173 -DIRECTION Inout
174
175 set_io SRAM_A\[5\] \
176 -pinname N13 \
177 -fixed yes \
178 -DIRECTION Inout
179
180 set_io SRAM_A\[6\] \
181 -pinname M16 \
182 -fixed yes \
183 -DIRECTION Inout
184
185 set_io SRAM_A\[7\] \
186 -pinname M13 \
187 -fixed yes \
188 -DIRECTION Inout
189
190 set_io SRAM_A\[8\] \
191 -pinname U12 \
192 -fixed yes \
193 -DIRECTION Inout
194
195 set_io SRAM_A\[9\] \
196 -pinname V11 \
197 -fixed yes \
198 -DIRECTION Inout
199
200 set_io SRAM_A\[10\] \
201 -pinname V13 \
202 -fixed yes \
203 -DIRECTION Inout
204
205 set_io SRAM_A\[11\] \
206 -pinname V14 \
207 -fixed yes \
208 -DIRECTION Inout
209
210 set_io SRAM_A\[12\] \
211 -pinname V15 \
212 -fixed yes \
213 -DIRECTION Inout
214
215 set_io SRAM_A\[13\] \
216 -pinname P16 \
217 -fixed yes \
218 -DIRECTION Inout
219
220 set_io SRAM_A\[14\] \
221 -pinname N16 \
222 -fixed yes \
223 -DIRECTION Inout
224
225 set_io SRAM_A\[15\] \
226 -pinname V16 \
227 -fixed yes \
228 -DIRECTION Inout
229
230 set_io SRAM_A\[16\] \
231 -pinname V17 \
232 -fixed yes \
233 -DIRECTION Inout
234
235 set_io SRAM_A\[17\] \
236 -pinname U18 \
237 -fixed yes \
238 -DIRECTION Inout
239
240 set_io SRAM_A\[18\] \
241 -pinname R18 \
242 -fixed yes \
243 -DIRECTION Inout
244
245
246
247 #================================
248 # SRAM DATA
249 #================================
250
251 set_io SRAM_DQ\[0\] \
252 -pinname T18 \
253 -fixed yes \
254 -DIRECTION Inout
255
256 set_io SRAM_DQ\[1\] \
257 -pinname L15 \
258 -fixed yes \
259 -DIRECTION Inout
260
261 set_io SRAM_DQ\[2\] \
262 -pinname K18 \
263 -fixed yes \
264 -DIRECTION Inout
265
266 set_io SRAM_DQ\[3\] \
267 -pinname G17 \
268 -fixed yes \
269 -DIRECTION Inout
270
271 set_io SRAM_DQ\[4\] \
272 -pinname K17 \
273 -fixed yes \
274 -DIRECTION Inout
275
276 set_io SRAM_DQ\[5\] \
277 -pinname H18 \
278 -fixed yes \
279 -DIRECTION Inout
280
281 set_io SRAM_DQ\[6\] \
282 -pinname L18 \
283 -fixed yes \
284 -DIRECTION Inout
285
286 set_io SRAM_DQ\[7\] \
287 -pinname J18 \
288 -fixed yes \
289 -DIRECTION Inout
290
291 set_io SRAM_DQ\[8\] \
292 -pinname M17 \
293 -fixed yes \
294 -DIRECTION Inout
295
296 set_io SRAM_DQ\[9\] \
297 -pinname J17 \
298 -fixed yes \
299 -DIRECTION Inout
300
301 set_io SRAM_DQ\[10\] \
302 -pinname N18 \
303 -fixed yes \
304 -DIRECTION Inout
305
306 set_io SRAM_DQ\[11\] \
307 -pinname J13 \
308 -fixed yes \
309 -DIRECTION Inout
310
311 set_io SRAM_DQ\[12\] \
312 -pinname N17 \
313 -fixed yes \
314 -DIRECTION Inout
315
316 set_io SRAM_DQ\[13\] \
317 -pinname K13 \
318 -fixed yes \
319 -DIRECTION Inout
320
321 set_io SRAM_DQ\[14\] \
322 -pinname P18 \
323 -fixed yes \
324 -DIRECTION Inout
325
326 set_io SRAM_DQ\[15\] \
327 -pinname K14 \
328 -fixed yes \
329 -DIRECTION Inout
330
331 set_io SRAM_DQ\[16\] \
332 -pinname K15 \
333 -fixed yes \
334 -DIRECTION Inout
335
336 set_io SRAM_DQ\[17\] \
337 -pinname B18 \
338 -fixed yes \
339 -DIRECTION Inout
340
341 set_io SRAM_DQ\[18\] \
342 -pinname D16 \
343 -fixed yes \
344 -DIRECTION Inout
345
346 set_io SRAM_DQ\[19\] \
347 -pinname D15 \
348 -fixed yes \
349 -DIRECTION Inout
350
351 set_io SRAM_DQ\[20\] \
352 -pinname C18 \
353 -fixed yes \
354 -DIRECTION Inout
355
356 set_io SRAM_DQ\[21\] \
357 -pinname E15 \
358 -fixed yes \
359 -DIRECTION Inout
360
361 set_io SRAM_DQ\[22\] \
362 -pinname D18 \
363 -fixed yes \
364 -DIRECTION Inout
365
366 set_io SRAM_DQ\[23\] \
367 -pinname F15 \
368 -fixed yes \
369 -DIRECTION Inout
370
371 set_io SRAM_DQ\[24\] \
372 -pinname E18 \
373 -fixed yes \
374 -DIRECTION Inout
375
376 set_io SRAM_DQ\[25\] \
377 -pinname G15 \
378 -fixed yes \
379 -DIRECTION Inout
380
381 set_io SRAM_DQ\[26\] \
382 -pinname F17 \
383 -fixed yes \
384 -DIRECTION Inout
385
386 set_io SRAM_DQ\[27\] \
387 -pinname H15 \
388 -fixed yes \
389 -DIRECTION Inout
390
391 set_io SRAM_DQ\[28\] \
392 -pinname F18 \
393 -fixed yes \
394 -DIRECTION Inout
395
396 set_io SRAM_DQ\[29\] \
397 -pinname J15 \
398 -fixed yes \
399 -DIRECTION Inout
400
401 set_io SRAM_DQ\[30\] \
402 -pinname D11 \
403 -fixed yes \
404 -DIRECTION Inout
405
406 set_io SRAM_DQ\[31\] \
407 -pinname C16 \
408 -fixed yes \
409 -DIRECTION Inout
410
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1 1 -----------------------------------------------------------------------------
2 2 -- LEON3 Demonstration design
3 3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 2 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19
20 20
21 21 LIBRARY ieee;
22 22 USE ieee.std_logic_1164.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 LIBRARY techmap;
27 27 USE techmap.gencomp.ALL;
28 28 LIBRARY gaisler;
29 29 USE gaisler.memctrl.ALL;
30 30 USE gaisler.leon3.ALL;
31 31 USE gaisler.uart.ALL;
32 32 USE gaisler.misc.ALL;
33 33 USE gaisler.spacewire.ALL; -- PLE
34 34 LIBRARY esa;
35 35 USE esa.memoryctrl.ALL;
36 36 LIBRARY lpp;
37 37 USE lpp.lpp_memory.ALL;
38 38 USE lpp.lpp_ad_conv.ALL;
39 39 USE lpp.lpp_lfr_pkg.ALL;
40 40 USE lpp.iir_filter.ALL;
41 41 USE lpp.general_purpose.ALL;
42 42 USE lpp.lpp_lfr_time_management.ALL;
43 43 USE lpp.lpp_leon3_soc_pkg.ALL;
44 44
45 45 ENTITY leon3_soc IS
46 46 GENERIC (
47 47 fabtech : INTEGER := apa3e;
48 48 memtech : INTEGER := apa3e;
49 49 padtech : INTEGER := inferred;
50 50 clktech : INTEGER := inferred;
51 51 disas : INTEGER := 0; -- Enable disassembly to console
52 52 dbguart : INTEGER := 0; -- Print UART on console
53 53 pclow : INTEGER := 2;
54 54 --
55 55 clk_freq : INTEGER := 25000; --kHz
56 56 --
57 57 NB_CPU : INTEGER := 1;
58 58 ENABLE_FPU : INTEGER := 1;
59 59 FPU_NETLIST : INTEGER := 1;
60 60 ENABLE_DSU : INTEGER := 1;
61 61 ENABLE_AHB_UART : INTEGER := 1;
62 62 ENABLE_APB_UART : INTEGER := 1;
63 63 ENABLE_IRQMP : INTEGER := 1;
64 64 ENABLE_GPT : INTEGER := 1;
65 65 --
66 66 NB_AHB_MASTER : INTEGER := 0;
67 67 NB_AHB_SLAVE : INTEGER := 0;
68 NB_APB_SLAVE : INTEGER := 0
68 NB_APB_SLAVE : INTEGER := 0;
69 --
70 ADDRESS_SIZE : INTEGER := 20
69 71 );
70 72 PORT (
71 73 clk : IN STD_ULOGIC;
72 74 reset : IN STD_ULOGIC;
73 75
74 76 errorn : OUT STD_ULOGIC;
75 77
76 78 -- UART AHB ---------------------------------------------------------------
77 79 ahbrxd : IN STD_ULOGIC; -- DSU rx data
78 80 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
79 81
80 82 -- UART APB ---------------------------------------------------------------
81 83 urxd1 : IN STD_ULOGIC; -- UART1 rx data
82 84 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83 85
84 86 -- RAM --------------------------------------------------------------------
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
87 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
86 88 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 89 nSRAM_BE0 : OUT STD_LOGIC;
88 90 nSRAM_BE1 : OUT STD_LOGIC;
89 91 nSRAM_BE2 : OUT STD_LOGIC;
90 92 nSRAM_BE3 : OUT STD_LOGIC;
91 93 nSRAM_WE : OUT STD_LOGIC;
92 94 nSRAM_CE : OUT STD_LOGIC;
93 95 nSRAM_OE : OUT STD_LOGIC;
94 96
95 97 -- APB --------------------------------------------------------------------
96 98 apbi_ext : OUT apb_slv_in_type;
97 99 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
98 100 -- AHB_Slave --------------------------------------------------------------
99 101 ahbi_s_ext : OUT ahb_slv_in_type;
100 102 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
101 103 -- AHB_Master -------------------------------------------------------------
102 104 ahbi_m_ext : OUT AHB_Mst_In_Type;
103 105 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
104 106
105 107 );
106 108 END;
107 109
108 110 ARCHITECTURE Behavioral OF leon3_soc IS
109 111
110 112 -----------------------------------------------------------------------------
111 113 -- CONFIG -------------------------------------------------------------------
112 114 -----------------------------------------------------------------------------
113 115
114 116 -- Clock generator
115 117 constant CFG_CLKMUL : integer := (1);
116 118 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
117 119 constant CFG_OCLKDIV : integer := (1);
118 120 constant CFG_CLK_NOFB : integer := 0;
119 121 -- LEON3 processor core
120 122 constant CFG_LEON3 : integer := 1;
121 123 constant CFG_NCPU : integer := NB_CPU;
122 124 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
123 125 constant CFG_V8 : integer := 0;
124 126 constant CFG_MAC : integer := 0;
125 127 constant CFG_SVT : integer := 0;
126 128 constant CFG_RSTADDR : integer := 16#00000#;
127 129 constant CFG_LDDEL : integer := (1);
128 130 constant CFG_NWP : integer := (0);
129 131 constant CFG_PWD : integer := 1*2;
130 132 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
131 133 -- 1*(8 + 16 * 0) => grfpu-light
132 134 -- 1*(8 + 16 * 1) => netlist
133 135 -- 0*(8 + 16 * 0) => No FPU
134 136 -- 0*(8 + 16 * 1) => No FPU;
135 137 constant CFG_ICEN : integer := 1;
136 138 constant CFG_ISETS : integer := 1;
137 139 constant CFG_ISETSZ : integer := 4;
138 140 constant CFG_ILINE : integer := 4;
139 141 constant CFG_IREPL : integer := 0;
140 142 constant CFG_ILOCK : integer := 0;
141 143 constant CFG_ILRAMEN : integer := 0;
142 144 constant CFG_ILRAMADDR: integer := 16#8E#;
143 145 constant CFG_ILRAMSZ : integer := 1;
144 146 constant CFG_DCEN : integer := 1;
145 147 constant CFG_DSETS : integer := 1;
146 148 constant CFG_DSETSZ : integer := 4;
147 149 constant CFG_DLINE : integer := 4;
148 150 constant CFG_DREPL : integer := 0;
149 151 constant CFG_DLOCK : integer := 0;
150 152 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
151 153 constant CFG_DLRAMEN : integer := 0;
152 154 constant CFG_DLRAMADDR: integer := 16#8F#;
153 155 constant CFG_DLRAMSZ : integer := 1;
154 156 constant CFG_MMUEN : integer := 0;
155 157 constant CFG_ITLBNUM : integer := 2;
156 158 constant CFG_DTLBNUM : integer := 2;
157 159 constant CFG_TLB_TYPE : integer := 1 + 0*2;
158 160 constant CFG_TLB_REP : integer := 1;
159 161
160 162 constant CFG_DSU : integer := ENABLE_DSU;
161 163 constant CFG_ITBSZ : integer := 0;
162 164 constant CFG_ATBSZ : integer := 0;
163 165
164 166 -- AMBA settings
165 167 constant CFG_DEFMST : integer := (0);
166 168 constant CFG_RROBIN : integer := 1;
167 169 constant CFG_SPLIT : integer := 0;
168 170 constant CFG_AHBIO : integer := 16#FFF#;
169 171 constant CFG_APBADDR : integer := 16#800#;
170 172
171 173 -- DSU UART
172 174 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
173 175
174 176 -- LEON2 memory controller
175 177 constant CFG_MCTRL_SDEN : integer := 0;
176 178
177 179 -- UART 1
178 180 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
179 181 constant CFG_UART1_FIFO : integer := 1;
180 182
181 183 -- LEON3 interrupt controller
182 184 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
183 185
184 186 -- Modular timer
185 187 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
186 188 constant CFG_GPT_NTIM : integer := (2);
187 189 constant CFG_GPT_SW : integer := (8);
188 190 constant CFG_GPT_TW : integer := (32);
189 191 constant CFG_GPT_IRQ : integer := (8);
190 192 constant CFG_GPT_SEPIRQ : integer := 1;
191 193 constant CFG_GPT_WDOGEN : integer := 0;
192 194 constant CFG_GPT_WDOG : integer := 16#0#;
193 195 -----------------------------------------------------------------------------
194 196
195 197 -----------------------------------------------------------------------------
196 198 -- SIGNALs
197 199 -----------------------------------------------------------------------------
198 200 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
199 201 -- CLK & RST --
200 202 SIGNAL clk2x : STD_ULOGIC;
201 203 SIGNAL clkmn : STD_ULOGIC;
202 204 SIGNAL clkm : STD_ULOGIC;
203 205 SIGNAL rstn : STD_ULOGIC;
204 206 SIGNAL rstraw : STD_ULOGIC;
205 207 SIGNAL pciclk : STD_ULOGIC;
206 208 SIGNAL sdclkl : STD_ULOGIC;
207 209 SIGNAL cgi : clkgen_in_type;
208 210 SIGNAL cgo : clkgen_out_type;
209 211 --- AHB / APB
210 212 SIGNAL apbi : apb_slv_in_type;
211 213 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
212 214 SIGNAL ahbsi : ahb_slv_in_type;
213 215 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
214 216 SIGNAL ahbmi : ahb_mst_in_type;
215 217 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
216 218 --UART
217 219 SIGNAL ahbuarti : uart_in_type;
218 220 SIGNAL ahbuarto : uart_out_type;
219 221 SIGNAL apbuarti : uart_in_type;
220 222 SIGNAL apbuarto : uart_out_type;
221 223 --MEM CTRLR
222 224 SIGNAL memi : memory_in_type;
223 225 SIGNAL memo : memory_out_type;
224 226 SIGNAL wpo : wprot_out_type;
225 227 SIGNAL sdo : sdram_out_type;
226 228 --IRQ
227 229 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
228 230 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
229 231 --Timer
230 232 SIGNAL gpti : gptimer_in_type;
231 233 SIGNAL gpto : gptimer_out_type;
232 234 --DSU
233 235 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
234 236 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
235 237 SIGNAL dsui : dsu_in_type;
236 238 SIGNAL dsuo : dsu_out_type;
237 239 -----------------------------------------------------------------------------
238 240
239 241 SIGNAL nSRAM_CE_s : STD_LOGIC;
240 242 BEGIN
241 243
242 244
243 245 ----------------------------------------------------------------------
244 246 --- Reset and Clock generation -------------------------------------
245 247 ----------------------------------------------------------------------
246 248
247 249 cgi.pllctrl <= "00";
248 250 cgi.pllrst <= rstraw;
249 251
250 252 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
251 253
252 254 clkgen0 : clkgen -- clock generator
253 255 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
254 256 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
255 257 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
256 258
257 259 ----------------------------------------------------------------------
258 260 --- LEON3 processor / DSU / IRQ ------------------------------------
259 261 ----------------------------------------------------------------------
260 262
261 263 l3 : IF CFG_LEON3 = 1 GENERATE
262 264 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
263 265 u0 : leon3s -- LEON3 processor
264 266 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
265 267 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
266 268 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
267 269 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
268 270 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
269 271 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
270 272 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
271 273 irqi(i), irqo(i), dbgi(i), dbgo(i));
272 274 END GENERATE;
273 275 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
274 276
275 277 dsugen : IF CFG_DSU = 1 GENERATE
276 278 dsu0 : dsu3 -- LEON3 Debug Support Unit
277 279 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
278 280 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
279 281 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
280 282 dsui.enable <= '1';
281 283 dsui.break <= '0';
282 284 END GENERATE;
283 285 END GENERATE;
284 286
285 287 nodsu : IF CFG_DSU = 0 GENERATE
286 288 ahbso(2) <= ahbs_none;
287 289 dsuo.tstop <= '0';
288 290 dsuo.active <= '0';
289 291 END GENERATE;
290 292
291 293 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
292 294 irqctrl0 : irqmp -- interrupt controller
293 295 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
294 296 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
295 297 END GENERATE;
296 298 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
297 299 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
298 300 irqi(i).irl <= "0000";
299 301 END GENERATE;
300 302 apbo(2) <= apb_none;
301 303 END GENERATE;
302 304
303 305 ----------------------------------------------------------------------
304 306 --- Memory controllers ---------------------------------------------
305 307 ----------------------------------------------------------------------
306 308 memctrlr : mctrl GENERIC MAP (
307 309 hindex => 0,
308 310 pindex => 0,
309 311 paddr => 0,
310 312 srbanks => 1
311 313 )
312 314 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
313 315
314 316 memi.brdyn <= '1';
315 317 memi.bexcn <= '1';
316 318 memi.writen <= '1';
317 319 memi.wrn <= "1111";
318 320 memi.bwidth <= "10";
319 321
320 322 bdr : FOR i IN 0 TO 3 GENERATE
321 323 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
322 324 PORT MAP (
323 325 data(31-i*8 DOWNTO 24-i*8),
324 326 memo.data(31-i*8 DOWNTO 24-i*8),
325 327 memo.bdrive(i),
326 328 memi.data(31-i*8 DOWNTO 24-i*8));
327 329 END GENERATE;
328 330
329 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
330 PORT MAP (address, memo.address(21 DOWNTO 2));
331 addr_pad : outpadv GENERIC MAP (width => ADDRESS_SIZE, tech => padtech)
332 PORT MAP (address, memo.address(ADDRESS_SIZE+1 DOWNTO 2));
331 333 nSRAM_CE_s <= NOT(memo.ramsn(0));
332 334 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s);
333 335 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
334 336 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
335 337 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
336 338 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
337 339 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
338 340 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
339 341
340 342 ----------------------------------------------------------------------
341 343 --- AHB CONTROLLER -------------------------------------------------
342 344 ----------------------------------------------------------------------
343 345 ahb0 : ahbctrl -- AHB arbiter/multiplexer
344 346 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
345 347 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
346 348 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
347 349 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
348 350
349 351 ----------------------------------------------------------------------
350 352 --- AHB UART -------------------------------------------------------
351 353 ----------------------------------------------------------------------
352 354 dcomgen : IF CFG_AHB_UART = 1 GENERATE
353 355 dcom0 : ahbuart
354 356 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
355 357 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
356 358 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
357 359 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
358 360 END GENERATE;
359 361 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
360 362
361 363 ----------------------------------------------------------------------
362 364 --- APB Bridge -----------------------------------------------------
363 365 ----------------------------------------------------------------------
364 366 apb0 : apbctrl -- AHB/APB bridge
365 367 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
366 368 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
367 369
368 370 ----------------------------------------------------------------------
369 371 --- GPT Timer ------------------------------------------------------
370 372 ----------------------------------------------------------------------
371 373 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
372 374 timer0 : gptimer -- timer unit
373 375 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
374 376 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
375 377 nbits => CFG_GPT_TW)
376 378 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
377 379 gpti.dhalt <= dsuo.tstop;
378 380 gpti.extclk <= '0';
379 381 END GENERATE;
380 382 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
381 383
382 384
383 385 ----------------------------------------------------------------------
384 386 --- APB UART -------------------------------------------------------
385 387 ----------------------------------------------------------------------
386 388 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
387 389 uart1 : apbuart -- UART 1
388 390 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
389 391 fifosize => CFG_UART1_FIFO)
390 392 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
391 393 apbuarti.rxd <= urxd1;
392 394 apbuarti.extclk <= '0';
393 395 utxd1 <= apbuarto.txd;
394 396 apbuarti.ctsn <= '0';
395 397 END GENERATE;
396 398 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
397
399
398 400 -------------------------------------------------------------------------------
399 401 -- AMBA BUS -------------------------------------------------------------------
400 402 -------------------------------------------------------------------------------
401 403
402 404 -- APB --------------------------------------------------------------------
403 405 apbi_ext <= apbi;
404 406 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
405 407 max_16_apb: IF I + 5 < 16 GENERATE
406 408 apbo(I+5)<= apbo_ext(I+5);
407 409 END GENERATE max_16_apb;
408 410 END GENERATE all_apb;
409 411 -- AHB_Slave --------------------------------------------------------------
410 412 ahbi_s_ext <= ahbsi;
411 413 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
412 414 max_16_ahbs: IF I + 3 < 16 GENERATE
413 415 ahbso(I+3) <= ahbo_s_ext(I+3);
414 416 END GENERATE max_16_ahbs;
415 417 END GENERATE all_ahbs;
416 418 -- AHB_Master -------------------------------------------------------------
417 419 ahbi_m_ext <= ahbmi;
418 420 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
419 421 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
420 422 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
421 423 END GENERATE max_16_ahbm;
422 424 END GENERATE all_ahbm;
423 425
424 426
425 427
426 428 END Behavioral;
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@@ -1,127 +1,128
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27
28 PACKAGE lpp_leon3_soc_pkg IS
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
34 COMPONENT leon3_soc
35 GENERIC (
36 fabtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
44 NB_CPU : INTEGER;
45 ENABLE_FPU : INTEGER;
46 FPU_NETLIST : INTEGER;
47 ENABLE_DSU : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
50 ENABLE_IRQMP : INTEGER;
51 ENABLE_GPT : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER);
55 PORT (
56 clk : IN STD_ULOGIC;
57 reset : IN STD_ULOGIC;
58 errorn : OUT STD_ULOGIC;
59 ahbrxd : IN STD_ULOGIC;
60 ahbtxd : OUT STD_ULOGIC;
61 urxd1 : IN STD_ULOGIC;
62 utxd1 : OUT STD_ULOGIC;
63 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
64 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65 nSRAM_BE0 : OUT STD_LOGIC;
66 nSRAM_BE1 : OUT STD_LOGIC;
67 nSRAM_BE2 : OUT STD_LOGIC;
68 nSRAM_BE3 : OUT STD_LOGIC;
69 nSRAM_WE : OUT STD_LOGIC;
70 nSRAM_CE : OUT STD_LOGIC;
71 nSRAM_OE : OUT STD_LOGIC;
72 apbi_ext : OUT apb_slv_in_type;
73 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
74 ahbi_s_ext : OUT ahb_slv_in_type;
75 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
76 ahbi_m_ext : OUT AHB_Mst_In_Type;
77 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
78 END COMPONENT;
79
80
81 COMPONENT leon3ft_soc
82 GENERIC (
83 fabtech : INTEGER;
84 memtech : INTEGER;
85 padtech : INTEGER;
86 clktech : INTEGER;
87 disas : INTEGER;
88 dbguart : INTEGER;
89 pclow : INTEGER;
90 clk_freq : INTEGER;
91 NB_CPU : INTEGER;
92 ENABLE_FPU : INTEGER;
93 FPU_NETLIST : INTEGER;
94 ENABLE_DSU : INTEGER;
95 ENABLE_AHB_UART : INTEGER;
96 ENABLE_APB_UART : INTEGER;
97 ENABLE_IRQMP : INTEGER;
98 ENABLE_GPT : INTEGER;
99 NB_AHB_MASTER : INTEGER;
100 NB_AHB_SLAVE : INTEGER;
101 NB_APB_SLAVE : INTEGER);
102 PORT (
103 clk : IN STD_ULOGIC;
104 reset : IN STD_ULOGIC;
105 errorn : OUT STD_ULOGIC;
106 ahbrxd : IN STD_ULOGIC;
107 ahbtxd : OUT STD_ULOGIC;
108 urxd1 : IN STD_ULOGIC;
109 utxd1 : OUT STD_ULOGIC;
110 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
111 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
112 nSRAM_BE0 : OUT STD_LOGIC;
113 nSRAM_BE1 : OUT STD_LOGIC;
114 nSRAM_BE2 : OUT STD_LOGIC;
115 nSRAM_BE3 : OUT STD_LOGIC;
116 nSRAM_WE : OUT STD_LOGIC;
117 nSRAM_CE : OUT STD_LOGIC;
118 nSRAM_OE : OUT STD_LOGIC;
119 apbi_ext : OUT apb_slv_in_type;
120 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
121 ahbi_s_ext : OUT ahb_slv_in_type;
122 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
123 ahbi_m_ext : OUT AHB_Mst_In_Type;
124 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
125 END COMPONENT;
126
127 END;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27
28 PACKAGE lpp_leon3_soc_pkg IS
29
30 type soc_ahb_mst_out_vector is array (natural range <>) of ahb_mst_out_type;
31 type soc_ahb_slv_out_vector is array (natural range <>) of ahb_slv_out_type;
32 type soc_apb_slv_out_vector is array (natural range <>) of apb_slv_out_type;
33
34 COMPONENT leon3_soc
35 GENERIC (
36 fabtech : INTEGER;
37 memtech : INTEGER;
38 padtech : INTEGER;
39 clktech : INTEGER;
40 disas : INTEGER;
41 dbguart : INTEGER;
42 pclow : INTEGER;
43 clk_freq : INTEGER;
44 NB_CPU : INTEGER;
45 ENABLE_FPU : INTEGER;
46 FPU_NETLIST : INTEGER;
47 ENABLE_DSU : INTEGER;
48 ENABLE_AHB_UART : INTEGER;
49 ENABLE_APB_UART : INTEGER;
50 ENABLE_IRQMP : INTEGER;
51 ENABLE_GPT : INTEGER;
52 NB_AHB_MASTER : INTEGER;
53 NB_AHB_SLAVE : INTEGER;
54 NB_APB_SLAVE : INTEGER;
55 ADDRESS_SIZE : INTEGER);
56 PORT (
57 clk : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59 errorn : OUT STD_ULOGIC;
60 ahbrxd : IN STD_ULOGIC;
61 ahbtxd : OUT STD_ULOGIC;
62 urxd1 : IN STD_ULOGIC;
63 utxd1 : OUT STD_ULOGIC;
64 address : OUT STD_LOGIC_VECTOR(ADDRESS_SIZE-1 DOWNTO 0);
65 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 nSRAM_BE0 : OUT STD_LOGIC;
67 nSRAM_BE1 : OUT STD_LOGIC;
68 nSRAM_BE2 : OUT STD_LOGIC;
69 nSRAM_BE3 : OUT STD_LOGIC;
70 nSRAM_WE : OUT STD_LOGIC;
71 nSRAM_CE : OUT STD_LOGIC;
72 nSRAM_OE : OUT STD_LOGIC;
73 apbi_ext : OUT apb_slv_in_type;
74 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
75 ahbi_s_ext : OUT ahb_slv_in_type;
76 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
77 ahbi_m_ext : OUT AHB_Mst_In_Type;
78 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
79 END COMPONENT;
80
81
82 COMPONENT leon3ft_soc
83 GENERIC (
84 fabtech : INTEGER;
85 memtech : INTEGER;
86 padtech : INTEGER;
87 clktech : INTEGER;
88 disas : INTEGER;
89 dbguart : INTEGER;
90 pclow : INTEGER;
91 clk_freq : INTEGER;
92 NB_CPU : INTEGER;
93 ENABLE_FPU : INTEGER;
94 FPU_NETLIST : INTEGER;
95 ENABLE_DSU : INTEGER;
96 ENABLE_AHB_UART : INTEGER;
97 ENABLE_APB_UART : INTEGER;
98 ENABLE_IRQMP : INTEGER;
99 ENABLE_GPT : INTEGER;
100 NB_AHB_MASTER : INTEGER;
101 NB_AHB_SLAVE : INTEGER;
102 NB_APB_SLAVE : INTEGER);
103 PORT (
104 clk : IN STD_ULOGIC;
105 reset : IN STD_ULOGIC;
106 errorn : OUT STD_ULOGIC;
107 ahbrxd : IN STD_ULOGIC;
108 ahbtxd : OUT STD_ULOGIC;
109 urxd1 : IN STD_ULOGIC;
110 utxd1 : OUT STD_ULOGIC;
111 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
112 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
113 nSRAM_BE0 : OUT STD_LOGIC;
114 nSRAM_BE1 : OUT STD_LOGIC;
115 nSRAM_BE2 : OUT STD_LOGIC;
116 nSRAM_BE3 : OUT STD_LOGIC;
117 nSRAM_WE : OUT STD_LOGIC;
118 nSRAM_CE : OUT STD_LOGIC;
119 nSRAM_OE : OUT STD_LOGIC;
120 apbi_ext : OUT apb_slv_in_type;
121 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
122 ahbi_s_ext : OUT ahb_slv_in_type;
123 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
124 ahbi_m_ext : OUT AHB_Mst_In_Type;
125 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU));
126 END COMPONENT;
127
128 END;
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