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Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Moved sig_reader to lpp.lpp_sim_pkg.
Jeandet Alexis -
r643:a691a9e23336 default draft
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@@ -0,0 +1,53
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
4
5 LIBRARY std;
6 USE std.textio.ALL;
7
8 LIBRARY lpp;
9 USE lpp.data_type_pkg.ALL;
10
11 ENTITY sig_reader IS
12 GENERIC(
13 FNAME : STRING := "input.txt";
14 WIDTH : INTEGER := 1;
15 RESOLUTION : INTEGER := 8;
16 GAIN : REAL := 1.0
17 );
18 PORT(
19 clk : IN std_logic;
20 end_of_simu : out std_logic;
21 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
22 );
23 END sig_reader;
24
25 ARCHITECTURE beh OF sig_reader IS
26 FILE input_file : TEXT OPEN read_mode IS FNAME;
27 SIGNAL out_signal_reg : sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0):=(others=>(others=>'0'));
28 SIGNAL end_of_simu_reg : std_logic:='0';
29 BEGIN
30 out_signal <= out_signal_reg;
31 end_of_simu <= end_of_simu_reg;
32 PROCESS
33 VARIABLE line_var : LINE;
34 VARIABLE value : INTEGER;
35 VARIABLE cell : STD_LOGIC_VECTOR(RESOLUTION-1 downto 0);
36 BEGIN
37 WAIT UNTIL clk = '1';
38 IF endfile(input_file) THEN
39 end_of_simu_reg <= '1';
40 ELSE
41 end_of_simu_reg <= '0';
42 readline(input_file,line_var);
43 FOR COL IN 0 TO WIDTH-1 LOOP
44 read(line_var, value);
45 cell := std_logic_vector(to_signed(INTEGER(GAIN*REAL(value)) , RESOLUTION));
46 FOR bit_idx IN RESOLUTION-1 downto 0 LOOP
47 out_signal_reg(COL,bit_idx) <= cell(bit_idx);
48 END LOOP;
49 END LOOP;
50 END IF;
51 END PROCESS;
52
53 END beh;
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@@ -1,61 +1,61
1 #GRLIB=../..
1 #GRLIB=../..
2 VHDLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=testbench
5 TOP=testbench
6 BOARD=LFR-EQM
6 BOARD=LFR-EQM
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
7 include $(VHDLIB)/boards/$(BOARD)/Makefile_RTAX.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
11 EFFORT=high
12 XSTOPT=
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd sig_reader.vhd
15 VHDLSYNFILES= IIR_CEL_TEST.vhd tb.vhd IIR_CEL_TEST_v3.vhd generator.vhd
16 VHDLSIMFILES= tb.vhd sig_reader.vhd
16 VHDLSIMFILES= tb.vhd
17 SIMTOP=testbench
17 SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
19 PDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_RTAX.pdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
20 SDC=$(VHDLIB)/boards/$(BOARD)/LFR_EQM_altran_syn_fanout.sdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
22 CLEAN=soft-clean
23
23
24 TECHLIBS = axcelerator
24 TECHLIBS = axcelerator
25
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
27 tmtc openchip hynix ihp gleichmann micron usbhc opencores
28
28
29 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
29 DIRSKIP = b1553 pcif leon2 leon3v3 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
30 pci grusbhc haps slink ascs can pwm greth coremp7 spi ac97 \
31 ./dsp/lpp_fft_rtax \
31 ./dsp/lpp_fft_rtax \
32 ./amba_lcd_16x2_ctrlr \
32 ./amba_lcd_16x2_ctrlr \
33 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_AMR \
34 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_balise \
35 ./general_purpose/lpp_delay \
35 ./general_purpose/lpp_delay \
36 ./lpp_bootloader \
36 ./lpp_bootloader \
37 ./lfr_management \
37 ./lfr_management \
38 ./lpp_sim \
38 ./lpp_sim/CY7C1061DV33 \
39 ./lpp_sim/CY7C1061DV33 \
39 ./lpp_cna \
40 ./lpp_cna \
40 ./lpp_uart \
41 ./lpp_uart \
41 ./lpp_usb \
42 ./lpp_usb \
42 ./dsp/lpp_fft \
43 ./dsp/lpp_fft \
43 ./lpp_leon3_soc \
44 ./lpp_leon3_soc \
44 ./lpp_debug_lfr
45 ./lpp_debug_lfr
45
46
46 FILESKIP = i2cmst.vhd \
47 FILESKIP = i2cmst.vhd \
47 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
48 APB_MULTI_DIODE.vhd \
49 APB_MULTI_DIODE.vhd \
49 Top_MatrixSpec.vhd \
50 Top_MatrixSpec.vhd \
50 APB_FFT.vhd \
51 APB_FFT.vhd \
51 lpp_lfr_ms_FFT.vhd \
52 lpp_lfr_ms_FFT.vhd \
52 lpp_lfr_apbreg.vhd \
53 lpp_lfr_apbreg.vhd \
53 CoreFFT.vhd \
54 CoreFFT.vhd \
54 lpp_lfr_ms.vhd \
55 lpp_lfr_ms.vhd
55 lpp_lfr_sim_pkg.vhd
56
56
57 include $(GRLIB)/bin/Makefile
57 include $(GRLIB)/bin/Makefile
58 include $(GRLIB)/software/leon3/Makefile
58 include $(GRLIB)/software/leon3/Makefile
59
59
60 ################## project specific targets ##########################
60 ################## project specific targets ##########################
61
61
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@@ -20,6 +20,7 USE lpp.general_purpose.ALL;
20 USE lpp.data_type_pkg.ALL;
20 USE lpp.data_type_pkg.ALL;
21 USE lpp.lpp_lfr_pkg.ALL;
21 USE lpp.lpp_lfr_pkg.ALL;
22 USE lpp.general_purpose.ALL;
22 USE lpp.general_purpose.ALL;
23 USE lpp.lpp_sim_pkg.ALL;
23
24
24 ENTITY testbench IS
25 ENTITY testbench IS
25 GENERIC(
26 GENERIC(
@@ -74,20 +75,20 ARCHITECTURE behav OF testbench IS
74 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
75 data : OUT STD_LOGIC_VECTOR(NB_BITS-1 DOWNTO 0)
75 );
76 );
76 END COMPONENT;
77 END COMPONENT;
77
78
78 COMPONENT sig_reader IS
79 -- COMPONENT sig_reader IS
79 GENERIC(
80 -- GENERIC(
80 FNAME : STRING := "input.txt";
81 -- FNAME : STRING := "input.txt";
81 WIDTH : INTEGER := 1;
82 -- WIDTH : INTEGER := 1;
82 RESOLUTION : INTEGER := 8;
83 -- RESOLUTION : INTEGER := 8;
83 GAIN : REAL := 1.0
84 -- GAIN : REAL := 1.0
84 );
85 -- );
85 PORT(
86 -- PORT(
86 clk : IN std_logic;
87 -- clk : IN std_logic;
87 end_of_simu : out std_logic;
88 -- end_of_simu : out std_logic;
88 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
89 -- out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
89 );
90 -- );
90 END COMPONENT;
91 -- END COMPONENT;
91
92
92
93
93 FILE input : TEXT OPEN read_mode IS "input.txt";
94 FILE input : TEXT OPEN read_mode IS "input.txt";
@@ -110,7 +111,7 BEGIN
110 WAIT UNTIL clk = '1';
111 WAIT UNTIL clk = '1';
111 rstn <= '1';
112 rstn <= '1';
112 WAIT UNTIL end_of_simu = '1';
113 WAIT UNTIL end_of_simu = '1';
113 WAIT UNTIL clk = '1';
114 WAIT UNTIL clk = '1';
114 REPORT "*** END simulation ***" SEVERITY failure;
115 REPORT "*** END simulation ***" SEVERITY failure;
115 WAIT;
116 WAIT;
116 END PROCESS;
117 END PROCESS;
@@ -188,8 +189,8 BEGIN
188 sample(i,17) <= signal_gen(i,17);
189 sample(i,17) <= signal_gen(i,17);
189 END GENERATE;
190 END GENERATE;
190
191
191
192
192
193
193 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
194 -- READ INPUT SIGNALS
195 -- READ INPUT SIGNALS
195 -----------------------------------------------------------------------------
196 -----------------------------------------------------------------------------
@@ -206,8 +207,8 BEGIN
206 end_of_simu => end_of_simu,
207 end_of_simu => end_of_simu,
207 out_signal => signal_gen
208 out_signal => signal_gen
208 );
209 );
209
210
210
211
211 -----------------------------------------------------------------------------
212 -----------------------------------------------------------------------------
212 -- RECORD OUTPUT SIGNALS
213 -- RECORD OUTPUT SIGNALS
213 -----------------------------------------------------------------------------
214 -----------------------------------------------------------------------------
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@@ -32,6 +32,9 USE gaisler.jtagtst.ALL;
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34
34
35 LIBRARY lpp;
36 USE lpp.data_type_pkg.ALL;
37
35 PACKAGE lpp_sim_pkg IS
38 PACKAGE lpp_sim_pkg IS
36
39
37 PROCEDURE UART_INIT (
40 PROCEDURE UART_INIT (
@@ -58,7 +61,19 PACKAGE lpp_sim_pkg IS
58 DATA : OUT STD_LOGIC_VECTOR
61 DATA : OUT STD_LOGIC_VECTOR
59 );
62 );
60
63
61
64 COMPONENT sig_reader IS
65 GENERIC(
66 FNAME : STRING := "input.txt";
67 WIDTH : INTEGER := 1;
68 RESOLUTION : INTEGER := 8;
69 GAIN : REAL := 1.0
70 );
71 PORT(
72 clk : IN std_logic;
73 end_of_simu : out std_logic;
74 out_signal : out sample_vector(0 to WIDTH-1,RESOLUTION-1 downto 0)
75 );
76 END COMPONENT;
62 END lpp_sim_pkg;
77 END lpp_sim_pkg;
63
78
64 PACKAGE BODY lpp_sim_pkg IS
79 PACKAGE BODY lpp_sim_pkg IS
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@@ -1,3 +1,3
1 sig_reader.vhd
1 lpp_sim_pkg.vhd
2 lpp_sim_pkg.vhd
2 lpp_lfr_sim_pkg.vhd
3 lpp_lfr_sim_pkg.vhd
3
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