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Add SDC constraint files for MINI-LFR board....
pellion -
r419:a02535067f54 JC
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1 # Top Level Design Parameters
2
3 # Clocks
4
5 create_clock -period 10.000000 -waveform {0.000000 5.000000} clk_50
6 create_clock -period 20.344999 -waveform {0.000000 10.172500} clk_49
7 create_clock -period 20.000000 -waveform {0.000000 10.000000} clk_50_s:Q
8 create_clock -period 40.000000 -waveform {0.000000 20.000000} clk_25:Q
9 create_clock -period 40.690000 -waveform {0.000000 20.345100} clk_24:Q
10 create_clock -name SPW_CLOCK -period 100.000000 -waveform {0.000000 50.000000} {SPW_NOM_DIN SPW_NOM_SIN SPW_RED_DIN SPW_RED_SIN}
11
12
13 # False Paths Between Clocks
14
15
16 # False Path Constraints
17
18
19 # Maximum Delay Constraints
20
21
22 # Multicycle Constraints
23
24
25 # Virtual Clocks
26 # Output Load Constraints
27 # Driving Cell Constraints
28 # Wire Loads
29 # set_wire_load_mode top
30
31 # Other Constraints
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1 # Synplicity, Inc. constraint file
2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 # Written on Wed Aug 1 19:29:24 2007
4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5
6 #
7 # Collections
8 #
9
10 #
11 # Clocks
12 #
13
14
15 define_clock {clk_50} -name {clk_50} -freq 100 -clockgroup default_clkgroup -route 5
16 define_clock {clk_49} -name {clk_49} -freq 49.152 -clockgroup default_clkgroup -route 5
17
18 #
19 # Clock to Clock
20 #
21
22 #
23 # Inputs/Outputs
24 #
25 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
26 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
27
28
29 #
30 # Registers
31 #
32
33 #
34 # Multicycle Path
35 #
36
37 #
38 # False Path
39 #
40
41 #
42 # Path Delay
43 #
44
45 #
46 # Attributes
47 #
48 define_global_attribute syn_useioff {1}
49 define_global_attribute -disable syn_netlist_hierarchy {0}
50 define_attribute {etx_clk} syn_noclockbuf {1}
51
52 #
53 # I/O standards
54 #
55
56 #
57 # Compile Points
58 #
59
60 #
61 # Other Constraints
62 #
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1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
17 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
19 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
20 CLEAN=soft-clean
18
21
19 TECHLIBS = proasic3e
22 TECHLIBS = proasic3e
20
23
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
25 tmtc openchip hynix ihp gleichmann micron usbhc
23
26
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
29 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
32 ./general_purpose/lpp_delay \
30 ./lpp_bootloader \
33 ./lpp_bootloader \
31 ./lpp_cna \
34 ./lpp_cna \
32 ./lpp_uart \
35 ./lpp_uart \
33 ./lpp_usb \
36 ./lpp_usb \
34 ./dsp/lpp_fft_rtax \
37 ./dsp/lpp_fft_rtax \
35 ./lpp_sim/CY7C1061DV33 \
38 ./lpp_sim/CY7C1061DV33 \
36
39
37 FILESKIP =i2cmst.vhd \
40 FILESKIP =i2cmst.vhd \
38 APB_MULTI_DIODE.vhd \
41 APB_MULTI_DIODE.vhd \
39 APB_SIMPLE_DIODE.vhd \
42 APB_SIMPLE_DIODE.vhd \
40 Top_MatrixSpec.vhd \
43 Top_MatrixSpec.vhd \
41 APB_FFT.vhd
44 APB_FFT.vhd
42
45
43 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/bin/Makefile
44 include $(GRLIB)/software/leon3/Makefile
47 include $(GRLIB)/software/leon3/Makefile
45
48
46 ################## project specific targets ##########################
49 ################## project specific targets ##########################
47
50
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