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Sync, Working on BeagleSynth design.
Jeandet Alexis -
r263:9bf9890b50e7 alexis
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@@ -1,20 +1,28
1 NET "CLK" LOC = "A6" | IOSTANDARD = LVCMOS33;
1
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 NET "CLK" LOC = "K20";
2
4
3 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
5 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
4 NET "RESET" LOC = "AB11" | IOSTANDARD = LVTTL;
6 NET "RESET" LOC = "AB11";
5
7
6 NET "DAC_nCLR" LOC = "R11" | IOSTANDARD = LVCMOS33;
8 NET "DAC_nCLR" LOC = "R11";
7 NET "DAC_nCS" LOC = "T12" | IOSTANDARD = LVCMOS33;
9 NET "DAC_nCS" LOC = "T12";
8 NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD = LVCMOS33;
10 NET "CAL_IN_SCK" LOC = "R13";
9 NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD = LVCMOS33;
11 NET "DAC_SDI(0)" LOC = "P5";
10 NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD = LVCMOS33;
12 NET "DAC_SDI(1)" LOC = "M5";
11 NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD = LVCMOS33;
13 NET "DAC_SDI(2)" LOC = "C8";
12 NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD = LVCMOS33;
14 NET "DAC_SDI(3)" LOC = "M6";
13 NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD = LVCMOS33;
15 NET "DAC_SDI(4)" LOC = "K22";
14 NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD = LVCMOS33;
16 NET "DAC_SDI(5)" LOC = "L22";
15 NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD = LVCMOS33;
17 NET "DAC_SDI(6)" LOC = "G19";
16 NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD = LVCMOS33;
18 NET "DAC_SDI(7)" LOC = "F20";
17
19
18
20
21 NET "TDX" LOC = "V22";
22 NET "RXD" LOC = "U22";
23 NET "LED(0)" LOC = "AB9";
24 NET "LED(1)" LOC = "AB8";
25 NET "LED(2)" LOC = "AA8";
19
26
20
27 NET "urxd1" LOC = "D3"; # Unused PIN
28 NET "utxd1" LOC = "C4"; # Unused PIN No newline at end of file
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@@ -24,8 +24,7 use work.config.all;
24 --==================================================================
24 --==================================================================
25 --
25 --
26 --
26 --
27 -- FPGA FREQ = 48MHz
27 -- FPGA FREQ = 100MHz
28 -- ADC Oscillator frequency = 12MHz
29 --
28 --
30 --
29 --
31 --==================================================================
30 --==================================================================
@@ -43,11 +42,68 entity BeagleSynth is
43 DAC_nCLR : out std_ulogic;
42 DAC_nCLR : out std_ulogic;
44 DAC_nCS : out std_ulogic;
43 DAC_nCS : out std_ulogic;
45 CAL_IN_SCK : out std_ulogic;
44 CAL_IN_SCK : out std_ulogic;
46 DAC_SDI : out std_ulogic_vector(7 downto 0)
45 DAC_SDI : out std_ulogic_vector(7 downto 0);
46 TXD : out std_ulogic;
47 RXD : in std_ulogic;
48 urxd1 : in std_ulogic;
49 utxd1 : out std_ulogic;
50 LED : out std_ulogic_vector(2 downto 0);
51 --------------------------------------------------------
52 ---- SDRAM
53 ---- For SDRAM config have a look on leon3-altera-ep1c20
54 ---- design from GRLIB, the IS42S32400E is similar to
55 ---- MT48LC4M32B2.
56 --------------------------------------------------------
57 sdcke : out std_logic_vector ( 1 downto 0); -- clk en
58 sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel
59 sdwen : out std_logic; -- write en
60 sdrasn : out std_logic; -- row addr stb
61 sdcasn : out std_logic; -- col addr stb
62 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
63 sdclk : out std_logic; -- sdram clk output
64 sdba : out std_logic_vector (3 downto 0); -- bank select address
65 Address : out std_logic_vector(11 downto 0); -- sdram address
66 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
47 );
67 );
48 end;
68 end;
49
69
50 architecture rtl of BeagleSynth is
70 architecture rtl of BeagleSynth is
71 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
72 CFG_GRETH+CFG_AHB_JTAG;
73 constant maxahbm : integer := maxahbmsp;
74 constant IOAEN : integer := CFG_CAN;
75 constant boardfreq : integer := 100000;
76
77 signal clk2x : std_ulogic;
78 signal lclk : std_ulogic;
79 signal clkm : std_ulogic;
80 signal rstn : std_ulogic;
81 signal rstraw : std_ulogic;
82 signal pciclk : std_ulogic;
83 signal sdclkl : std_ulogic;
84 signal cgi : clkgen_in_type;
85 signal cgo : clkgen_out_type;
86
87 --- AHB / APB
88 signal apbi : apb_slv_in_type;
89 signal apbo : apb_slv_out_vector := (others => apb_none);
90 signal ahbsi : ahb_slv_in_type;
91 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
92 signal ahbmi : ahb_mst_in_type;
93 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
94
95 --- MEM CTRLR
96 signal memi : memory_in_type;
97 signal memo : memory_out_type;
98 signal sdo : sdram_out_type;
99
100 --UART
101 signal ahbuarti : uart_in_type;
102 signal ahbuarto : uart_out_type;
103 signal apbuarti : uart_in_type;
104 signal apbuarto : uart_out_type;
105
106 signal led2int : std_logic;
51
107
52 begin
108 begin
53
109
@@ -56,6 +112,116 DAC_nCS <= '1';
56 CAL_IN_SCK <= '1';
112 CAL_IN_SCK <= '1';
57 DAC_SDI <= (others =>'1');
113 DAC_SDI <= (others =>'1');
58
114
115 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
116
117 lclk <= clk;
118
119 clkgen0 : clkgen -- clock generatorsa
120 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
121 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
122 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
123
124
125 ----------------------------------------------------------------------
126 --- AHB CONTROLLER -------------------------------------------------
127 ----------------------------------------------------------------------
128
129 ahb0 : ahbctrl -- AHB arbiter/multiplexer
130 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
131 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
132 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
133 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
134
135 ----------------------------------------------------------------------
136 --- AHB UART -------------------------------------------------------
137 ----------------------------------------------------------------------
138
139 dcomgen : if CFG_AHB_UART = 1 generate
140 dcom0: ahbuart -- Debug UART
141 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
142 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
143 ahbuarti.rxd <= RXD;
144 TXD <= ahbuarto.txd;
145 led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
146 end generate;
147 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
148
149 ----------------------------------------------------------------------
150 --- APB Bridge -----------------------------------------------------
151 ----------------------------------------------------------------------
152
153 apb0 : apbctrl -- AHB/APB bridge
154 generic map (hindex => 1, haddr => CFG_APBADDR)
155 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
156
157 ----------------------------------------------------------------------
158 --- APB UART -------------------------------------------------------
159 ----------------------------------------------------------------------
160
161 ua1 : if CFG_UART1_ENABLE /= 0 generate
162 uart1 : apbuart -- UART 1
163 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
164 fifosize => CFG_UART1_FIFO)
165 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
166 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
167 apbuarti.ctsn <= '0';
168 end generate;
169 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
170
171
172
173
174 --div0: Clk_divider
175 -- generic map( 100000000,1)
176 -- Port map( clkm,rstn,LED(2));
177
178 LED(2) <= led2int;
179
180 process(clkm,rstn)
181 begin
182 if rstn = '0' then
183 led2int <= '0';
184 elsif clkm'event and clkm='1' then
185 led2int <= not led2int;
186 end if;
187 end process;
188
189
190
191
192 mctrl0 : mctrl generic map (srbanks => 4, sden => 1)
193 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo);
194
195 -- memory controller inputs not used in this configuration
196 memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111";
197
198 memi.sd <= Data;
199 -- prom width at reset
200 memi.bwidth <= "10";
201 -- I/O pads driving data memory bus data signals
202 datapads : for i in 0 to 3 generate
203 data_pad : iopadv generic map (width => 8)
204 port map (
205 pad => data(31-i*8 downto 24-i*8),
206 o => memi.data(31-i*8 downto 24-i*8),
207 en => memo.bdrive(i),
208 i => memo.data(31-i*8 downto 24-i*8)
209 );
210 end generate;
211 -- connect memory controller outputs to entity output signals
212 Address <= memo.sa(11 downto 0);
213 sdba <= memo.sa(13 downto 12);
214 writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
215 sdcke <= sdo.sdcke;
216 sdwen <= sdo.sdwen;
217 sdcsn <= sdo.sdcsn;
218 sdrasn <= sdo.rasn;
219 sdcasn <= sdo.casn;
220 sddqm <= sdo.dqm(3 downto 0);
221
222 end;
223
224
59
225
60 end rtl;
226 end rtl;
61
227
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@@ -43,4 +43,4 include $(GRLIB)/software/leon3/Makefile
43 ################## project specific targets ##########################
43 ################## project specific targets ##########################
44
44
45 flash:
45 flash:
46 xc3sprog -c ftdi -p 1 ici4.bit
46 xc3sprog -c ftdi -p 1 BeagleSynth.bit
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@@ -19,127 +19,59 package config is
19 constant CFG_FABTECH : integer := spartan6;
19 constant CFG_FABTECH : integer := spartan6;
20 constant CFG_MEMTECH : integer := spartan6;
20 constant CFG_MEMTECH : integer := spartan6;
21 constant CFG_PADTECH : integer := spartan6;
21 constant CFG_PADTECH : integer := spartan6;
22
22 -- Clock generator
23 -- Clock generator
23 constant CFG_CLKTECH : integer := spartan6;
24 constant CFG_CLKTECH : integer := spartan6;
24 constant SEND_CONSTANT_DATA : integer := 0;
25 constant CFG_CLKMUL : integer := (2);
25 constant SEND_MINF_VALUE : integer := 0;
26 constant CFG_CLKDIV : integer := (8);
26
27 constant CFG_OCLKDIV : integer := (1);
27
28 constant CFG_PCIDLL : integer := 0;
29 constant CFG_PCISYSCLK: integer := 0;
30 constant CFG_CLK_NOFB : integer := 0;
28
31
29 constant LF1cst : std_logic_vector(15 downto 0) := X"1111";
32 -- AMBA settings
30 constant LF2cst : std_logic_vector(15 downto 0) := X"2222";
33 constant CFG_DEFMST : integer := (0);
31 constant LF3cst : std_logic_vector(15 downto 0) := X"3333";
34 constant CFG_RROBIN : integer := 1;
32
35 constant CFG_SPLIT : integer := 0;
33
36 constant CFG_AHBIO : integer := 16#FFF#;
34 constant AMR1Xcst : std_logic_vector(23 downto 0):= X"000001";
37 constant CFG_APBADDR : integer := 16#800#;
35 constant AMR1Ycst : std_logic_vector(23 downto 0):= X"111111";
38 constant CFG_AHB_MON : integer := 0;
36 constant AMR1Zcst : std_logic_vector(23 downto 0):= X"7FFFFF";
39 constant CFG_AHB_MONERR : integer := 0;
37
40 constant CFG_AHB_MONWAR : integer := 0;
38 constant AMR2Xcst : std_logic_vector(23 downto 0):= X"800000";
41
39 constant AMR2Ycst : std_logic_vector(23 downto 0):= X"000002";
42 -- LEON3 processor core
40 constant AMR2Zcst : std_logic_vector(23 downto 0):= X"800001";
43 constant CFG_LEON3 : integer := 0;
41
44 constant CFG_NCPU : integer := (0);
42 constant AMR3Xcst : std_logic_vector(23 downto 0):= X"AAAAAA";
43 constant AMR3Ycst : std_logic_vector(23 downto 0):= X"BBBBBB";
44 constant AMR3Zcst : std_logic_vector(23 downto 0):= X"CCCCCC";
45
46 constant AMR4Xcst : std_logic_vector(23 downto 0):= X"DDDDDD";
47 constant AMR4Ycst : std_logic_vector(23 downto 0):= X"EEEEEE";
48 constant AMR4Zcst : std_logic_vector(23 downto 0):= X"FFFFFF";
49
45
50 constant Temp1cst : std_logic_vector(23 downto 0):= X"121212";
46 -- DSU UART
51 constant Temp2cst : std_logic_vector(23 downto 0):= X"343434";
47 constant CFG_AHB_UART : integer := 1;
52 constant Temp3cst : std_logic_vector(23 downto 0):= X"565656";
53 constant Temp4cst : std_logic_vector(23 downto 0):= X"787878";
54
55
56
57 --===========================================================|
58 --========F I L T E R C O N F I G V A L U E S=============|
59 --===========================================================|
60 --____________________________
61 --Bus Width and chanels number|
62 --____________________________|
63 constant ChanelsCount : integer := 3;
64 constant Sample_SZ : integer := 16;
65 constant Coef_SZ : integer := 9;
66 constant CoefCntPerCel: integer := 6;
67 constant CoefPerCel: integer := 5;
68 constant Cels_count : integer := 5;
69 constant virgPos : integer := 7;
70 constant Mem_use : integer := 1;
71
72
73
74 --============================================================
75 -- create each initial values for each coefs ============
76 --!!!!!!!!!!It should be interfaced with a software !!!!!!!!!!
77 --============================================================
78 constant b0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
79 constant b0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-66,Coef_SZ));
80 constant b0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
81
48
82 constant b1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
49 -- JTAG based DSU interface
83 constant b1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-57,Coef_SZ));
50 constant CFG_AHB_JTAG : integer := 0;
84 constant b1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(58,Coef_SZ));
51
85
52 -- UART 1
86 constant b2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
53 constant CFG_UART1_ENABLE : integer := 1;
87 constant b2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-17,Coef_SZ));
54 constant CFG_UART1_FIFO : integer := 1;
88 constant b2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(29,Coef_SZ));
55
89
56 -- GRLIB debugging
90 constant b3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
57 constant CFG_DUART : integer := 0;
91 constant b3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(4,Coef_SZ));
58
92 constant b3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
59 -- LEON2 memory controller
93
60 constant CFG_MCTRL_LEON2 : integer := 1;
94 constant b4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
61 constant CFG_MCTRL_RAM8BIT : integer := 0;
95 constant b4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(24,Coef_SZ));
62 constant CFG_MCTRL_RAM16BIT : integer := 0;
96 constant b4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(15,Coef_SZ));
63 constant CFG_MCTRL_5CS : integer := 0;
97
64 constant CFG_MCTRL_SDEN : integer := 0;
98 --constant b5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
65 constant CFG_MCTRL_SEPBUS : integer := 0;
99 --constant b5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-153,Coef_SZ));
66 constant CFG_MCTRL_INVCLK : integer := 0;
100 --constant b5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-171,Coef_SZ));
67 constant CFG_MCTRL_SD64 : integer := 0;
101
68 constant CFG_MCTRL_PAGE : integer := 0 + 0;
102 --constant b6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-144,Coef_SZ));
69
103 --constant b6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-72,Coef_SZ));
70 -- Gaisler Ethernet core
104 --constant b6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-25,Coef_SZ));
71 constant CFG_GRETH : integer := 0;
105
72
106
73 -- CAN 2.0 interface
107 constant a0_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
74 constant CFG_CAN : integer := 0;
108 constant a0_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(189,Coef_SZ));
109 constant a0_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-111,Coef_SZ));
110
111 constant a1_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
112 constant a1_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(162,Coef_SZ));
113 constant a1_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-81,Coef_SZ));
114
115 constant a2_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
116 constant a2_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(136,Coef_SZ));
117 constant a2_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-55,Coef_SZ));
118
119 constant a3_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
120 constant a3_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(114,Coef_SZ));
121 constant a3_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-33,Coef_SZ));
122
123 constant a4_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
124 constant a4_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(100,Coef_SZ));
125 constant a4_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-20,Coef_SZ));
126
127 --constant a5_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
128 --constant a5_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
129 --constant a5_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
130 --constant a6_0 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(60,Coef_SZ));
131 --constant a6_1 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(-128,Coef_SZ));
132 --constant a6_2 : std_logic_vector(Coef_SZ-1 downto 0) := std_logic_vector(TO_SIGNED(87,Coef_SZ));
133
134 constant CoefsInitValCst : std_logic_vector((Cels_count*CoefCntPerCel*Coef_SZ)-1 downto 0) := (a4_2 & a4_1 & a4_0 & b4_2 & b4_1 & b4_0 & a3_2 & a3_1 & a3_0 & b3_2 & b3_1 & b3_0 & a2_2 & a2_1 & a2_0 & b2_2 & b2_1 & b2_0 & a1_2 & a1_1 & a1_0 & b1_2 & b1_1 & b1_0 & a0_2 & a0_1 & a0_0 & b0_2 & b0_1 & b0_0);
135
136 constant CoefsInitValCst_v2 : std_logic_vector((Cels_count*CoefPerCel*Coef_SZ)-1 downto 0) :=
137 (a4_1 & a4_2 & b4_0 & b4_1 & b4_2 &
138 a3_1 & a3_2 & b3_0 & b3_1 & b3_2 &
139 a2_1 & a2_2 & b2_0 & b2_1 & b2_2 &
140 a1_1 & a1_2 & b1_0 & b1_1 & b1_2 &
141 a0_1 & a0_2 & b0_0 & b0_1 & b0_2 );
142
143
75
144
76
145 end;
77 end;
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