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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31
32
33 entity FFTDriver is
34 generic (
35 pindex : integer := 0;
36 paddr : integer := 0;
37 pmask : integer := 16#fff#;
38 pirq : integer := 0;
39 abits : integer := 8;
40 LPP_DEVICE : integer;
41 Data_sz : integer := 16;
42 Addr_sz : integer := 8;
43 addr_max_int : integer := 256);
44 port (
45 clk : in std_logic; --! Horloge du composant
46 rst : in std_logic; --! Reset general du composant
47 Rz : out std_logic;
48 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
53 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
54 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
55 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
57 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 );
59 end FFTDriver;
60
61 architecture ar_FFTDriver of FFTDriver is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 type DEVICE_ctrlr_Reg is record
70 DEVICE_Cfg : std_logic_vector(3 downto 0);
71 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
72 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
73 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
74 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
75 end record;
76
77 signal Rec : DEVICE_ctrlr_Reg;
78 signal Rdata : std_logic_vector(31 downto 0);
79
80 signal FlagWR : std_logic;
81 begin
82
83 Rz <= Rec.DEVICE_Cfg(0);
84 ReadEnable <= Rec.DEVICE_Cfg(1);
85 Rec.DEVICE_Cfg(2) <= FlagEmpty;
86 Rec.DEVICE_Cfg(3) <= FlagFull;
87
88 DataIn <= Rec.DEVICE_DataW;
89 Rec.DEVICE_DataR <= DataOut;
90 Rec.DEVICE_AddrW <= AddrIn;
91 Rec.DEVICE_AddrR <= AddrOut;
92
93
94
95 process(rst,clk)
96 begin
97 if(rst='0')then
98 Rec.DEVICE_DataW <= (others => '0');
99 Rec.DEVICE_Cfg(0) <= '0';
100 Rec.DEVICE_Cfg(1) <= '0';
101 FlagWR <= '0';
102
103 elsif(clk'event and clk='1')then
104
105 --APB Write OP
106 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 FlagWR <= '1';
110 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
111 When "000010" =>
112 Rec.DEVICE_Cfg(0) <= apbi.pwdata(0);
113 Rec.DEVICE_Cfg(1) <= apbi.pwdata(4);
114 when others =>
115 null;
116 end case;
117 else
118 FlagWR <= '0';
119 end if;
120
121 --APB Read OP
122 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
123 case apbi.paddr(abits-1 downto 2) is
124 when "000000" =>
125 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
126 when "000001" =>
127 Rdata(31 downto 8) <= X"AAAAAA";
128 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
129 when "000101" =>
130 Rdata(31 downto 8) <= X"AAAAAA";
131 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
132 when "000010" =>
133 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
134 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
135 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
136 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
137 Rdata(31 downto 16) <= X"CCCC";
138 when others =>
139 Rdata <= (others => '0');
140 end case;
141 end if;
142
143 end if;
144 apbo.pconfig <= pconfig;
145 end process;
146
147 apbo.prdata <= Rdata when apbi.penable = '1';
148 WriteEnable <= FlagWR;
149
150 end ar_FFTDriver; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31 use lpp.lpp_fft.all;
32 32 use lpp.lpp_memory.all;
33 33 use work.fft_components.all;
34 34
35 35 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
36 36
37 37 entity APB_FFT is
38 38 generic (
39 39 pindex : integer := 0;
40 40 paddr : integer := 0;
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 43 abits : integer := 8;
44 Data_sz : integer := 16;
44 Data_sz : integer := 32;
45 45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 48 clk : in std_logic; --! Horloge du composant
49 49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
50 54 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
51 55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 56 );
53 57 end APB_FFT;
54 58
55 59
56 60 architecture ar_APB_FFT of APB_FFT is
57 61
58 signal ReadEnable : std_logic;
59 signal WriteEnable : std_logic;
60 signal FlagEmpty : std_logic;
61 signal FlagFull : std_logic;
62 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
63 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
62 signal ReadEnable : std_logic;
63 signal WriteEnable : std_logic;
64 signal FlagEmpty : std_logic;
65 signal FlagFull : std_logic;
66 signal DataIn_re : std_logic_vector(gWSIZE-1 downto 0);
67 signal DataOut_re : std_logic_vector(gWSIZE-1 downto 0);
68 signal DataIn_im : std_logic_vector(gWSIZE-1 downto 0);
69 signal DataOut_im : std_logic_vector(gWSIZE-1 downto 0);
70 signal DataIn : std_logic_vector(Data_sz-1 downto 0);
71 signal DataOut : std_logic_vector(Data_sz-1 downto 0);
64 72 signal AddrIn : std_logic_vector(Addr_sz-1 downto 0);
65 73 signal AddrOut : std_logic_vector(Addr_sz-1 downto 0);
66 74
67 75 signal start : std_logic;
68 76 signal load : std_logic;
69 77 signal rdy : std_logic;
70 signal DummyIn : std_logic_vector(Data_sz-1 downto 0);
78 signal raz : std_logic;
71 79
72
80
73 81 begin
74 82
75 83 APB : ApbDriver
76 84 generic map(pindex,paddr,pmask,pirq,abits,LPP_FFT,Data_sz,Addr_sz,addr_max_int)
77 port map(clk,rst,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
78
85 port map(clk,rst,raz,ReadEnable,WriteEnable,FlagEmpty,FlagFull,DataIn,DataOut,AddrIn,AddrOut,apbi,apbo);
86
79 87
80 88 Extremum : Flag_Extremum
81 port map(clk,raz,load,rdy,WriteEnable,ReadEnable,FlagFull,FlagEmpty);
82
89 port map(clk,raz,load,rdy,FlagFull,FlagEmpty);
90
83 91
84 92 DEVICE : CoreFFT
85 93 generic map(
86 94 LOGPTS => gLOGPTS,
87 95 LOGLOGPTS => gLOGLOGPTS,
88 96 WSIZE => gWSIZE,
89 97 TWIDTH => gTWIDTH,
90 98 DWIDTH => gDWIDTH,
91 99 TDWIDTH => gTDWIDTH,
92 100 RND_MODE => gRND_MODE,
93 101 SCALE_MODE => gSCALE_MODE,
94 102 PTS => gPTS,
95 103 HALFPTS => gHALFPTS,
96 104 inBuf_RWDLY => gInBuf_RWDLY)
97 port map(clk,start,rst,WriteEnable,ReadEnable,DummyIn,DataIn,load,open,open,DataOut,open,rdy);
105 port map(clk,start,raz,WriteEnable,ReadEnable,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,rdy);
106
107 start <= not rst;
108
109 DataIn_re <= DataIn(31 downto 16);
110 DataIn_im <= DataIn(15 downto 0);
111 DataOut <= DataOut_re & DataOut_im;
112
98 113
99 start <= not rst;
100 --FlagFull <= not load;
101 --FlagEmpty <= not rdy;
102 DummyIn <= (others => '0');
114 full <= FlagFull;
115 empty <= FlagEmpty;
116 WR <= WriteEnable;
117 RE <= ReadEnable;
118 flg_load <= load;
119 flg_rdy <= rdy;
120 RZ <= raz;
121
103 122
104 123 end ar_APB_FFT; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library IEEE;
23 23 use IEEE.std_logic_1164.all;
24 24 use IEEE.numeric_std.all;
25 25 use work.FFT_config.all;
26 26
27 27 entity Flag_Extremum is
28 28 port(
29 29 clk,raz : in std_logic;
30 30 load : in std_logic;
31 31 y_rdy : in std_logic;
32 d_valid_WR : in std_logic;
33 read_y_RE : in std_logic;
34 32 full : out std_logic;
35 33 empty : out std_logic
36 34 );
37 35 end Flag_Extremum;
38 36
39 37 architecture ar_Flag_Extremum of Flag_Extremum is
40 38
41 type etat is (eA,eB,eC,eD,eX,e0,e1,e2,e3);
42 signal ect : etat;
39 --type etat is (eA,eB,eC,e0,e1,e2);
40 --signal ect : etat;
43 41
44 42 signal load_reg : std_logic;
45 43 signal y_rdy_reg : std_logic;
46 signal RE_reg : std_logic;
47 signal WR_reg : std_logic;
48 44
49 45 begin
50 46 process (clk,raz)
51 47 begin
52 48 if(raz='0')then
53 full <= '0';
49 full <= '1';
54 50 empty <= '1';
55 ect <= eA;
51 -- ect <= eA;
56 52
57 53 elsif(clk' event and clk='1')then
58 load_reg <= load;
59 y_rdy_reg <= y_rdy;
60 RE_reg <= read_y_RE;
61 WR_reg <= d_valid_WR;
62
63 case ect is
54 -- load_reg <= load;
55 -- y_rdy_reg <= y_rdy;
64 56
65 when eA =>
66 if(WR_reg='0' and d_valid_WR='1')then
67 empty <= '0';
68 ect <= eB;
69 end if;
70
71 when eB =>
72 if(load_reg='1' and load='0')then
73 ect <= eC;
74 end if;
75
76 when eC =>
77 if(load_reg='1' and load='0')then
78 full <= '1';
79 ect <= eD;
80 end if;
57 if(load='1' and y_rdy='0')then
58 full <= '0';
59 empty <= '1';
60
61 elsif(y_rdy='1')then
62 full <= '1';
63 empty <= '0';
64
65 else
66 full <= '1';
67 empty <= '1';
68
69 end if;
70
71 -- case ect is
81 72
82 when eD =>
83 if(RE_reg='0' and read_y_RE='1')then
84 full <= '0';
85 ect <= eX;
86 end if;
87
88 when eX =>
89 empty <= '1';
90 ect <= e0;
91
92 when e0 =>
93 if(WR_reg='0' and d_valid_WR='1')then
94 empty <= '0';
95 ect <= e1;
96 end if;
97
98 when e1 =>
99 if(load_reg='1' and load='0')then
100 full <= '1';
101 ect <= e2;
102 end if;
73 -- when eA =>
74 -- if(load_reg='0' and load='1')then
75 -- full <= '0';
76 -- ect <= eB;
77 -- end if;
78 --
79 -- when eB =>
80 -- if(load_reg='1' and load='0')then
81 -- ect <= eC;
82 -- end if;
83 --
84 -- when eC =>
85 -- if(load_reg='1' and load='0')then
86 -- full <= '1';
87 -- ect <= e0;
88 -- end if;
89
90 --===================================================================================
103 91
104 when e2 =>
105 if(RE_reg='0' and read_y_RE='1')then
106 full <= '0';
107 ect <= e3;
108 end if;
109
110 when e3 =>
111 if(y_rdy_reg='1' and y_rdy='0')then
112 empty <= '1';
113 ect <= e0;
114 end if;
115
116 end case;
92 -- when e0 =>
93 -- if(load_reg='0' and load='1')then
94 -- full <= '0';
95 -- ect <= e1;
96 -- end if;
97 --
98 -- when e1 =>
99 -- if(load_reg='1' and load='0')then
100 -- full <= '1';
101 -- empty <= '0';
102 -- ect <= e2;
103 -- end if;
104 --
105 -- when e2 =>
106 -- if(y_rdy_reg='1' and y_rdy='0')then
107 -- empty <= '1';
108 -- ect <= e0;
109 -- end if;
110 --
111 --
112 -- end case;
117 113 end if;
118 114 end process;
119 115
120 116 end ar_Flag_Extremum;
121 117
122 118
123 119
124 120
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@@ -1,142 +1,144
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29 use lpp.lpp_memory.all;
30 30 use work.fft_components.all;
31 31
32 32
33 33 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
34 34
35 35 package lpp_fft is
36 36
37 37 component APB_FFT is
38 38 generic (
39 39 pindex : integer := 0;
40 40 paddr : integer := 0;
41 41 pmask : integer := 16#fff#;
42 42 pirq : integer := 0;
43 abits : integer := 8;
44 Data_sz : integer := 16;
45 Addr_sz : integer := 8;
43 abits : integer := 8;
44 Data_sz : integer := 32;
45 Addr_sz : integer := 8;
46 46 addr_max_int : integer := 256);
47 47 port (
48 clk : in std_logic;
49 rst : in std_logic;
50 apbi : in apb_slv_in_type;
51 apbo : out apb_slv_out_type
48 clk : in std_logic; --! Horloge du composant
49 rst : in std_logic; --! Reset general du composant
50 full,empty : out std_logic;
51 WR,RE : out std_logic;
52 flg_load,flg_rdy : out std_logic;
53 RZ : out std_logic;
54 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
55 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 56 );
53 57 end component;
54 58
55 59
56 60 component Flag_Extremum is
57 61 port(
58 62 clk,raz : in std_logic;
59 63 load : in std_logic;
60 64 y_rdy : in std_logic;
61 d_valid_WR : in std_logic;
62 read_y_RE : in std_logic;
63 65 full : out std_logic;
64 66 empty : out std_logic
65 67 );
66 68 end component;
67 69
68 70
69 71 component CoreFFT IS
70 72 GENERIC (
71 73 LOGPTS : integer := gLOGPTS;
72 74 LOGLOGPTS : integer := gLOGLOGPTS;
73 75 WSIZE : integer := gWSIZE;
74 76 TWIDTH : integer := gTWIDTH;
75 77 DWIDTH : integer := gDWIDTH;
76 78 TDWIDTH : integer := gTDWIDTH;
77 79 RND_MODE : integer := gRND_MODE;
78 80 SCALE_MODE : integer := gSCALE_MODE;
79 81 PTS : integer := gPTS;
80 82 HALFPTS : integer := gHALFPTS;
81 83 inBuf_RWDLY : integer := gInBuf_RWDLY );
82 84 PORT (
83 85 clk,ifiStart,ifiNreset : IN std_logic;
84 86 ifiD_valid, ifiRead_y : IN std_logic;
85 87 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
86 88 ifoLoad, ifoPong : OUT std_logic;
87 89 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
88 90 ifoY_valid, ifoY_rdy : OUT std_logic);
89 91 END component;
90 92
91 93
92 94 component actar is
93 95 port( DataA : in std_logic_vector(15 downto 0); DataB : in
94 96 std_logic_vector(15 downto 0); Mult : out
95 97 std_logic_vector(31 downto 0);Clock : in std_logic) ;
96 98 end component;
97 99
98 100 component actram is
99 101 port( DI : in std_logic_vector(31 downto 0); DO : out
100 102 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
101 103 WADDR : in std_logic_vector(6 downto 0); RADDR : in
102 104 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
103 105 std_logic) ;
104 106 end component;
105 107
106 108 component switch IS
107 109 GENERIC ( DWIDTH : integer := 32 );
108 110 PORT (
109 111 clk, sel, validIn : IN std_logic;
110 112 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
111 113 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
112 114 validOut : OUT std_logic);
113 115 END component;
114 116
115 117 component twid_rA IS
116 118 GENERIC (LOGPTS : integer := 8;
117 119 LOGLOGPTS : integer := 3 );
118 120 PORT (clk : IN std_logic;
119 121 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
120 122 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
121 123 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
122 124 END component;
123 125
124 126 component counter IS
125 127 GENERIC (
126 128 WIDTH : integer := 7;
127 129 TERMCOUNT : integer := 127 );
128 130 PORT (
129 131 clk, nGrst, rst, cntEn : IN std_logic;
130 132 tc : OUT std_logic;
131 133 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
132 134 END component;
133 135
134 136
135 137 component twiddle IS
136 138 PORT (
137 139 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
138 140 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
139 141 END component;
140 142
141 143
142 144 end; No newline at end of file
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@@ -1,154 +1,159
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use grlib.stdlib.all;
27 27 use grlib.devices.all;
28 28 library lpp;
29 29 use lpp.lpp_amba.all;
30 30 use lpp.apb_devices_list.all;
31 31
32 32 --! Driver APB "GοΏ½nοΏ½rique" qui va faire le lien entre le bus Amba et la FIFO
33 33
34 34 entity ApbDriver is
35 35 generic (
36 36 pindex : integer := 0;
37 37 paddr : integer := 0;
38 38 pmask : integer := 16#fff#;
39 39 pirq : integer := 0;
40 40 abits : integer := 8;
41 41 LPP_DEVICE : integer;
42 42 Data_sz : integer := 16;
43 43 Addr_sz : integer := 8;
44 44 addr_max_int : integer := 256);
45 45 port (
46 46 clk : in std_logic; --! Horloge du composant
47 47 rst : in std_logic; --! Reset general du composant
48 RZ : out std_logic;
48 49 ReadEnable : out std_logic; --! Instruction de lecture en mοΏ½moire
49 50 WriteEnable : out std_logic; --! Instruction d'οΏ½criture en mοΏ½moire
50 51 FlagEmpty : in std_logic; --! Flag, MοΏ½moire vide
51 52 FlagFull : in std_logic; --! Flag, MοΏ½moire pleine
52 53 DataIn : out std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
53 54 DataOut : in std_logic_vector(Data_sz-1 downto 0); --! Registre de donnοΏ½es en sortie
54 55 AddrIn : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (οΏ½criture)
55 56 AddrOut : in std_logic_vector(Addr_sz-1 downto 0); --! Registre d'addresse (lecture)
56 57 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
57 58 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
58 59 );
59 60 end ApbDriver;
60 61
61 62 --! @details Utilisable avec n'importe quelle IP VHDL de type FIFO
62 63
63 64 architecture ar_ApbDriver of ApbDriver is
64 65
65 66 constant REVISION : integer := 1;
66 67
67 68 constant pconfig : apb_config_type := (
68 69 0 => ahb_device_reg (VENDOR_LPP, LPP_DEVICE, 0, REVISION, 0),
69 70 1 => apb_iobar(paddr, pmask));
70 71
71 72 type DEVICE_ctrlr_Reg is record
72 DEVICE_Cfg : std_logic_vector(3 downto 0);
73 DEVICE_Cfg : std_logic_vector(4 downto 0);
73 74 DEVICE_DataW : std_logic_vector(Data_sz-1 downto 0);
74 75 DEVICE_DataR : std_logic_vector(Data_sz-1 downto 0);
75 76 DEVICE_AddrW : std_logic_vector(Addr_sz-1 downto 0);
76 77 DEVICE_AddrR : std_logic_vector(Addr_sz-1 downto 0);
77 78 end record;
78 79
79 80 signal Rec : DEVICE_ctrlr_Reg;
80 81 signal Rdata : std_logic_vector(31 downto 0);
81 82
82 83 signal FlagRE : std_logic;
83 84 signal FlagWR : std_logic;
84 85 begin
85 86
86 87 Rec.DEVICE_Cfg(0) <= FlagRE;
87 88 Rec.DEVICE_Cfg(1) <= FlagWR;
88 89 Rec.DEVICE_Cfg(2) <= FlagEmpty;
89 90 Rec.DEVICE_Cfg(3) <= FlagFull;
91 Rz <= Rec.DEVICE_Cfg(4);
90 92
91 93 DataIn <= Rec.DEVICE_DataW;
92 94 Rec.DEVICE_DataR <= DataOut;
93 95 Rec.DEVICE_AddrW <= AddrIn;
94 96 Rec.DEVICE_AddrR <= AddrOut;
95 97
96 98
97 99
98 100 process(rst,clk)
99 101 begin
100 102 if(rst='0')then
101 103 Rec.DEVICE_DataW <= (others => '0');
104 Rec.DEVICE_Cfg(4) <= '0';
102 105 FlagWR <= '0';
103 106 FlagRE <= '0';
104 107
105 108 elsif(clk'event and clk='1')then
106 109
107 110 --APB Write OP
108 111 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
109 112 case apbi.paddr(abits-1 downto 2) is
110 113 when "000000" =>
111 114 FlagWR <= '1';
112 Rec.DEVICE_DataW <= apbi.pwdata(15 downto 0);
115 Rec.DEVICE_DataW <= apbi.pwdata(Data_sz-1 downto 0);
116 when "000010" =>
117 Rec.DEVICE_Cfg(4) <= apbi.pwdata(16);
113 118 when others =>
114 119 null;
115 120 end case;
116 121 else
117 122 FlagWR <= '0';
118 123 end if;
119 124
120 125 --APB Read OP
121 126 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
122 127 case apbi.paddr(abits-1 downto 2) is
123 128 when "000000" =>
124 129 FlagRE <= '1';
125 Rdata(31 downto 16) <= X"DDDD";
126 Rdata(15 downto 0) <= Rec.DEVICE_DataR;
130 Rdata(Data_sz-1 downto 0) <= Rec.DEVICE_DataR;
127 131 when "000001" =>
128 132 Rdata(31 downto 8) <= X"AAAAAA";
129 133 Rdata(7 downto 0) <= Rec.DEVICE_AddrR;
130 134 when "000101" =>
131 135 Rdata(31 downto 8) <= X"AAAAAA";
132 136 Rdata(7 downto 0) <= Rec.DEVICE_AddrW;
133 137 when "000010" =>
134 138 Rdata(3 downto 0) <= "000" & Rec.DEVICE_Cfg(0);
135 139 Rdata(7 downto 4) <= "000" & Rec.DEVICE_Cfg(1);
136 140 Rdata(11 downto 8) <= "000" & Rec.DEVICE_Cfg(2);
137 141 Rdata(15 downto 12) <= "000" & Rec.DEVICE_Cfg(3);
138 Rdata(31 downto 16) <= X"CCCC";
142 Rdata(19 downto 16) <= "000" & Rec.DEVICE_Cfg(4);
143 Rdata(31 downto 20) <= X"CCC";
139 144 when others =>
140 145 Rdata <= (others => '0');
141 146 end case;
142 147 else
143 148 FlagRE <= '0';
144 149 end if;
145 150
146 151 end if;
147 152 apbo.pconfig <= pconfig;
148 153 end process;
149 154
150 155 apbo.prdata <= Rdata when apbi.penable = '1';
151 156 WriteEnable <= FlagWR;
152 157 ReadEnable <= FlagRE;
153 158
154 159 end ar_ApbDriver; No newline at end of file
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 ------------------------------------------------------------------------------
19 19 -- Author : Martin Morlot
20 20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 21 ------------------------------------------------------------------------------
22 22 library ieee;
23 23 use ieee.std_logic_1164.all;
24 24 library grlib;
25 25 use grlib.amba.all;
26 26 use std.textio.all;
27 27 library lpp;
28 28 use lpp.lpp_amba.all;
29 29
30 30
31 31 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
32 32
33 33 package lpp_memory is
34 34
35 35 --===========================================================|
36 36 --================= FIFOW SRAM FIFOR ========================|
37 37 --===========================================================|
38 38
39 39 component APB_FIFO is
40 40 generic (
41 41 pindex : integer := 0;
42 42 paddr : integer := 0;
43 43 pmask : integer := 16#fff#;
44 44 pirq : integer := 0;
45 45 abits : integer := 8;
46 46 Data_sz : integer := 16;
47 47 Addr_sz : integer := 8;
48 48 addr_max_int : integer := 256);
49 49 port (
50 50 clk : in std_logic;
51 51 rst : in std_logic;
52 52 apbi : in apb_slv_in_type;
53 53 apbo : out apb_slv_out_type
54 54 );
55 55 end component;
56 56
57 57
58 58 component ApbDriver is
59 59 generic (
60 60 pindex : integer := 0;
61 61 paddr : integer := 0;
62 62 pmask : integer := 16#fff#;
63 63 pirq : integer := 0;
64 64 abits : integer := 8;
65 65 LPP_DEVICE : integer;
66 66 Data_sz : integer := 16;
67 67 Addr_sz : integer := 8;
68 68 addr_max_int : integer := 256);
69 69 port (
70 70 clk : in std_logic;
71 71 rst : in std_logic;
72 RZ : out std_logic;
72 73 ReadEnable : in std_logic;
73 74 WriteEnable : in std_logic;
74 75 FlagEmpty : in std_logic;
75 76 FlagFull : in std_logic;
76 77 DataIn : out std_logic_vector(Data_sz-1 downto 0);
77 78 DataOut : in std_logic_vector(Data_sz-1 downto 0);
78 79 AddrIn : in std_logic_vector(Addr_sz-1 downto 0);
79 80 AddrOut : in std_logic_vector(Addr_sz-1 downto 0);
80 81 apbi : in apb_slv_in_type;
81 82 apbo : out apb_slv_out_type
82 83 );
83 84 end component;
84 85
85 86
86 87 component Top_FIFO is
87 88 generic(
88 89 Data_sz : integer := 16;
89 90 Addr_sz : integer := 8;
90 91 addr_max_int : integer := 256
91 92 );
92 93 port(
93 94 clk,raz : in std_logic; --! Horloge et reset general du composant
94 95 flag_RE : in std_logic; --! Flag, Demande la lecture de la mοΏ½moire
95 96 flag_WR : in std_logic; --! Flag, Demande l'οΏ½criture dans la mοΏ½moire
96 97 Data_in : in std_logic_vector(Data_sz-1 downto 0); --! Data en entrοΏ½e du composant
97 98 Addr_RE : out std_logic_vector(addr_sz-1 downto 0); --! Adresse d'οΏ½criture
98 99 Addr_WR : out std_logic_vector(addr_sz-1 downto 0); --! Adresse de lecture
99 100 full : out std_logic; --! Flag, MοΏ½moire pleine
100 101 empty : out std_logic; --! Flag, MοΏ½moire vide
101 102 Data_out : out std_logic_vector(Data_sz-1 downto 0) --! Data en sortie du composant
102 103 );
103 104 end component;
104 105
105 106
106 107 component Fifo_Read is
107 108 generic(
108 109 Addr_sz : integer := 8;
109 110 addr_max_int : integer := 256);
110 111 port(
111 112 clk : in std_logic;
112 113 raz : in std_logic;
113 114 flag_RE : in std_logic;
114 115 Waddr : in std_logic_vector(addr_sz-1 downto 0);
115 116 empty : out std_logic;
116 117 Raddr : out std_logic_vector(addr_sz-1 downto 0)
117 118 );
118 119 end component;
119 120
120 121
121 122 component Fifo_Write is
122 123 generic(
123 124 Addr_sz : integer := 8;
124 125 addr_max_int : integer := 256);
125 126 port(
126 127 clk : in std_logic;
127 128 raz : in std_logic;
128 129 flag_WR : in std_logic;
129 130 Raddr : in std_logic_vector(addr_sz-1 downto 0);
130 131 full : out std_logic;
131 132 Waddr : out std_logic_vector(addr_sz-1 downto 0)
132 133 );
133 134 end component;
134 135
135 136
136 137 component Link_Reg is
137 138 generic(Data_sz : integer := 16);
138 139 port(
139 140 clk,raz : in std_logic;
140 141 Data_one : in std_logic_vector(Data_sz-1 downto 0);
141 142 Data_two : in std_logic_vector(Data_sz-1 downto 0);
142 143 flag_RE : in std_logic;
143 144 flag_WR : in std_logic;
144 145 empty : in std_logic;
145 146 Data_out : out std_logic_vector(Data_sz-1 downto 0)
146 147 );
147 148 end component;
148 149
149 150 --===========================================================|
150 151 --===================== FIFOW SRAM ==========================|
151 152 --===========================================================|
152 153
153 154 component APB_FifoWrite is
154 155 generic (
155 156 pindex : integer := 0;
156 157 paddr : integer := 0;
157 158 pmask : integer := 16#fff#;
158 159 pirq : integer := 0;
159 160 abits : integer := 8;
160 161 Data_sz : integer := 16;
161 162 Addr_sz : integer := 8;
162 163 addr_max_int : integer := 256);
163 164 port (
164 165 clk : in std_logic;
165 166 rst : in std_logic;
166 167 apbi : in apb_slv_in_type;
167 168 apbo : out apb_slv_out_type
168 169 );
169 170 end component;
170 171
171 172
172 173 component Top_FifoWrite is
173 174 generic(
174 175 Data_sz : integer := 16;
175 176 Addr_sz : integer := 8;
176 177 addr_max_int : integer := 256);
177 178 port(
178 179 clk : in std_logic;
179 180 raz : in std_logic;
180 181 flag_RE : in std_logic;
181 182 flag_WR : in std_logic;
182 183 Data_in : in std_logic_vector(Data_sz-1 downto 0);
183 184 Raddr : in std_logic_vector(addr_sz-1 downto 0);
184 185 full : out std_logic;
185 186 empty : out std_logic;
186 187 Waddr : out std_logic_vector(addr_sz-1 downto 0);
187 188 Data_out : out std_logic_vector(Data_sz-1 downto 0)
188 189 );
189 190 end component;
190 191
191 192 --===========================================================|
192 193 --===================== SRAM FIFOR ==========================|
193 194 --===========================================================|
194 195
195 196 component APB_FifoRead is
196 197 generic (
197 198 pindex : integer := 0;
198 199 paddr : integer := 0;
199 200 pmask : integer := 16#fff#;
200 201 pirq : integer := 0;
201 202 abits : integer := 8;
202 203 Data_sz : integer := 16;
203 204 Addr_sz : integer := 8;
204 205 addr_max_int : integer := 256);
205 206 port (
206 207 clk : in std_logic;
207 208 rst : in std_logic;
208 209 apbi : in apb_slv_in_type;
209 210 apbo : out apb_slv_out_type
210 211 );
211 212 end component;
212 213
213 214
214 215 component Top_FifoRead is
215 216 generic(
216 217 Data_sz : integer := 16;
217 218 Addr_sz : integer := 8;
218 219 addr_max_int : integer := 256);
219 220 port(
220 221 clk : in std_logic;
221 222 raz : in std_logic;
222 223 flag_RE : in std_logic;
223 224 flag_WR : in std_logic;
224 225 Data_in : in std_logic_vector(Data_sz-1 downto 0);
225 226 Waddr : in std_logic_vector(addr_sz-1 downto 0);
226 227 full : out std_logic;
227 228 empty : out std_logic;
228 229 Raddr : out std_logic_vector(addr_sz-1 downto 0);
229 230 Data_out : out std_logic_vector(Data_sz-1 downto 0)
230 231 );
231 232 end component;
232 233
233 234 end;
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