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Partially Working BeagleSynth base design, SDRAM still f****** buggy.
Jeandet Alexis -
r265:9504f3e37fb4 alexis
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@@ -1,28 +1,109
1
1
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
2 NET "CLK" CLOCK_DEDICATED_ROUTE = FALSE;
3 NET "CLK" LOC = "K20";
3 NET "CLK" LOC = "K20"| slew=FAST | IOSTANDARD=LVTTL;
4 #NET "CLKM" TNM_NET = "clkm_net";
5 #TIMESPEC "TS_clkm_net" = PERIOD "clkm_net" 10 ns HIGH 50%;
4
6
5 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
7 NET "RESET" CLOCK_DEDICATED_ROUTE = FALSE;
6 NET "RESET" LOC = "AB11";
8 NET "RESET" LOC = "AB11" | slew=FAST | IOSTANDARD=LVTTL;
7
9
8 NET "DAC_nCLR" LOC = "R11";
10 NET "DAC_nCLR" LOC = "R11" | IOSTANDARD=LVTTL;
9 NET "DAC_nCS" LOC = "T12";
11 NET "DAC_nCS" LOC = "T12" | IOSTANDARD=LVTTL;
10 NET "CAL_IN_SCK" LOC = "R13";
12 NET "CAL_IN_SCK" LOC = "R13" | IOSTANDARD=LVTTL;
11 NET "DAC_SDI(0)" LOC = "P5";
13 NET "DAC_SDI(0)" LOC = "P5" | IOSTANDARD=LVTTL;
12 NET "DAC_SDI(1)" LOC = "M5";
14 NET "DAC_SDI(1)" LOC = "M5" | IOSTANDARD=LVTTL;
13 NET "DAC_SDI(2)" LOC = "C8";
15 NET "DAC_SDI(2)" LOC = "C8" | IOSTANDARD=LVTTL;
14 NET "DAC_SDI(3)" LOC = "M6";
16 NET "DAC_SDI(3)" LOC = "M6" | IOSTANDARD=LVTTL;
15 NET "DAC_SDI(4)" LOC = "K22";
17 NET "DAC_SDI(4)" LOC = "K22" | IOSTANDARD=LVTTL;
16 NET "DAC_SDI(5)" LOC = "L22";
18 NET "DAC_SDI(5)" LOC = "L22" | IOSTANDARD=LVTTL;
17 NET "DAC_SDI(6)" LOC = "G19";
19 NET "DAC_SDI(6)" LOC = "G19" | IOSTANDARD=LVTTL;
18 NET "DAC_SDI(7)" LOC = "F20";
20 NET "DAC_SDI(7)" LOC = "F20" | IOSTANDARD=LVTTL;
19
21
20
22
21 NET "TDX" LOC = "V22";
23 NET "TXD" LOC = "V22"| slew=FAST | IOSTANDARD=LVTTL;
22 NET "RXD" LOC = "U22";
24 NET "RXD" LOC = "U22"| slew=FAST | IOSTANDARD=LVTTL;
23 NET "LED(0)" LOC = "AB9";
25 NET "LED(0)" LOC = "AB9"| slew=FAST | IOSTANDARD=LVTTL;
24 NET "LED(1)" LOC = "AB8";
26 NET "LED(1)" LOC = "AB8"| slew=FAST | IOSTANDARD=LVTTL;
25 NET "LED(2)" LOC = "AA8";
27 NET "LED(2)" LOC = "AA8"| slew=FAST | IOSTANDARD=LVTTL;
26
28
27 NET "urxd1" LOC = "D3"; # Unused PIN
29 NET "urxd1" LOC = "D3" | IOSTANDARD=LVTTL; # Unused PIN
28 NET "utxd1" LOC = "C4"; # Unused PIN No newline at end of file
30 NET "utxd1" LOC = "C4" | IOSTANDARD=LVTTL; # Unused PIN
31
32 NET "sdcke" LOC = "B6" | slew=FAST | IOSTANDARD=LVTTL; # clk en
33 NET "sdcsn" LOC = "G20"| slew=FAST | IOSTANDARD=LVTTL; # chip sel
34 NET "sdwen" LOC = "D14"| slew=FAST | IOSTANDARD=LVTTL; # write en
35 NET "sdrasn" LOC = "H19"| slew=FAST | IOSTANDARD=LVTTL; # row addr stb
36 NET "sdcasn" LOC = "C14"| slew=FAST | IOSTANDARD=LVTTL; # col addr stb
37
38 NET "sddqm(3)" LOC = "A5" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
39 NET "sddqm(2)" LOC = "D21"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
40 NET "sddqm(1)" LOC = "C7" | slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
41 NET "sddqm(0)" LOC = "D15"| slew=FAST | IOSTANDARD=LVTTL; # data i/o mask
42
43 NET "sdclk" CLOCK_DEDICATED_ROUTE = FALSE;
44 NET "sdclk" LOC = "A6" | slew=FAST | IOSTANDARD=LVTTL; # sdram clk output
45 NET "sdba(1)" LOC = "J20"| slew=FAST | IOSTANDARD=LVTTL; # bank select address
46 NET "sdba(0)" LOC = "G16"| slew=FAST | IOSTANDARD=LVTTL; # bank select address
47
48 NET "Address(11)" LOC = "H8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
49 NET "Address(10)" LOC = "G7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
50 NET "Address(9)" LOC = "K7"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
51 NET "Address(8)" LOC = "H6"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
52 NET "Address(7)" LOC = "H5"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
53 NET "Address(6)" LOC = "K8"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
54 NET "Address(5)" LOC = "G4"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
55 NET "Address(4)" LOC = "H3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
56 NET "Address(3)" LOC = "D2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
57 NET "Address(2)" LOC = "B3"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
58 NET "Address(1)" LOC = "A2"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
59 NET "Address(0)" LOC = "C22"| slew=FAST | IOSTANDARD=LVTTL; # sdram address
60
61 NET "Data(31)" LOC = "C5" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
62 NET "Data(30)" LOC = "A4" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
63 NET "Data(29)" LOC = "A3" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
64 NET "Data(28)" LOC = "B2" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
65 NET "Data(27)" LOC = "B1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
66 NET "Data(26)" LOC = "C1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
67 NET "Data(25)" LOC = "D1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
68 NET "Data(24)" LOC = "E1" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
69 NET "Data(23)" LOC = "J22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
70 NET "Data(22)" LOC = "H22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
71 NET "Data(21)" LOC = "H21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
72 NET "Data(20)" LOC = "G22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
73 NET "Data(19)" LOC = "F22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
74 NET "Data(18)" LOC = "F21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
75 NET "Data(17)" LOC = "E22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
76 NET "Data(16)" LOC = "D22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
77 NET "Data(15)" LOC = "A7" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
78 NET "Data(14)" LOC = "B8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
79 NET "Data(13)" LOC = "A8" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
80 NET "Data(12)" LOC = "C9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
81 NET "Data(11)" LOC = "A9" | slew=FAST | IOSTANDARD=LVTTL; # sdram data
82 NET "Data(10)" LOC = "B10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
83 NET "Data(9)" LOC = "A10"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
84 NET "Data(8)" LOC = "C11"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
85 NET "Data(7)" LOC = "A13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
86 NET "Data(6)" LOC = "C13"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
87 NET "Data(5)" LOC = "B22"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
88 NET "Data(4)" LOC = "B21"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
89 NET "Data(3)" LOC = "B20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
90 NET "Data(2)" LOC = "A20"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
91 NET "Data(1)" LOC = "B18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
92 NET "Data(0)" LOC = "A18"| slew=FAST | IOSTANDARD=LVTTL; # sdram data
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@@ -12,6 +12,8 use gaisler.memctrl.all;
12 use gaisler.leon3.all;
12 use gaisler.leon3.all;
13 use gaisler.uart.all;
13 use gaisler.uart.all;
14 use gaisler.misc.all;
14 use gaisler.misc.all;
15 library esa;
16 use esa.memoryctrl.all;
15 --use gaisler.sim.all;
17 --use gaisler.sim.all;
16 library lpp;
18 library lpp;
17 use lpp.lpp_ad_conv.all;
19 use lpp.lpp_ad_conv.all;
@@ -19,6 +21,9 use lpp.lpp_amba.all;
19 use lpp.apb_devices_list.all;
21 use lpp.apb_devices_list.all;
20 use lpp.general_purpose.all;
22 use lpp.general_purpose.all;
21
23
24 Library UNISIM;
25 use UNISIM.vcomponents.all;
26
22
27
23 use work.config.all;
28 use work.config.all;
24 --==================================================================
29 --==================================================================
@@ -54,14 +59,14 entity BeagleSynth is
54 ---- design from GRLIB, the IS42S32400E is similar to
59 ---- design from GRLIB, the IS42S32400E is similar to
55 ---- MT48LC4M32B2.
60 ---- MT48LC4M32B2.
56 --------------------------------------------------------
61 --------------------------------------------------------
57 sdcke : out std_logic_vector ( 1 downto 0); -- clk en
62 sdcke : out std_logic; -- clk en
58 sdcsn : out std_logic_vector ( 1 downto 0); -- chip sel
63 sdcsn : out std_logic; -- chip sel
59 sdwen : out std_logic; -- write en
64 sdwen : out std_logic; -- write en
60 sdrasn : out std_logic; -- row addr stb
65 sdrasn : out std_logic; -- row addr stb
61 sdcasn : out std_logic; -- col addr stb
66 sdcasn : out std_logic; -- col addr stb
62 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
67 sddqm : out std_logic_vector (3 downto 0); -- data i/o mask
63 sdclk : out std_logic; -- sdram clk output
68 sdclk : out std_logic; -- sdram clk output
64 sdba : out std_logic_vector (3 downto 0); -- bank select address
69 sdba : out std_logic_vector (1 downto 0); -- bank select address
65 Address : out std_logic_vector(11 downto 0); -- sdram address
70 Address : out std_logic_vector(11 downto 0); -- sdram address
66 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
71 Data : inout std_logic_vector(31 downto 0) -- optional sdram data
67 );
72 );
@@ -78,9 +83,11 signal clk2x : std_ulogic;
78 signal lclk : std_ulogic;
83 signal lclk : std_ulogic;
79 signal clkm : std_ulogic;
84 signal clkm : std_ulogic;
80 signal rstn : std_ulogic;
85 signal rstn : std_ulogic;
86 signal rst : std_ulogic;
81 signal rstraw : std_ulogic;
87 signal rstraw : std_ulogic;
82 signal pciclk : std_ulogic;
88 signal pciclk : std_ulogic;
83 signal sdclkl : std_ulogic;
89 signal sdclkl : std_ulogic;
90 signal sdclkl_DDR2 : std_ulogic;
84 signal cgi : clkgen_in_type;
91 signal cgi : clkgen_in_type;
85 signal cgo : clkgen_out_type;
92 signal cgo : clkgen_out_type;
86
93
@@ -93,9 +100,8 signal ahbmi : ahb_mst_in_type;
93 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
100 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
94
101
95 --- MEM CTRLR
102 --- MEM CTRLR
96 signal memi : memory_in_type;
103 signal sdi : sdctrl_in_type;
97 signal memo : memory_out_type;
104 signal sdo : sdctrl_out_type;
98 signal sdo : sdram_out_type;
99
105
100 --UART
106 --UART
101 signal ahbuarti : uart_in_type;
107 signal ahbuarti : uart_in_type;
@@ -112,15 +118,36 DAC_nCS <= '1';
112 CAL_IN_SCK <= '1';
118 CAL_IN_SCK <= '1';
113 DAC_SDI <= (others =>'1');
119 DAC_SDI <= (others =>'1');
114
120
115 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
121 resetn_pad : inpad generic map (tech => padtech) port map (reset, rst);
122 rst0 : rstgen port map (rst, lclk, '1', rstn, rstraw);
123 --rstn <= reset;
124 --lclk <= clk;
125 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk, lclk);
116
126
117 lclk <= clk;
127 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
128 clkgen0 : clkgen -- clock generator
129 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, CFG_CLK_NOFB, 0, 0, 0, boardfreq)
130 port map (lclk, lclk, clkm, open, open, sdclkl, open, cgi, cgo,open,open);
131
132 -- sdclk_pad : outpad generic map (tech => padtech) port map (sdclk, sdclkl_DDR2);
133 --sdclk <= sdclkl;
134 sdclk <= sdclkl_DDR2;
118
135
119 clkgen0 : clkgen -- clock generatorsa
136 ODDR2_inst : ODDR2
120 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
137 generic map(
121 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
138 DDR_ALIGNMENT => "C0", -- Sets output alignment to "NONE", "C0", "C1"
122 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
139 INIT => '0', -- Sets initial state of the Q output to '0' or '1'
123
140 SRTYPE => "ASYNC") -- Specifies "SYNC" or "ASYNC" set/reset
141 port map (
142 Q => sdclkl_DDR2, -- 1-bit output data
143 C0 => sdclkl, -- 1-bit clock input
144 C1 => not sdclkl, -- 1-bit clock input
145 CE => '1', -- 1-bit clock enable input
146 D0 => '1', -- 1-bit data input (associated with C0)
147 D1 => '0', -- 1-bit data input (associated with C1)
148 R => '0', -- 1-bit reset input
149 S => '0' -- 1-bit set input
150 );
124
151
125 ----------------------------------------------------------------------
152 ----------------------------------------------------------------------
126 --- AHB CONTROLLER -------------------------------------------------
153 --- AHB CONTROLLER -------------------------------------------------
@@ -142,7 +169,7 DAC_SDI <= (others =>'1');
142 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
169 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
143 ahbuarti.rxd <= RXD;
170 ahbuarti.rxd <= RXD;
144 TXD <= ahbuarto.txd;
171 TXD <= ahbuarto.txd;
145 led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
172 led(0) <= ahbuarti.rxd; led(1) <= ahbuarto.txd;
146 end generate;
173 end generate;
147 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
174 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
148
175
@@ -162,7 +189,7 DAC_SDI <= (others =>'1');
162 uart1 : apbuart -- UART 1
189 uart1 : apbuart -- UART 1
163 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
190 generic map (pindex => 1, paddr => 1, pirq => 2, console => CFG_DUART,
164 fifosize => CFG_UART1_FIFO)
191 fifosize => CFG_UART1_FIFO)
165 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
192 port map (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
166 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
193 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
167 apbuarti.ctsn <= '0';
194 apbuarti.ctsn <= '0';
168 end generate;
195 end generate;
@@ -189,37 +216,32 end process;
189
216
190
217
191
218
192 mctrl0 : mctrl generic map (srbanks => 4, sden => 1)
219 sdc : sdctrl
193 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wprot, sdo);
220 generic map (hindex => 0, haddr => 16#600#, hmask => 16#F00#,ioaddr => 1, pwron => 0,
221 invclk => 0,sdbits =>32)
222 port map (rstn, clkm, ahbsi, ahbso(0), sdi, sdo);
194
223
195 -- memory controller inputs not used in this configuration
224
196 memi.brdyn <= '1'; memi.bexcn <= '1'; memi.wrn <= "1111";
225
226 --Alternative data pad instantiation with vectored bdrive
227 sd_pad : iopadvv generic map (tech=> padtech,width => 32)
228 port map (
229 data(31 downto 0),
230 sdo.data(31 downto 0),
231 sdo.vbdrive(31 downto 0),
232 sdi.data(31 downto 0));
197
233
198 memi.sd <= Data;
234
199 -- prom width at reset
200 memi.bwidth <= "10";
201 -- I/O pads driving data memory bus data signals
202 datapads : for i in 0 to 3 generate
203 data_pad : iopadv generic map (width => 8)
204 port map (
205 pad => data(31-i*8 downto 24-i*8),
206 o => memi.data(31-i*8 downto 24-i*8),
207 en => memo.bdrive(i),
208 i => memo.data(31-i*8 downto 24-i*8)
209 );
210 end generate;
211 -- connect memory controller outputs to entity output signals
235 -- connect memory controller outputs to entity output signals
212 Address <= memo.sa(11 downto 0);
236 Address <= sdo.address(13 downto 2);
213 sdba <= memo.sa(13 downto 12);
237 sdba <= sdo.address(16 downto 15);
214 writen <= memo.writen; read <= memo.read; iosn <= memo.iosn;
238 sdcke <= sdo.sdcke(0);
215 sdcke <= sdo.sdcke;
216 sdwen <= sdo.sdwen;
239 sdwen <= sdo.sdwen;
217 sdcsn <= sdo.sdcsn;
240 sdcsn <= sdo.sdcsn(0);
218 sdrasn <= sdo.rasn;
241 sdrasn <= sdo.rasn;
219 sdcasn <= sdo.casn;
242 sdcasn <= sdo.casn;
220 sddqm <= sdo.dqm(3 downto 0);
243 sddqm <= sdo.dqm(3 downto 0);
221
244 --sdi.data(31 downto 0) <= data(31 downto 0);
222 end;
223
245
224
246
225
247
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@@ -44,3 +44,6 include $(GRLIB)/software/leon3/Makefile
44
44
45 flash:
45 flash:
46 xc3sprog -c ftdi -p 1 BeagleSynth.bit
46 xc3sprog -c ftdi -p 1 BeagleSynth.bit
47
48 ram:
49 xc3sprog -c ftdi -p 0 BeagleSynth.bit
Show file before | Show file after | Hide comments
@@ -58,14 +58,14 package config is
58
58
59 -- LEON2 memory controller
59 -- LEON2 memory controller
60 constant CFG_MCTRL_LEON2 : integer := 1;
60 constant CFG_MCTRL_LEON2 : integer := 1;
61 constant CFG_MCTRL_RAM8BIT : integer := 0;
61 constant CFG_MCTRL_RAM8BIT : integer := 1;
62 constant CFG_MCTRL_RAM16BIT : integer := 0;
62 constant CFG_MCTRL_RAM16BIT : integer := 0;
63 constant CFG_MCTRL_5CS : integer := 0;
63 constant CFG_MCTRL_5CS : integer := 0;
64 constant CFG_MCTRL_SDEN : integer := 0;
64 constant CFG_MCTRL_SDEN : integer := 1;
65 constant CFG_MCTRL_SEPBUS : integer := 0;
65 constant CFG_MCTRL_SEPBUS : integer := 0;
66 constant CFG_MCTRL_INVCLK : integer := 0;
66 constant CFG_MCTRL_INVCLK : integer := 0;
67 constant CFG_MCTRL_SD64 : integer := 0;
67 constant CFG_MCTRL_SD64 : integer := 0;
68 constant CFG_MCTRL_PAGE : integer := 0 + 0;
68 constant CFG_MCTRL_PAGE : integer := 1 + 0;
69
69
70 -- Gaisler Ethernet core
70 -- Gaisler Ethernet core
71 constant CFG_GRETH : integer := 0;
71 constant CFG_GRETH : integer := 0;
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