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(LFR-EM) WFP_MS-1-1-16
pellion -
r377:8f748b61300a (LFR-EM) WFP_MS_1-1-16 JC
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@@ -340,7 +340,7 BEGIN -- beh
340 -------------------------------------------------------------------------------
340 -------------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
343 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 lpp_lfr_1 : lpp_lfr
344 GENERIC MAP (
344 GENERIC MAP (
345 Mem_use => use_RAM,
345 Mem_use => use_RAM,
346 nb_data_by_buffer_size => 32,
346 nb_data_by_buffer_size => 32,
@@ -354,7 +354,7 BEGIN -- beh
354 pirq_ms => 6,
354 pirq_ms => 6,
355 pirq_wfp => 14,
355 pirq_wfp => 14,
356 hindex => 2,
356 hindex => 2,
357 top_lfr_version => X"00010B") -- aa.bb.cc version
357 top_lfr_version => X"010110") -- aa.bb.cc version
358 -- AA : BOARD NUMBER
358 -- AA : BOARD NUMBER
359 -- 0 => MINI_LFR
359 -- 0 => MINI_LFR
360 -- 1 => EM
360 -- 1 => EM
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@@ -426,7 +426,7 BEGIN -- beh
426 pirq_ms => 6,
426 pirq_ms => 6,
427 pirq_wfp => 14,
427 pirq_wfp => 14,
428 hindex => 2,
428 hindex => 2,
429 top_lfr_version => X"00010F") -- aa.bb.cc version
429 top_lfr_version => X"000110") -- aa.bb.cc version
430 PORT MAP (
430 PORT MAP (
431 clk => clk_25,
431 clk => clk_25,
432 rstn => reset,
432 rstn => reset,
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@@ -113,11 +113,22 ARCHITECTURE beh OF TB IS
113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115 SIGNAL apbi : apb_slv_in_type;
115 SIGNAL apbi : apb_slv_in_type;
116 SIGNAL apbo : apb_slv_out_type;
116 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120
121 --
122 SIGNAL ready_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
123 SIGNAL irq_ongoing : STD_LOGIC;
124 --
125 SIGNAL read_status : STD_LOGIC;
126 SIGNAL read_status_t : STD_LOGIC;
127
128
129 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
130 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
131
121 BEGIN -- beh
132 BEGIN -- beh
122
133
123 clk25MHz <= NOT clk25MHz AFTER 20 ns;
134 clk25MHz <= NOT clk25MHz AFTER 20 ns;
@@ -262,6 +273,11 BEGIN -- beh
262 error_input_fifo_write => error_input_fifo_write,
273 error_input_fifo_write => error_input_fifo_write,
263
274
264 debug_reg => debug_reg,
275 debug_reg => debug_reg,
276
277 --
278 observation_vector_0 => observation_vector_0,
279 observation_vector_1 => observation_vector_1,
280 --
265 status_ready_matrix_f0 => status_ready_matrix_f0,
281 status_ready_matrix_f0 => status_ready_matrix_f0,
266 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
282 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
267 status_ready_matrix_f1 => status_ready_matrix_f1,
283 status_ready_matrix_f1 => status_ready_matrix_f1,
@@ -281,7 +297,7 BEGIN -- beh
281
297
282
298
283
299
284 apbi.psel(4) <= '0';
300
285
301
286 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
302 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
287 GENERIC MAP (
303 GENERIC MAP (
@@ -301,7 +317,7 BEGIN -- beh
301 HCLK => clk25MHz,
317 HCLK => clk25MHz,
302 HRESETn => rstn,
318 HRESETn => rstn,
303 apbi => apbi,
319 apbi => apbi,
304 apbo => OPEN,
320 apbo => apbo,
305
321
306 run_ms => OPEN,
322 run_ms => OPEN,
307
323
@@ -359,8 +375,40 BEGIN -- beh
359
375
360
376
361
377
378 read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us;
362
379
380 PROCESS (clk25MHz, rstn)
381 BEGIN
382 IF rstn = '0' THEN
383 ready_reg <= (OTHERS => '0');
384 --read_status <= '0';
385 apbi.psel(4) <= '0';
386 apbi.pwrite <= '0';
387 apbi.penable <= '0';
388 apbi.paddr(7 DOWNTO 2) <= (OTHERS => '0');
389 ELSIF clk25MHz'event AND clk25MHz = '1' THEN
390 apbi.psel(4) <= '1';
391 apbi.paddr(7 DOWNTO 2) <= "000001";
392 apbi.penable <= '1';
393 read_status <= apbo.pirq(0);
363
394
395 IF read_status = '1' AND irq_ongoing = '0' THEN
396 ready_reg <= apbo.prdata(5 DOWNTO 0);
397 irq_ongoing <= '1';
398 END IF;
399
400 IF read_status_t = '0' THEN
401 apbi.pwrite <= '0';
402 ELSE
403 irq_ongoing <= '0';
404 apbi.pwrite <= '1';
405 apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0');
406 apbi.pwdata(5 DOWNTO 0) <= ready_reg;
407 ready_reg <= (OTHERS => '0');
408 END IF;
409
410 END IF;
411 END PROCESS;
364
412
365
413
366
414
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@@ -1,5 +1,23
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -expand -group debug -expand /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -expand -group debug -subitemconfig {/tb/lpp_lfr_apbreg_1/apbo.pirq {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -expand -group debug /tb/ready_reg
16 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -divider {New Divider}
3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
21 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
22 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
23 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
@@ -192,7 +210,7 add wave -noupdate /tb/lpp_lfr_apbreg_1/
192 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
210 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
193 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
211 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
194 TreeUpdate [SetDefaultTree]
212 TreeUpdate [SetDefaultTree]
195 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {30152624373 ps} 0} {{Cursor 3} {10666401890 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {87243365384 ps} 0}
213 WaveRestoreCursors {{Cursor 1} {123239471127 ps} 0}
196 configure wave -namecolwidth 486
214 configure wave -namecolwidth 486
197 configure wave -valuecolwidth 112
215 configure wave -valuecolwidth 112
198 configure wave -justifyvalue left
216 configure wave -justifyvalue left
@@ -207,6 +225,6 configure wave -griddelta 40
207 configure wave -timeline 0
225 configure wave -timeline 0
208 configure wave -timelineunits ps
226 configure wave -timelineunits ps
209 update
227 update
210 WaveRestoreZoom {0 ps} {105000147 ns}
228 WaveRestoreZoom {124629370639 ps} {125891337681 ps}
211 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
229 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
212 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
230 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
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@@ -61,6 +61,10 ENTITY lpp_lfr IS
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
69
66 --debug
70 --debug
@@ -284,6 +288,7 ARCHITECTURE beh OF lpp_lfr IS
284 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
285
289
286 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
287
292
288 BEGIN
293 BEGIN
289
294
@@ -395,7 +400,8 BEGIN
395 addr_data_f1 => addr_data_f1,
400 addr_data_f1 => addr_data_f1,
396 addr_data_f2 => addr_data_f2,
401 addr_data_f2 => addr_data_f2,
397 addr_data_f3 => addr_data_f3,
402 addr_data_f3 => addr_data_f3,
398 start_date => start_date);
403 start_date => start_date,
404 debug_signal => debug_signal);
399
405
400 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
401 -----------------------------------------------------------------------------
407 -----------------------------------------------------------------------------
@@ -710,6 +716,8 BEGIN
710 error_input_fifo_write => error_input_fifo_write,
716 error_input_fifo_write => error_input_fifo_write,
711
717
712 debug_reg => debug_ms,--observation_reg,
718 debug_reg => debug_ms,--observation_reg,
719 observation_vector_0 => observation_vector_0,
720 observation_vector_1 => observation_vector_1,
713
721
714 status_ready_matrix_f0 => status_ready_matrix_f0,
722 status_ready_matrix_f0 => status_ready_matrix_f0,
715 status_ready_matrix_f1 => status_ready_matrix_f1,
723 status_ready_matrix_f1 => status_ready_matrix_f1,
@@ -725,11 +733,16 BEGIN
725 matrix_time_f2 => matrix_time_f2);
733 matrix_time_f2 => matrix_time_f2);
726
734
727 -----------------------------------------------------------------------------
735 -----------------------------------------------------------------------------
728 observation_reg(31 DOWNTO 0) <= debug_ms(31-9 DOWNTO 0) &
736
729 dma_ms_ongoing & -- 8
737
730 data_ms_done & -- 7
738 observation_reg(31 DOWNTO 0) <=
731 dma_done & -- 6
739 dma_sel(4) & -- 31
732 dma_sel & -- 5 .. 1
740 dma_ms_ongoing & -- 30
733 ms_softandhard_rstn; -- 0
741 data_ms_done & -- 29
742 dma_done & -- 28
743 ms_softandhard_rstn & --27
744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
734
747
735 END beh;
748 END beh;
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@@ -127,7 +127,9 ENTITY lpp_lfr_apbreg IS
127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 ---------------------------------------------------------------------------
132 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
131 ---------------------------------------------------------------------------
133 ---------------------------------------------------------------------------
132 );
134 );
133
135
@@ -140,7 +142,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
140 CONSTANT pconfig : apb_config_type := (
142 CONSTANT pconfig : apb_config_type := (
141 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
143 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
142 1 => apb_iobar(paddr, pmask));
144 1 => apb_iobar(paddr, pmask));
143
145
144 TYPE lpp_SpectralMatrix_regs IS RECORD
146 TYPE lpp_SpectralMatrix_regs IS RECORD
145 config_active_interruption_onNewMatrix : STD_LOGIC;
147 config_active_interruption_onNewMatrix : STD_LOGIC;
146 config_active_interruption_onError : STD_LOGIC;
148 config_active_interruption_onError : STD_LOGIC;
@@ -154,20 +156,20 ARCHITECTURE beh OF lpp_lfr_apbreg IS
154 status_error_bad_component_error : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
155 status_error_buffer_full : STD_LOGIC;
157 status_error_buffer_full : STD_LOGIC;
156 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
158 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
157
159
158 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164
166
165 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
167 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
166 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
167 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 END RECORD;
173 END RECORD;
172 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
174 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
173
175
@@ -222,26 +224,28 ARCHITECTURE beh OF lpp_lfr_apbreg IS
222 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
224 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
223 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
226 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
225
227
226 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
228 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
227 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229
231
230 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
232 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
231 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
233 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233
235
234 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
236 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
235 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237
239
238 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
240 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
239 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241
243
242 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
244 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
243 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
245 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 SIGNAL apbo_irq_ms : STD_LOGIC;
248 SIGNAL apbo_irq_wfp : STD_LOGIC;
245
249
246 BEGIN -- beh
250 BEGIN -- beh
247
251
@@ -251,8 +255,8 BEGIN -- beh
251
255
252 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
256 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
253 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
257 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
254
258
255
259
256 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
260 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
257 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
261 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
258 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
262 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
@@ -315,18 +319,21 BEGIN -- beh
315 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
319 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
316 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
320 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
317 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
321 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
318
322
319 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
323 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
320 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
324 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
321 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
322
326
323 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
327 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
324 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
328 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
329 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
326
330
327 prdata <= (OTHERS => '0');
331 prdata <= (OTHERS => '0');
328
332
329 apbo.pirq <= (OTHERS => '0');
333
334 apbo_irq_ms <= '0';
335 apbo_irq_wfp <= '0';
336
330
337
331 status_full_ack <= (OTHERS => '0');
338 status_full_ack <= (OTHERS => '0');
332
339
@@ -392,21 +399,21 BEGIN -- beh
392 IF apbi.psel(pindex) = '1' THEN
399 IF apbi.psel(pindex) = '1' THEN
393 -- APB DMA READ --
400 -- APB DMA READ --
394 CASE paddr(7 DOWNTO 2) IS
401 CASE paddr(7 DOWNTO 2) IS
395 --0
402 --0
396 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
403 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
397 prdata(1) <= reg_sp.config_active_interruption_onError;
404 prdata(1) <= reg_sp.config_active_interruption_onError;
398 prdata(2) <= reg_sp.config_ms_run;
405 prdata(2) <= reg_sp.config_ms_run;
399 --1
406 --1
400 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
407 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
401 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
408 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
402 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
409 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
403 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
410 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
404 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
411 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
405 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
412 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
406 prdata(6) <= reg_sp.status_error_bad_component_error;
413 prdata(6) <= reg_sp.status_error_bad_component_error;
407 prdata(7) <= reg_sp.status_error_buffer_full;
414 prdata(7) <= reg_sp.status_error_buffer_full;
408 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
415 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
409 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
416 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
410 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
417 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
411 --2
418 --2
412 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
419 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
@@ -423,30 +430,30 BEGIN -- beh
423 --8
430 --8
424 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
431 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
425 --9
432 --9
426 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
433 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
427 --10
434 --10
428 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
435 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
429 --11
436 --11
430 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
437 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
431 --12
438 --12
432 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
439 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
433 --13
440 --13
434 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
441 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
435 --14
442 --14
436 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
443 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
437 --15
444 --15
438 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
445 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
439 --16
446 --16
440 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
447 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
441 --17
448 --17
442 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
449 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
443 --18
450 --18
444 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
451 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
445 --19
452 --19
446 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
453 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
447 ---------------------------------------------------------------------
454 ---------------------------------------------------------------------
448 --20
455 --20
449 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
456 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
450 prdata(1) <= reg_wp.data_shaping_SP0;
457 prdata(1) <= reg_wp.data_shaping_SP0;
451 prdata(2) <= reg_wp.data_shaping_SP1;
458 prdata(2) <= reg_wp.data_shaping_SP1;
452 prdata(3) <= reg_wp.data_shaping_R0;
459 prdata(3) <= reg_wp.data_shaping_R0;
@@ -500,26 +507,28 BEGIN -- beh
500 CASE paddr(7 DOWNTO 2) IS
507 CASE paddr(7 DOWNTO 2) IS
501 --
508 --
502 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
509 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
503 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
510 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
504 reg_sp.config_ms_run <= apbi.pwdata(2);
511 reg_sp.config_ms_run <= apbi.pwdata(2);
505 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
512
506 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
513 WHEN "000001" =>
507 reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2);
514 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
508 reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3);
515 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
509 reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4);
516 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
510 reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5);
517 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
511 reg_sp.status_error_bad_component_error <= apbi.pwdata(6);
518 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
512 reg_sp.status_error_buffer_full <= apbi.pwdata(7);
519 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
513 reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8);
520 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
514 reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9);
521 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
515 reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10);
522 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
516 --2
523 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
517 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
524 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
518 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
525 --2
519 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
526 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
520 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
527 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
521 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
528 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
522 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
529 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
530 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
531 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
523 --8 to 19
532 --8 to 19
524 --20
533 --20
525 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
534 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
@@ -562,8 +571,8 BEGIN -- beh
562 END CASE;
571 END CASE;
563 END IF;
572 END IF;
564 END IF;
573 END IF;
565
574 --apbo.pirq(pirq_ms) <=
566 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
575 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
567 ready_matrix_f1 OR
576 ready_matrix_f1 OR
568 ready_matrix_f2)
577 ready_matrix_f2)
569 )
578 )
@@ -575,12 +584,15 BEGIN -- beh
575 OR error_input_fifo_write(1)
584 OR error_input_fifo_write(1)
576 OR error_input_fifo_write(2))
585 OR error_input_fifo_write(2))
577 ));
586 ));
578
587 -- apbo.pirq(pirq_wfp)
579 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
588 apbo_irq_wfp<= ored_irq_wfp;
580
589
581 END IF;
590 END IF;
582 END PROCESS lpp_lfr_apbreg;
591 END PROCESS lpp_lfr_apbreg;
583
592
593 apbo.pirq(pirq_ms) <= apbo_irq_ms;
594 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
595
584 apbo.pindex <= pindex;
596 apbo.pindex <= pindex;
585 apbo.pconfig <= pconfig;
597 apbo.pconfig <= pconfig;
586 apbo.prdata <= prdata;
598 apbo.prdata <= prdata;
@@ -618,18 +630,18 BEGIN -- beh
618
630
619 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
631 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
620 reg0_ready_matrix => reg0_ready_matrix_f0,
632 reg0_ready_matrix => reg0_ready_matrix_f0,
621 reg0_addr_matrix => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0,
633 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
622 reg0_matrix_time => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0,
634 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
623
635
624 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
636 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
625 reg1_ready_matrix => reg1_ready_matrix_f0,
637 reg1_ready_matrix => reg1_ready_matrix_f0,
626 reg1_addr_matrix => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0,
638 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
627 reg1_matrix_time => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0,
639 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
628
640
629 ready_matrix => ready_matrix_f0,
641 ready_matrix => ready_matrix_f0,
630 status_ready_matrix => status_ready_matrix_f0,
642 status_ready_matrix => status_ready_matrix_f0,
631 addr_matrix => addr_matrix_f0,
643 addr_matrix => addr_matrix_f0,
632 matrix_time => matrix_time_f0);
644 matrix_time => matrix_time_f0);
633
645
634 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
646 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
635 PORT MAP (
647 PORT MAP (
@@ -638,19 +650,19 BEGIN -- beh
638
650
639 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
651 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
640 reg0_ready_matrix => reg0_ready_matrix_f1,
652 reg0_ready_matrix => reg0_ready_matrix_f1,
641 reg0_addr_matrix => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1,
653 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
642 reg0_matrix_time => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1,
654 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
643
655
644 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
656 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
645 reg1_ready_matrix => reg1_ready_matrix_f1,
657 reg1_ready_matrix => reg1_ready_matrix_f1,
646 reg1_addr_matrix => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1,
658 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
647 reg1_matrix_time => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1,
659 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
648
660
649 ready_matrix => ready_matrix_f1,
661 ready_matrix => ready_matrix_f1,
650 status_ready_matrix => status_ready_matrix_f1,
662 status_ready_matrix => status_ready_matrix_f1,
651 addr_matrix => addr_matrix_f1,
663 addr_matrix => addr_matrix_f1,
652 matrix_time => matrix_time_f1);
664 matrix_time => matrix_time_f1);
653
665
654 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
666 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
655 PORT MAP (
667 PORT MAP (
656 clk => HCLK,
668 clk => HCLK,
@@ -658,18 +670,28 BEGIN -- beh
658
670
659 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
671 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
660 reg0_ready_matrix => reg0_ready_matrix_f2,
672 reg0_ready_matrix => reg0_ready_matrix_f2,
661 reg0_addr_matrix => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2,
673 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
662 reg0_matrix_time => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2,
674 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
663
675
664 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
676 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
665 reg1_ready_matrix => reg1_ready_matrix_f2,
677 reg1_ready_matrix => reg1_ready_matrix_f2,
666 reg1_addr_matrix => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2,
678 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
667 reg1_matrix_time => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2,
679 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
680
681 ready_matrix => ready_matrix_f2,
682 status_ready_matrix => status_ready_matrix_f2,
683 addr_matrix => addr_matrix_f2,
684 matrix_time => matrix_time_f2);
668
685
669 ready_matrix => ready_matrix_f2,
686 -----------------------------------------------------------------------------
670 status_ready_matrix => status_ready_matrix_f2,
687 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
671 addr_matrix => addr_matrix_f2,
688 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
672 matrix_time => matrix_time_f2);
689 reg_sp.status_error_input_fifo_write(2) &--10
673
690 reg_sp.status_error_input_fifo_write(1) &--9
674
691 reg_sp.status_error_input_fifo_write(0) &--8
692 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
693 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
694 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
695 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
696
675 END beh;
697 END beh;
Show file before | Show file after | Hide comments
@@ -57,6 +57,9 ENTITY lpp_lfr_ms IS
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
58
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
60
63
61 -- Reg In
64 -- Reg In
62 status_ready_matrix_f0 : IN STD_LOGIC;
65 status_ready_matrix_f0 : IN STD_LOGIC;
@@ -570,6 +573,14 BEGIN
570 fft_data_valid => fft_data_valid,
573 fft_data_valid => fft_data_valid,
571 fft_ready => fft_ready);
574 fft_ready => fft_ready);
572
575
576 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
577 fft_data_valid & --4
578 fft_pong & --3
579 sample_load & --2
580 fft_read & --1
581 sample_valid; --0
582
583
573 -----------------------------------------------------------------------------
584 -----------------------------------------------------------------------------
574 PROCESS (clk, rstn)
585 PROCESS (clk, rstn)
575 BEGIN
586 BEGIN
@@ -638,6 +649,8 BEGIN
638 (fft_data_im & fft_data_re) &
649 (fft_data_im & fft_data_re) &
639 (fft_data_im & fft_data_re) &
650 (fft_data_im & fft_data_re) &
640 (fft_data_im & fft_data_re);
651 (fft_data_im & fft_data_re);
652 -----------------------------------------------------------------------------
653
641
654
642 -----------------------------------------------------------------------------
655 -----------------------------------------------------------------------------
643 Mem_In_SpectralMatrix : lppFIFOxN
656 Mem_In_SpectralMatrix : lppFIFOxN
Show file before | Show file after | Hide comments
@@ -46,12 +46,12 ENTITY lpp_lfr_ms_fsmdma IS
46
46
47 ---------------------------------------------------------------------------
47 ---------------------------------------------------------------------------
48 -- FIFO - IN
48 -- FIFO - IN
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
53 fifo_empty : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55
55
56 ---------------------------------------------------------------------------
56 ---------------------------------------------------------------------------
57 -- DMA - OUT
57 -- DMA - OUT
@@ -64,7 +64,7 ENTITY lpp_lfr_ms_fsmdma IS
64
64
65 ---------------------------------------------------------------------------
65 ---------------------------------------------------------------------------
66 -- Reg out
66 -- Reg out
67 ready_matrix_f0 : OUT STD_LOGIC;
67 ready_matrix_f0 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
70
70
@@ -73,13 +73,13 ENTITY lpp_lfr_ms_fsmdma IS
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- Reg In
75 -- Reg In
76 status_ready_matrix_f0 : IN STD_LOGIC;
76 status_ready_matrix_f0 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85
85
@@ -190,7 +190,7 BEGIN
190
190
191
191
192
192
193 ready_matrix_f0 <= '0';
193 ready_matrix_f0 <= '0';
194 ready_matrix_f1 <= '0';
194 ready_matrix_f1 <= '0';
195 ready_matrix_f2 <= '0';
195 ready_matrix_f2 <= '0';
196 error_bad_component_error <= '0';
196 error_bad_component_error <= '0';
@@ -215,7 +215,7 BEGIN
215 IF component_type = "0000" THEN
215 IF component_type = "0000" THEN
216 address <= address_matrix;
216 address <= address_matrix;
217 CASE matrix_type IS
217 CASE matrix_type IS
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
221 WHEN OTHERS => NULL;
221 WHEN OTHERS => NULL;
@@ -233,7 +233,8 BEGIN
233
233
234 WHEN TRASH_FIFO =>
234 WHEN TRASH_FIFO =>
235 debug_reg_s(2 DOWNTO 0) <= "100";
235 debug_reg_s(2 DOWNTO 0) <= "100";
236
236
237 error_buffer_full <= '0';
237 error_bad_component_error <= '0';
238 error_bad_component_error <= '0';
238 IF fifo_empty = '1' THEN
239 IF fifo_empty = '1' THEN
239 state <= IDLE;
240 state <= IDLE;
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@@ -103,6 +103,10 PACKAGE lpp_lfr_pkg IS
103 error_buffer_full : OUT STD_LOGIC;
103 error_buffer_full : OUT STD_LOGIC;
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
109 -------------------------------------------------------------------------
106 status_ready_matrix_f0 : IN STD_LOGIC;
110 status_ready_matrix_f0 : IN STD_LOGIC;
107 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
108 status_ready_matrix_f1 : IN STD_LOGIC;
112 status_ready_matrix_f1 : IN STD_LOGIC;
@@ -239,6 +243,9 PACKAGE lpp_lfr_pkg IS
239 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
240 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
244 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
241 data_shaping_BW : OUT STD_LOGIC;
245 data_shaping_BW : OUT STD_LOGIC;
246 --
247 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
248 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
242 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
249 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
243 );
250 );
244 END COMPONENT;
251 END COMPONENT;
@@ -345,7 +352,10 PACKAGE lpp_lfr_pkg IS
345 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
346 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
347 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
348 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
355 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
356
357 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
358
349 );
359 );
350 END COMPONENT;
360 END COMPONENT;
351
361
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