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(LFR-EM) WFP_MS-1-1-16
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r377:8f748b61300a (LFR-EM) WFP_MS_1-1-16 JC
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY LFR_em IS
48 ENTITY LFR_em IS
49
49
50 PORT (
50 PORT (
51 clk100MHz : IN STD_ULOGIC;
51 clk100MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
52 clk49_152MHz : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
53 reset : IN STD_ULOGIC;
54
54
55 -- TAG --------------------------------------------------------------------
55 -- TAG --------------------------------------------------------------------
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
56 TAG1 : IN STD_ULOGIC; -- DSU rx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
57 TAG3 : OUT STD_ULOGIC; -- DSU tx data
58 -- UART APB ---------------------------------------------------------------
58 -- UART APB ---------------------------------------------------------------
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
59 TAG2 : IN STD_ULOGIC; -- UART1 rx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
60 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
61 -- RAM --------------------------------------------------------------------
61 -- RAM --------------------------------------------------------------------
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
62 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
63 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 nSRAM_BE0 : OUT STD_LOGIC;
64 nSRAM_BE0 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
65 nSRAM_BE1 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
66 nSRAM_BE2 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
67 nSRAM_BE3 : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
68 nSRAM_WE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
69 nSRAM_CE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
70 nSRAM_OE : OUT STD_LOGIC;
71 -- SPW --------------------------------------------------------------------
71 -- SPW --------------------------------------------------------------------
72 spw1_din : IN STD_LOGIC;
72 spw1_din : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
73 spw1_sin : IN STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
74 spw1_dout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
75 spw1_sout : OUT STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
76 spw2_din : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
77 spw2_sin : IN STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
78 spw2_dout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
79 spw2_sout : OUT STD_LOGIC;
80 -- ADC --------------------------------------------------------------------
80 -- ADC --------------------------------------------------------------------
81 bias_fail_sw : OUT STD_LOGIC;
81 bias_fail_sw : OUT STD_LOGIC;
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
82 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
83 ADC_smpclk : OUT STD_LOGIC;
83 ADC_smpclk : OUT STD_LOGIC;
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
84 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 TAG8 : OUT STD_LOGIC;
86 TAG8 : OUT STD_LOGIC;
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
87 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
88 );
88 );
89
89
90 END LFR_em;
90 END LFR_em;
91
91
92
92
93 ARCHITECTURE beh OF LFR_em IS
93 ARCHITECTURE beh OF LFR_em IS
94 SIGNAL clk_50_s : STD_LOGIC := '0';
94 SIGNAL clk_50_s : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
95 SIGNAL clk_25 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
96 SIGNAL clk_24 : STD_LOGIC := '0';
97 -----------------------------------------------------------------------------
97 -----------------------------------------------------------------------------
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
100
100
101 -- CONSTANTS
101 -- CONSTANTS
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
102 CONSTANT CFG_PADTECH : INTEGER := inferred;
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
103 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
104 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
105 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
106
106
107 SIGNAL apbi_ext : apb_slv_in_type;
107 SIGNAL apbi_ext : apb_slv_in_type;
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
108 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
109 SIGNAL ahbi_s_ext : ahb_slv_in_type;
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
110 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
111 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
112 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
113
113
114 -- Spacewire signals
114 -- Spacewire signals
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
118 SIGNAL spw_rxtxclk : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
119 SIGNAL spw_rxclkn : STD_ULOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
120 SIGNAL spw_clk : STD_LOGIC;
121 SIGNAL swni : grspw_in_type;
121 SIGNAL swni : grspw_in_type;
122 SIGNAL swno : grspw_out_type;
122 SIGNAL swno : grspw_out_type;
123
123
124 --GPIO
124 --GPIO
125 SIGNAL gpioi : gpio_in_type;
125 SIGNAL gpioi : gpio_in_type;
126 SIGNAL gpioo : gpio_out_type;
126 SIGNAL gpioo : gpio_out_type;
127
127
128 -- AD Converter ADS7886
128 -- AD Converter ADS7886
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
129 SIGNAL sample : Samples14v(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
130 SIGNAL sample_s : Samples(7 DOWNTO 0);
131 SIGNAL sample_val : STD_LOGIC;
131 SIGNAL sample_val : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
132 SIGNAL ADC_nCS_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
133 SIGNAL ADC_CLK_sig : STD_LOGIC;
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
134 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
135
135
136 -----------------------------------------------------------------------------
136 -----------------------------------------------------------------------------
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
137 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
138
138
139 -----------------------------------------------------------------------------
139 -----------------------------------------------------------------------------
140 SIGNAL rstn : STD_LOGIC;
140 SIGNAL rstn : STD_LOGIC;
141 BEGIN -- beh
141 BEGIN -- beh
142
142
143 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
144 -- CLK
144 -- CLK
145 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
146 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
146 rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
147
147
148 PROCESS(clk100MHz)
148 PROCESS(clk100MHz)
149 BEGIN
149 BEGIN
150 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
150 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
151 clk_50_s <= NOT clk_50_s;
151 clk_50_s <= NOT clk_50_s;
152 END IF;
152 END IF;
153 END PROCESS;
153 END PROCESS;
154
154
155 PROCESS(clk_50_s)
155 PROCESS(clk_50_s)
156 BEGIN
156 BEGIN
157 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
157 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
158 clk_25 <= NOT clk_25;
158 clk_25 <= NOT clk_25;
159 END IF;
159 END IF;
160 END PROCESS;
160 END PROCESS;
161
161
162 PROCESS(clk49_152MHz)
162 PROCESS(clk49_152MHz)
163 BEGIN
163 BEGIN
164 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
164 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
165 clk_24 <= NOT clk_24;
165 clk_24 <= NOT clk_24;
166 END IF;
166 END IF;
167 END PROCESS;
167 END PROCESS;
168
168
169 -----------------------------------------------------------------------------
169 -----------------------------------------------------------------------------
170
170
171 PROCESS (clk_25, rstn)
171 PROCESS (clk_25, rstn)
172 BEGIN -- PROCESS
172 BEGIN -- PROCESS
173 IF rstn = '0' THEN -- asynchronous reset (active low)
173 IF rstn = '0' THEN -- asynchronous reset (active low)
174 led(0) <= '0';
174 led(0) <= '0';
175 led(1) <= '0';
175 led(1) <= '0';
176 led(2) <= '0';
176 led(2) <= '0';
177 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
177 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
178 led(0) <= '0';
178 led(0) <= '0';
179 led(1) <= '1';
179 led(1) <= '1';
180 led(2) <= '1';
180 led(2) <= '1';
181 END IF;
181 END IF;
182 END PROCESS;
182 END PROCESS;
183
183
184 --
184 --
185 leon3_soc_1 : leon3_soc
185 leon3_soc_1 : leon3_soc
186 GENERIC MAP (
186 GENERIC MAP (
187 fabtech => apa3e,
187 fabtech => apa3e,
188 memtech => apa3e,
188 memtech => apa3e,
189 padtech => inferred,
189 padtech => inferred,
190 clktech => inferred,
190 clktech => inferred,
191 disas => 0,
191 disas => 0,
192 dbguart => 0,
192 dbguart => 0,
193 pclow => 2,
193 pclow => 2,
194 clk_freq => 25000,
194 clk_freq => 25000,
195 NB_CPU => 1,
195 NB_CPU => 1,
196 ENABLE_FPU => 1,
196 ENABLE_FPU => 1,
197 FPU_NETLIST => 0,
197 FPU_NETLIST => 0,
198 ENABLE_DSU => 1,
198 ENABLE_DSU => 1,
199 ENABLE_AHB_UART => 1,
199 ENABLE_AHB_UART => 1,
200 ENABLE_APB_UART => 1,
200 ENABLE_APB_UART => 1,
201 ENABLE_IRQMP => 1,
201 ENABLE_IRQMP => 1,
202 ENABLE_GPT => 1,
202 ENABLE_GPT => 1,
203 NB_AHB_MASTER => NB_AHB_MASTER,
203 NB_AHB_MASTER => NB_AHB_MASTER,
204 NB_AHB_SLAVE => NB_AHB_SLAVE,
204 NB_AHB_SLAVE => NB_AHB_SLAVE,
205 NB_APB_SLAVE => NB_APB_SLAVE)
205 NB_APB_SLAVE => NB_APB_SLAVE)
206 PORT MAP (
206 PORT MAP (
207 clk => clk_25,
207 clk => clk_25,
208 reset => rstn,
208 reset => rstn,
209 errorn => OPEN,
209 errorn => OPEN,
210
210
211 ahbrxd => TAG1,
211 ahbrxd => TAG1,
212 ahbtxd => TAG3,
212 ahbtxd => TAG3,
213 urxd1 => TAG2,
213 urxd1 => TAG2,
214 utxd1 => TAG4,
214 utxd1 => TAG4,
215
215
216 address => address,
216 address => address,
217 data => data,
217 data => data,
218 nSRAM_BE0 => nSRAM_BE0,
218 nSRAM_BE0 => nSRAM_BE0,
219 nSRAM_BE1 => nSRAM_BE1,
219 nSRAM_BE1 => nSRAM_BE1,
220 nSRAM_BE2 => nSRAM_BE2,
220 nSRAM_BE2 => nSRAM_BE2,
221 nSRAM_BE3 => nSRAM_BE3,
221 nSRAM_BE3 => nSRAM_BE3,
222 nSRAM_WE => nSRAM_WE,
222 nSRAM_WE => nSRAM_WE,
223 nSRAM_CE => nSRAM_CE,
223 nSRAM_CE => nSRAM_CE,
224 nSRAM_OE => nSRAM_OE,
224 nSRAM_OE => nSRAM_OE,
225
225
226 apbi_ext => apbi_ext,
226 apbi_ext => apbi_ext,
227 apbo_ext => apbo_ext,
227 apbo_ext => apbo_ext,
228 ahbi_s_ext => ahbi_s_ext,
228 ahbi_s_ext => ahbi_s_ext,
229 ahbo_s_ext => ahbo_s_ext,
229 ahbo_s_ext => ahbo_s_ext,
230 ahbi_m_ext => ahbi_m_ext,
230 ahbi_m_ext => ahbi_m_ext,
231 ahbo_m_ext => ahbo_m_ext);
231 ahbo_m_ext => ahbo_m_ext);
232
232
233
233
234 -------------------------------------------------------------------------------
234 -------------------------------------------------------------------------------
235 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
235 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
236 -------------------------------------------------------------------------------
236 -------------------------------------------------------------------------------
237 apb_lfr_time_management_1 : apb_lfr_time_management
237 apb_lfr_time_management_1 : apb_lfr_time_management
238 GENERIC MAP (
238 GENERIC MAP (
239 pindex => 6,
239 pindex => 6,
240 paddr => 6,
240 paddr => 6,
241 pmask => 16#fff#,
241 pmask => 16#fff#,
242 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
242 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
243 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
243 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
244 PORT MAP (
244 PORT MAP (
245 clk25MHz => clk_25,
245 clk25MHz => clk_25,
246 clk24_576MHz => clk_24, -- 49.152MHz/2
246 clk24_576MHz => clk_24, -- 49.152MHz/2
247 resetn => rstn,
247 resetn => rstn,
248 grspw_tick => swno.tickout,
248 grspw_tick => swno.tickout,
249 apbi => apbi_ext,
249 apbi => apbi_ext,
250 apbo => apbo_ext(6),
250 apbo => apbo_ext(6),
251 coarse_time => coarse_time,
251 coarse_time => coarse_time,
252 fine_time => fine_time);
252 fine_time => fine_time);
253
253
254 -----------------------------------------------------------------------
254 -----------------------------------------------------------------------
255 --- SpaceWire --------------------------------------------------------
255 --- SpaceWire --------------------------------------------------------
256 -----------------------------------------------------------------------
256 -----------------------------------------------------------------------
257
257
258 -- SPW_EN <= '1';
258 -- SPW_EN <= '1';
259
259
260 spw_clk <= clk_50_s;
260 spw_clk <= clk_50_s;
261 spw_rxtxclk <= spw_clk;
261 spw_rxtxclk <= spw_clk;
262 spw_rxclkn <= NOT spw_rxtxclk;
262 spw_rxclkn <= NOT spw_rxtxclk;
263
263
264 -- PADS for SPW1
264 -- PADS for SPW1
265 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
265 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
266 PORT MAP (spw1_din, dtmp(0));
266 PORT MAP (spw1_din, dtmp(0));
267 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
267 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
268 PORT MAP (spw1_sin, stmp(0));
268 PORT MAP (spw1_sin, stmp(0));
269 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
269 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
270 PORT MAP (spw1_dout, swno.d(0));
270 PORT MAP (spw1_dout, swno.d(0));
271 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
271 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
272 PORT MAP (spw1_sout, swno.s(0));
272 PORT MAP (spw1_sout, swno.s(0));
273 -- PADS FOR SPW2
273 -- PADS FOR SPW2
274 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
274 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
275 PORT MAP (spw2_sin, dtmp(1));
275 PORT MAP (spw2_sin, dtmp(1));
276 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
276 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
277 PORT MAP (spw2_din, stmp(1));
277 PORT MAP (spw2_din, stmp(1));
278 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
278 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
279 PORT MAP (spw2_dout, swno.d(1));
279 PORT MAP (spw2_dout, swno.d(1));
280 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
280 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
281 PORT MAP (spw2_sout, swno.s(1));
281 PORT MAP (spw2_sout, swno.s(1));
282
282
283 -- GRSPW PHY
283 -- GRSPW PHY
284 --spw1_input: if CFG_SPW_GRSPW = 1 generate
284 --spw1_input: if CFG_SPW_GRSPW = 1 generate
285 spw_inputloop : FOR j IN 0 TO 1 GENERATE
285 spw_inputloop : FOR j IN 0 TO 1 GENERATE
286 spw_phy0 : grspw_phy
286 spw_phy0 : grspw_phy
287 GENERIC MAP(
287 GENERIC MAP(
288 tech => apa3e,
288 tech => apa3e,
289 rxclkbuftype => 1,
289 rxclkbuftype => 1,
290 scantest => 0)
290 scantest => 0)
291 PORT MAP(
291 PORT MAP(
292 rxrst => swno.rxrst,
292 rxrst => swno.rxrst,
293 di => dtmp(j),
293 di => dtmp(j),
294 si => stmp(j),
294 si => stmp(j),
295 rxclko => spw_rxclk(j),
295 rxclko => spw_rxclk(j),
296 do => swni.d(j),
296 do => swni.d(j),
297 ndo => swni.nd(j*5+4 DOWNTO j*5),
297 ndo => swni.nd(j*5+4 DOWNTO j*5),
298 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
298 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
299 END GENERATE spw_inputloop;
299 END GENERATE spw_inputloop;
300
300
301 -- SPW core
301 -- SPW core
302 sw0 : grspwm GENERIC MAP(
302 sw0 : grspwm GENERIC MAP(
303 tech => apa3e,
303 tech => apa3e,
304 hindex => 1,
304 hindex => 1,
305 pindex => 5,
305 pindex => 5,
306 paddr => 5,
306 paddr => 5,
307 pirq => 11,
307 pirq => 11,
308 sysfreq => 25000, -- CPU_FREQ
308 sysfreq => 25000, -- CPU_FREQ
309 rmap => 1,
309 rmap => 1,
310 rmapcrc => 1,
310 rmapcrc => 1,
311 fifosize1 => 16,
311 fifosize1 => 16,
312 fifosize2 => 16,
312 fifosize2 => 16,
313 rxclkbuftype => 1,
313 rxclkbuftype => 1,
314 rxunaligned => 0,
314 rxunaligned => 0,
315 rmapbufs => 4,
315 rmapbufs => 4,
316 ft => 0,
316 ft => 0,
317 netlist => 0,
317 netlist => 0,
318 ports => 2,
318 ports => 2,
319 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
319 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
320 memtech => apa3e,
320 memtech => apa3e,
321 destkey => 2,
321 destkey => 2,
322 spwcore => 1
322 spwcore => 1
323 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
323 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
324 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
324 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
325 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
325 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
326 )
326 )
327 PORT MAP(rstn, clk_25, spw_rxclk(0),
327 PORT MAP(rstn, clk_25, spw_rxclk(0),
328 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
328 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
329 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
329 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
330 swni, swno);
330 swni, swno);
331
331
332 swni.tickin <= '0';
332 swni.tickin <= '0';
333 swni.rmapen <= '1';
333 swni.rmapen <= '1';
334 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
334 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
335 swni.tickinraw <= '0';
335 swni.tickinraw <= '0';
336 swni.timein <= (OTHERS => '0');
336 swni.timein <= (OTHERS => '0');
337 swni.dcrstval <= (OTHERS => '0');
337 swni.dcrstval <= (OTHERS => '0');
338 swni.timerrstval <= (OTHERS => '0');
338 swni.timerrstval <= (OTHERS => '0');
339
339
340 -------------------------------------------------------------------------------
340 -------------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
341 -- LFR ------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
342 -------------------------------------------------------------------------------
343 lpp_lfr_1 : lpp_lfr_WFP_nMS
343 lpp_lfr_1 : lpp_lfr
344 GENERIC MAP (
344 GENERIC MAP (
345 Mem_use => use_RAM,
345 Mem_use => use_RAM,
346 nb_data_by_buffer_size => 32,
346 nb_data_by_buffer_size => 32,
347 nb_word_by_buffer_size => 30,
347 nb_word_by_buffer_size => 30,
348 nb_snapshot_param_size => 32,
348 nb_snapshot_param_size => 32,
349 delta_vector_size => 32,
349 delta_vector_size => 32,
350 delta_vector_size_f0_2 => 7, -- log2(96)
350 delta_vector_size_f0_2 => 7, -- log2(96)
351 pindex => 15,
351 pindex => 15,
352 paddr => 15,
352 paddr => 15,
353 pmask => 16#fff#,
353 pmask => 16#fff#,
354 pirq_ms => 6,
354 pirq_ms => 6,
355 pirq_wfp => 14,
355 pirq_wfp => 14,
356 hindex => 2,
356 hindex => 2,
357 top_lfr_version => X"00010B") -- aa.bb.cc version
357 top_lfr_version => X"010110") -- aa.bb.cc version
358 -- AA : BOARD NUMBER
358 -- AA : BOARD NUMBER
359 -- 0 => MINI_LFR
359 -- 0 => MINI_LFR
360 -- 1 => EM
360 -- 1 => EM
361 PORT MAP (
361 PORT MAP (
362 clk => clk_25,
362 clk => clk_25,
363 rstn => rstn,
363 rstn => rstn,
364 sample_B => sample_s(2 DOWNTO 0),
364 sample_B => sample_s(2 DOWNTO 0),
365 sample_E => sample_s(7 DOWNTO 3),
365 sample_E => sample_s(7 DOWNTO 3),
366 sample_val => sample_val,
366 sample_val => sample_val,
367 apbi => apbi_ext,
367 apbi => apbi_ext,
368 apbo => apbo_ext(15),
368 apbo => apbo_ext(15),
369 ahbi => ahbi_m_ext,
369 ahbi => ahbi_m_ext,
370 ahbo => ahbo_m_ext(2),
370 ahbo => ahbo_m_ext(2),
371 coarse_time => coarse_time,
371 coarse_time => coarse_time,
372 fine_time => fine_time,
372 fine_time => fine_time,
373 data_shaping_BW => bias_fail_sw,
373 data_shaping_BW => bias_fail_sw,
374 observation_reg => observation_reg);
374 observation_reg => observation_reg);
375
375
376
376
377 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
377 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
378 sample_s(I) <= sample(I) & '0' & '0';
378 sample_s(I) <= sample(I) & '0' & '0';
379 END GENERATE all_sample;
379 END GENERATE all_sample;
380
380
381 -----------------------------------------------------------------------------
381 -----------------------------------------------------------------------------
382 --
382 --
383 -----------------------------------------------------------------------------
383 -----------------------------------------------------------------------------
384 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
384 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
385 GENERIC MAP (
385 GENERIC MAP (
386 ChanelCount => 8,
386 ChanelCount => 8,
387 ncycle_cnv_high => 40, -- TODO : 79
387 ncycle_cnv_high => 40, -- TODO : 79
388 ncycle_cnv => 250) -- TODO : 500
388 ncycle_cnv => 250) -- TODO : 500
389 PORT MAP (
389 PORT MAP (
390 cnv_clk => clk_24, -- TODO : 49.152
390 cnv_clk => clk_24, -- TODO : 49.152
391 cnv_rstn => rstn, -- ok
391 cnv_rstn => rstn, -- ok
392 cnv => ADC_smpclk, -- ok
392 cnv => ADC_smpclk, -- ok
393 clk => clk_25, -- ok
393 clk => clk_25, -- ok
394 rstn => rstn, -- ok
394 rstn => rstn, -- ok
395 ADC_data => ADC_data, -- ok
395 ADC_data => ADC_data, -- ok
396 ADC_nOE => ADC_OEB_bar_CH, -- ok
396 ADC_nOE => ADC_OEB_bar_CH, -- ok
397 sample => sample, -- ok
397 sample => sample, -- ok
398 sample_val => sample_val); -- ok
398 sample_val => sample_val); -- ok
399
399
400 TAG8 <= ADC_smpclk;
400 TAG8 <= ADC_smpclk;
401
401
402 END beh;
402 END beh;
Show file before | Show file after | Hide comments
@@ -1,587 +1,587
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL;
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 USE lpp.iir_filter.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_leon3_soc_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
118 SIGNAL clk_24 : STD_LOGIC := '0';
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 --
122 --
123 SIGNAL errorn : STD_LOGIC;
123 SIGNAL errorn : STD_LOGIC;
124 -- UART AHB ---------------------------------------------------------------
124 -- UART AHB ---------------------------------------------------------------
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127
127
128 -- UART APB ---------------------------------------------------------------
128 -- UART APB ---------------------------------------------------------------
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 --
131 --
132 SIGNAL I00_s : STD_LOGIC;
132 SIGNAL I00_s : STD_LOGIC;
133
133
134 -- CONSTANTS
134 -- CONSTANTS
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 --
136 --
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140
140
141 SIGNAL apbi_ext : apb_slv_in_type;
141 SIGNAL apbi_ext : apb_slv_in_type;
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
147
147
148 -- Spacewire signals
148 -- Spacewire signals
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
154 SIGNAL spw_clk : STD_LOGIC;
155 SIGNAL swni : grspw_in_type;
155 SIGNAL swni : grspw_in_type;
156 SIGNAL swno : grspw_out_type;
156 SIGNAL swno : grspw_out_type;
157 -- SIGNAL clkmn : STD_ULOGIC;
157 -- SIGNAL clkmn : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
158 -- SIGNAL txclk : STD_ULOGIC;
159
159
160 --GPIO
160 --GPIO
161 SIGNAL gpioi : gpio_in_type;
161 SIGNAL gpioi : gpio_in_type;
162 SIGNAL gpioo : gpio_out_type;
162 SIGNAL gpioo : gpio_out_type;
163
163
164 -- AD Converter ADS7886
164 -- AD Converter ADS7886
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 SIGNAL sample_val : STD_LOGIC;
167 SIGNAL sample_val : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171
171
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173
173
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176
176
177 BEGIN -- beh
177 BEGIN -- beh
178
178
179 -----------------------------------------------------------------------------
179 -----------------------------------------------------------------------------
180 -- CLK
180 -- CLK
181 -----------------------------------------------------------------------------
181 -----------------------------------------------------------------------------
182
182
183 PROCESS(clk_50)
183 PROCESS(clk_50)
184 BEGIN
184 BEGIN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
185 IF clk_50'EVENT AND clk_50 = '1' THEN
186 clk_50_s <= NOT clk_50_s;
186 clk_50_s <= NOT clk_50_s;
187 END IF;
187 END IF;
188 END PROCESS;
188 END PROCESS;
189
189
190 PROCESS(clk_50_s)
190 PROCESS(clk_50_s)
191 BEGIN
191 BEGIN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
192 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
193 clk_25 <= NOT clk_25;
193 clk_25 <= NOT clk_25;
194 END IF;
194 END IF;
195 END PROCESS;
195 END PROCESS;
196
196
197 PROCESS(clk_49)
197 PROCESS(clk_49)
198 BEGIN
198 BEGIN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
199 IF clk_49'EVENT AND clk_49 = '1' THEN
200 clk_24 <= NOT clk_24;
200 clk_24 <= NOT clk_24;
201 END IF;
201 END IF;
202 END PROCESS;
202 END PROCESS;
203
203
204 -----------------------------------------------------------------------------
204 -----------------------------------------------------------------------------
205
205
206 PROCESS (clk_25, reset)
206 PROCESS (clk_25, reset)
207 BEGIN -- PROCESS
207 BEGIN -- PROCESS
208 IF reset = '0' THEN -- asynchronous reset (active low)
208 IF reset = '0' THEN -- asynchronous reset (active low)
209 LED0 <= '0';
209 LED0 <= '0';
210 LED1 <= '0';
210 LED1 <= '0';
211 LED2 <= '0';
211 LED2 <= '0';
212 --IO1 <= '0';
212 --IO1 <= '0';
213 --IO2 <= '1';
213 --IO2 <= '1';
214 --IO3 <= '0';
214 --IO3 <= '0';
215 --IO4 <= '0';
215 --IO4 <= '0';
216 --IO5 <= '0';
216 --IO5 <= '0';
217 --IO6 <= '0';
217 --IO6 <= '0';
218 --IO7 <= '0';
218 --IO7 <= '0';
219 --IO8 <= '0';
219 --IO8 <= '0';
220 --IO9 <= '0';
220 --IO9 <= '0';
221 --IO10 <= '0';
221 --IO10 <= '0';
222 --IO11 <= '0';
222 --IO11 <= '0';
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
223 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
224 LED0 <= '0';
224 LED0 <= '0';
225 LED1 <= '1';
225 LED1 <= '1';
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
226 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
227 --IO1 <= '1';
227 --IO1 <= '1';
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
228 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
229 --IO3 <= ADC_SDO(0);
229 --IO3 <= ADC_SDO(0);
230 --IO4 <= ADC_SDO(1);
230 --IO4 <= ADC_SDO(1);
231 --IO5 <= ADC_SDO(2);
231 --IO5 <= ADC_SDO(2);
232 --IO6 <= ADC_SDO(3);
232 --IO6 <= ADC_SDO(3);
233 --IO7 <= ADC_SDO(4);
233 --IO7 <= ADC_SDO(4);
234 --IO8 <= ADC_SDO(5);
234 --IO8 <= ADC_SDO(5);
235 --IO9 <= ADC_SDO(6);
235 --IO9 <= ADC_SDO(6);
236 --IO10 <= ADC_SDO(7);
236 --IO10 <= ADC_SDO(7);
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
237 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
238 END IF;
238 END IF;
239 END PROCESS;
239 END PROCESS;
240
240
241 PROCESS (clk_24, reset)
241 PROCESS (clk_24, reset)
242 BEGIN -- PROCESS
242 BEGIN -- PROCESS
243 IF reset = '0' THEN -- asynchronous reset (active low)
243 IF reset = '0' THEN -- asynchronous reset (active low)
244 I00_s <= '0';
244 I00_s <= '0';
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
245 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
246 I00_s <= NOT I00_s ;
246 I00_s <= NOT I00_s ;
247 END IF;
247 END IF;
248 END PROCESS;
248 END PROCESS;
249 -- IO0 <= I00_s;
249 -- IO0 <= I00_s;
250
250
251 --UARTs
251 --UARTs
252 nCTS1 <= '1';
252 nCTS1 <= '1';
253 nCTS2 <= '1';
253 nCTS2 <= '1';
254 nDCD2 <= '1';
254 nDCD2 <= '1';
255
255
256 --EXT CONNECTOR
256 --EXT CONNECTOR
257
257
258 --SPACE WIRE
258 --SPACE WIRE
259
259
260 leon3_soc_1 : leon3_soc
260 leon3_soc_1 : leon3_soc
261 GENERIC MAP (
261 GENERIC MAP (
262 fabtech => apa3e,
262 fabtech => apa3e,
263 memtech => apa3e,
263 memtech => apa3e,
264 padtech => inferred,
264 padtech => inferred,
265 clktech => inferred,
265 clktech => inferred,
266 disas => 0,
266 disas => 0,
267 dbguart => 0,
267 dbguart => 0,
268 pclow => 2,
268 pclow => 2,
269 clk_freq => 25000,
269 clk_freq => 25000,
270 NB_CPU => 1,
270 NB_CPU => 1,
271 ENABLE_FPU => 1,
271 ENABLE_FPU => 1,
272 FPU_NETLIST => 0,
272 FPU_NETLIST => 0,
273 ENABLE_DSU => 1,
273 ENABLE_DSU => 1,
274 ENABLE_AHB_UART => 1,
274 ENABLE_AHB_UART => 1,
275 ENABLE_APB_UART => 1,
275 ENABLE_APB_UART => 1,
276 ENABLE_IRQMP => 1,
276 ENABLE_IRQMP => 1,
277 ENABLE_GPT => 1,
277 ENABLE_GPT => 1,
278 NB_AHB_MASTER => NB_AHB_MASTER,
278 NB_AHB_MASTER => NB_AHB_MASTER,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
279 NB_AHB_SLAVE => NB_AHB_SLAVE,
280 NB_APB_SLAVE => NB_APB_SLAVE)
280 NB_APB_SLAVE => NB_APB_SLAVE)
281 PORT MAP (
281 PORT MAP (
282 clk => clk_25,
282 clk => clk_25,
283 reset => reset,
283 reset => reset,
284 errorn => errorn,
284 errorn => errorn,
285 ahbrxd => TXD1,
285 ahbrxd => TXD1,
286 ahbtxd => RXD1,
286 ahbtxd => RXD1,
287 urxd1 => TXD2,
287 urxd1 => TXD2,
288 utxd1 => RXD2,
288 utxd1 => RXD2,
289 address => SRAM_A,
289 address => SRAM_A,
290 data => SRAM_DQ,
290 data => SRAM_DQ,
291 nSRAM_BE0 => SRAM_nBE(0),
291 nSRAM_BE0 => SRAM_nBE(0),
292 nSRAM_BE1 => SRAM_nBE(1),
292 nSRAM_BE1 => SRAM_nBE(1),
293 nSRAM_BE2 => SRAM_nBE(2),
293 nSRAM_BE2 => SRAM_nBE(2),
294 nSRAM_BE3 => SRAM_nBE(3),
294 nSRAM_BE3 => SRAM_nBE(3),
295 nSRAM_WE => SRAM_nWE,
295 nSRAM_WE => SRAM_nWE,
296 nSRAM_CE => SRAM_CE,
296 nSRAM_CE => SRAM_CE,
297 nSRAM_OE => SRAM_nOE,
297 nSRAM_OE => SRAM_nOE,
298
298
299 apbi_ext => apbi_ext,
299 apbi_ext => apbi_ext,
300 apbo_ext => apbo_ext,
300 apbo_ext => apbo_ext,
301 ahbi_s_ext => ahbi_s_ext,
301 ahbi_s_ext => ahbi_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
302 ahbo_s_ext => ahbo_s_ext,
303 ahbi_m_ext => ahbi_m_ext,
303 ahbi_m_ext => ahbi_m_ext,
304 ahbo_m_ext => ahbo_m_ext);
304 ahbo_m_ext => ahbo_m_ext);
305
305
306 -------------------------------------------------------------------------------
306 -------------------------------------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
307 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
308 -------------------------------------------------------------------------------
308 -------------------------------------------------------------------------------
309 apb_lfr_time_management_1 : apb_lfr_time_management
309 apb_lfr_time_management_1 : apb_lfr_time_management
310 GENERIC MAP (
310 GENERIC MAP (
311 pindex => 6,
311 pindex => 6,
312 paddr => 6,
312 paddr => 6,
313 pmask => 16#fff#,
313 pmask => 16#fff#,
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
314 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
315 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
316 PORT MAP (
316 PORT MAP (
317 clk25MHz => clk_25,
317 clk25MHz => clk_25,
318 clk24_576MHz => clk_24, -- 49.152MHz/2
318 clk24_576MHz => clk_24, -- 49.152MHz/2
319 resetn => reset,
319 resetn => reset,
320 grspw_tick => swno.tickout,
320 grspw_tick => swno.tickout,
321 apbi => apbi_ext,
321 apbi => apbi_ext,
322 apbo => apbo_ext(6),
322 apbo => apbo_ext(6),
323 coarse_time => coarse_time,
323 coarse_time => coarse_time,
324 fine_time => fine_time);
324 fine_time => fine_time);
325
325
326 -----------------------------------------------------------------------
326 -----------------------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
327 --- SpaceWire --------------------------------------------------------
328 -----------------------------------------------------------------------
328 -----------------------------------------------------------------------
329
329
330 SPW_EN <= '1';
330 SPW_EN <= '1';
331
331
332 spw_clk <= clk_50_s;
332 spw_clk <= clk_50_s;
333 spw_rxtxclk <= spw_clk;
333 spw_rxtxclk <= spw_clk;
334 spw_rxclkn <= NOT spw_rxtxclk;
334 spw_rxclkn <= NOT spw_rxtxclk;
335
335
336 -- PADS for SPW1
336 -- PADS for SPW1
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
337 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
338 PORT MAP (SPW_NOM_DIN, dtmp(0));
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
339 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_NOM_SIN, stmp(0));
340 PORT MAP (SPW_NOM_SIN, stmp(0));
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
341 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
342 PORT MAP (SPW_NOM_DOUT, swno.d(0));
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
343 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
344 PORT MAP (SPW_NOM_SOUT, swno.s(0));
345 -- PADS FOR SPW2
345 -- PADS FOR SPW2
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
346 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
347 PORT MAP (SPW_RED_SIN, dtmp(1));
347 PORT MAP (SPW_RED_SIN, dtmp(1));
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
348 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
349 PORT MAP (SPW_RED_DIN, stmp(1));
349 PORT MAP (SPW_RED_DIN, stmp(1));
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
350 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
351 PORT MAP (SPW_RED_DOUT, swno.d(1));
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
352 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
353 PORT MAP (SPW_RED_SOUT, swno.s(1));
354
354
355 -- GRSPW PHY
355 -- GRSPW PHY
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
356 --spw1_input: if CFG_SPW_GRSPW = 1 generate
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
357 spw_inputloop : FOR j IN 0 TO 1 GENERATE
358 spw_phy0 : grspw_phy
358 spw_phy0 : grspw_phy
359 GENERIC MAP(
359 GENERIC MAP(
360 tech => apa3e,
360 tech => apa3e,
361 rxclkbuftype => 1,
361 rxclkbuftype => 1,
362 scantest => 0)
362 scantest => 0)
363 PORT MAP(
363 PORT MAP(
364 rxrst => swno.rxrst,
364 rxrst => swno.rxrst,
365 di => dtmp(j),
365 di => dtmp(j),
366 si => stmp(j),
366 si => stmp(j),
367 rxclko => spw_rxclk(j),
367 rxclko => spw_rxclk(j),
368 do => swni.d(j),
368 do => swni.d(j),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
369 ndo => swni.nd(j*5+4 DOWNTO j*5),
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
370 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
371 END GENERATE spw_inputloop;
371 END GENERATE spw_inputloop;
372
372
373 -- SPW core
373 -- SPW core
374 sw0 : grspwm GENERIC MAP(
374 sw0 : grspwm GENERIC MAP(
375 tech => apa3e,
375 tech => apa3e,
376 hindex => 1,
376 hindex => 1,
377 pindex => 5,
377 pindex => 5,
378 paddr => 5,
378 paddr => 5,
379 pirq => 11,
379 pirq => 11,
380 sysfreq => 25000, -- CPU_FREQ
380 sysfreq => 25000, -- CPU_FREQ
381 rmap => 1,
381 rmap => 1,
382 rmapcrc => 1,
382 rmapcrc => 1,
383 fifosize1 => 16,
383 fifosize1 => 16,
384 fifosize2 => 16,
384 fifosize2 => 16,
385 rxclkbuftype => 1,
385 rxclkbuftype => 1,
386 rxunaligned => 0,
386 rxunaligned => 0,
387 rmapbufs => 4,
387 rmapbufs => 4,
388 ft => 0,
388 ft => 0,
389 netlist => 0,
389 netlist => 0,
390 ports => 2,
390 ports => 2,
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
391 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
392 memtech => apa3e,
392 memtech => apa3e,
393 destkey => 2,
393 destkey => 2,
394 spwcore => 1
394 spwcore => 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
395 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
396 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
397 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
398 )
398 )
399 PORT MAP(reset, clk_25, spw_rxclk(0),
399 PORT MAP(reset, clk_25, spw_rxclk(0),
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
400 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
401 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
402 swni, swno);
402 swni, swno);
403
403
404 swni.tickin <= '0';
404 swni.tickin <= '0';
405 swni.rmapen <= '1';
405 swni.rmapen <= '1';
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
406 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
407 swni.tickinraw <= '0';
407 swni.tickinraw <= '0';
408 swni.timein <= (OTHERS => '0');
408 swni.timein <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
409 swni.dcrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
410 swni.timerrstval <= (OTHERS => '0');
411
411
412 -------------------------------------------------------------------------------
412 -------------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
413 -- LFR ------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
414 -------------------------------------------------------------------------------
415 lpp_lfr_1 : lpp_lfr
415 lpp_lfr_1 : lpp_lfr
416 GENERIC MAP (
416 GENERIC MAP (
417 Mem_use => use_RAM,
417 Mem_use => use_RAM,
418 nb_data_by_buffer_size => 32,
418 nb_data_by_buffer_size => 32,
419 nb_word_by_buffer_size => 30,
419 nb_word_by_buffer_size => 30,
420 nb_snapshot_param_size => 32,
420 nb_snapshot_param_size => 32,
421 delta_vector_size => 32,
421 delta_vector_size => 32,
422 delta_vector_size_f0_2 => 7, -- log2(96)
422 delta_vector_size_f0_2 => 7, -- log2(96)
423 pindex => 15,
423 pindex => 15,
424 paddr => 15,
424 paddr => 15,
425 pmask => 16#fff#,
425 pmask => 16#fff#,
426 pirq_ms => 6,
426 pirq_ms => 6,
427 pirq_wfp => 14,
427 pirq_wfp => 14,
428 hindex => 2,
428 hindex => 2,
429 top_lfr_version => X"00010F") -- aa.bb.cc version
429 top_lfr_version => X"000110") -- aa.bb.cc version
430 PORT MAP (
430 PORT MAP (
431 clk => clk_25,
431 clk => clk_25,
432 rstn => reset,
432 rstn => reset,
433 sample_B => sample_s(2 DOWNTO 0),
433 sample_B => sample_s(2 DOWNTO 0),
434 sample_E => sample_s(7 DOWNTO 3),
434 sample_E => sample_s(7 DOWNTO 3),
435 sample_val => sample_val,
435 sample_val => sample_val,
436 apbi => apbi_ext,
436 apbi => apbi_ext,
437 apbo => apbo_ext(15),
437 apbo => apbo_ext(15),
438 ahbi => ahbi_m_ext,
438 ahbi => ahbi_m_ext,
439 ahbo => ahbo_m_ext(2),
439 ahbo => ahbo_m_ext(2),
440 coarse_time => coarse_time,
440 coarse_time => coarse_time,
441 fine_time => fine_time,
441 fine_time => fine_time,
442 data_shaping_BW => bias_fail_sw_sig,
442 data_shaping_BW => bias_fail_sw_sig,
443 observation_reg => observation_reg);
443 observation_reg => observation_reg);
444
444
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
445 all_sample: FOR I IN 7 DOWNTO 0 GENERATE
446 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
446 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
447 END GENERATE all_sample;
447 END GENERATE all_sample;
448
448
449
449
450
450
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
451 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
452 GENERIC MAP(
452 GENERIC MAP(
453 ChannelCount => 8,
453 ChannelCount => 8,
454 SampleNbBits => 14,
454 SampleNbBits => 14,
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
455 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
456 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
457 PORT MAP (
457 PORT MAP (
458 -- CONV
458 -- CONV
459 cnv_clk => clk_24,
459 cnv_clk => clk_24,
460 cnv_rstn => reset,
460 cnv_rstn => reset,
461 cnv => ADC_nCS_sig,
461 cnv => ADC_nCS_sig,
462 -- DATA
462 -- DATA
463 clk => clk_25,
463 clk => clk_25,
464 rstn => reset,
464 rstn => reset,
465 sck => ADC_CLK_sig,
465 sck => ADC_CLK_sig,
466 sdo => ADC_SDO_sig,
466 sdo => ADC_SDO_sig,
467 -- SAMPLE
467 -- SAMPLE
468 sample => sample,
468 sample => sample,
469 sample_val => sample_val);
469 sample_val => sample_val);
470
470
471 --IO10 <= ADC_SDO_sig(5);
471 --IO10 <= ADC_SDO_sig(5);
472 --IO9 <= ADC_SDO_sig(4);
472 --IO9 <= ADC_SDO_sig(4);
473 --IO8 <= ADC_SDO_sig(3);
473 --IO8 <= ADC_SDO_sig(3);
474
474
475 ADC_nCS <= ADC_nCS_sig;
475 ADC_nCS <= ADC_nCS_sig;
476 ADC_CLK <= ADC_CLK_sig;
476 ADC_CLK <= ADC_CLK_sig;
477 ADC_SDO_sig <= ADC_SDO;
477 ADC_SDO_sig <= ADC_SDO;
478
478
479 ----------------------------------------------------------------------
479 ----------------------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
480 --- GPIO -----------------------------------------------------------
481 ----------------------------------------------------------------------
481 ----------------------------------------------------------------------
482
482
483 grgpio0 : grgpio
483 grgpio0 : grgpio
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
484 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
485 PORT MAP(reset, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
486
486
487 --pio_pad_0 : iopad
487 --pio_pad_0 : iopad
488 -- GENERIC MAP (tech => CFG_PADTECH)
488 -- GENERIC MAP (tech => CFG_PADTECH)
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
489 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
490 --pio_pad_1 : iopad
490 --pio_pad_1 : iopad
491 -- GENERIC MAP (tech => CFG_PADTECH)
491 -- GENERIC MAP (tech => CFG_PADTECH)
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
492 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
493 --pio_pad_2 : iopad
493 --pio_pad_2 : iopad
494 -- GENERIC MAP (tech => CFG_PADTECH)
494 -- GENERIC MAP (tech => CFG_PADTECH)
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
495 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
496 --pio_pad_3 : iopad
496 --pio_pad_3 : iopad
497 -- GENERIC MAP (tech => CFG_PADTECH)
497 -- GENERIC MAP (tech => CFG_PADTECH)
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
498 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
499 --pio_pad_4 : iopad
499 --pio_pad_4 : iopad
500 -- GENERIC MAP (tech => CFG_PADTECH)
500 -- GENERIC MAP (tech => CFG_PADTECH)
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
501 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
502 --pio_pad_5 : iopad
502 --pio_pad_5 : iopad
503 -- GENERIC MAP (tech => CFG_PADTECH)
503 -- GENERIC MAP (tech => CFG_PADTECH)
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
504 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
505 --pio_pad_6 : iopad
505 --pio_pad_6 : iopad
506 -- GENERIC MAP (tech => CFG_PADTECH)
506 -- GENERIC MAP (tech => CFG_PADTECH)
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
507 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
508 --pio_pad_7 : iopad
508 --pio_pad_7 : iopad
509 -- GENERIC MAP (tech => CFG_PADTECH)
509 -- GENERIC MAP (tech => CFG_PADTECH)
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
510 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
511
511
512 PROCESS (clk_25, reset)
512 PROCESS (clk_25, reset)
513 BEGIN -- PROCESS
513 BEGIN -- PROCESS
514 IF reset = '0' THEN -- asynchronous reset (active low)
514 IF reset = '0' THEN -- asynchronous reset (active low)
515 IO0 <= '0';
515 IO0 <= '0';
516 IO1 <= '0';
516 IO1 <= '0';
517 IO2 <= '0';
517 IO2 <= '0';
518 IO3 <= '0';
518 IO3 <= '0';
519 IO4 <= '0';
519 IO4 <= '0';
520 IO5 <= '0';
520 IO5 <= '0';
521 IO6 <= '0';
521 IO6 <= '0';
522 IO7 <= '0';
522 IO7 <= '0';
523 IO8 <= '0';
523 IO8 <= '0';
524 IO9 <= '0';
524 IO9 <= '0';
525 IO10 <= '0';
525 IO10 <= '0';
526 IO11 <= '0';
526 IO11 <= '0';
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
527 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
528 CASE gpioo.dout(1 DOWNTO 0) IS
528 CASE gpioo.dout(1 DOWNTO 0) IS
529 WHEN "00" =>
529 WHEN "00" =>
530 IO0 <= observation_reg(0 );
530 IO0 <= observation_reg(0 );
531 IO1 <= observation_reg(1 );
531 IO1 <= observation_reg(1 );
532 IO2 <= observation_reg(2 );
532 IO2 <= observation_reg(2 );
533 IO3 <= observation_reg(3 );
533 IO3 <= observation_reg(3 );
534 IO4 <= observation_reg(4 );
534 IO4 <= observation_reg(4 );
535 IO5 <= observation_reg(5 );
535 IO5 <= observation_reg(5 );
536 IO6 <= observation_reg(6 );
536 IO6 <= observation_reg(6 );
537 IO7 <= observation_reg(7 );
537 IO7 <= observation_reg(7 );
538 IO8 <= observation_reg(8 );
538 IO8 <= observation_reg(8 );
539 IO9 <= observation_reg(9 );
539 IO9 <= observation_reg(9 );
540 IO10 <= observation_reg(10);
540 IO10 <= observation_reg(10);
541 IO11 <= observation_reg(11);
541 IO11 <= observation_reg(11);
542 WHEN "01" =>
542 WHEN "01" =>
543 IO0 <= observation_reg(0 + 12);
543 IO0 <= observation_reg(0 + 12);
544 IO1 <= observation_reg(1 + 12);
544 IO1 <= observation_reg(1 + 12);
545 IO2 <= observation_reg(2 + 12);
545 IO2 <= observation_reg(2 + 12);
546 IO3 <= observation_reg(3 + 12);
546 IO3 <= observation_reg(3 + 12);
547 IO4 <= observation_reg(4 + 12);
547 IO4 <= observation_reg(4 + 12);
548 IO5 <= observation_reg(5 + 12);
548 IO5 <= observation_reg(5 + 12);
549 IO6 <= observation_reg(6 + 12);
549 IO6 <= observation_reg(6 + 12);
550 IO7 <= observation_reg(7 + 12);
550 IO7 <= observation_reg(7 + 12);
551 IO8 <= observation_reg(8 + 12);
551 IO8 <= observation_reg(8 + 12);
552 IO9 <= observation_reg(9 + 12);
552 IO9 <= observation_reg(9 + 12);
553 IO10 <= observation_reg(10 + 12);
553 IO10 <= observation_reg(10 + 12);
554 IO11 <= observation_reg(11 + 12);
554 IO11 <= observation_reg(11 + 12);
555 WHEN "10" =>
555 WHEN "10" =>
556 IO0 <= observation_reg(0 + 12 + 12);
556 IO0 <= observation_reg(0 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
557 IO1 <= observation_reg(1 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
558 IO2 <= observation_reg(2 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
559 IO3 <= observation_reg(3 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
560 IO4 <= observation_reg(4 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
561 IO5 <= observation_reg(5 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
562 IO6 <= observation_reg(6 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
563 IO7 <= observation_reg(7 + 12 + 12);
564 IO8 <= '0';
564 IO8 <= '0';
565 IO9 <= '0';
565 IO9 <= '0';
566 IO10 <= '0';
566 IO10 <= '0';
567 IO11 <= '0';
567 IO11 <= '0';
568 WHEN "11" =>
568 WHEN "11" =>
569 IO0 <= '0';
569 IO0 <= '0';
570 IO1 <= '0';
570 IO1 <= '0';
571 IO2 <= '0';
571 IO2 <= '0';
572 IO3 <= '0';
572 IO3 <= '0';
573 IO4 <= '0';
573 IO4 <= '0';
574 IO5 <= '0';
574 IO5 <= '0';
575 IO6 <= '0';
575 IO6 <= '0';
576 IO7 <= '0';
576 IO7 <= '0';
577 IO8 <= '0';
577 IO8 <= '0';
578 IO9 <= '0';
578 IO9 <= '0';
579 IO10 <= '0';
579 IO10 <= '0';
580 IO11 <= '0';
580 IO11 <= '0';
581 WHEN OTHERS => NULL;
581 WHEN OTHERS => NULL;
582 END CASE;
582 END CASE;
583
583
584 END IF;
584 END IF;
585 END PROCESS;
585 END PROCESS;
586
586
587 END beh;
587 END beh;
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@@ -1,432 +1,480
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22
22
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
25 USE IEEE.NUMERIC_STD.ALL;
26
26
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.lpp_lfr_pkg.ALL;
28 USE lpp.lpp_lfr_pkg.ALL;
29 USE lpp.lpp_memory.ALL;
29 USE lpp.lpp_memory.ALL;
30 USE lpp.iir_filter.ALL;
30 USE lpp.iir_filter.ALL;
31 USE lpp.spectral_matrix_package.ALL;
31 USE lpp.spectral_matrix_package.ALL;
32 use lpp.lpp_fft.all;
32 use lpp.lpp_fft.all;
33 use lpp.fft_components.all;
33 use lpp.fft_components.all;
34
34
35 LIBRARY grlib;
35 LIBRARY grlib;
36 USE grlib.amba.ALL;
36 USE grlib.amba.ALL;
37 USE grlib.stdlib.ALL;
37 USE grlib.stdlib.ALL;
38 USE grlib.devices.ALL;
38 USE grlib.devices.ALL;
39 USE GRLIB.DMA2AHB_Package.ALL;
39 USE GRLIB.DMA2AHB_Package.ALL;
40
40
41 ENTITY TB IS
41 ENTITY TB IS
42
42
43
43
44 END TB;
44 END TB;
45
45
46
46
47 ARCHITECTURE beh OF TB IS
47 ARCHITECTURE beh OF TB IS
48
48
49 -----------------------------------------------------------------------------
49 -----------------------------------------------------------------------------
50 SIGNAL clk25MHz : STD_LOGIC := '0';
50 SIGNAL clk25MHz : STD_LOGIC := '0';
51 SIGNAL rstn : STD_LOGIC := '0';
51 SIGNAL rstn : STD_LOGIC := '0';
52
52
53 -----------------------------------------------------------------------------
53 -----------------------------------------------------------------------------
54 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
54 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
55 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
55 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
56 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
56 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
57 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
57 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
58 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
58 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
59 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
59 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
60 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
60 SIGNAL sample_f2_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
61 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
61 SIGNAL sample_f2_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
62 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
62 SIGNAL dma_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
63 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
63 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 SIGNAL dma_valid : STD_LOGIC;
64 SIGNAL dma_valid : STD_LOGIC;
65 SIGNAL dma_valid_burst : STD_LOGIC;
65 SIGNAL dma_valid_burst : STD_LOGIC;
66 SIGNAL dma_ren : STD_LOGIC;
66 SIGNAL dma_ren : STD_LOGIC;
67 SIGNAL dma_done : STD_LOGIC;
67 SIGNAL dma_done : STD_LOGIC;
68 SIGNAL ready_matrix_f0 : STD_LOGIC;
68 SIGNAL ready_matrix_f0 : STD_LOGIC;
69 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
69 -- SIGNAL ready_matrix_f0_1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
70 SIGNAL ready_matrix_f1 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
71 SIGNAL ready_matrix_f2 : STD_LOGIC;
72 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
72 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
73 SIGNAL error_bad_component_error : STD_LOGIC;
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
75 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
76 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
76 -- SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
77 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
78 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
79 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
79 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
80 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
80 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
81 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
82 SIGNAL config_active_interruption_onError : STD_LOGIC;
83 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
83 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
84 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
85 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
86 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
87 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
87 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
88 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
88 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
89 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
89 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
90 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
90 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
91
91
92 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
93 SIGNAL clk49_152MHz : STD_LOGIC := '0';
93 SIGNAL clk49_152MHz : STD_LOGIC := '0';
94 SIGNAL sample_counter_24k : INTEGER;
94 SIGNAL sample_counter_24k : INTEGER;
95 SIGNAL s_24576Hz : STD_LOGIC;
95 SIGNAL s_24576Hz : STD_LOGIC;
96
96
97 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
97 SIGNAL s_24_sync_reg_0 : STD_LOGIC;
98 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
98 SIGNAL s_24_sync_reg_1 : STD_LOGIC;
99
99
100 SIGNAL s_24576Hz_sync : STD_LOGIC;
100 SIGNAL s_24576Hz_sync : STD_LOGIC;
101
101
102 SIGNAL sample_counter_f1 : INTEGER;
102 SIGNAL sample_counter_f1 : INTEGER;
103 SIGNAL sample_counter_f2 : INTEGER;
103 SIGNAL sample_counter_f2 : INTEGER;
104 --
104 --
105 SIGNAL sample_f0_val : STD_LOGIC;
105 SIGNAL sample_f0_val : STD_LOGIC;
106 SIGNAL sample_f1_val : STD_LOGIC;
106 SIGNAL sample_f1_val : STD_LOGIC;
107 SIGNAL sample_f2_val : STD_LOGIC;
107 SIGNAL sample_f2_val : STD_LOGIC;
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL ren_counter : INTEGER;
110 SIGNAL ren_counter : INTEGER;
111
111
112 SIGNAL error_buffer_full : STD_LOGIC;
112 SIGNAL error_buffer_full : STD_LOGIC;
113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
113 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115 SIGNAL apbi : apb_slv_in_type;
115 SIGNAL apbi : apb_slv_in_type;
116 SIGNAL apbo : apb_slv_out_type;
116 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
120
121 --
122 SIGNAL ready_reg : STD_LOGIC_VECTOR(5 DOWNTO 0);
123 SIGNAL irq_ongoing : STD_LOGIC;
124 --
125 SIGNAL read_status : STD_LOGIC;
126 SIGNAL read_status_t : STD_LOGIC;
127
128
129 SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
130 SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
131
121 BEGIN -- beh
132 BEGIN -- beh
122
133
123 clk25MHz <= NOT clk25MHz AFTER 20 ns;
134 clk25MHz <= NOT clk25MHz AFTER 20 ns;
124 clk25MHz <= NOT clk25MHz AFTER 20 ns;
135 clk25MHz <= NOT clk25MHz AFTER 20 ns;
125 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
136 clk49_152MHz <= NOT clk49_152MHz AFTER 10173 ps; -- 49.152/2 MHz
126
137
127 PROCESS
138 PROCESS
128 BEGIN -- PROCESS
139 BEGIN -- PROCESS
129 WAIT UNTIL clk25MHz = '1';
140 WAIT UNTIL clk25MHz = '1';
130 WAIT UNTIL clk25MHz = '1';
141 WAIT UNTIL clk25MHz = '1';
131 WAIT UNTIL clk25MHz = '1';
142 WAIT UNTIL clk25MHz = '1';
132 rstn <= '1';
143 rstn <= '1';
133 WAIT UNTIL clk25MHz = '1';
144 WAIT UNTIL clk25MHz = '1';
134
145
135
146
136 WAIT FOR 100 ms;
147 WAIT FOR 100 ms;
137
148
138 REPORT "*** END simulation ***" SEVERITY failure;
149 REPORT "*** END simulation ***" SEVERITY failure;
139 WAIT;
150 WAIT;
140
151
141 END PROCESS;
152 END PROCESS;
142
153
143
154
144 -----------------------------------------------------------------------------
155 -----------------------------------------------------------------------------
145 PROCESS (clk49_152MHz, rstn)
156 PROCESS (clk49_152MHz, rstn)
146 BEGIN -- PROCESS
157 BEGIN -- PROCESS
147 IF rstn = '0' THEN -- asynchronous reset (active low)
158 IF rstn = '0' THEN -- asynchronous reset (active low)
148 sample_counter_24k <= 0;
159 sample_counter_24k <= 0;
149 s_24576Hz <= '0';
160 s_24576Hz <= '0';
150 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
161 ELSIF clk49_152MHz'event AND clk49_152MHz = '1' THEN -- rising clock edge
151 IF sample_counter_24k = 0 THEN
162 IF sample_counter_24k = 0 THEN
152 sample_counter_24k <= 2000;
163 sample_counter_24k <= 2000;
153 s_24576Hz <= NOT s_24576Hz;
164 s_24576Hz <= NOT s_24576Hz;
154 ELSE
165 ELSE
155 sample_counter_24k <= sample_counter_24k - 1;
166 sample_counter_24k <= sample_counter_24k - 1;
156 END IF;
167 END IF;
157 END IF;
168 END IF;
158 END PROCESS;
169 END PROCESS;
159
170
160 PROCESS (clk25MHz, rstn)
171 PROCESS (clk25MHz, rstn)
161 BEGIN -- PROCESS
172 BEGIN -- PROCESS
162 IF rstn = '0' THEN -- asynchronous reset (active low)
173 IF rstn = '0' THEN -- asynchronous reset (active low)
163 s_24_sync_reg_0 <= '0';
174 s_24_sync_reg_0 <= '0';
164 s_24_sync_reg_1 <= '0';
175 s_24_sync_reg_1 <= '0';
165 s_24576Hz_sync <= '0';
176 s_24576Hz_sync <= '0';
166 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
177 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
167 s_24_sync_reg_0 <= s_24576Hz;
178 s_24_sync_reg_0 <= s_24576Hz;
168 s_24_sync_reg_1 <= s_24_sync_reg_0;
179 s_24_sync_reg_1 <= s_24_sync_reg_0;
169 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
180 s_24576Hz_sync <= s_24_sync_reg_0 XOR s_24_sync_reg_1;
170 END IF;
181 END IF;
171 END PROCESS;
182 END PROCESS;
172
183
173 PROCESS (clk25MHz, rstn)
184 PROCESS (clk25MHz, rstn)
174 BEGIN -- PROCESS
185 BEGIN -- PROCESS
175 IF rstn = '0' THEN -- asynchronous reset (active low)
186 IF rstn = '0' THEN -- asynchronous reset (active low)
176 sample_f0_val <= '0';
187 sample_f0_val <= '0';
177 sample_f1_val <= '0';
188 sample_f1_val <= '0';
178 sample_f2_val <= '0';
189 sample_f2_val <= '0';
179
190
180 sample_counter_f1 <= 0;
191 sample_counter_f1 <= 0;
181 sample_counter_f2 <= 0;
192 sample_counter_f2 <= 0;
182 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
193 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
183 IF s_24576Hz_sync = '1' THEN
194 IF s_24576Hz_sync = '1' THEN
184 sample_f0_val <= '1';
195 sample_f0_val <= '1';
185 IF sample_counter_f1 = 0 THEN
196 IF sample_counter_f1 = 0 THEN
186 sample_f1_val <= '1';
197 sample_f1_val <= '1';
187 sample_counter_f1 <= 5;
198 sample_counter_f1 <= 5;
188 ELSE
199 ELSE
189 sample_f1_val <= '0';
200 sample_f1_val <= '0';
190 sample_counter_f1 <= sample_counter_f1 -1;
201 sample_counter_f1 <= sample_counter_f1 -1;
191 END IF;
202 END IF;
192 IF sample_counter_f2 = 0 THEN
203 IF sample_counter_f2 = 0 THEN
193 sample_f2_val <= '1';
204 sample_f2_val <= '1';
194 sample_counter_f2 <= 95;
205 sample_counter_f2 <= 95;
195 ELSE
206 ELSE
196 sample_f2_val <= '0';
207 sample_f2_val <= '0';
197 sample_counter_f2 <= sample_counter_f2 -1;
208 sample_counter_f2 <= sample_counter_f2 -1;
198 END IF;
209 END IF;
199 ELSE
210 ELSE
200 sample_f0_val <= '0';
211 sample_f0_val <= '0';
201 sample_f1_val <= '0';
212 sample_f1_val <= '0';
202 sample_f2_val <= '0';
213 sample_f2_val <= '0';
203 END IF;
214 END IF;
204 END IF;
215 END IF;
205 END PROCESS;
216 END PROCESS;
206
217
207
218
208
219
209 -----------------------------------------------------------------------------
220 -----------------------------------------------------------------------------
210 coarse_time <= (OTHERS => '1');
221 coarse_time <= (OTHERS => '1');
211
222
212 PROCESS (clk25MHz, rstn)
223 PROCESS (clk25MHz, rstn)
213 BEGIN
224 BEGIN
214 IF rstn = '0' THEN
225 IF rstn = '0' THEN
215 fine_time <= (OTHERS => '0');
226 fine_time <= (OTHERS => '0');
216 ELSIF clk25MHz'event AND clk25MHz = '1' THEN
227 ELSIF clk25MHz'event AND clk25MHz = '1' THEN
217 fine_time <= fine_time + 1;
228 fine_time <= fine_time + 1;
218 END IF;
229 END IF;
219 END PROCESS;
230 END PROCESS;
220
231
221
232
222 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
233 sample_f0_wdata <= X"A000" & X"A111" & X"A222" & X"A333" & X"A444";
223 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
234 sample_f1_wdata <= X"B000" & X"B111" & X"B222" & X"B333" & X"B444";
224 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
235 sample_f2_wdata <= X"C000" & X"C111" & X"C222" & X"C333" & X"C444";
225
236
226 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
237 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val);
227 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
238 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val);
228 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
239 sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val);
229 -----------------------------------------------------------------------------
240 -----------------------------------------------------------------------------
230
241
231 lpp_lfr_ms_1: lpp_lfr_ms
242 lpp_lfr_ms_1: lpp_lfr_ms
232 GENERIC MAP (
243 GENERIC MAP (
233 Mem_use => use_CEL)
244 Mem_use => use_CEL)
234 PORT MAP (
245 PORT MAP (
235 clk => clk25MHz,
246 clk => clk25MHz,
236 rstn => rstn,
247 rstn => rstn,
237 --
248 --
238 coarse_time => coarse_time,
249 coarse_time => coarse_time,
239 fine_time => fine_time,
250 fine_time => fine_time,
240 --
251 --
241 sample_f0_wen => sample_f0_wen,
252 sample_f0_wen => sample_f0_wen,
242 sample_f0_wdata => sample_f0_wdata,
253 sample_f0_wdata => sample_f0_wdata,
243 sample_f1_wen => sample_f1_wen,
254 sample_f1_wen => sample_f1_wen,
244 sample_f1_wdata => sample_f1_wdata,
255 sample_f1_wdata => sample_f1_wdata,
245 sample_f2_wen => sample_f2_wen,
256 sample_f2_wen => sample_f2_wen,
246 sample_f2_wdata => sample_f2_wdata,
257 sample_f2_wdata => sample_f2_wdata,
247 --
258 --
248 dma_addr => dma_addr,
259 dma_addr => dma_addr,
249 dma_data => dma_data,
260 dma_data => dma_data,
250 dma_valid => dma_valid,
261 dma_valid => dma_valid,
251 dma_valid_burst => dma_valid_burst,
262 dma_valid_burst => dma_valid_burst,
252 dma_ren => dma_ren,
263 dma_ren => dma_ren,
253 dma_done => dma_done,
264 dma_done => dma_done,
254
265
255 ready_matrix_f0 => ready_matrix_f0,
266 ready_matrix_f0 => ready_matrix_f0,
256 -- ready_matrix_f0_1 => ready_matrix_f0_1,
267 -- ready_matrix_f0_1 => ready_matrix_f0_1,
257 ready_matrix_f1 => ready_matrix_f1,
268 ready_matrix_f1 => ready_matrix_f1,
258 ready_matrix_f2 => ready_matrix_f2,
269 ready_matrix_f2 => ready_matrix_f2,
259 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
270 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
260 error_bad_component_error => error_bad_component_error,
271 error_bad_component_error => error_bad_component_error,
261 error_buffer_full => error_buffer_full,
272 error_buffer_full => error_buffer_full,
262 error_input_fifo_write => error_input_fifo_write,
273 error_input_fifo_write => error_input_fifo_write,
263
274
264 debug_reg => debug_reg,
275 debug_reg => debug_reg,
276
277 --
278 observation_vector_0 => observation_vector_0,
279 observation_vector_1 => observation_vector_1,
280 --
265 status_ready_matrix_f0 => status_ready_matrix_f0,
281 status_ready_matrix_f0 => status_ready_matrix_f0,
266 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
282 -- status_ready_matrix_f0 => status_ready_matrix_f0_1,
267 status_ready_matrix_f1 => status_ready_matrix_f1,
283 status_ready_matrix_f1 => status_ready_matrix_f1,
268 status_ready_matrix_f2 => status_ready_matrix_f2,
284 status_ready_matrix_f2 => status_ready_matrix_f2,
269 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
285 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
270 -- status_error_bad_component_error => status_error_bad_component_error,
286 -- status_error_bad_component_error => status_error_bad_component_error,
271 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
287 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
272 config_active_interruption_onError => config_active_interruption_onError,
288 config_active_interruption_onError => config_active_interruption_onError,
273 addr_matrix_f0 => addr_matrix_f0,
289 addr_matrix_f0 => addr_matrix_f0,
274 -- addr_matrix_f0_1 => addr_matrix_f0_1,
290 -- addr_matrix_f0_1 => addr_matrix_f0_1,
275 addr_matrix_f1 => addr_matrix_f1,
291 addr_matrix_f1 => addr_matrix_f1,
276 addr_matrix_f2 => addr_matrix_f2,
292 addr_matrix_f2 => addr_matrix_f2,
277 matrix_time_f0 => matrix_time_f0,
293 matrix_time_f0 => matrix_time_f0,
278 -- matrix_time_f0_1 => matrix_time_f0_1,
294 -- matrix_time_f0_1 => matrix_time_f0_1,
279 matrix_time_f1 => matrix_time_f1,
295 matrix_time_f1 => matrix_time_f1,
280 matrix_time_f2 => matrix_time_f2);
296 matrix_time_f2 => matrix_time_f2);
281
297
282
298
283
299
284 apbi.psel(4) <= '0';
300
285
301
286 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
302 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
287 GENERIC MAP (
303 GENERIC MAP (
288 nb_data_by_buffer_size => 11,
304 nb_data_by_buffer_size => 11,
289 nb_word_by_buffer_size => 11,
305 nb_word_by_buffer_size => 11,
290 nb_snapshot_param_size => 11,
306 nb_snapshot_param_size => 11,
291 delta_vector_size => 20,
307 delta_vector_size => 20,
292 delta_vector_size_f0_2 => 7,
308 delta_vector_size_f0_2 => 7,
293 pindex => 4,
309 pindex => 4,
294 paddr => 4,
310 paddr => 4,
295 pmask => 16#fff#,
311 pmask => 16#fff#,
296 pirq_ms => 0,
312 pirq_ms => 0,
297 pirq_wfp => 1,
313 pirq_wfp => 1,
298 top_lfr_version => (OTHERS => '0')
314 top_lfr_version => (OTHERS => '0')
299 )
315 )
300 PORT MAP (
316 PORT MAP (
301 HCLK => clk25MHz,
317 HCLK => clk25MHz,
302 HRESETn => rstn,
318 HRESETn => rstn,
303 apbi => apbi,
319 apbi => apbi,
304 apbo => OPEN,
320 apbo => apbo,
305
321
306 run_ms => OPEN,
322 run_ms => OPEN,
307
323
308 ready_matrix_f0 => ready_matrix_f0,
324 ready_matrix_f0 => ready_matrix_f0,
309 ready_matrix_f1 => ready_matrix_f1,
325 ready_matrix_f1 => ready_matrix_f1,
310 ready_matrix_f2 => ready_matrix_f2,
326 ready_matrix_f2 => ready_matrix_f2,
311 error_bad_component_error => error_bad_component_error,
327 error_bad_component_error => error_bad_component_error,
312 error_buffer_full => error_buffer_full, -- TODO
328 error_buffer_full => error_buffer_full, -- TODO
313 error_input_fifo_write => error_input_fifo_write, -- TODO
329 error_input_fifo_write => error_input_fifo_write, -- TODO
314 status_ready_matrix_f0 => status_ready_matrix_f0,
330 status_ready_matrix_f0 => status_ready_matrix_f0,
315 status_ready_matrix_f1 => status_ready_matrix_f1,
331 status_ready_matrix_f1 => status_ready_matrix_f1,
316 status_ready_matrix_f2 => status_ready_matrix_f2,
332 status_ready_matrix_f2 => status_ready_matrix_f2,
317 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
333 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
318 config_active_interruption_onError => config_active_interruption_onError,
334 config_active_interruption_onError => config_active_interruption_onError,
319
335
320 matrix_time_f0 => matrix_time_f0,
336 matrix_time_f0 => matrix_time_f0,
321 matrix_time_f1 => matrix_time_f1,
337 matrix_time_f1 => matrix_time_f1,
322 matrix_time_f2 => matrix_time_f2,
338 matrix_time_f2 => matrix_time_f2,
323
339
324 addr_matrix_f0 => addr_matrix_f0,
340 addr_matrix_f0 => addr_matrix_f0,
325 addr_matrix_f1 => addr_matrix_f1,
341 addr_matrix_f1 => addr_matrix_f1,
326 addr_matrix_f2 => addr_matrix_f2,
342 addr_matrix_f2 => addr_matrix_f2,
327 -------------------------------------------------------------------------
343 -------------------------------------------------------------------------
328 status_full => status_full,
344 status_full => status_full,
329 status_full_ack => status_full_ack,
345 status_full_ack => status_full_ack,
330 status_full_err => status_full_err,
346 status_full_err => status_full_err,
331 status_new_err => status_new_err,
347 status_new_err => status_new_err,
332 data_shaping_BW => OPEN,
348 data_shaping_BW => OPEN,
333 data_shaping_SP0 => OPEN,
349 data_shaping_SP0 => OPEN,
334 data_shaping_SP1 => OPEN,
350 data_shaping_SP1 => OPEN,
335 data_shaping_R0 => OPEN,
351 data_shaping_R0 => OPEN,
336 data_shaping_R1 => OPEN,
352 data_shaping_R1 => OPEN,
337 delta_snapshot => OPEN,
353 delta_snapshot => OPEN,
338 delta_f0 => OPEN,
354 delta_f0 => OPEN,
339 delta_f0_2 => OPEN,
355 delta_f0_2 => OPEN,
340 delta_f1 => OPEN,
356 delta_f1 => OPEN,
341 delta_f2 => OPEN,
357 delta_f2 => OPEN,
342 nb_data_by_buffer => OPEN,
358 nb_data_by_buffer => OPEN,
343 nb_word_by_buffer => OPEN,
359 nb_word_by_buffer => OPEN,
344 nb_snapshot_param => OPEN,
360 nb_snapshot_param => OPEN,
345 enable_f0 => OPEN,
361 enable_f0 => OPEN,
346 enable_f1 => OPEN,
362 enable_f1 => OPEN,
347 enable_f2 => OPEN,
363 enable_f2 => OPEN,
348 enable_f3 => OPEN,
364 enable_f3 => OPEN,
349 burst_f0 => OPEN,
365 burst_f0 => OPEN,
350 burst_f1 => OPEN,
366 burst_f1 => OPEN,
351 burst_f2 => OPEN,
367 burst_f2 => OPEN,
352 run => OPEN,
368 run => OPEN,
353 addr_data_f0 => OPEN,
369 addr_data_f0 => OPEN,
354 addr_data_f1 => OPEN,
370 addr_data_f1 => OPEN,
355 addr_data_f2 => OPEN,
371 addr_data_f2 => OPEN,
356 addr_data_f3 => OPEN,
372 addr_data_f3 => OPEN,
357 start_date => OPEN);
373 start_date => OPEN);
358
374
359
375
360
376
361
377
378 read_status_t <= TRANSPORT apbo.pirq(0) AFTER 200 us;
362
379
380 PROCESS (clk25MHz, rstn)
381 BEGIN
382 IF rstn = '0' THEN
383 ready_reg <= (OTHERS => '0');
384 --read_status <= '0';
385 apbi.psel(4) <= '0';
386 apbi.pwrite <= '0';
387 apbi.penable <= '0';
388 apbi.paddr(7 DOWNTO 2) <= (OTHERS => '0');
389 ELSIF clk25MHz'event AND clk25MHz = '1' THEN
390 apbi.psel(4) <= '1';
391 apbi.paddr(7 DOWNTO 2) <= "000001";
392 apbi.penable <= '1';
393 read_status <= apbo.pirq(0);
363
394
395 IF read_status = '1' AND irq_ongoing = '0' THEN
396 ready_reg <= apbo.prdata(5 DOWNTO 0);
397 irq_ongoing <= '1';
398 END IF;
399
400 IF read_status_t = '0' THEN
401 apbi.pwrite <= '0';
402 ELSE
403 irq_ongoing <= '0';
404 apbi.pwrite <= '1';
405 apbi.pwdata(31 DOWNTO 6) <= (OTHERS => '0');
406 apbi.pwdata(5 DOWNTO 0) <= ready_reg;
407 ready_reg <= (OTHERS => '0');
408 END IF;
409
410 END IF;
411 END PROCESS;
364
412
365
413
366
414
367
415
368
416
369
417
370
418
371
419
372
420
373
421
374 -- PROCESS (clk25MHz, rstn)
422 -- PROCESS (clk25MHz, rstn)
375 -- BEGIN -- PROCESS
423 -- BEGIN -- PROCESS
376 -- IF rstn = '0' THEN -- asynchronous reset (active low)
424 -- IF rstn = '0' THEN -- asynchronous reset (active low)
377 -- status_ready_matrix_f0 <= '0';
425 -- status_ready_matrix_f0 <= '0';
378 ---- status_ready_matrix_f0_1 <= '0';
426 ---- status_ready_matrix_f0_1 <= '0';
379 -- status_ready_matrix_f1 <= '0';
427 -- status_ready_matrix_f1 <= '0';
380 -- status_ready_matrix_f2 <= '0';
428 -- status_ready_matrix_f2 <= '0';
381 -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
429 -- ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
382 -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
430 -- status_ready_matrix_f0 <= status_ready_matrix_f0 OR ready_matrix_f0;
383 ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
431 ---- status_ready_matrix_f0_1 <= status_ready_matrix_f0_1 OR ready_matrix_f0_1;
384 -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
432 -- status_ready_matrix_f1 <= status_ready_matrix_f1 OR ready_matrix_f1;
385 -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
433 -- status_ready_matrix_f2 <= status_ready_matrix_f2 OR ready_matrix_f2;
386 -- END IF;
434 -- END IF;
387 -- END PROCESS;
435 -- END PROCESS;
388
436
389
437
390
438
391 -- status_error_anticipating_empty_fifo <= '0';
439 -- status_error_anticipating_empty_fifo <= '0';
392 -- status_error_bad_component_error <= '0';
440 -- status_error_bad_component_error <= '0';
393
441
394 -- config_active_interruption_onNewMatrix <= '0';
442 -- config_active_interruption_onNewMatrix <= '0';
395 -- config_active_interruption_onError <= '0';
443 -- config_active_interruption_onError <= '0';
396 -- addr_matrix_f0 <= (OTHERS => '0');
444 -- addr_matrix_f0 <= (OTHERS => '0');
397 -- addr_matrix_f0_1 <= (OTHERS => '0');
445 -- addr_matrix_f0_1 <= (OTHERS => '0');
398 -- addr_matrix_f1 <= (OTHERS => '0');
446 -- addr_matrix_f1 <= (OTHERS => '0');
399 -- addr_matrix_f2 <= (OTHERS => '0');
447 -- addr_matrix_f2 <= (OTHERS => '0');
400
448
401
449
402 PROCESS (clk25MHz, rstn)
450 PROCESS (clk25MHz, rstn)
403 BEGIN -- PROCESS
451 BEGIN -- PROCESS
404 IF rstn = '0' THEN -- asynchronous reset (active low)
452 IF rstn = '0' THEN -- asynchronous reset (active low)
405
453
406 dma_ren <= '1';
454 dma_ren <= '1';
407 dma_done <= '0';
455 dma_done <= '0';
408 ren_counter <= 0;
456 ren_counter <= 0;
409 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
457 ELSIF clk25MHz'event AND clk25MHz = '1' THEN -- rising clock edge
410 dma_ren <= '1';
458 dma_ren <= '1';
411 dma_done <= '0';
459 dma_done <= '0';
412
460
413 IF dma_valid_burst = '1' THEN
461 IF dma_valid_burst = '1' THEN
414 ren_counter <= 17;
462 ren_counter <= 17;
415 END IF;
463 END IF;
416
464
417 IF ren_counter > 1 THEN
465 IF ren_counter > 1 THEN
418 ren_counter <= ren_counter - 1;
466 ren_counter <= ren_counter - 1;
419 dma_ren <= '0';
467 dma_ren <= '0';
420 END IF;
468 END IF;
421
469
422 IF ren_counter = 1 THEN
470 IF ren_counter = 1 THEN
423 ren_counter <= 0;
471 ren_counter <= 0;
424 dma_done <= '1';
472 dma_done <= '1';
425 END IF;
473 END IF;
426
474
427 END IF;
475 END IF;
428 END PROCESS;
476 END PROCESS;
429
477
430
478
431 END beh;
479 END beh;
432
480
Show file before | Show file after | Hide comments
@@ -1,212 +1,230
1 onerror {resume}
1 onerror {resume}
2 quietly WaveActivateNextPane {} 0
2 quietly WaveActivateNextPane {} 0
3 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(0)
4 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(1)
5 add wave -noupdate -expand -group debug -expand -group FSM_MS_DMA_state /tb/lpp_lfr_ms_1/debug_reg(2)
6 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(5)
7 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(4)
8 add wave -noupdate -expand -group debug -expand -group status_ready_matrix /tb/lpp_lfr_ms_1/debug_reg(3)
9 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(8)
10 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(7)
11 add wave -noupdate -expand -group debug -expand -group matrix_ready /tb/lpp_lfr_ms_1/debug_reg(6)
12 add wave -noupdate -expand -group debug -expand /tb/lpp_lfr_ms_1/debug_reg
13 add wave -noupdate -expand -group debug /tb/lpp_lfr_apbreg_1/apbi
14 add wave -noupdate -expand -group debug -subitemconfig {/tb/lpp_lfr_apbreg_1/apbo.pirq {-height 15 -radix hexadecimal}} /tb/lpp_lfr_apbreg_1/apbo
15 add wave -noupdate -expand -group debug /tb/ready_reg
16 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(0)
17 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(1)
18 add wave -noupdate -expand -group Logic /tb/lpp_lfr_ms_1/debug_reg(2)
19 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/debug_signal
20 add wave -noupdate -divider {New Divider}
3 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
21 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_wen
4 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
22 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f0_wdata
5 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
23 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f1_wen
6 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
24 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f1_wdata
7 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
25 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f2_wen
8 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
26 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/sample_f2_wdata
9 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
27 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/wen
10 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
28 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/full
11 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
29 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/almost_full
12 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
30 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/empty
13 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
31 add wave -noupdate -group FIFO_f0_A /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/ren
14 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
32 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/raddr_vect
15 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
33 add wave -noupdate -group FIFO_f0_A -radix decimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/waddr_vect
16 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
34 add wave -noupdate -group FIFO_f0_A -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f0_a/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
17 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
35 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/wen
18 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
36 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/full
19 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
37 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/almost_full
20 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
38 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/empty
21 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
39 add wave -noupdate -expand -group FIFO_f0_B /tb/lpp_lfr_ms_1/lppfifoxn_f0_b/ren
22 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
40 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/wen
23 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk
41 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/rwclk
24 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
42 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/full
25 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
43 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/almost_full
26 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
44 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/empty
27 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
45 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/ren
28 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
46 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull
29 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
47 add wave -noupdate -expand -group FIFO_f1 /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/sfull_s
30 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
48 add wave -noupdate -expand -group FIFO_f1 -radix hexadecimal /tb/lpp_lfr_ms_1/lppfifoxn_f1/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
31 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
49 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/wen
32 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
50 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/full
33 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
51 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/almost_full
34 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
52 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/empty
35 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
53 add wave -noupdate -expand -group FIFO_f2 /tb/lpp_lfr_ms_1/lppfifoxn_f2/ren
36 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
54 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_select_channel
37 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
55 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_fft
38 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
56 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f0
39 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
57 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f1
40 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
58 add wave -noupdate -expand -group ERROR /tb/lpp_lfr_ms_1/error_wen_f2
41 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
59 add wave -noupdate /tb/lpp_lfr_ms_1/status_channel
42 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
60 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
43 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
61 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
44 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
62 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(2)/lpp_fifo_1/memcel/cram/ramarray
45 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
63 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(3)/lpp_fifo_1/memcel/cram/ramarray
46 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
64 add wave -noupdate -group FIFO_MS_INPUT -radix hexadecimal /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/fifos(4)/lpp_fifo_1/memcel/cram/ramarray
47 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
65 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/current_fifo_load
48 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
66 add wave -noupdate /tb/lpp_lfr_ms_1/state_fsm_load_ms_memory
49 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
67 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/almost_full
50 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
68 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/empty
51 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
69 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/full
52 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
70 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wdata
53 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
71 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_spectralmatrix/wen
54 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
72 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_locked
55 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
73 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_rdata
56 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
74 add wave -noupdate /tb/lpp_lfr_ms_1/mem_in_sm_ren
57 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
75 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_auto
58 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
76 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_done
59 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
77 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/correlation_start
60 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
78 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_data
61 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
79 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_empty
62 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
80 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_in_ren
63 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
81 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_data
64 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
82 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_full
65 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
83 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/fifo_out_wen
66 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
84 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op1
67 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
85 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/op2
68 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
86 add wave -noupdate -group MS_CALCULATION -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/res
69 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
87 add wave -noupdate -group MS_CALCULATION /tb/lpp_lfr_ms_1/ms_calculation_1/state
70 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
88 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
71 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
89 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
72 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
90 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
73 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
91 add wave -noupdate /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
74 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect
92 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect
75 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s
93 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/raddr_vect_s
76 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect
94 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect
77 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s
95 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/waddr_vect_s
78 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
96 add wave -noupdate -expand -group FIFO_1 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
79 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect
97 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect
80 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s
98 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/raddr_vect_s
81 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect
99 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect
82 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s
100 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/waddr_vect_s
83 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
101 add wave -noupdate -expand -group FIF0_0 -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
84 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
102 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
85 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
103 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0_end
86 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
104 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
87 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
105 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1_end
88 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
106 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_0_ready
89 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
107 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_1_ready
90 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
108 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fifo_ongoing
91 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data
109 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_data
92 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty
110 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_empty
93 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren
111 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_ren
94 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
112 add wave -noupdate -expand -group FSM_DMA_FIFO_IN -radix hexadecimal /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
95 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr
113 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_addr
96 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data
114 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_data
97 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done
115 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_done
98 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
116 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_ren
99 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
117 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid
100 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
118 add wave -noupdate -expand -group DMA_OUTPUT /tb/dma_valid_burst
101 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
119 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f1
102 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
120 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/matrix_time_f2
103 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
121 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f1
104 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
122 add wave -noupdate -expand -group DMA_OUTPUT -radix hexadecimal /tb/ready_matrix_f2
105 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
123 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/state
106 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type
124 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/matrix_type
107 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
125 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type_pre
108 add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
126 add wave -noupdate -radix unsigned /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/component_type
109 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
127 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/header_check_ok
110 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
128 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_empty
111 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
129 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/log_empty_fifo
112 add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error
130 add wave -noupdate /tb/lpp_lfr_ms_1/error_bad_component_error
113 add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full
131 add wave -noupdate /tb/lpp_lfr_ms_1/error_buffer_full
114 add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write
132 add wave -noupdate /tb/lpp_lfr_ms_1/error_input_fifo_write
115 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
133 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op1
116 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
134 add wave -noupdate -group ALU -radix decimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/op2
117 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
135 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/res
118 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
136 add wave -noupdate -group ALU -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/comp
119 add wave -noupdate -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
137 add wave -noupdate -group ALU -radix hexadecimal -expand -subitemconfig {/tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(2) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(1) {-height 15 -radix hexadecimal} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl(0) {-height 15 -radix hexadecimal}} /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/ctrl
120 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
138 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/reuse
121 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
139 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wen
122 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
140 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/wdata
123 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
141 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/ren
124 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
142 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/rdata
125 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
143 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/empty
126 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
144 add wave -noupdate -group MEM_OUT_WRITE -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/full
127 add wave -noupdate -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
145 add wave -noupdate -group MEM_OUT_WRITE /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/almost_full
128 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
146 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(0)/lpp_fifo_1/memcel/cram/ramarray
129 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
147 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/mem_out_spectralmatrix/fifos(1)/lpp_fifo_1/memcel/cram/ramarray
130 add wave -noupdate -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
148 add wave -noupdate -group MULT /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/mult
131 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
149 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op1
132 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
150 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/op2
133 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
151 add wave -noupdate -group MULT -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/multiplieri_nst/res
134 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
152 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/add
135 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
153 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/clr
136 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
154 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/load
137 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
155 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op1
138 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
156 add wave -noupdate -group ADD -radix hexadecimal /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/op2
139 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
157 add wave -noupdate -group ADD /tb/lpp_lfr_ms_1/ms_calculation_1/alu_ms/arith/macinst/adder_inst/res
140 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/reg_sp
158 add wave -noupdate -expand /tb/lpp_lfr_apbreg_1/reg_sp
141 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
159 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
142 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
160 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
143 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
161 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
144 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
162 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
145 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
163 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
146 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
164 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
147 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
165 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
148 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
166 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
149 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
167 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
150 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
168 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
151 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
169 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
152 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
170 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
153 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
171 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
154 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 -radix hexadecimal /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
172 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 -radix hexadecimal /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
155 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
173 add wave -noupdate -expand -group APB_REG_MS_POInTER_F0 /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
156 add wave -noupdate /tb/lpp_lfr_ms_1/coarse_time
174 add wave -noupdate /tb/lpp_lfr_ms_1/coarse_time
157 add wave -noupdate /tb/lpp_lfr_ms_1/fine_time
175 add wave -noupdate /tb/lpp_lfr_ms_1/fine_time
158 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_matrix_time
176 add wave -noupdate /tb/lpp_lfr_ms_1/lpp_lfr_ms_fsmdma_1/fifo_matrix_time
159 add wave -noupdate /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
177 add wave -noupdate /tb/lpp_lfr_ms_1/fsm_dma_fifo_status
160 add wave -noupdate /tb/lpp_lfr_ms_1/status_component
178 add wave -noupdate /tb/lpp_lfr_ms_1/status_component
161 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
179 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_0
162 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
180 add wave -noupdate /tb/lpp_lfr_ms_1/status_component_fifo_1
163 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_ms
181 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_ms
164 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_component
182 add wave -noupdate /tb/lpp_lfr_ms_1/ms_control_1/current_status_component
165 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/status_channel
183 add wave -noupdate -radix hexadecimal /tb/lpp_lfr_ms_1/status_channel
166 add wave -noupdate /tb/lpp_lfr_ms_1/all_time
184 add wave -noupdate /tb/lpp_lfr_ms_1/all_time
167 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_a
185 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_a
168 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_b
186 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f0_b
169 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f1
187 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f1
170 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f2
188 add wave -noupdate /tb/lpp_lfr_ms_1/time_reg_f2
171 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_wen
189 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_wen
172 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_ren
190 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_ren
173 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_rdata
191 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_rdata
174 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_full
192 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_full
175 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_empty
193 add wave -noupdate /tb/lpp_lfr_ms_1/sample_f0_a_empty
176 add wave -noupdate /tb/matrix_time_f0
194 add wave -noupdate /tb/matrix_time_f0
177 add wave -noupdate /tb/matrix_time_f1
195 add wave -noupdate /tb/matrix_time_f1
178 add wave -noupdate /tb/matrix_time_f2
196 add wave -noupdate /tb/matrix_time_f2
179 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
197 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/clk
180 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
198 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/rstn
181 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
199 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_status_ready_matrix
182 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
200 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_ready_matrix
183 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
201 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_addr_matrix
184 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
202 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg0_matrix_time
185 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
203 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_status_ready_matrix
186 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
204 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_ready_matrix
187 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
205 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_addr_matrix
188 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
206 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/reg1_matrix_time
189 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
207 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/ready_matrix
190 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
208 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/status_ready_matrix
191 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
209 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/addr_matrix
192 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
210 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/matrix_time
193 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
211 add wave -noupdate /tb/lpp_lfr_apbreg_1/lpp_apbreg_ms_pointer_f0/current_reg
194 TreeUpdate [SetDefaultTree]
212 TreeUpdate [SetDefaultTree]
195 WaveRestoreCursors {{Cursor 1} {189796403054 ps} 0} {{Cursor 2} {30152624373 ps} 0} {{Cursor 3} {10666401890 ps} 0} {{Cursor 4} {69917366400 ps} 0} {{Cursor 5} {87243365384 ps} 0}
213 WaveRestoreCursors {{Cursor 1} {123239471127 ps} 0}
196 configure wave -namecolwidth 486
214 configure wave -namecolwidth 486
197 configure wave -valuecolwidth 112
215 configure wave -valuecolwidth 112
198 configure wave -justifyvalue left
216 configure wave -justifyvalue left
199 configure wave -signalnamewidth 0
217 configure wave -signalnamewidth 0
200 configure wave -snapdistance 10
218 configure wave -snapdistance 10
201 configure wave -datasetprefix 0
219 configure wave -datasetprefix 0
202 configure wave -rowmargin 4
220 configure wave -rowmargin 4
203 configure wave -childrowmargin 2
221 configure wave -childrowmargin 2
204 configure wave -gridoffset 0
222 configure wave -gridoffset 0
205 configure wave -gridperiod 1
223 configure wave -gridperiod 1
206 configure wave -griddelta 40
224 configure wave -griddelta 40
207 configure wave -timeline 0
225 configure wave -timeline 0
208 configure wave -timelineunits ps
226 configure wave -timelineunits ps
209 update
227 update
210 WaveRestoreZoom {0 ps} {105000147 ns}
228 WaveRestoreZoom {124629370639 ps} {125891337681 ps}
211 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
229 bookmark add wave bookmark0 {{61745287067 ps} {63754655343 ps}} 0
212 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
230 bookmark add wave bookmark1 {{61745287067 ps} {63754655343 ps}} 0
Show file before | Show file after | Hide comments
@@ -1,735 +1,748
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples(2 DOWNTO 0);
49 sample_B : IN Samples(2 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
50 sample_E : IN Samples(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63 --
63 --
64 --
65 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
66 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
67
64 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
68 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
65
69
66 --debug
70 --debug
67 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 --debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 --debug_f0_data_valid : OUT STD_LOGIC;
72 --debug_f0_data_valid : OUT STD_LOGIC;
69 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
73 --debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 --debug_f1_data_valid : OUT STD_LOGIC;
74 --debug_f1_data_valid : OUT STD_LOGIC;
71 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
75 --debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 --debug_f2_data_valid : OUT STD_LOGIC;
76 --debug_f2_data_valid : OUT STD_LOGIC;
73 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
77 --debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
74 --debug_f3_data_valid : OUT STD_LOGIC;
78 --debug_f3_data_valid : OUT STD_LOGIC;
75
79
76 ---- debug FIFO_IN
80 ---- debug FIFO_IN
77 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 --debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
82 --debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
79 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 --debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
84 --debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
81 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 --debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
86 --debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
83 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 --debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
88 --debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
85
89
86 ----debug FIFO OUT
90 ----debug FIFO OUT
87 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 --debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
92 --debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
89 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
93 --debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
94 --debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
91 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
95 --debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
96 --debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
93 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
97 --debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
94 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
98 --debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
95
99
96 ----debug DMA IN
100 ----debug DMA IN
97 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
101 --debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
102 --debug_f0_data_dma_in_valid : OUT STD_LOGIC;
99 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
103 --debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
104 --debug_f1_data_dma_in_valid : OUT STD_LOGIC;
101 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 --debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
106 --debug_f2_data_dma_in_valid : OUT STD_LOGIC;
103 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 --debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
104 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
108 --debug_f3_data_dma_in_valid : OUT STD_LOGIC
105 );
109 );
106 END lpp_lfr;
110 END lpp_lfr;
107
111
108 ARCHITECTURE beh OF lpp_lfr IS
112 ARCHITECTURE beh OF lpp_lfr IS
109 --SIGNAL sample : Samples14v(7 DOWNTO 0);
113 --SIGNAL sample : Samples14v(7 DOWNTO 0);
110 SIGNAL sample_s : Samples(7 DOWNTO 0);
114 SIGNAL sample_s : Samples(7 DOWNTO 0);
111 --
115 --
112 SIGNAL data_shaping_SP0 : STD_LOGIC;
116 SIGNAL data_shaping_SP0 : STD_LOGIC;
113 SIGNAL data_shaping_SP1 : STD_LOGIC;
117 SIGNAL data_shaping_SP1 : STD_LOGIC;
114 SIGNAL data_shaping_R0 : STD_LOGIC;
118 SIGNAL data_shaping_R0 : STD_LOGIC;
115 SIGNAL data_shaping_R1 : STD_LOGIC;
119 SIGNAL data_shaping_R1 : STD_LOGIC;
116 --
120 --
117 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
121 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
122 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
120 --
124 --
121 SIGNAL sample_f0_val : STD_LOGIC;
125 SIGNAL sample_f0_val : STD_LOGIC;
122 SIGNAL sample_f1_val : STD_LOGIC;
126 SIGNAL sample_f1_val : STD_LOGIC;
123 SIGNAL sample_f2_val : STD_LOGIC;
127 SIGNAL sample_f2_val : STD_LOGIC;
124 SIGNAL sample_f3_val : STD_LOGIC;
128 SIGNAL sample_f3_val : STD_LOGIC;
125 --
129 --
126 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
131 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
128 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
132 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
129 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
130 --
134 --
131 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
135 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
132 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
136 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
133 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
137 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
134
138
135 -- SM
139 -- SM
136 SIGNAL ready_matrix_f0 : STD_LOGIC;
140 SIGNAL ready_matrix_f0 : STD_LOGIC;
137 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
141 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
138 SIGNAL ready_matrix_f1 : STD_LOGIC;
142 SIGNAL ready_matrix_f1 : STD_LOGIC;
139 SIGNAL ready_matrix_f2 : STD_LOGIC;
143 SIGNAL ready_matrix_f2 : STD_LOGIC;
140 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
144 -- SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
141 SIGNAL error_bad_component_error : STD_LOGIC;
145 SIGNAL error_bad_component_error : STD_LOGIC;
142 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 -- SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
147 SIGNAL status_ready_matrix_f0 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
148 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
145 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
149 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
146 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
150 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
147 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
151 -- SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
148 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
152 -- SIGNAL status_error_bad_component_error : STD_LOGIC;
149 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
153 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
150 SIGNAL config_active_interruption_onError : STD_LOGIC;
154 SIGNAL config_active_interruption_onError : STD_LOGIC;
151 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
156 -- SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
153 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
155
159
156 -- WFP
160 -- WFP
157 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
160 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
167 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166
170
167 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
171 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
168 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
172 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
169 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
173 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
170 SIGNAL enable_f0 : STD_LOGIC;
174 SIGNAL enable_f0 : STD_LOGIC;
171 SIGNAL enable_f1 : STD_LOGIC;
175 SIGNAL enable_f1 : STD_LOGIC;
172 SIGNAL enable_f2 : STD_LOGIC;
176 SIGNAL enable_f2 : STD_LOGIC;
173 SIGNAL enable_f3 : STD_LOGIC;
177 SIGNAL enable_f3 : STD_LOGIC;
174 SIGNAL burst_f0 : STD_LOGIC;
178 SIGNAL burst_f0 : STD_LOGIC;
175 SIGNAL burst_f1 : STD_LOGIC;
179 SIGNAL burst_f1 : STD_LOGIC;
176 SIGNAL burst_f2 : STD_LOGIC;
180 SIGNAL burst_f2 : STD_LOGIC;
177 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
179 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181
185
182 SIGNAL run : STD_LOGIC;
186 SIGNAL run : STD_LOGIC;
183 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
187 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
184
188
185 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
187 SIGNAL data_f0_data_out_valid : STD_LOGIC;
191 SIGNAL data_f0_data_out_valid : STD_LOGIC;
188 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
192 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
189 SIGNAL data_f0_data_out_ren : STD_LOGIC;
193 SIGNAL data_f0_data_out_ren : STD_LOGIC;
190 --f1
194 --f1
191 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f1_data_out_valid : STD_LOGIC;
197 SIGNAL data_f1_data_out_valid : STD_LOGIC;
194 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
198 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
195 SIGNAL data_f1_data_out_ren : STD_LOGIC;
199 SIGNAL data_f1_data_out_ren : STD_LOGIC;
196 --f2
200 --f2
197 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
199 SIGNAL data_f2_data_out_valid : STD_LOGIC;
203 SIGNAL data_f2_data_out_valid : STD_LOGIC;
200 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
204 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
201 SIGNAL data_f2_data_out_ren : STD_LOGIC;
205 SIGNAL data_f2_data_out_ren : STD_LOGIC;
202 --f3
206 --f3
203 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
207 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
208 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL data_f3_data_out_valid : STD_LOGIC;
209 SIGNAL data_f3_data_out_valid : STD_LOGIC;
206 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
210 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
207 SIGNAL data_f3_data_out_ren : STD_LOGIC;
211 SIGNAL data_f3_data_out_ren : STD_LOGIC;
208
212
209 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
210 --
214 --
211 -----------------------------------------------------------------------------
215 -----------------------------------------------------------------------------
212 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
216 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
213 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
217 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
214 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
218 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
215 --f1
219 --f1
216 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
220 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
217 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
221 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
218 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
222 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
219 --f2
223 --f2
220 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
221 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
225 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
222 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
226 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
223 --f3
227 --f3
224 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
229 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
226 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
230 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
227
231
228 -----------------------------------------------------------------------------
232 -----------------------------------------------------------------------------
229 -- DMA RR
233 -- DMA RR
230 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
231 SIGNAL dma_sel_valid : STD_LOGIC;
235 SIGNAL dma_sel_valid : STD_LOGIC;
232 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
236 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
233 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
237 SIGNAL dma_rr_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
234 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
235 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
239 SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
236
240
237 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
241 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
238 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
242 SIGNAL dma_sel : STD_LOGIC_VECTOR(4 DOWNTO 0);
239
243
240 -----------------------------------------------------------------------------
244 -----------------------------------------------------------------------------
241 -- DMA_REG
245 -- DMA_REG
242 -----------------------------------------------------------------------------
246 -----------------------------------------------------------------------------
243 SIGNAL ongoing_reg : STD_LOGIC;
247 SIGNAL ongoing_reg : STD_LOGIC;
244 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
248 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
245 SIGNAL dma_send_reg : STD_LOGIC;
249 SIGNAL dma_send_reg : STD_LOGIC;
246 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
250 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
247 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
251 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
248 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
249
253
250
254
251 -----------------------------------------------------------------------------
255 -----------------------------------------------------------------------------
252 -- DMA
256 -- DMA
253 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
254 SIGNAL dma_send : STD_LOGIC;
258 SIGNAL dma_send : STD_LOGIC;
255 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
259 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
256 SIGNAL dma_done : STD_LOGIC;
260 SIGNAL dma_done : STD_LOGIC;
257 SIGNAL dma_ren : STD_LOGIC;
261 SIGNAL dma_ren : STD_LOGIC;
258 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
262 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
259 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
263 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
260 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
264 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
261
265
262 -----------------------------------------------------------------------------
266 -----------------------------------------------------------------------------
263 -- MS
267 -- MS
264 -----------------------------------------------------------------------------
268 -----------------------------------------------------------------------------
265
269
266 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 SIGNAL data_ms_addr : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL data_ms_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 SIGNAL data_ms_valid : STD_LOGIC;
272 SIGNAL data_ms_valid : STD_LOGIC;
269 SIGNAL data_ms_valid_burst : STD_LOGIC;
273 SIGNAL data_ms_valid_burst : STD_LOGIC;
270 SIGNAL data_ms_ren : STD_LOGIC;
274 SIGNAL data_ms_ren : STD_LOGIC;
271 SIGNAL data_ms_done : STD_LOGIC;
275 SIGNAL data_ms_done : STD_LOGIC;
272 SIGNAL dma_ms_ongoing : STD_LOGIC;
276 SIGNAL dma_ms_ongoing : STD_LOGIC;
273
277
274 SIGNAL run_ms : STD_LOGIC;
278 SIGNAL run_ms : STD_LOGIC;
275 SIGNAL ms_softandhard_rstn : STD_LOGIC;
279 SIGNAL ms_softandhard_rstn : STD_LOGIC;
276
280
277 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
281 SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
278 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
282 -- SIGNAL matrix_time_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
279 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
283 SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
280 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
284 SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
281
285
282
286
283 SIGNAL error_buffer_full : STD_LOGIC;
287 SIGNAL error_buffer_full : STD_LOGIC;
284 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
288 SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
285
289
286 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
290 SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
291 SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
287
292
288 BEGIN
293 BEGIN
289
294
290 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
295 sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
291 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
296 sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
292
297
293 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
298 --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
294 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
299 -- sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
295 --END GENERATE all_channel;
300 --END GENERATE all_channel;
296
301
297 -----------------------------------------------------------------------------
302 -----------------------------------------------------------------------------
298 lpp_lfr_filter_1 : lpp_lfr_filter
303 lpp_lfr_filter_1 : lpp_lfr_filter
299 GENERIC MAP (
304 GENERIC MAP (
300 Mem_use => Mem_use)
305 Mem_use => Mem_use)
301 PORT MAP (
306 PORT MAP (
302 sample => sample_s,
307 sample => sample_s,
303 sample_val => sample_val,
308 sample_val => sample_val,
304 clk => clk,
309 clk => clk,
305 rstn => rstn,
310 rstn => rstn,
306 data_shaping_SP0 => data_shaping_SP0,
311 data_shaping_SP0 => data_shaping_SP0,
307 data_shaping_SP1 => data_shaping_SP1,
312 data_shaping_SP1 => data_shaping_SP1,
308 data_shaping_R0 => data_shaping_R0,
313 data_shaping_R0 => data_shaping_R0,
309 data_shaping_R1 => data_shaping_R1,
314 data_shaping_R1 => data_shaping_R1,
310 sample_f0_val => sample_f0_val,
315 sample_f0_val => sample_f0_val,
311 sample_f1_val => sample_f1_val,
316 sample_f1_val => sample_f1_val,
312 sample_f2_val => sample_f2_val,
317 sample_f2_val => sample_f2_val,
313 sample_f3_val => sample_f3_val,
318 sample_f3_val => sample_f3_val,
314 sample_f0_wdata => sample_f0_data,
319 sample_f0_wdata => sample_f0_data,
315 sample_f1_wdata => sample_f1_data,
320 sample_f1_wdata => sample_f1_data,
316 sample_f2_wdata => sample_f2_data,
321 sample_f2_wdata => sample_f2_data,
317 sample_f3_wdata => sample_f3_data);
322 sample_f3_wdata => sample_f3_data);
318
323
319 -----------------------------------------------------------------------------
324 -----------------------------------------------------------------------------
320 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
325 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
321 GENERIC MAP (
326 GENERIC MAP (
322 nb_data_by_buffer_size => nb_data_by_buffer_size,
327 nb_data_by_buffer_size => nb_data_by_buffer_size,
323 nb_word_by_buffer_size => nb_word_by_buffer_size,
328 nb_word_by_buffer_size => nb_word_by_buffer_size,
324 nb_snapshot_param_size => nb_snapshot_param_size,
329 nb_snapshot_param_size => nb_snapshot_param_size,
325 delta_vector_size => delta_vector_size,
330 delta_vector_size => delta_vector_size,
326 delta_vector_size_f0_2 => delta_vector_size_f0_2,
331 delta_vector_size_f0_2 => delta_vector_size_f0_2,
327 pindex => pindex,
332 pindex => pindex,
328 paddr => paddr,
333 paddr => paddr,
329 pmask => pmask,
334 pmask => pmask,
330 pirq_ms => pirq_ms,
335 pirq_ms => pirq_ms,
331 pirq_wfp => pirq_wfp,
336 pirq_wfp => pirq_wfp,
332 top_lfr_version => top_lfr_version)
337 top_lfr_version => top_lfr_version)
333 PORT MAP (
338 PORT MAP (
334 HCLK => clk,
339 HCLK => clk,
335 HRESETn => rstn,
340 HRESETn => rstn,
336 apbi => apbi,
341 apbi => apbi,
337 apbo => apbo,
342 apbo => apbo,
338
343
339 run_ms => run_ms,
344 run_ms => run_ms,
340
345
341 ready_matrix_f0 => ready_matrix_f0,
346 ready_matrix_f0 => ready_matrix_f0,
342 -- ready_matrix_f0_1 => ready_matrix_f0_1,
347 -- ready_matrix_f0_1 => ready_matrix_f0_1,
343 ready_matrix_f1 => ready_matrix_f1,
348 ready_matrix_f1 => ready_matrix_f1,
344 ready_matrix_f2 => ready_matrix_f2,
349 ready_matrix_f2 => ready_matrix_f2,
345 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
350 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
346 error_bad_component_error => error_bad_component_error,
351 error_bad_component_error => error_bad_component_error,
347 error_buffer_full => error_buffer_full, -- TODO
352 error_buffer_full => error_buffer_full, -- TODO
348 error_input_fifo_write => error_input_fifo_write, -- TODO
353 error_input_fifo_write => error_input_fifo_write, -- TODO
349 -- debug_reg => debug_reg,
354 -- debug_reg => debug_reg,
350 status_ready_matrix_f0 => status_ready_matrix_f0,
355 status_ready_matrix_f0 => status_ready_matrix_f0,
351 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
356 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
352 status_ready_matrix_f1 => status_ready_matrix_f1,
357 status_ready_matrix_f1 => status_ready_matrix_f1,
353 status_ready_matrix_f2 => status_ready_matrix_f2,
358 status_ready_matrix_f2 => status_ready_matrix_f2,
354 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
359 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
355 -- status_error_bad_component_error => status_error_bad_component_error,
360 -- status_error_bad_component_error => status_error_bad_component_error,
356 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
361 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
357 config_active_interruption_onError => config_active_interruption_onError,
362 config_active_interruption_onError => config_active_interruption_onError,
358
363
359 matrix_time_f0 => matrix_time_f0,
364 matrix_time_f0 => matrix_time_f0,
360 -- matrix_time_f0_1 => matrix_time_f0_1,
365 -- matrix_time_f0_1 => matrix_time_f0_1,
361 matrix_time_f1 => matrix_time_f1,
366 matrix_time_f1 => matrix_time_f1,
362 matrix_time_f2 => matrix_time_f2,
367 matrix_time_f2 => matrix_time_f2,
363
368
364 addr_matrix_f0 => addr_matrix_f0,
369 addr_matrix_f0 => addr_matrix_f0,
365 -- addr_matrix_f0_1 => addr_matrix_f0_1,
370 -- addr_matrix_f0_1 => addr_matrix_f0_1,
366 addr_matrix_f1 => addr_matrix_f1,
371 addr_matrix_f1 => addr_matrix_f1,
367 addr_matrix_f2 => addr_matrix_f2,
372 addr_matrix_f2 => addr_matrix_f2,
368 -------------------------------------------------------------------------
373 -------------------------------------------------------------------------
369 status_full => status_full,
374 status_full => status_full,
370 status_full_ack => status_full_ack,
375 status_full_ack => status_full_ack,
371 status_full_err => status_full_err,
376 status_full_err => status_full_err,
372 status_new_err => status_new_err,
377 status_new_err => status_new_err,
373 data_shaping_BW => data_shaping_BW,
378 data_shaping_BW => data_shaping_BW,
374 data_shaping_SP0 => data_shaping_SP0,
379 data_shaping_SP0 => data_shaping_SP0,
375 data_shaping_SP1 => data_shaping_SP1,
380 data_shaping_SP1 => data_shaping_SP1,
376 data_shaping_R0 => data_shaping_R0,
381 data_shaping_R0 => data_shaping_R0,
377 data_shaping_R1 => data_shaping_R1,
382 data_shaping_R1 => data_shaping_R1,
378 delta_snapshot => delta_snapshot,
383 delta_snapshot => delta_snapshot,
379 delta_f0 => delta_f0,
384 delta_f0 => delta_f0,
380 delta_f0_2 => delta_f0_2,
385 delta_f0_2 => delta_f0_2,
381 delta_f1 => delta_f1,
386 delta_f1 => delta_f1,
382 delta_f2 => delta_f2,
387 delta_f2 => delta_f2,
383 nb_data_by_buffer => nb_data_by_buffer,
388 nb_data_by_buffer => nb_data_by_buffer,
384 nb_word_by_buffer => nb_word_by_buffer,
389 nb_word_by_buffer => nb_word_by_buffer,
385 nb_snapshot_param => nb_snapshot_param,
390 nb_snapshot_param => nb_snapshot_param,
386 enable_f0 => enable_f0,
391 enable_f0 => enable_f0,
387 enable_f1 => enable_f1,
392 enable_f1 => enable_f1,
388 enable_f2 => enable_f2,
393 enable_f2 => enable_f2,
389 enable_f3 => enable_f3,
394 enable_f3 => enable_f3,
390 burst_f0 => burst_f0,
395 burst_f0 => burst_f0,
391 burst_f1 => burst_f1,
396 burst_f1 => burst_f1,
392 burst_f2 => burst_f2,
397 burst_f2 => burst_f2,
393 run => run,
398 run => run,
394 addr_data_f0 => addr_data_f0,
399 addr_data_f0 => addr_data_f0,
395 addr_data_f1 => addr_data_f1,
400 addr_data_f1 => addr_data_f1,
396 addr_data_f2 => addr_data_f2,
401 addr_data_f2 => addr_data_f2,
397 addr_data_f3 => addr_data_f3,
402 addr_data_f3 => addr_data_f3,
398 start_date => start_date);
403 start_date => start_date,
404 debug_signal => debug_signal);
399
405
400 -----------------------------------------------------------------------------
406 -----------------------------------------------------------------------------
401 -----------------------------------------------------------------------------
407 -----------------------------------------------------------------------------
402 lpp_waveform_1 : lpp_waveform
408 lpp_waveform_1 : lpp_waveform
403 GENERIC MAP (
409 GENERIC MAP (
404 tech => inferred,
410 tech => inferred,
405 data_size => 6*16,
411 data_size => 6*16,
406 nb_data_by_buffer_size => nb_data_by_buffer_size,
412 nb_data_by_buffer_size => nb_data_by_buffer_size,
407 nb_word_by_buffer_size => nb_word_by_buffer_size,
413 nb_word_by_buffer_size => nb_word_by_buffer_size,
408 nb_snapshot_param_size => nb_snapshot_param_size,
414 nb_snapshot_param_size => nb_snapshot_param_size,
409 delta_vector_size => delta_vector_size,
415 delta_vector_size => delta_vector_size,
410 delta_vector_size_f0_2 => delta_vector_size_f0_2
416 delta_vector_size_f0_2 => delta_vector_size_f0_2
411 )
417 )
412 PORT MAP (
418 PORT MAP (
413 clk => clk,
419 clk => clk,
414 rstn => rstn,
420 rstn => rstn,
415
421
416 reg_run => run,
422 reg_run => run,
417 reg_start_date => start_date,
423 reg_start_date => start_date,
418 reg_delta_snapshot => delta_snapshot,
424 reg_delta_snapshot => delta_snapshot,
419 reg_delta_f0 => delta_f0,
425 reg_delta_f0 => delta_f0,
420 reg_delta_f0_2 => delta_f0_2,
426 reg_delta_f0_2 => delta_f0_2,
421 reg_delta_f1 => delta_f1,
427 reg_delta_f1 => delta_f1,
422 reg_delta_f2 => delta_f2,
428 reg_delta_f2 => delta_f2,
423
429
424 enable_f0 => enable_f0,
430 enable_f0 => enable_f0,
425 enable_f1 => enable_f1,
431 enable_f1 => enable_f1,
426 enable_f2 => enable_f2,
432 enable_f2 => enable_f2,
427 enable_f3 => enable_f3,
433 enable_f3 => enable_f3,
428 burst_f0 => burst_f0,
434 burst_f0 => burst_f0,
429 burst_f1 => burst_f1,
435 burst_f1 => burst_f1,
430 burst_f2 => burst_f2,
436 burst_f2 => burst_f2,
431
437
432 nb_data_by_buffer => nb_data_by_buffer,
438 nb_data_by_buffer => nb_data_by_buffer,
433 nb_word_by_buffer => nb_word_by_buffer,
439 nb_word_by_buffer => nb_word_by_buffer,
434 nb_snapshot_param => nb_snapshot_param,
440 nb_snapshot_param => nb_snapshot_param,
435 status_full => status_full,
441 status_full => status_full,
436 status_full_ack => status_full_ack,
442 status_full_ack => status_full_ack,
437 status_full_err => status_full_err,
443 status_full_err => status_full_err,
438 status_new_err => status_new_err,
444 status_new_err => status_new_err,
439
445
440 coarse_time => coarse_time,
446 coarse_time => coarse_time,
441 fine_time => fine_time,
447 fine_time => fine_time,
442
448
443 --f0
449 --f0
444 addr_data_f0 => addr_data_f0,
450 addr_data_f0 => addr_data_f0,
445 data_f0_in_valid => sample_f0_val,
451 data_f0_in_valid => sample_f0_val,
446 data_f0_in => sample_f0_data,
452 data_f0_in => sample_f0_data,
447 --f1
453 --f1
448 addr_data_f1 => addr_data_f1,
454 addr_data_f1 => addr_data_f1,
449 data_f1_in_valid => sample_f1_val,
455 data_f1_in_valid => sample_f1_val,
450 data_f1_in => sample_f1_data,
456 data_f1_in => sample_f1_data,
451 --f2
457 --f2
452 addr_data_f2 => addr_data_f2,
458 addr_data_f2 => addr_data_f2,
453 data_f2_in_valid => sample_f2_val,
459 data_f2_in_valid => sample_f2_val,
454 data_f2_in => sample_f2_data,
460 data_f2_in => sample_f2_data,
455 --f3
461 --f3
456 addr_data_f3 => addr_data_f3,
462 addr_data_f3 => addr_data_f3,
457 data_f3_in_valid => sample_f3_val,
463 data_f3_in_valid => sample_f3_val,
458 data_f3_in => sample_f3_data,
464 data_f3_in => sample_f3_data,
459 -- OUTPUT -- DMA interface
465 -- OUTPUT -- DMA interface
460 --f0
466 --f0
461 data_f0_addr_out => data_f0_addr_out_s,
467 data_f0_addr_out => data_f0_addr_out_s,
462 data_f0_data_out => data_f0_data_out,
468 data_f0_data_out => data_f0_data_out,
463 data_f0_data_out_valid => data_f0_data_out_valid_s,
469 data_f0_data_out_valid => data_f0_data_out_valid_s,
464 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
470 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
465 data_f0_data_out_ren => data_f0_data_out_ren,
471 data_f0_data_out_ren => data_f0_data_out_ren,
466 --f1
472 --f1
467 data_f1_addr_out => data_f1_addr_out_s,
473 data_f1_addr_out => data_f1_addr_out_s,
468 data_f1_data_out => data_f1_data_out,
474 data_f1_data_out => data_f1_data_out,
469 data_f1_data_out_valid => data_f1_data_out_valid_s,
475 data_f1_data_out_valid => data_f1_data_out_valid_s,
470 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
476 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
471 data_f1_data_out_ren => data_f1_data_out_ren,
477 data_f1_data_out_ren => data_f1_data_out_ren,
472 --f2
478 --f2
473 data_f2_addr_out => data_f2_addr_out_s,
479 data_f2_addr_out => data_f2_addr_out_s,
474 data_f2_data_out => data_f2_data_out,
480 data_f2_data_out => data_f2_data_out,
475 data_f2_data_out_valid => data_f2_data_out_valid_s,
481 data_f2_data_out_valid => data_f2_data_out_valid_s,
476 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
482 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
477 data_f2_data_out_ren => data_f2_data_out_ren,
483 data_f2_data_out_ren => data_f2_data_out_ren,
478 --f3
484 --f3
479 data_f3_addr_out => data_f3_addr_out_s,
485 data_f3_addr_out => data_f3_addr_out_s,
480 data_f3_data_out => data_f3_data_out,
486 data_f3_data_out => data_f3_data_out,
481 data_f3_data_out_valid => data_f3_data_out_valid_s,
487 data_f3_data_out_valid => data_f3_data_out_valid_s,
482 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
488 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
483 data_f3_data_out_ren => data_f3_data_out_ren ,
489 data_f3_data_out_ren => data_f3_data_out_ren ,
484
490
485 -------------------------------------------------------------------------
491 -------------------------------------------------------------------------
486 observation_reg => OPEN
492 observation_reg => OPEN
487
493
488 );
494 );
489
495
490
496
491 -----------------------------------------------------------------------------
497 -----------------------------------------------------------------------------
492 -- TEMP
498 -- TEMP
493 -----------------------------------------------------------------------------
499 -----------------------------------------------------------------------------
494
500
495 PROCESS (clk, rstn)
501 PROCESS (clk, rstn)
496 BEGIN -- PROCESS
502 BEGIN -- PROCESS
497 IF rstn = '0' THEN -- asynchronous reset (active low)
503 IF rstn = '0' THEN -- asynchronous reset (active low)
498 data_f0_data_out_valid <= '0';
504 data_f0_data_out_valid <= '0';
499 data_f0_data_out_valid_burst <= '0';
505 data_f0_data_out_valid_burst <= '0';
500 data_f1_data_out_valid <= '0';
506 data_f1_data_out_valid <= '0';
501 data_f1_data_out_valid_burst <= '0';
507 data_f1_data_out_valid_burst <= '0';
502 data_f2_data_out_valid <= '0';
508 data_f2_data_out_valid <= '0';
503 data_f2_data_out_valid_burst <= '0';
509 data_f2_data_out_valid_burst <= '0';
504 data_f3_data_out_valid <= '0';
510 data_f3_data_out_valid <= '0';
505 data_f3_data_out_valid_burst <= '0';
511 data_f3_data_out_valid_burst <= '0';
506 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
512 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
507 data_f0_data_out_valid <= data_f0_data_out_valid_s;
513 data_f0_data_out_valid <= data_f0_data_out_valid_s;
508 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
514 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
509 data_f1_data_out_valid <= data_f1_data_out_valid_s;
515 data_f1_data_out_valid <= data_f1_data_out_valid_s;
510 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
516 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
511 data_f2_data_out_valid <= data_f2_data_out_valid_s;
517 data_f2_data_out_valid <= data_f2_data_out_valid_s;
512 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
518 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
513 data_f3_data_out_valid <= data_f3_data_out_valid_s;
519 data_f3_data_out_valid <= data_f3_data_out_valid_s;
514 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
520 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
515 END IF;
521 END IF;
516 END PROCESS;
522 END PROCESS;
517
523
518 data_f0_addr_out <= data_f0_addr_out_s;
524 data_f0_addr_out <= data_f0_addr_out_s;
519 data_f1_addr_out <= data_f1_addr_out_s;
525 data_f1_addr_out <= data_f1_addr_out_s;
520 data_f2_addr_out <= data_f2_addr_out_s;
526 data_f2_addr_out <= data_f2_addr_out_s;
521 data_f3_addr_out <= data_f3_addr_out_s;
527 data_f3_addr_out <= data_f3_addr_out_s;
522
528
523 -----------------------------------------------------------------------------
529 -----------------------------------------------------------------------------
524 -- RoundRobin Selection For DMA
530 -- RoundRobin Selection For DMA
525 -----------------------------------------------------------------------------
531 -----------------------------------------------------------------------------
526
532
527 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
533 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
528 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
534 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
529 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
535 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
530 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
536 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
531
537
532 RR_Arbiter_4_1 : RR_Arbiter_4
538 RR_Arbiter_4_1 : RR_Arbiter_4
533 PORT MAP (
539 PORT MAP (
534 clk => clk,
540 clk => clk,
535 rstn => rstn,
541 rstn => rstn,
536 in_valid => dma_rr_valid,
542 in_valid => dma_rr_valid,
537 out_grant => dma_rr_grant_s);
543 out_grant => dma_rr_grant_s);
538
544
539 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
545 dma_rr_valid_ms(0) <= data_ms_valid OR data_ms_valid_burst;
540 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
546 dma_rr_valid_ms(1) <= '0' WHEN dma_rr_grant_s = "0000" ELSE '1';
541 dma_rr_valid_ms(2) <= '0';
547 dma_rr_valid_ms(2) <= '0';
542 dma_rr_valid_ms(3) <= '0';
548 dma_rr_valid_ms(3) <= '0';
543
549
544 RR_Arbiter_4_2 : RR_Arbiter_4
550 RR_Arbiter_4_2 : RR_Arbiter_4
545 PORT MAP (
551 PORT MAP (
546 clk => clk,
552 clk => clk,
547 rstn => rstn,
553 rstn => rstn,
548 in_valid => dma_rr_valid_ms,
554 in_valid => dma_rr_valid_ms,
549 out_grant => dma_rr_grant_ms);
555 out_grant => dma_rr_grant_ms);
550
556
551 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
557 dma_rr_grant <= dma_rr_grant_ms(0) & "0000" WHEN dma_rr_grant_ms(0) = '1' ELSE '0' & dma_rr_grant_s;
552
558
553
559
554 -----------------------------------------------------------------------------
560 -----------------------------------------------------------------------------
555 -- in : dma_rr_grant
561 -- in : dma_rr_grant
556 -- send
562 -- send
557 -- out : dma_sel
563 -- out : dma_sel
558 -- dma_valid_burst
564 -- dma_valid_burst
559 -- dma_sel_valid
565 -- dma_sel_valid
560 -----------------------------------------------------------------------------
566 -----------------------------------------------------------------------------
561 PROCESS (clk, rstn)
567 PROCESS (clk, rstn)
562 BEGIN -- PROCESS
568 BEGIN -- PROCESS
563 IF rstn = '0' THEN -- asynchronous reset (active low)
569 IF rstn = '0' THEN -- asynchronous reset (active low)
564 dma_sel <= (OTHERS => '0');
570 dma_sel <= (OTHERS => '0');
565 dma_send <= '0';
571 dma_send <= '0';
566 dma_valid_burst <= '0';
572 dma_valid_burst <= '0';
567 data_ms_done <= '0';
573 data_ms_done <= '0';
568 dma_ms_ongoing <= '0';
574 dma_ms_ongoing <= '0';
569 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
570 IF run = '1' THEN
576 IF run = '1' THEN
571 data_ms_done <= '0';
577 data_ms_done <= '0';
572 IF dma_sel = "00000" OR dma_done = '1' THEN
578 IF dma_sel = "00000" OR dma_done = '1' THEN
573 dma_sel <= dma_rr_grant;
579 dma_sel <= dma_rr_grant;
574 IF dma_rr_grant(0) = '1' THEN
580 IF dma_rr_grant(0) = '1' THEN
575 dma_ms_ongoing <= '0';
581 dma_ms_ongoing <= '0';
576 dma_send <= '1';
582 dma_send <= '1';
577 dma_valid_burst <= data_f0_data_out_valid_burst;
583 dma_valid_burst <= data_f0_data_out_valid_burst;
578 dma_sel_valid <= data_f0_data_out_valid;
584 dma_sel_valid <= data_f0_data_out_valid;
579 ELSIF dma_rr_grant(1) = '1' THEN
585 ELSIF dma_rr_grant(1) = '1' THEN
580 dma_ms_ongoing <= '0';
586 dma_ms_ongoing <= '0';
581 dma_send <= '1';
587 dma_send <= '1';
582 dma_valid_burst <= data_f1_data_out_valid_burst;
588 dma_valid_burst <= data_f1_data_out_valid_burst;
583 dma_sel_valid <= data_f1_data_out_valid;
589 dma_sel_valid <= data_f1_data_out_valid;
584 ELSIF dma_rr_grant(2) = '1' THEN
590 ELSIF dma_rr_grant(2) = '1' THEN
585 dma_ms_ongoing <= '0';
591 dma_ms_ongoing <= '0';
586 dma_send <= '1';
592 dma_send <= '1';
587 dma_valid_burst <= data_f2_data_out_valid_burst;
593 dma_valid_burst <= data_f2_data_out_valid_burst;
588 dma_sel_valid <= data_f2_data_out_valid;
594 dma_sel_valid <= data_f2_data_out_valid;
589 ELSIF dma_rr_grant(3) = '1' THEN
595 ELSIF dma_rr_grant(3) = '1' THEN
590 dma_ms_ongoing <= '0';
596 dma_ms_ongoing <= '0';
591 dma_send <= '1';
597 dma_send <= '1';
592 dma_valid_burst <= data_f3_data_out_valid_burst;
598 dma_valid_burst <= data_f3_data_out_valid_burst;
593 dma_sel_valid <= data_f3_data_out_valid;
599 dma_sel_valid <= data_f3_data_out_valid;
594 ELSIF dma_rr_grant(4) = '1' THEN
600 ELSIF dma_rr_grant(4) = '1' THEN
595 dma_ms_ongoing <= '1';
601 dma_ms_ongoing <= '1';
596 dma_send <= '1';
602 dma_send <= '1';
597 dma_valid_burst <= data_ms_valid_burst;
603 dma_valid_burst <= data_ms_valid_burst;
598 dma_sel_valid <= data_ms_valid;
604 dma_sel_valid <= data_ms_valid;
599 --ELSE
605 --ELSE
600 --dma_ms_ongoing <= '0';
606 --dma_ms_ongoing <= '0';
601 END IF;
607 END IF;
602
608
603 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
609 IF dma_ms_ongoing = '1' AND dma_done = '1' THEN
604 data_ms_done <= '1';
610 data_ms_done <= '1';
605 END IF;
611 END IF;
606 ELSE
612 ELSE
607 dma_sel <= dma_sel;
613 dma_sel <= dma_sel;
608 dma_send <= '0';
614 dma_send <= '0';
609 END IF;
615 END IF;
610 ELSE
616 ELSE
611 data_ms_done <= '0';
617 data_ms_done <= '0';
612 dma_sel <= (OTHERS => '0');
618 dma_sel <= (OTHERS => '0');
613 dma_send <= '0';
619 dma_send <= '0';
614 dma_valid_burst <= '0';
620 dma_valid_burst <= '0';
615 END IF;
621 END IF;
616 END IF;
622 END IF;
617 END PROCESS;
623 END PROCESS;
618
624
619
625
620 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
626 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
621 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
627 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
622 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
628 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
623 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
629 data_f3_addr_out WHEN dma_sel(3) = '1' ELSE
624 data_ms_addr;
630 data_ms_addr;
625
631
626 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
632 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
627 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
633 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
628 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
634 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
629 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
635 data_f3_data_out WHEN dma_sel(3) = '1' ELSE
630 data_ms_data;
636 data_ms_data;
631
637
632 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
638 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
633 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
639 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
634 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
640 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
635 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
641 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
636 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
642 data_ms_ren <= dma_ren WHEN dma_sel(4) = '1' ELSE '1';
637
643
638 dma_data_2 <= dma_data;
644 dma_data_2 <= dma_data;
639
645
640
646
641 -----------------------------------------------------------------------------
647 -----------------------------------------------------------------------------
642 -- DMA
648 -- DMA
643 -----------------------------------------------------------------------------
649 -----------------------------------------------------------------------------
644 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
650 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
645 GENERIC MAP (
651 GENERIC MAP (
646 tech => inferred,
652 tech => inferred,
647 hindex => hindex)
653 hindex => hindex)
648 PORT MAP (
654 PORT MAP (
649 HCLK => clk,
655 HCLK => clk,
650 HRESETn => rstn,
656 HRESETn => rstn,
651 run => run,
657 run => run,
652 AHB_Master_In => ahbi,
658 AHB_Master_In => ahbi,
653 AHB_Master_Out => ahbo,
659 AHB_Master_Out => ahbo,
654
660
655 send => dma_send,
661 send => dma_send,
656 valid_burst => dma_valid_burst,
662 valid_burst => dma_valid_burst,
657 done => dma_done,
663 done => dma_done,
658 ren => dma_ren,
664 ren => dma_ren,
659 address => dma_address,
665 address => dma_address,
660 data => dma_data_2);
666 data => dma_data_2);
661
667
662 -----------------------------------------------------------------------------
668 -----------------------------------------------------------------------------
663 -- Matrix Spectral
669 -- Matrix Spectral
664 -----------------------------------------------------------------------------
670 -----------------------------------------------------------------------------
665 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
671 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
666 NOT(sample_f0_val) & NOT(sample_f0_val);
672 NOT(sample_f0_val) & NOT(sample_f0_val);
667 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
673 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
668 NOT(sample_f1_val) & NOT(sample_f1_val);
674 NOT(sample_f1_val) & NOT(sample_f1_val);
669 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
675 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
670 NOT(sample_f3_val) & NOT(sample_f3_val);
676 NOT(sample_f3_val) & NOT(sample_f3_val);
671
677
672 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
678 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
673 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
679 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
674 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
680 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
675
681
676 -------------------------------------------------------------------------------
682 -------------------------------------------------------------------------------
677
683
678 ms_softandhard_rstn <= rstn AND run_ms AND run;
684 ms_softandhard_rstn <= rstn AND run_ms AND run;
679
685
680 -----------------------------------------------------------------------------
686 -----------------------------------------------------------------------------
681 lpp_lfr_ms_1 : lpp_lfr_ms
687 lpp_lfr_ms_1 : lpp_lfr_ms
682 GENERIC MAP (
688 GENERIC MAP (
683 Mem_use => Mem_use)
689 Mem_use => Mem_use)
684 PORT MAP (
690 PORT MAP (
685 clk => clk,
691 clk => clk,
686 rstn => ms_softandhard_rstn, --rstn,
692 rstn => ms_softandhard_rstn, --rstn,
687
693
688 coarse_time => coarse_time,
694 coarse_time => coarse_time,
689 fine_time => fine_time,
695 fine_time => fine_time,
690
696
691 sample_f0_wen => sample_f0_wen,
697 sample_f0_wen => sample_f0_wen,
692 sample_f0_wdata => sample_f0_wdata,
698 sample_f0_wdata => sample_f0_wdata,
693 sample_f1_wen => sample_f1_wen,
699 sample_f1_wen => sample_f1_wen,
694 sample_f1_wdata => sample_f1_wdata,
700 sample_f1_wdata => sample_f1_wdata,
695 sample_f2_wen => sample_f3_wen, -- TODO
701 sample_f2_wen => sample_f3_wen, -- TODO
696 sample_f2_wdata => sample_f3_wdata,-- TODO
702 sample_f2_wdata => sample_f3_wdata,-- TODO
697
703
698 dma_addr => data_ms_addr, --
704 dma_addr => data_ms_addr, --
699 dma_data => data_ms_data, --
705 dma_data => data_ms_data, --
700 dma_valid => data_ms_valid, --
706 dma_valid => data_ms_valid, --
701 dma_valid_burst => data_ms_valid_burst, --
707 dma_valid_burst => data_ms_valid_burst, --
702 dma_ren => data_ms_ren, --
708 dma_ren => data_ms_ren, --
703 dma_done => data_ms_done, --
709 dma_done => data_ms_done, --
704
710
705 ready_matrix_f0 => ready_matrix_f0,
711 ready_matrix_f0 => ready_matrix_f0,
706 ready_matrix_f1 => ready_matrix_f1,
712 ready_matrix_f1 => ready_matrix_f1,
707 ready_matrix_f2 => ready_matrix_f2,
713 ready_matrix_f2 => ready_matrix_f2,
708 error_bad_component_error => error_bad_component_error,
714 error_bad_component_error => error_bad_component_error,
709 error_buffer_full => error_buffer_full,
715 error_buffer_full => error_buffer_full,
710 error_input_fifo_write => error_input_fifo_write,
716 error_input_fifo_write => error_input_fifo_write,
711
717
712 debug_reg => debug_ms,--observation_reg,
718 debug_reg => debug_ms,--observation_reg,
719 observation_vector_0 => observation_vector_0,
720 observation_vector_1 => observation_vector_1,
713
721
714 status_ready_matrix_f0 => status_ready_matrix_f0,
722 status_ready_matrix_f0 => status_ready_matrix_f0,
715 status_ready_matrix_f1 => status_ready_matrix_f1,
723 status_ready_matrix_f1 => status_ready_matrix_f1,
716 status_ready_matrix_f2 => status_ready_matrix_f2,
724 status_ready_matrix_f2 => status_ready_matrix_f2,
717 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
725 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
718 config_active_interruption_onError => config_active_interruption_onError,
726 config_active_interruption_onError => config_active_interruption_onError,
719 addr_matrix_f0 => addr_matrix_f0,
727 addr_matrix_f0 => addr_matrix_f0,
720 addr_matrix_f1 => addr_matrix_f1,
728 addr_matrix_f1 => addr_matrix_f1,
721 addr_matrix_f2 => addr_matrix_f2,
729 addr_matrix_f2 => addr_matrix_f2,
722
730
723 matrix_time_f0 => matrix_time_f0,
731 matrix_time_f0 => matrix_time_f0,
724 matrix_time_f1 => matrix_time_f1,
732 matrix_time_f1 => matrix_time_f1,
725 matrix_time_f2 => matrix_time_f2);
733 matrix_time_f2 => matrix_time_f2);
726
734
727 -----------------------------------------------------------------------------
735 -----------------------------------------------------------------------------
728 observation_reg(31 DOWNTO 0) <= debug_ms(31-9 DOWNTO 0) &
736
729 dma_ms_ongoing & -- 8
737
730 data_ms_done & -- 7
738 observation_reg(31 DOWNTO 0) <=
731 dma_done & -- 6
739 dma_sel(4) & -- 31
732 dma_sel & -- 5 .. 1
740 dma_ms_ongoing & -- 30
733 ms_softandhard_rstn; -- 0
741 data_ms_done & -- 29
742 dma_done & -- 28
743 ms_softandhard_rstn & --27
744 debug_ms(14 DOWNTO 12) & -- 26 .. 24
745 debug_ms(11 DOWNTO 0) & -- 23 .. 12
746 debug_signal(11 DOWNTO 0); -- 11 .. 0
734
747
735 END beh;
748 END beh;
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@@ -1,675 +1,697
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_lfr_pkg.ALL;
31 USE lpp.lpp_lfr_pkg.ALL;
32 --USE lpp.lpp_amba.ALL;
32 --USE lpp.lpp_amba.ALL;
33 USE lpp.apb_devices_list.ALL;
33 USE lpp.apb_devices_list.ALL;
34 USE lpp.lpp_memory.ALL;
34 USE lpp.lpp_memory.ALL;
35 LIBRARY techmap;
35 LIBRARY techmap;
36 USE techmap.gencomp.ALL;
36 USE techmap.gencomp.ALL;
37
37
38 ENTITY lpp_lfr_apbreg IS
38 ENTITY lpp_lfr_apbreg IS
39 GENERIC (
39 GENERIC (
40 nb_data_by_buffer_size : INTEGER := 11;
40 nb_data_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
41 nb_word_by_buffer_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
42 nb_snapshot_param_size : INTEGER := 11;
43 delta_vector_size : INTEGER := 20;
43 delta_vector_size : INTEGER := 20;
44 delta_vector_size_f0_2 : INTEGER := 3;
44 delta_vector_size_f0_2 : INTEGER := 3;
45
45
46 pindex : INTEGER := 4;
46 pindex : INTEGER := 4;
47 paddr : INTEGER := 4;
47 paddr : INTEGER := 4;
48 pmask : INTEGER := 16#fff#;
48 pmask : INTEGER := 16#fff#;
49 pirq_ms : INTEGER := 0;
49 pirq_ms : INTEGER := 0;
50 pirq_wfp : INTEGER := 1;
50 pirq_wfp : INTEGER := 1;
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
51 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
52 PORT (
52 PORT (
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56
56
57 -- AMBA APB Slave Interface
57 -- AMBA APB Slave Interface
58 apbi : IN apb_slv_in_type;
58 apbi : IN apb_slv_in_type;
59 apbo : OUT apb_slv_out_type;
59 apbo : OUT apb_slv_out_type;
60
60
61 ---------------------------------------------------------------------------
61 ---------------------------------------------------------------------------
62 -- Spectral Matrix Reg
62 -- Spectral Matrix Reg
63 run_ms : OUT STD_LOGIC;
63 run_ms : OUT STD_LOGIC;
64 -- IN
64 -- IN
65 ready_matrix_f0 : IN STD_LOGIC;
65 ready_matrix_f0 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f1 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
67 ready_matrix_f2 : IN STD_LOGIC;
68
68
69 error_bad_component_error : IN STD_LOGIC;
69 error_bad_component_error : IN STD_LOGIC;
70 error_buffer_full : IN STD_LOGIC; -- TODO
70 error_buffer_full : IN STD_LOGIC; -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
71 error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO
72
72
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- OUT
75 -- OUT
76 status_ready_matrix_f0 : OUT STD_LOGIC;
76 status_ready_matrix_f0 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
77 status_ready_matrix_f1 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
78 status_ready_matrix_f2 : OUT STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
81 config_active_interruption_onError : OUT STD_LOGIC;
82
82
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86
86
87 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
89 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
90
90
91 ---------------------------------------------------------------------------
91 ---------------------------------------------------------------------------
92 ---------------------------------------------------------------------------
92 ---------------------------------------------------------------------------
93 -- WaveForm picker Reg
93 -- WaveForm picker Reg
94 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
94 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
95 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
95 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
96 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
97 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
98
98
99 -- OUT
99 -- OUT
100 data_shaping_BW : OUT STD_LOGIC;
100 data_shaping_BW : OUT STD_LOGIC;
101 data_shaping_SP0 : OUT STD_LOGIC;
101 data_shaping_SP0 : OUT STD_LOGIC;
102 data_shaping_SP1 : OUT STD_LOGIC;
102 data_shaping_SP1 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
103 data_shaping_R0 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
104 data_shaping_R1 : OUT STD_LOGIC;
105
105
106 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
106 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
107 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
108 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
108 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
109 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
109 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
110 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
111 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
111 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
112 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
112 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
113 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
113 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
114
114
115 enable_f0 : OUT STD_LOGIC;
115 enable_f0 : OUT STD_LOGIC;
116 enable_f1 : OUT STD_LOGIC;
116 enable_f1 : OUT STD_LOGIC;
117 enable_f2 : OUT STD_LOGIC;
117 enable_f2 : OUT STD_LOGIC;
118 enable_f3 : OUT STD_LOGIC;
118 enable_f3 : OUT STD_LOGIC;
119
119
120 burst_f0 : OUT STD_LOGIC;
120 burst_f0 : OUT STD_LOGIC;
121 burst_f1 : OUT STD_LOGIC;
121 burst_f1 : OUT STD_LOGIC;
122 burst_f2 : OUT STD_LOGIC;
122 burst_f2 : OUT STD_LOGIC;
123
123
124 run : OUT STD_LOGIC;
124 run : OUT STD_LOGIC;
125
125
126 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
129 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
130 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
131 ---------------------------------------------------------------------------
132 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
131 ---------------------------------------------------------------------------
133 ---------------------------------------------------------------------------
132 );
134 );
133
135
134 END lpp_lfr_apbreg;
136 END lpp_lfr_apbreg;
135
137
136 ARCHITECTURE beh OF lpp_lfr_apbreg IS
138 ARCHITECTURE beh OF lpp_lfr_apbreg IS
137
139
138 CONSTANT REVISION : INTEGER := 1;
140 CONSTANT REVISION : INTEGER := 1;
139
141
140 CONSTANT pconfig : apb_config_type := (
142 CONSTANT pconfig : apb_config_type := (
141 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
143 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
142 1 => apb_iobar(paddr, pmask));
144 1 => apb_iobar(paddr, pmask));
143
145
144 TYPE lpp_SpectralMatrix_regs IS RECORD
146 TYPE lpp_SpectralMatrix_regs IS RECORD
145 config_active_interruption_onNewMatrix : STD_LOGIC;
147 config_active_interruption_onNewMatrix : STD_LOGIC;
146 config_active_interruption_onError : STD_LOGIC;
148 config_active_interruption_onError : STD_LOGIC;
147 config_ms_run : STD_LOGIC;
149 config_ms_run : STD_LOGIC;
148 status_ready_matrix_f0_0 : STD_LOGIC;
150 status_ready_matrix_f0_0 : STD_LOGIC;
149 status_ready_matrix_f1_0 : STD_LOGIC;
151 status_ready_matrix_f1_0 : STD_LOGIC;
150 status_ready_matrix_f2_0 : STD_LOGIC;
152 status_ready_matrix_f2_0 : STD_LOGIC;
151 status_ready_matrix_f0_1 : STD_LOGIC;
153 status_ready_matrix_f0_1 : STD_LOGIC;
152 status_ready_matrix_f1_1 : STD_LOGIC;
154 status_ready_matrix_f1_1 : STD_LOGIC;
153 status_ready_matrix_f2_1 : STD_LOGIC;
155 status_ready_matrix_f2_1 : STD_LOGIC;
154 status_error_bad_component_error : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
155 status_error_buffer_full : STD_LOGIC;
157 status_error_buffer_full : STD_LOGIC;
156 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
158 status_error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
157
159
158 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
162 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
164
166
165 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
167 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
166 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
167 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
168 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
169 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
170 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
172 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
171 END RECORD;
173 END RECORD;
172 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
174 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
173
175
174 TYPE lpp_WaveformPicker_regs IS RECORD
176 TYPE lpp_WaveformPicker_regs IS RECORD
175 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 data_shaping_BW : STD_LOGIC;
180 data_shaping_BW : STD_LOGIC;
179 data_shaping_SP0 : STD_LOGIC;
181 data_shaping_SP0 : STD_LOGIC;
180 data_shaping_SP1 : STD_LOGIC;
182 data_shaping_SP1 : STD_LOGIC;
181 data_shaping_R0 : STD_LOGIC;
183 data_shaping_R0 : STD_LOGIC;
182 data_shaping_R1 : STD_LOGIC;
184 data_shaping_R1 : STD_LOGIC;
183 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
185 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
184 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
186 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
185 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
187 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
186 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
188 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
187 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
189 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
188 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
190 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
189 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
191 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
190 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
192 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
191 enable_f0 : STD_LOGIC;
193 enable_f0 : STD_LOGIC;
192 enable_f1 : STD_LOGIC;
194 enable_f1 : STD_LOGIC;
193 enable_f2 : STD_LOGIC;
195 enable_f2 : STD_LOGIC;
194 enable_f3 : STD_LOGIC;
196 enable_f3 : STD_LOGIC;
195 burst_f0 : STD_LOGIC;
197 burst_f0 : STD_LOGIC;
196 burst_f1 : STD_LOGIC;
198 burst_f1 : STD_LOGIC;
197 burst_f2 : STD_LOGIC;
199 burst_f2 : STD_LOGIC;
198 run : STD_LOGIC;
200 run : STD_LOGIC;
199 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
200 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
204 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
203 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
205 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
204 END RECORD;
206 END RECORD;
205 SIGNAL reg_wp : lpp_WaveformPicker_regs;
207 SIGNAL reg_wp : lpp_WaveformPicker_regs;
206
208
207 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
209 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
208
210
209 -----------------------------------------------------------------------------
211 -----------------------------------------------------------------------------
210 -- IRQ
212 -- IRQ
211 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
212 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
214 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
213 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
215 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
214 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
216 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
215 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
217 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
216 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
218 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
217 SIGNAL ored_irq_wfp : STD_LOGIC;
219 SIGNAL ored_irq_wfp : STD_LOGIC;
218
220
219 -----------------------------------------------------------------------------
221 -----------------------------------------------------------------------------
220 --
222 --
221 -----------------------------------------------------------------------------
223 -----------------------------------------------------------------------------
222 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
224 SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
223 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225 SIGNAL reg0_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
226 SIGNAL reg0_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
225
227
226 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
228 SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
227 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
229 SIGNAL reg1_addr_matrix_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
228 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
230 SIGNAL reg1_matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
229
231
230 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
232 SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
231 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
233 SIGNAL reg0_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
232 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
234 SIGNAL reg0_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
233
235
234 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
236 SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
235 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 SIGNAL reg1_addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
238 SIGNAL reg1_matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
237
239
238 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
240 SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
239 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL reg0_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
242 SIGNAL reg0_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
241
243
242 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
244 SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
243 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
245 SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
244 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
246 SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
247 SIGNAL apbo_irq_ms : STD_LOGIC;
248 SIGNAL apbo_irq_wfp : STD_LOGIC;
245
249
246 BEGIN -- beh
250 BEGIN -- beh
247
251
248 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
252 -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
249 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
253 -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
250 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
254 -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
251
255
252 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
256 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
253 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
257 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
254
258
255
259
256 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
260 -- addr_matrix_f0 <= reg_sp.addr_matrix_f0;
257 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
261 -- addr_matrix_f1 <= reg_sp.addr_matrix_f1;
258 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
262 -- addr_matrix_f2 <= reg_sp.addr_matrix_f2;
259
263
260
264
261 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
265 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
262 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
266 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
263 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
267 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
264 data_shaping_R0 <= reg_wp.data_shaping_R0;
268 data_shaping_R0 <= reg_wp.data_shaping_R0;
265 data_shaping_R1 <= reg_wp.data_shaping_R1;
269 data_shaping_R1 <= reg_wp.data_shaping_R1;
266
270
267 delta_snapshot <= reg_wp.delta_snapshot;
271 delta_snapshot <= reg_wp.delta_snapshot;
268 delta_f0 <= reg_wp.delta_f0;
272 delta_f0 <= reg_wp.delta_f0;
269 delta_f0_2 <= reg_wp.delta_f0_2;
273 delta_f0_2 <= reg_wp.delta_f0_2;
270 delta_f1 <= reg_wp.delta_f1;
274 delta_f1 <= reg_wp.delta_f1;
271 delta_f2 <= reg_wp.delta_f2;
275 delta_f2 <= reg_wp.delta_f2;
272 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
276 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
273 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
277 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
274 nb_snapshot_param <= reg_wp.nb_snapshot_param;
278 nb_snapshot_param <= reg_wp.nb_snapshot_param;
275
279
276 enable_f0 <= reg_wp.enable_f0;
280 enable_f0 <= reg_wp.enable_f0;
277 enable_f1 <= reg_wp.enable_f1;
281 enable_f1 <= reg_wp.enable_f1;
278 enable_f2 <= reg_wp.enable_f2;
282 enable_f2 <= reg_wp.enable_f2;
279 enable_f3 <= reg_wp.enable_f3;
283 enable_f3 <= reg_wp.enable_f3;
280
284
281 burst_f0 <= reg_wp.burst_f0;
285 burst_f0 <= reg_wp.burst_f0;
282 burst_f1 <= reg_wp.burst_f1;
286 burst_f1 <= reg_wp.burst_f1;
283 burst_f2 <= reg_wp.burst_f2;
287 burst_f2 <= reg_wp.burst_f2;
284
288
285 run <= reg_wp.run;
289 run <= reg_wp.run;
286
290
287 addr_data_f0 <= reg_wp.addr_data_f0;
291 addr_data_f0 <= reg_wp.addr_data_f0;
288 addr_data_f1 <= reg_wp.addr_data_f1;
292 addr_data_f1 <= reg_wp.addr_data_f1;
289 addr_data_f2 <= reg_wp.addr_data_f2;
293 addr_data_f2 <= reg_wp.addr_data_f2;
290 addr_data_f3 <= reg_wp.addr_data_f3;
294 addr_data_f3 <= reg_wp.addr_data_f3;
291
295
292 start_date <= reg_wp.start_date;
296 start_date <= reg_wp.start_date;
293
297
294 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
298 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
295 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
299 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
296 BEGIN -- PROCESS lpp_dma_top
300 BEGIN -- PROCESS lpp_dma_top
297 IF HRESETn = '0' THEN -- asynchronous reset (active low)
301 IF HRESETn = '0' THEN -- asynchronous reset (active low)
298 reg_sp.config_active_interruption_onNewMatrix <= '0';
302 reg_sp.config_active_interruption_onNewMatrix <= '0';
299 reg_sp.config_active_interruption_onError <= '0';
303 reg_sp.config_active_interruption_onError <= '0';
300 reg_sp.config_ms_run <= '1';
304 reg_sp.config_ms_run <= '1';
301 reg_sp.status_ready_matrix_f0_0 <= '0';
305 reg_sp.status_ready_matrix_f0_0 <= '0';
302 reg_sp.status_ready_matrix_f1_0 <= '0';
306 reg_sp.status_ready_matrix_f1_0 <= '0';
303 reg_sp.status_ready_matrix_f2_0 <= '0';
307 reg_sp.status_ready_matrix_f2_0 <= '0';
304 reg_sp.status_ready_matrix_f0_1 <= '0';
308 reg_sp.status_ready_matrix_f0_1 <= '0';
305 reg_sp.status_ready_matrix_f1_1 <= '0';
309 reg_sp.status_ready_matrix_f1_1 <= '0';
306 reg_sp.status_ready_matrix_f2_1 <= '0';
310 reg_sp.status_ready_matrix_f2_1 <= '0';
307 reg_sp.status_error_bad_component_error <= '0';
311 reg_sp.status_error_bad_component_error <= '0';
308 reg_sp.status_error_buffer_full <= '0';
312 reg_sp.status_error_buffer_full <= '0';
309 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
313 reg_sp.status_error_input_fifo_write <= (OTHERS => '0');
310
314
311 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
315 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
312 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
316 reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
313 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
317 reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
314
318
315 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
319 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
316 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
320 reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
317 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
321 reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
318
322
319 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
323 -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok
320 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
324 -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok
321 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok
322
326
323 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
327 -- reg_sp.time_matrix_f0_1 <= (OTHERS => '0'); -- ok
324 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
328 --reg_sp.time_matrix_f1_1 <= (OTHERS => '0'); -- ok
325 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
329 -- reg_sp.time_matrix_f2_1 <= (OTHERS => '0'); -- ok
326
330
327 prdata <= (OTHERS => '0');
331 prdata <= (OTHERS => '0');
328
332
329 apbo.pirq <= (OTHERS => '0');
333
334 apbo_irq_ms <= '0';
335 apbo_irq_wfp <= '0';
336
330
337
331 status_full_ack <= (OTHERS => '0');
338 status_full_ack <= (OTHERS => '0');
332
339
333 reg_wp.data_shaping_BW <= '0';
340 reg_wp.data_shaping_BW <= '0';
334 reg_wp.data_shaping_SP0 <= '0';
341 reg_wp.data_shaping_SP0 <= '0';
335 reg_wp.data_shaping_SP1 <= '0';
342 reg_wp.data_shaping_SP1 <= '0';
336 reg_wp.data_shaping_R0 <= '0';
343 reg_wp.data_shaping_R0 <= '0';
337 reg_wp.data_shaping_R1 <= '0';
344 reg_wp.data_shaping_R1 <= '0';
338 reg_wp.enable_f0 <= '0';
345 reg_wp.enable_f0 <= '0';
339 reg_wp.enable_f1 <= '0';
346 reg_wp.enable_f1 <= '0';
340 reg_wp.enable_f2 <= '0';
347 reg_wp.enable_f2 <= '0';
341 reg_wp.enable_f3 <= '0';
348 reg_wp.enable_f3 <= '0';
342 reg_wp.burst_f0 <= '0';
349 reg_wp.burst_f0 <= '0';
343 reg_wp.burst_f1 <= '0';
350 reg_wp.burst_f1 <= '0';
344 reg_wp.burst_f2 <= '0';
351 reg_wp.burst_f2 <= '0';
345 reg_wp.run <= '0';
352 reg_wp.run <= '0';
346 reg_wp.addr_data_f0 <= (OTHERS => '0');
353 reg_wp.addr_data_f0 <= (OTHERS => '0');
347 reg_wp.addr_data_f1 <= (OTHERS => '0');
354 reg_wp.addr_data_f1 <= (OTHERS => '0');
348 reg_wp.addr_data_f2 <= (OTHERS => '0');
355 reg_wp.addr_data_f2 <= (OTHERS => '0');
349 reg_wp.addr_data_f3 <= (OTHERS => '0');
356 reg_wp.addr_data_f3 <= (OTHERS => '0');
350 reg_wp.status_full <= (OTHERS => '0');
357 reg_wp.status_full <= (OTHERS => '0');
351 reg_wp.status_full_err <= (OTHERS => '0');
358 reg_wp.status_full_err <= (OTHERS => '0');
352 reg_wp.status_new_err <= (OTHERS => '0');
359 reg_wp.status_new_err <= (OTHERS => '0');
353 reg_wp.delta_snapshot <= (OTHERS => '0');
360 reg_wp.delta_snapshot <= (OTHERS => '0');
354 reg_wp.delta_f0 <= (OTHERS => '0');
361 reg_wp.delta_f0 <= (OTHERS => '0');
355 reg_wp.delta_f0_2 <= (OTHERS => '0');
362 reg_wp.delta_f0_2 <= (OTHERS => '0');
356 reg_wp.delta_f1 <= (OTHERS => '0');
363 reg_wp.delta_f1 <= (OTHERS => '0');
357 reg_wp.delta_f2 <= (OTHERS => '0');
364 reg_wp.delta_f2 <= (OTHERS => '0');
358 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
365 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
359 reg_wp.nb_snapshot_param <= (OTHERS => '0');
366 reg_wp.nb_snapshot_param <= (OTHERS => '0');
360 reg_wp.start_date <= (OTHERS => '0');
367 reg_wp.start_date <= (OTHERS => '0');
361
368
362 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
369 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
363
370
364 status_full_ack <= (OTHERS => '0');
371 status_full_ack <= (OTHERS => '0');
365
372
366 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
373 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
367 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
374 reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
368 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
375 reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
369
376
370 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
377 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
371 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
378 reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
372 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
379 reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
373
380
374 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
381 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
375
382
376 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
383 reg_sp.status_error_buffer_full <= reg_sp.status_error_buffer_full OR error_buffer_full;
377 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
384 reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
378 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
385 reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
379 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
386 reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
380
387
381
388
382
389
383 all_status : FOR I IN 3 DOWNTO 0 LOOP
390 all_status : FOR I IN 3 DOWNTO 0 LOOP
384 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
391 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
385 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
392 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
386 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
393 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run;
387 END LOOP all_status;
394 END LOOP all_status;
388
395
389 paddr := "000000";
396 paddr := "000000";
390 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
397 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
391 prdata <= (OTHERS => '0');
398 prdata <= (OTHERS => '0');
392 IF apbi.psel(pindex) = '1' THEN
399 IF apbi.psel(pindex) = '1' THEN
393 -- APB DMA READ --
400 -- APB DMA READ --
394 CASE paddr(7 DOWNTO 2) IS
401 CASE paddr(7 DOWNTO 2) IS
395 --0
402 --0
396 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
403 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
397 prdata(1) <= reg_sp.config_active_interruption_onError;
404 prdata(1) <= reg_sp.config_active_interruption_onError;
398 prdata(2) <= reg_sp.config_ms_run;
405 prdata(2) <= reg_sp.config_ms_run;
399 --1
406 --1
400 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
407 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
401 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
408 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
402 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
409 prdata(2) <= reg_sp.status_ready_matrix_f1_0;
403 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
410 prdata(3) <= reg_sp.status_ready_matrix_f1_1;
404 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
411 prdata(4) <= reg_sp.status_ready_matrix_f2_0;
405 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
412 prdata(5) <= reg_sp.status_ready_matrix_f2_1;
406 prdata(6) <= reg_sp.status_error_bad_component_error;
413 prdata(6) <= reg_sp.status_error_bad_component_error;
407 prdata(7) <= reg_sp.status_error_buffer_full;
414 prdata(7) <= reg_sp.status_error_buffer_full;
408 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
415 prdata(8) <= reg_sp.status_error_input_fifo_write(0);
409 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
416 prdata(9) <= reg_sp.status_error_input_fifo_write(1);
410 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
417 prdata(10) <= reg_sp.status_error_input_fifo_write(2);
411 --2
418 --2
412 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
419 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
413 --3
420 --3
414 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
421 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
415 --4
422 --4
416 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
423 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1_0;
417 --5
424 --5
418 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
425 WHEN "000101" => prdata <= reg_sp.addr_matrix_f1_1;
419 --6
426 --6
420 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
427 WHEN "000110" => prdata <= reg_sp.addr_matrix_f2_0;
421 --7
428 --7
422 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
429 WHEN "000111" => prdata <= reg_sp.addr_matrix_f2_1;
423 --8
430 --8
424 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
431 WHEN "001000" => prdata <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
425 --9
432 --9
426 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
433 WHEN "001001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
427 --10
434 --10
428 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
435 WHEN "001010" => prdata <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
429 --11
436 --11
430 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
437 WHEN "001011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
431 --12
438 --12
432 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
439 WHEN "001100" => prdata <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
433 --13
440 --13
434 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
441 WHEN "001101" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
435 --14
442 --14
436 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
443 WHEN "001110" => prdata <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
437 --15
444 --15
438 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
445 WHEN "001111" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
439 --16
446 --16
440 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
447 WHEN "010000" => prdata <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
441 --17
448 --17
442 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
449 WHEN "010001" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
443 --18
450 --18
444 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
451 WHEN "010010" => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
445 --19
452 --19
446 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
453 WHEN "010011" => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
447 ---------------------------------------------------------------------
454 ---------------------------------------------------------------------
448 --20
455 --20
449 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
456 WHEN "010100" => prdata(0) <= reg_wp.data_shaping_BW;
450 prdata(1) <= reg_wp.data_shaping_SP0;
457 prdata(1) <= reg_wp.data_shaping_SP0;
451 prdata(2) <= reg_wp.data_shaping_SP1;
458 prdata(2) <= reg_wp.data_shaping_SP1;
452 prdata(3) <= reg_wp.data_shaping_R0;
459 prdata(3) <= reg_wp.data_shaping_R0;
453 prdata(4) <= reg_wp.data_shaping_R1;
460 prdata(4) <= reg_wp.data_shaping_R1;
454 --21
461 --21
455 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
462 WHEN "010101" => prdata(0) <= reg_wp.enable_f0;
456 prdata(1) <= reg_wp.enable_f1;
463 prdata(1) <= reg_wp.enable_f1;
457 prdata(2) <= reg_wp.enable_f2;
464 prdata(2) <= reg_wp.enable_f2;
458 prdata(3) <= reg_wp.enable_f3;
465 prdata(3) <= reg_wp.enable_f3;
459 prdata(4) <= reg_wp.burst_f0;
466 prdata(4) <= reg_wp.burst_f0;
460 prdata(5) <= reg_wp.burst_f1;
467 prdata(5) <= reg_wp.burst_f1;
461 prdata(6) <= reg_wp.burst_f2;
468 prdata(6) <= reg_wp.burst_f2;
462 prdata(7) <= reg_wp.run;
469 prdata(7) <= reg_wp.run;
463 --22
470 --22
464 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
471 WHEN "010110" => prdata <= reg_wp.addr_data_f0;
465 --23
472 --23
466 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
473 WHEN "010111" => prdata <= reg_wp.addr_data_f1;
467 --24
474 --24
468 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
475 WHEN "011000" => prdata <= reg_wp.addr_data_f2;
469 --25
476 --25
470 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
477 WHEN "011001" => prdata <= reg_wp.addr_data_f3;
471 --26
478 --26
472 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
479 WHEN "011010" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
473 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
480 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
474 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
481 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
475 --27
482 --27
476 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
483 WHEN "011011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
477 --28
484 --28
478 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
485 WHEN "011100" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
479 --29
486 --29
480 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
487 WHEN "011101" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
481 --30
488 --30
482 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
489 WHEN "011110" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
483 --31
490 --31
484 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
491 WHEN "011111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
485 --32
492 --32
486 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
493 WHEN "100000" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
487 --33
494 --33
488 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
495 WHEN "100001" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
489 --34
496 --34
490 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
497 WHEN "100010" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
491 --35
498 --35
492 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
499 WHEN "100011" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
493 ----------------------------------------------------
500 ----------------------------------------------------
494 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
501 WHEN "111100" => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0);
495 WHEN OTHERS => NULL;
502 WHEN OTHERS => NULL;
496
503
497 END CASE;
504 END CASE;
498 IF (apbi.pwrite AND apbi.penable) = '1' THEN
505 IF (apbi.pwrite AND apbi.penable) = '1' THEN
499 -- APB DMA WRITE --
506 -- APB DMA WRITE --
500 CASE paddr(7 DOWNTO 2) IS
507 CASE paddr(7 DOWNTO 2) IS
501 --
508 --
502 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
509 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
503 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
510 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
504 reg_sp.config_ms_run <= apbi.pwdata(2);
511 reg_sp.config_ms_run <= apbi.pwdata(2);
505 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
512
506 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
513 WHEN "000001" =>
507 reg_sp.status_ready_matrix_f1_0 <= apbi.pwdata(2);
514 reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0 ) OR reg0_ready_matrix_f0;
508 reg_sp.status_ready_matrix_f1_1 <= apbi.pwdata(3);
515 reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1 ) OR reg1_ready_matrix_f0;
509 reg_sp.status_ready_matrix_f2_0 <= apbi.pwdata(4);
516 reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0 ) OR reg0_ready_matrix_f1;
510 reg_sp.status_ready_matrix_f2_1 <= apbi.pwdata(5);
517 reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1 ) OR reg1_ready_matrix_f1;
511 reg_sp.status_error_bad_component_error <= apbi.pwdata(6);
518 reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0 ) OR reg0_ready_matrix_f2;
512 reg_sp.status_error_buffer_full <= apbi.pwdata(7);
519 reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1 ) OR reg1_ready_matrix_f2;
513 reg_sp.status_error_input_fifo_write(0) <= apbi.pwdata(8);
520 reg_sp.status_error_bad_component_error <= ((NOT apbi.pwdata(6) ) AND reg_sp.status_error_bad_component_error) OR error_bad_component_error;
514 reg_sp.status_error_input_fifo_write(1) <= apbi.pwdata(9);
521 reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full ) OR error_buffer_full;
515 reg_sp.status_error_input_fifo_write(2) <= apbi.pwdata(10);
522 reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
516 --2
523 reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
517 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
524 reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
518 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
525 --2
519 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
526 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
520 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
527 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
521 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
528 WHEN "000100" => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
522 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
529 WHEN "000101" => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
530 WHEN "000110" => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
531 WHEN "000111" => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
523 --8 to 19
532 --8 to 19
524 --20
533 --20
525 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
534 WHEN "010100" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
526 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
535 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
527 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
536 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
528 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
537 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
529 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
538 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
530 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
539 WHEN "010101" => reg_wp.enable_f0 <= apbi.pwdata(0);
531 reg_wp.enable_f1 <= apbi.pwdata(1);
540 reg_wp.enable_f1 <= apbi.pwdata(1);
532 reg_wp.enable_f2 <= apbi.pwdata(2);
541 reg_wp.enable_f2 <= apbi.pwdata(2);
533 reg_wp.enable_f3 <= apbi.pwdata(3);
542 reg_wp.enable_f3 <= apbi.pwdata(3);
534 reg_wp.burst_f0 <= apbi.pwdata(4);
543 reg_wp.burst_f0 <= apbi.pwdata(4);
535 reg_wp.burst_f1 <= apbi.pwdata(5);
544 reg_wp.burst_f1 <= apbi.pwdata(5);
536 reg_wp.burst_f2 <= apbi.pwdata(6);
545 reg_wp.burst_f2 <= apbi.pwdata(6);
537 reg_wp.run <= apbi.pwdata(7);
546 reg_wp.run <= apbi.pwdata(7);
538 --22
547 --22
539 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
548 WHEN "010110" => reg_wp.addr_data_f0 <= apbi.pwdata;
540 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
549 WHEN "010111" => reg_wp.addr_data_f1 <= apbi.pwdata;
541 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
550 WHEN "011000" => reg_wp.addr_data_f2 <= apbi.pwdata;
542 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
551 WHEN "011001" => reg_wp.addr_data_f3 <= apbi.pwdata;
543 --26
552 --26
544 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
553 WHEN "011010" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
545 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
554 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
546 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
555 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
547 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
556 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
548 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
557 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
549 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
558 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
550 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
559 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
551 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
560 WHEN "011011" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
552 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
561 WHEN "011100" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
553 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
562 WHEN "011101" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
554 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
563 WHEN "011110" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
555 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
564 WHEN "011111" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
556 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
565 WHEN "100000" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
557 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
566 WHEN "100001" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
558 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
567 WHEN "100010" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
559 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
568 WHEN "100011" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
560 --
569 --
561 WHEN OTHERS => NULL;
570 WHEN OTHERS => NULL;
562 END CASE;
571 END CASE;
563 END IF;
572 END IF;
564 END IF;
573 END IF;
565
574 --apbo.pirq(pirq_ms) <=
566 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
575 apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
567 ready_matrix_f1 OR
576 ready_matrix_f1 OR
568 ready_matrix_f2)
577 ready_matrix_f2)
569 )
578 )
570 OR
579 OR
571 (reg_sp.config_active_interruption_onError AND (
580 (reg_sp.config_active_interruption_onError AND (
572 error_bad_component_error
581 error_bad_component_error
573 OR error_buffer_full
582 OR error_buffer_full
574 OR error_input_fifo_write(0)
583 OR error_input_fifo_write(0)
575 OR error_input_fifo_write(1)
584 OR error_input_fifo_write(1)
576 OR error_input_fifo_write(2))
585 OR error_input_fifo_write(2))
577 ));
586 ));
578
587 -- apbo.pirq(pirq_wfp)
579 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
588 apbo_irq_wfp<= ored_irq_wfp;
580
589
581 END IF;
590 END IF;
582 END PROCESS lpp_lfr_apbreg;
591 END PROCESS lpp_lfr_apbreg;
583
592
593 apbo.pirq(pirq_ms) <= apbo_irq_ms;
594 apbo.pirq(pirq_wfp) <= apbo_irq_wfp;
595
584 apbo.pindex <= pindex;
596 apbo.pindex <= pindex;
585 apbo.pconfig <= pconfig;
597 apbo.pconfig <= pconfig;
586 apbo.prdata <= prdata;
598 apbo.prdata <= prdata;
587
599
588 -----------------------------------------------------------------------------
600 -----------------------------------------------------------------------------
589 -- IRQ
601 -- IRQ
590 -----------------------------------------------------------------------------
602 -----------------------------------------------------------------------------
591 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
603 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
592
604
593 PROCESS (HCLK, HRESETn)
605 PROCESS (HCLK, HRESETn)
594 BEGIN -- PROCESS
606 BEGIN -- PROCESS
595 IF HRESETn = '0' THEN -- asynchronous reset (active low)
607 IF HRESETn = '0' THEN -- asynchronous reset (active low)
596 irq_wfp_reg <= (OTHERS => '0');
608 irq_wfp_reg <= (OTHERS => '0');
597 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
609 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
598 irq_wfp_reg <= irq_wfp_reg_s;
610 irq_wfp_reg <= irq_wfp_reg_s;
599 END IF;
611 END IF;
600 END PROCESS;
612 END PROCESS;
601
613
602 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
614 all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
603 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
615 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
604 END GENERATE all_irq_wfp;
616 END GENERATE all_irq_wfp;
605
617
606 irq_wfp_ZERO <= (OTHERS => '0');
618 irq_wfp_ZERO <= (OTHERS => '0');
607 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
619 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
608
620
609 run_ms <= reg_sp.config_ms_run;
621 run_ms <= reg_sp.config_ms_run;
610
622
611 -----------------------------------------------------------------------------
623 -----------------------------------------------------------------------------
612 --
624 --
613 -----------------------------------------------------------------------------
625 -----------------------------------------------------------------------------
614 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
626 lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
615 PORT MAP (
627 PORT MAP (
616 clk => HCLK,
628 clk => HCLK,
617 rstn => HRESETn,
629 rstn => HRESETn,
618
630
619 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
631 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
620 reg0_ready_matrix => reg0_ready_matrix_f0,
632 reg0_ready_matrix => reg0_ready_matrix_f0,
621 reg0_addr_matrix => reg_sp.addr_matrix_f0_0,--reg0_addr_matrix_f0,
633 reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0,
622 reg0_matrix_time => reg_sp.time_matrix_f0_0,--reg0_matrix_time_f0,
634 reg0_matrix_time => reg_sp.time_matrix_f0_0, --reg0_matrix_time_f0,
623
635
624 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
636 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
625 reg1_ready_matrix => reg1_ready_matrix_f0,
637 reg1_ready_matrix => reg1_ready_matrix_f0,
626 reg1_addr_matrix => reg_sp.addr_matrix_f0_1,--reg1_addr_matrix_f0,
638 reg1_addr_matrix => reg_sp.addr_matrix_f0_1, --reg1_addr_matrix_f0,
627 reg1_matrix_time => reg_sp.time_matrix_f0_1,--reg1_matrix_time_f0,
639 reg1_matrix_time => reg_sp.time_matrix_f0_1, --reg1_matrix_time_f0,
628
640
629 ready_matrix => ready_matrix_f0,
641 ready_matrix => ready_matrix_f0,
630 status_ready_matrix => status_ready_matrix_f0,
642 status_ready_matrix => status_ready_matrix_f0,
631 addr_matrix => addr_matrix_f0,
643 addr_matrix => addr_matrix_f0,
632 matrix_time => matrix_time_f0);
644 matrix_time => matrix_time_f0);
633
645
634 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
646 lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
635 PORT MAP (
647 PORT MAP (
636 clk => HCLK,
648 clk => HCLK,
637 rstn => HRESETn,
649 rstn => HRESETn,
638
650
639 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
651 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
640 reg0_ready_matrix => reg0_ready_matrix_f1,
652 reg0_ready_matrix => reg0_ready_matrix_f1,
641 reg0_addr_matrix => reg_sp.addr_matrix_f1_0,--reg0_addr_matrix_f1,
653 reg0_addr_matrix => reg_sp.addr_matrix_f1_0, --reg0_addr_matrix_f1,
642 reg0_matrix_time => reg_sp.time_matrix_f1_0,--reg0_matrix_time_f1,
654 reg0_matrix_time => reg_sp.time_matrix_f1_0, --reg0_matrix_time_f1,
643
655
644 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
656 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
645 reg1_ready_matrix => reg1_ready_matrix_f1,
657 reg1_ready_matrix => reg1_ready_matrix_f1,
646 reg1_addr_matrix => reg_sp.addr_matrix_f1_1,--reg1_addr_matrix_f1,
658 reg1_addr_matrix => reg_sp.addr_matrix_f1_1, --reg1_addr_matrix_f1,
647 reg1_matrix_time => reg_sp.time_matrix_f1_1,--reg1_matrix_time_f1,
659 reg1_matrix_time => reg_sp.time_matrix_f1_1, --reg1_matrix_time_f1,
648
660
649 ready_matrix => ready_matrix_f1,
661 ready_matrix => ready_matrix_f1,
650 status_ready_matrix => status_ready_matrix_f1,
662 status_ready_matrix => status_ready_matrix_f1,
651 addr_matrix => addr_matrix_f1,
663 addr_matrix => addr_matrix_f1,
652 matrix_time => matrix_time_f1);
664 matrix_time => matrix_time_f1);
653
665
654 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
666 lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
655 PORT MAP (
667 PORT MAP (
656 clk => HCLK,
668 clk => HCLK,
657 rstn => HRESETn,
669 rstn => HRESETn,
658
670
659 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
671 reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
660 reg0_ready_matrix => reg0_ready_matrix_f2,
672 reg0_ready_matrix => reg0_ready_matrix_f2,
661 reg0_addr_matrix => reg_sp.addr_matrix_f2_0,--reg0_addr_matrix_f2,
673 reg0_addr_matrix => reg_sp.addr_matrix_f2_0, --reg0_addr_matrix_f2,
662 reg0_matrix_time => reg_sp.time_matrix_f2_0,--reg0_matrix_time_f2,
674 reg0_matrix_time => reg_sp.time_matrix_f2_0, --reg0_matrix_time_f2,
663
675
664 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
676 reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
665 reg1_ready_matrix => reg1_ready_matrix_f2,
677 reg1_ready_matrix => reg1_ready_matrix_f2,
666 reg1_addr_matrix => reg_sp.addr_matrix_f2_1,--reg1_addr_matrix_f2,
678 reg1_addr_matrix => reg_sp.addr_matrix_f2_1, --reg1_addr_matrix_f2,
667 reg1_matrix_time => reg_sp.time_matrix_f2_1,--reg1_matrix_time_f2,
679 reg1_matrix_time => reg_sp.time_matrix_f2_1, --reg1_matrix_time_f2,
680
681 ready_matrix => ready_matrix_f2,
682 status_ready_matrix => status_ready_matrix_f2,
683 addr_matrix => addr_matrix_f2,
684 matrix_time => matrix_time_f2);
668
685
669 ready_matrix => ready_matrix_f2,
686 -----------------------------------------------------------------------------
670 status_ready_matrix => status_ready_matrix_f2,
687 debug_signal(31 DOWNTO 12) <= (OTHERS => '0');
671 addr_matrix => addr_matrix_f2,
688 debug_signal(11 DOWNTO 0) <= apbo_irq_ms & --11
672 matrix_time => matrix_time_f2);
689 reg_sp.status_error_input_fifo_write(2) &--10
673
690 reg_sp.status_error_input_fifo_write(1) &--9
674
691 reg_sp.status_error_input_fifo_write(0) &--8
692 reg_sp.status_error_buffer_full & reg_sp.status_error_bad_component_error & --7 6
693 reg_sp.status_ready_matrix_f2_1 & reg_sp.status_ready_matrix_f2_0 &--5 4
694 reg_sp.status_ready_matrix_f1_1 & reg_sp.status_ready_matrix_f1_0 &--3 2
695 reg_sp.status_ready_matrix_f0_1 & reg_sp.status_ready_matrix_f0_0; --1 0
696
675 END beh;
697 END beh;
Show file before | Show file after | Hide comments
@@ -1,929 +1,942
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.spectral_matrix_package.ALL;
8 USE lpp.spectral_matrix_package.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
9 USE lpp.lpp_dma_pkg.ALL;
10 USE lpp.lpp_Header.ALL;
10 USE lpp.lpp_Header.ALL;
11 USE lpp.lpp_matrix.ALL;
11 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
12 USE lpp.lpp_matrix.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.lpp_fft.ALL;
14 USE lpp.lpp_fft.ALL;
15 USE lpp.fft_components.ALL;
15 USE lpp.fft_components.ALL;
16
16
17 ENTITY lpp_lfr_ms IS
17 ENTITY lpp_lfr_ms IS
18 GENERIC (
18 GENERIC (
19 Mem_use : INTEGER := use_RAM
19 Mem_use : INTEGER := use_RAM
20 );
20 );
21 PORT (
21 PORT (
22 clk : IN STD_LOGIC;
22 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
24
24
25 ---------------------------------------------------------------------------
25 ---------------------------------------------------------------------------
26 -- DATA INPUT
26 -- DATA INPUT
27 ---------------------------------------------------------------------------
27 ---------------------------------------------------------------------------
28 -- TIME
28 -- TIME
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
29 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
30 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
31 --
31 --
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
32 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
33 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 --
34 --
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
35 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
36 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 --
37 --
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
38 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
39 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- DMA
42 -- DMA
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
45 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
46 dma_valid : OUT STD_LOGIC;
46 dma_valid : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
47 dma_valid_burst : OUT STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
48 dma_ren : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
49 dma_done : IN STD_LOGIC;
50
50
51 -- Reg out
51 -- Reg out
52 ready_matrix_f0 : OUT STD_LOGIC;
52 ready_matrix_f0 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
53 ready_matrix_f1 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
54 ready_matrix_f2 : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
55 error_bad_component_error : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
56 error_buffer_full : OUT STD_LOGIC;
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
57 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
58
58
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 --
61 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
62 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
60
63
61 -- Reg In
64 -- Reg In
62 status_ready_matrix_f0 : IN STD_LOGIC;
65 status_ready_matrix_f0 : IN STD_LOGIC;
63 status_ready_matrix_f1 : IN STD_LOGIC;
66 status_ready_matrix_f1 : IN STD_LOGIC;
64 status_ready_matrix_f2 : IN STD_LOGIC;
67 status_ready_matrix_f2 : IN STD_LOGIC;
65
68
66 config_active_interruption_onNewMatrix : IN STD_LOGIC;
69 config_active_interruption_onNewMatrix : IN STD_LOGIC;
67 config_active_interruption_onError : IN STD_LOGIC;
70 config_active_interruption_onError : IN STD_LOGIC;
68 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
73 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
71
74
72 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
75 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
73 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
76 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
74 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
77 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
75
78
76 );
79 );
77 END;
80 END;
78
81
79 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
82 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
80
83
81 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
84 SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
83 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f0_A_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
84 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f0_A_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86
89
87 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
90 SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
89 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
92 SIGNAL sample_f0_B_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
90 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
93 SIGNAL sample_f0_B_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
91 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
92
95
93 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
96 SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
94 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
97 SIGNAL sample_f1_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
98 SIGNAL sample_f1_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
96 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
99 SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
97
100
98 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
99
102
100 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
103 SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
104 SIGNAL sample_f2_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
105 SIGNAL sample_f2_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
104
107
105 SIGNAL error_wen_f0 : STD_LOGIC;
108 SIGNAL error_wen_f0 : STD_LOGIC;
106 SIGNAL error_wen_f1 : STD_LOGIC;
109 SIGNAL error_wen_f1 : STD_LOGIC;
107 SIGNAL error_wen_f2 : STD_LOGIC;
110 SIGNAL error_wen_f2 : STD_LOGIC;
108
111
109 SIGNAL one_sample_f1_full : STD_LOGIC;
112 SIGNAL one_sample_f1_full : STD_LOGIC;
110 SIGNAL one_sample_f1_wen : STD_LOGIC;
113 SIGNAL one_sample_f1_wen : STD_LOGIC;
111 SIGNAL one_sample_f2_full : STD_LOGIC;
114 SIGNAL one_sample_f2_full : STD_LOGIC;
112 SIGNAL one_sample_f2_wen : STD_LOGIC;
115 SIGNAL one_sample_f2_wen : STD_LOGIC;
113
116
114 -----------------------------------------------------------------------------
117 -----------------------------------------------------------------------------
115 -- FSM / SWITCH SELECT CHANNEL
118 -- FSM / SWITCH SELECT CHANNEL
116 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
117 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
120 TYPE fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
118 SIGNAL state_fsm_select_channel : fsm_select_channel;
121 SIGNAL state_fsm_select_channel : fsm_select_channel;
119 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
122 SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
120
123
121 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
124 SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
122 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
125 SIGNAL sample_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
123 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
126 SIGNAL sample_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
124 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
127 SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
125
128
126 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
127 -- FSM LOAD FFT
130 -- FSM LOAD FFT
128 -----------------------------------------------------------------------------
131 -----------------------------------------------------------------------------
129 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
132 TYPE fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
130 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
133 SIGNAL state_fsm_load_FFT : fsm_load_FFT;
131 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
134 SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
132
135
133 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
136 SIGNAL sample_ren_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
134 SIGNAL sample_load : STD_LOGIC;
137 SIGNAL sample_load : STD_LOGIC;
135 SIGNAL sample_valid : STD_LOGIC;
138 SIGNAL sample_valid : STD_LOGIC;
136 SIGNAL sample_valid_r : STD_LOGIC;
139 SIGNAL sample_valid_r : STD_LOGIC;
137 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
140 SIGNAL sample_data : STD_LOGIC_VECTOR(15 DOWNTO 0);
138
141
139
142
140 -----------------------------------------------------------------------------
143 -----------------------------------------------------------------------------
141 -- FFT
144 -- FFT
142 -----------------------------------------------------------------------------
145 -----------------------------------------------------------------------------
143 SIGNAL fft_read : STD_LOGIC;
146 SIGNAL fft_read : STD_LOGIC;
144 SIGNAL fft_pong : STD_LOGIC;
147 SIGNAL fft_pong : STD_LOGIC;
145 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
148 SIGNAL fft_data_im : STD_LOGIC_VECTOR(15 DOWNTO 0);
146 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
149 SIGNAL fft_data_re : STD_LOGIC_VECTOR(15 DOWNTO 0);
147 SIGNAL fft_data_valid : STD_LOGIC;
150 SIGNAL fft_data_valid : STD_LOGIC;
148 SIGNAL fft_ready : STD_LOGIC;
151 SIGNAL fft_ready : STD_LOGIC;
149 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
150 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
153 -- SIGNAL fft_linker_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
151 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
152 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
155 TYPE fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
153 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
156 SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
154 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
157 SIGNAL current_fifo_load : STD_LOGIC_VECTOR(4 DOWNTO 0);
155 SIGNAL current_fifo_empty : STD_LOGIC;
158 SIGNAL current_fifo_empty : STD_LOGIC;
156 SIGNAL current_fifo_locked : STD_LOGIC;
159 SIGNAL current_fifo_locked : STD_LOGIC;
157 SIGNAL current_fifo_full : STD_LOGIC;
160 SIGNAL current_fifo_full : STD_LOGIC;
158 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
161 SIGNAL MEM_IN_SM_locked : STD_LOGIC_VECTOR(4 DOWNTO 0);
159
162
160 -----------------------------------------------------------------------------
163 -----------------------------------------------------------------------------
161 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
162 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
163 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
166 SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
164 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
167 SIGNAL MEM_IN_SM_ren : STD_LOGIC_VECTOR(4 DOWNTO 0);
165 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
168 SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
166 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
169 SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
167 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
170 SIGNAL MEM_IN_SM_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
168 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
171 SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
169 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
170 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
173 SIGNAL SM_in_data : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
171 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
174 SIGNAL SM_in_ren : STD_LOGIC_VECTOR(1 DOWNTO 0);
172 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
175 SIGNAL SM_in_empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
173
176
174 SIGNAL SM_correlation_start : STD_LOGIC;
177 SIGNAL SM_correlation_start : STD_LOGIC;
175 SIGNAL SM_correlation_auto : STD_LOGIC;
178 SIGNAL SM_correlation_auto : STD_LOGIC;
176 SIGNAL SM_correlation_done : STD_LOGIC;
179 SIGNAL SM_correlation_done : STD_LOGIC;
177 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
180 SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
178 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
181 SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
179 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
182 SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
180 SIGNAL SM_correlation_begin : STD_LOGIC;
183 SIGNAL SM_correlation_begin : STD_LOGIC;
181
184
182 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
185 SIGNAL MEM_OUT_SM_Full_s : STD_LOGIC;
183 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
186 SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
187 SIGNAL MEM_OUT_SM_Write_s : STD_LOGIC;
185
188
186 SIGNAL current_matrix_write : STD_LOGIC;
189 SIGNAL current_matrix_write : STD_LOGIC;
187 SIGNAL current_matrix_wait_empty : STD_LOGIC;
190 SIGNAL current_matrix_wait_empty : STD_LOGIC;
188 -----------------------------------------------------------------------------
191 -----------------------------------------------------------------------------
189 SIGNAL fifo_0_ready : STD_LOGIC;
192 SIGNAL fifo_0_ready : STD_LOGIC;
190 SIGNAL fifo_1_ready : STD_LOGIC;
193 SIGNAL fifo_1_ready : STD_LOGIC;
191 SIGNAL fifo_ongoing : STD_LOGIC;
194 SIGNAL fifo_ongoing : STD_LOGIC;
192
195
193 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
196 SIGNAL FSM_DMA_fifo_ren : STD_LOGIC;
194 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
197 SIGNAL FSM_DMA_fifo_empty : STD_LOGIC;
195 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
198 SIGNAL FSM_DMA_fifo_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
199 SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
197 -----------------------------------------------------------------------------
200 -----------------------------------------------------------------------------
198 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
199 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
200 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Data_in : STD_LOGIC_VECTOR(63 DOWNTO 0);
201 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
204 SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
202 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
205 SIGNAL MEM_OUT_SM_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
203 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
206 SIGNAL MEM_OUT_SM_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
204
207
205 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
206 -- TIME REG & INFOs
209 -- TIME REG & INFOs
207 -----------------------------------------------------------------------------
210 -----------------------------------------------------------------------------
208 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
211 SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
209
212
210 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL f_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
211 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
214 SIGNAL f_empty_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
212 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
215 SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
213 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
216 SIGNAL time_reg_f : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
214
217
215 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
216 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
219 SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
217 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
220 SIGNAL time_reg_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
218 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
221 SIGNAL time_reg_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
219
222
220 --SIGNAL time_update_f0_A : STD_LOGIC;
223 --SIGNAL time_update_f0_A : STD_LOGIC;
221 --SIGNAL time_update_f0_B : STD_LOGIC;
224 --SIGNAL time_update_f0_B : STD_LOGIC;
222 --SIGNAL time_update_f1 : STD_LOGIC;
225 --SIGNAL time_update_f1 : STD_LOGIC;
223 --SIGNAL time_update_f2 : STD_LOGIC;
226 --SIGNAL time_update_f2 : STD_LOGIC;
224 --
227 --
225 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
228 SIGNAL status_channel : STD_LOGIC_VECTOR(49 DOWNTO 0);
226 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
229 SIGNAL status_MS_input : STD_LOGIC_VECTOR(49 DOWNTO 0);
227 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
230 SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
228
231
229 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
232 SIGNAL status_component_fifo_0 : STD_LOGIC_VECTOR(53 DOWNTO 0);
230 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
233 SIGNAL status_component_fifo_1 : STD_LOGIC_VECTOR(53 DOWNTO 0);
231 SIGNAL status_component_fifo_0_end : STD_LOGIC;
234 SIGNAL status_component_fifo_0_end : STD_LOGIC;
232 SIGNAL status_component_fifo_1_end : STD_LOGIC;
235 SIGNAL status_component_fifo_1_end : STD_LOGIC;
233 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
234
237
235 BEGIN
238 BEGIN
236
239
237
240
238 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
241 error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
239
242
240
243
241 switch_f0_inst : spectral_matrix_switch_f0
244 switch_f0_inst : spectral_matrix_switch_f0
242 PORT MAP (
245 PORT MAP (
243 clk => clk,
246 clk => clk,
244 rstn => rstn,
247 rstn => rstn,
245
248
246 sample_wen => sample_f0_wen,
249 sample_wen => sample_f0_wen,
247
250
248 fifo_A_empty => sample_f0_A_empty,
251 fifo_A_empty => sample_f0_A_empty,
249 fifo_A_full => sample_f0_A_full,
252 fifo_A_full => sample_f0_A_full,
250 fifo_A_wen => sample_f0_A_wen,
253 fifo_A_wen => sample_f0_A_wen,
251
254
252 fifo_B_empty => sample_f0_B_empty,
255 fifo_B_empty => sample_f0_B_empty,
253 fifo_B_full => sample_f0_B_full,
256 fifo_B_full => sample_f0_B_full,
254 fifo_B_wen => sample_f0_B_wen,
257 fifo_B_wen => sample_f0_B_wen,
255
258
256 error_wen => error_wen_f0); -- TODO
259 error_wen => error_wen_f0); -- TODO
257
260
258 -----------------------------------------------------------------------------
261 -----------------------------------------------------------------------------
259 -- FIFO IN
262 -- FIFO IN
260 -----------------------------------------------------------------------------
263 -----------------------------------------------------------------------------
261 lppFIFOxN_f0_a : lppFIFOxN
264 lppFIFOxN_f0_a : lppFIFOxN
262 GENERIC MAP (
265 GENERIC MAP (
263 tech => 0,
266 tech => 0,
264 Mem_use => Mem_use,
267 Mem_use => Mem_use,
265 Data_sz => 16,
268 Data_sz => 16,
266 Addr_sz => 8,
269 Addr_sz => 8,
267 FifoCnt => 5)
270 FifoCnt => 5)
268 PORT MAP (
271 PORT MAP (
269 clk => clk,
272 clk => clk,
270 rstn => rstn,
273 rstn => rstn,
271
274
272 ReUse => (OTHERS => '0'),
275 ReUse => (OTHERS => '0'),
273
276
274 wen => sample_f0_A_wen,
277 wen => sample_f0_A_wen,
275 wdata => sample_f0_wdata,
278 wdata => sample_f0_wdata,
276
279
277 ren => sample_f0_A_ren,
280 ren => sample_f0_A_ren,
278 rdata => sample_f0_A_rdata,
281 rdata => sample_f0_A_rdata,
279
282
280 empty => sample_f0_A_empty,
283 empty => sample_f0_A_empty,
281 full => sample_f0_A_full,
284 full => sample_f0_A_full,
282 almost_full => OPEN);
285 almost_full => OPEN);
283
286
284 lppFIFOxN_f0_b : lppFIFOxN
287 lppFIFOxN_f0_b : lppFIFOxN
285 GENERIC MAP (
288 GENERIC MAP (
286 tech => 0,
289 tech => 0,
287 Mem_use => Mem_use,
290 Mem_use => Mem_use,
288 Data_sz => 16,
291 Data_sz => 16,
289 Addr_sz => 8,
292 Addr_sz => 8,
290 FifoCnt => 5)
293 FifoCnt => 5)
291 PORT MAP (
294 PORT MAP (
292 clk => clk,
295 clk => clk,
293 rstn => rstn,
296 rstn => rstn,
294
297
295 ReUse => (OTHERS => '0'),
298 ReUse => (OTHERS => '0'),
296
299
297 wen => sample_f0_B_wen,
300 wen => sample_f0_B_wen,
298 wdata => sample_f0_wdata,
301 wdata => sample_f0_wdata,
299 ren => sample_f0_B_ren,
302 ren => sample_f0_B_ren,
300 rdata => sample_f0_B_rdata,
303 rdata => sample_f0_B_rdata,
301 empty => sample_f0_B_empty,
304 empty => sample_f0_B_empty,
302 full => sample_f0_B_full,
305 full => sample_f0_B_full,
303 almost_full => OPEN);
306 almost_full => OPEN);
304
307
305 lppFIFOxN_f1 : lppFIFOxN
308 lppFIFOxN_f1 : lppFIFOxN
306 GENERIC MAP (
309 GENERIC MAP (
307 tech => 0,
310 tech => 0,
308 Mem_use => Mem_use,
311 Mem_use => Mem_use,
309 Data_sz => 16,
312 Data_sz => 16,
310 Addr_sz => 8,
313 Addr_sz => 8,
311 FifoCnt => 5)
314 FifoCnt => 5)
312 PORT MAP (
315 PORT MAP (
313 clk => clk,
316 clk => clk,
314 rstn => rstn,
317 rstn => rstn,
315
318
316 ReUse => (OTHERS => '0'),
319 ReUse => (OTHERS => '0'),
317
320
318 wen => sample_f1_wen,
321 wen => sample_f1_wen,
319 wdata => sample_f1_wdata,
322 wdata => sample_f1_wdata,
320 ren => sample_f1_ren,
323 ren => sample_f1_ren,
321 rdata => sample_f1_rdata,
324 rdata => sample_f1_rdata,
322 empty => sample_f1_empty,
325 empty => sample_f1_empty,
323 full => sample_f1_full,
326 full => sample_f1_full,
324 almost_full => sample_f1_almost_full);
327 almost_full => sample_f1_almost_full);
325
328
326
329
327 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
330 one_sample_f1_wen <= '0' WHEN sample_f1_wen = "11111" ELSE '1';
328
331
329 PROCESS (clk, rstn)
332 PROCESS (clk, rstn)
330 BEGIN -- PROCESS
333 BEGIN -- PROCESS
331 IF rstn = '0' THEN -- asynchronous reset (active low)
334 IF rstn = '0' THEN -- asynchronous reset (active low)
332 one_sample_f1_full <= '0';
335 one_sample_f1_full <= '0';
333 error_wen_f1 <= '0';
336 error_wen_f1 <= '0';
334 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
337 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
335 IF sample_f1_full = "00000" THEN
338 IF sample_f1_full = "00000" THEN
336 one_sample_f1_full <= '0';
339 one_sample_f1_full <= '0';
337 ELSE
340 ELSE
338 one_sample_f1_full <= '1';
341 one_sample_f1_full <= '1';
339 END IF;
342 END IF;
340 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
343 error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
341 END IF;
344 END IF;
342 END PROCESS;
345 END PROCESS;
343
346
344
347
345 lppFIFOxN_f2 : lppFIFOxN
348 lppFIFOxN_f2 : lppFIFOxN
346 GENERIC MAP (
349 GENERIC MAP (
347 tech => 0,
350 tech => 0,
348 Mem_use => Mem_use,
351 Mem_use => Mem_use,
349 Data_sz => 16,
352 Data_sz => 16,
350 Addr_sz => 8,
353 Addr_sz => 8,
351 FifoCnt => 5)
354 FifoCnt => 5)
352 PORT MAP (
355 PORT MAP (
353 clk => clk,
356 clk => clk,
354 rstn => rstn,
357 rstn => rstn,
355
358
356 ReUse => (OTHERS => '0'),
359 ReUse => (OTHERS => '0'),
357
360
358 wen => sample_f2_wen,
361 wen => sample_f2_wen,
359 wdata => sample_f2_wdata,
362 wdata => sample_f2_wdata,
360 ren => sample_f2_ren,
363 ren => sample_f2_ren,
361 rdata => sample_f2_rdata,
364 rdata => sample_f2_rdata,
362 empty => sample_f2_empty,
365 empty => sample_f2_empty,
363 full => sample_f2_full,
366 full => sample_f2_full,
364 almost_full => OPEN);
367 almost_full => OPEN);
365
368
366
369
367 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
370 one_sample_f2_wen <= '0' WHEN sample_f2_wen = "11111" ELSE '1';
368
371
369 PROCESS (clk, rstn)
372 PROCESS (clk, rstn)
370 BEGIN -- PROCESS
373 BEGIN -- PROCESS
371 IF rstn = '0' THEN -- asynchronous reset (active low)
374 IF rstn = '0' THEN -- asynchronous reset (active low)
372 one_sample_f2_full <= '0';
375 one_sample_f2_full <= '0';
373 error_wen_f2 <= '0';
376 error_wen_f2 <= '0';
374 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
377 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
375 IF sample_f2_full = "00000" THEN
378 IF sample_f2_full = "00000" THEN
376 one_sample_f2_full <= '0';
379 one_sample_f2_full <= '0';
377 ELSE
380 ELSE
378 one_sample_f2_full <= '1';
381 one_sample_f2_full <= '1';
379 END IF;
382 END IF;
380 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
383 error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
381 END IF;
384 END IF;
382 END PROCESS;
385 END PROCESS;
383
386
384 -----------------------------------------------------------------------------
387 -----------------------------------------------------------------------------
385 -- FSM SELECT CHANNEL
388 -- FSM SELECT CHANNEL
386 -----------------------------------------------------------------------------
389 -----------------------------------------------------------------------------
387 PROCESS (clk, rstn)
390 PROCESS (clk, rstn)
388 BEGIN
391 BEGIN
389 IF rstn = '0' THEN
392 IF rstn = '0' THEN
390 state_fsm_select_channel <= IDLE;
393 state_fsm_select_channel <= IDLE;
391 ELSIF clk'EVENT AND clk = '1' THEN
394 ELSIF clk'EVENT AND clk = '1' THEN
392 CASE state_fsm_select_channel IS
395 CASE state_fsm_select_channel IS
393 WHEN IDLE =>
396 WHEN IDLE =>
394 IF sample_f1_full = "11111" THEN
397 IF sample_f1_full = "11111" THEN
395 state_fsm_select_channel <= SWITCH_F1;
398 state_fsm_select_channel <= SWITCH_F1;
396 ELSIF sample_f1_almost_full = "00000" THEN
399 ELSIF sample_f1_almost_full = "00000" THEN
397 IF sample_f0_A_full = "11111" THEN
400 IF sample_f0_A_full = "11111" THEN
398 state_fsm_select_channel <= SWITCH_F0_A;
401 state_fsm_select_channel <= SWITCH_F0_A;
399 ELSIF sample_f0_B_full = "11111" THEN
402 ELSIF sample_f0_B_full = "11111" THEN
400 state_fsm_select_channel <= SWITCH_F0_B;
403 state_fsm_select_channel <= SWITCH_F0_B;
401 ELSIF sample_f2_full = "11111" THEN
404 ELSIF sample_f2_full = "11111" THEN
402 state_fsm_select_channel <= SWITCH_F2;
405 state_fsm_select_channel <= SWITCH_F2;
403 END IF;
406 END IF;
404 END IF;
407 END IF;
405
408
406 WHEN SWITCH_F0_A =>
409 WHEN SWITCH_F0_A =>
407 IF sample_f0_A_empty = "11111" THEN
410 IF sample_f0_A_empty = "11111" THEN
408 state_fsm_select_channel <= IDLE;
411 state_fsm_select_channel <= IDLE;
409 END IF;
412 END IF;
410 WHEN SWITCH_F0_B =>
413 WHEN SWITCH_F0_B =>
411 IF sample_f0_B_empty = "11111" THEN
414 IF sample_f0_B_empty = "11111" THEN
412 state_fsm_select_channel <= IDLE;
415 state_fsm_select_channel <= IDLE;
413 END IF;
416 END IF;
414 WHEN SWITCH_F1 =>
417 WHEN SWITCH_F1 =>
415 IF sample_f1_empty = "11111" THEN
418 IF sample_f1_empty = "11111" THEN
416 state_fsm_select_channel <= IDLE;
419 state_fsm_select_channel <= IDLE;
417 END IF;
420 END IF;
418 WHEN SWITCH_F2 =>
421 WHEN SWITCH_F2 =>
419 IF sample_f2_empty = "11111" THEN
422 IF sample_f2_empty = "11111" THEN
420 state_fsm_select_channel <= IDLE;
423 state_fsm_select_channel <= IDLE;
421 END IF;
424 END IF;
422 WHEN OTHERS => NULL;
425 WHEN OTHERS => NULL;
423 END CASE;
426 END CASE;
424
427
425 END IF;
428 END IF;
426 END PROCESS;
429 END PROCESS;
427
430
428 PROCESS (clk, rstn)
431 PROCESS (clk, rstn)
429 BEGIN
432 BEGIN
430 IF rstn = '0' THEN
433 IF rstn = '0' THEN
431 pre_state_fsm_select_channel <= IDLE;
434 pre_state_fsm_select_channel <= IDLE;
432 ELSIF clk'EVENT AND clk = '1' THEN
435 ELSIF clk'EVENT AND clk = '1' THEN
433 pre_state_fsm_select_channel <= state_fsm_select_channel;
436 pre_state_fsm_select_channel <= state_fsm_select_channel;
434 END IF;
437 END IF;
435 END PROCESS;
438 END PROCESS;
436
439
437
440
438 -----------------------------------------------------------------------------
441 -----------------------------------------------------------------------------
439 -- SWITCH SELECT CHANNEL
442 -- SWITCH SELECT CHANNEL
440 -----------------------------------------------------------------------------
443 -----------------------------------------------------------------------------
441 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
444 sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
442 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
445 sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
443 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
446 sample_f1_empty WHEN state_fsm_select_channel = SWITCH_F1 ELSE
444 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
447 sample_f2_empty WHEN state_fsm_select_channel = SWITCH_F2 ELSE
445 (OTHERS => '1');
448 (OTHERS => '1');
446
449
447 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
450 sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
448 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
451 sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
449 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
452 sample_f1_full WHEN state_fsm_select_channel = SWITCH_F1 ELSE
450 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
453 sample_f2_full WHEN state_fsm_select_channel = SWITCH_F2 ELSE
451 (OTHERS => '0');
454 (OTHERS => '0');
452
455
453 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
456 sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
454 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
457 sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
455 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
458 sample_f1_rdata WHEN pre_state_fsm_select_channel = SWITCH_F1 ELSE
456 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
459 sample_f2_rdata; -- WHEN state_fsm_select_channel = SWITCH_F2 ELSE
457
460
458
461
459 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
462 sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
460 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
463 sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
461 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
464 sample_f1_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1 ELSE (OTHERS => '1');
462 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
465 sample_f2_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2 ELSE (OTHERS => '1');
463
466
464
467
465 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
468 status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
466 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
469 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
467 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
470 time_reg_f1 & "01" WHEN state_fsm_select_channel = SWITCH_F1 ELSE
468 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
471 time_reg_f2 & "10"; -- WHEN state_fsm_select_channel = SWITCH_F2
469
472
470 -----------------------------------------------------------------------------
473 -----------------------------------------------------------------------------
471 -- FSM LOAD FFT
474 -- FSM LOAD FFT
472 -----------------------------------------------------------------------------
475 -----------------------------------------------------------------------------
473
476
474 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
477 sample_ren <= sample_ren_s WHEN sample_load = '1' ELSE (OTHERS => '1');
475
478
476 PROCESS (clk, rstn)
479 PROCESS (clk, rstn)
477 BEGIN
480 BEGIN
478 IF rstn = '0' THEN
481 IF rstn = '0' THEN
479 sample_ren_s <= (OTHERS => '1');
482 sample_ren_s <= (OTHERS => '1');
480 state_fsm_load_FFT <= IDLE;
483 state_fsm_load_FFT <= IDLE;
481 status_MS_input <= (OTHERS => '0');
484 status_MS_input <= (OTHERS => '0');
482 --next_state_fsm_load_FFT <= IDLE;
485 --next_state_fsm_load_FFT <= IDLE;
483 --sample_valid <= '0';
486 --sample_valid <= '0';
484 ELSIF clk'EVENT AND clk = '1' THEN
487 ELSIF clk'EVENT AND clk = '1' THEN
485 CASE state_fsm_load_FFT IS
488 CASE state_fsm_load_FFT IS
486 WHEN IDLE =>
489 WHEN IDLE =>
487 --sample_valid <= '0';
490 --sample_valid <= '0';
488 sample_ren_s <= (OTHERS => '1');
491 sample_ren_s <= (OTHERS => '1');
489 IF sample_full = "11111" AND sample_load = '1' THEN
492 IF sample_full = "11111" AND sample_load = '1' THEN
490 state_fsm_load_FFT <= FIFO_1;
493 state_fsm_load_FFT <= FIFO_1;
491 status_MS_input <= status_channel;
494 status_MS_input <= status_channel;
492 END IF;
495 END IF;
493
496
494 WHEN FIFO_1 =>
497 WHEN FIFO_1 =>
495 sample_ren_s <= "1111" & NOT(sample_load);
498 sample_ren_s <= "1111" & NOT(sample_load);
496 IF sample_empty(0) = '1' THEN
499 IF sample_empty(0) = '1' THEN
497 sample_ren_s <= (OTHERS => '1');
500 sample_ren_s <= (OTHERS => '1');
498 state_fsm_load_FFT <= FIFO_2;
501 state_fsm_load_FFT <= FIFO_2;
499 END IF;
502 END IF;
500
503
501 WHEN FIFO_2 =>
504 WHEN FIFO_2 =>
502 sample_ren_s <= "111" & NOT(sample_load) & '1';
505 sample_ren_s <= "111" & NOT(sample_load) & '1';
503 IF sample_empty(1) = '1' THEN
506 IF sample_empty(1) = '1' THEN
504 sample_ren_s <= (OTHERS => '1');
507 sample_ren_s <= (OTHERS => '1');
505 state_fsm_load_FFT <= FIFO_3;
508 state_fsm_load_FFT <= FIFO_3;
506 END IF;
509 END IF;
507
510
508 WHEN FIFO_3 =>
511 WHEN FIFO_3 =>
509 sample_ren_s <= "11" & NOT(sample_load) & "11";
512 sample_ren_s <= "11" & NOT(sample_load) & "11";
510 IF sample_empty(2) = '1' THEN
513 IF sample_empty(2) = '1' THEN
511 sample_ren_s <= (OTHERS => '1');
514 sample_ren_s <= (OTHERS => '1');
512 state_fsm_load_FFT <= FIFO_4;
515 state_fsm_load_FFT <= FIFO_4;
513 END IF;
516 END IF;
514
517
515 WHEN FIFO_4 =>
518 WHEN FIFO_4 =>
516 sample_ren_s <= '1' & NOT(sample_load) & "111";
519 sample_ren_s <= '1' & NOT(sample_load) & "111";
517 IF sample_empty(3) = '1' THEN
520 IF sample_empty(3) = '1' THEN
518 sample_ren_s <= (OTHERS => '1');
521 sample_ren_s <= (OTHERS => '1');
519 state_fsm_load_FFT <= FIFO_5;
522 state_fsm_load_FFT <= FIFO_5;
520 END IF;
523 END IF;
521
524
522 WHEN FIFO_5 =>
525 WHEN FIFO_5 =>
523 sample_ren_s <= NOT(sample_load) & "1111";
526 sample_ren_s <= NOT(sample_load) & "1111";
524 IF sample_empty(4) = '1' THEN
527 IF sample_empty(4) = '1' THEN
525 sample_ren_s <= (OTHERS => '1');
528 sample_ren_s <= (OTHERS => '1');
526 state_fsm_load_FFT <= IDLE;
529 state_fsm_load_FFT <= IDLE;
527 END IF;
530 END IF;
528 WHEN OTHERS => NULL;
531 WHEN OTHERS => NULL;
529 END CASE;
532 END CASE;
530 END IF;
533 END IF;
531 END PROCESS;
534 END PROCESS;
532
535
533 PROCESS (clk, rstn)
536 PROCESS (clk, rstn)
534 BEGIN
537 BEGIN
535 IF rstn = '0' THEN
538 IF rstn = '0' THEN
536 sample_valid_r <= '0';
539 sample_valid_r <= '0';
537 next_state_fsm_load_FFT <= IDLE;
540 next_state_fsm_load_FFT <= IDLE;
538 ELSIF clk'EVENT AND clk = '1' THEN
541 ELSIF clk'EVENT AND clk = '1' THEN
539 next_state_fsm_load_FFT <= state_fsm_load_FFT;
542 next_state_fsm_load_FFT <= state_fsm_load_FFT;
540 IF sample_ren_s = "11111" THEN
543 IF sample_ren_s = "11111" THEN
541 sample_valid_r <= '0';
544 sample_valid_r <= '0';
542 ELSE
545 ELSE
543 sample_valid_r <= '1';
546 sample_valid_r <= '1';
544 END IF;
547 END IF;
545 END IF;
548 END IF;
546 END PROCESS;
549 END PROCESS;
547
550
548 sample_valid <= sample_valid_r AND sample_load;
551 sample_valid <= sample_valid_r AND sample_load;
549
552
550 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
553 sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
551 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
554 sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
552 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
555 sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
553 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
556 sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
554 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
557 sample_rdata(16*5-1 DOWNTO 16*4); --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
555
558
556 -----------------------------------------------------------------------------
559 -----------------------------------------------------------------------------
557 -- FFT
560 -- FFT
558 -----------------------------------------------------------------------------
561 -----------------------------------------------------------------------------
559 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
562 lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
560 PORT MAP (
563 PORT MAP (
561 clk => clk,
564 clk => clk,
562 rstn => rstn,
565 rstn => rstn,
563 sample_valid => sample_valid,
566 sample_valid => sample_valid,
564 fft_read => fft_read,
567 fft_read => fft_read,
565 sample_data => sample_data,
568 sample_data => sample_data,
566 sample_load => sample_load,
569 sample_load => sample_load,
567 fft_pong => fft_pong,
570 fft_pong => fft_pong,
568 fft_data_im => fft_data_im,
571 fft_data_im => fft_data_im,
569 fft_data_re => fft_data_re,
572 fft_data_re => fft_data_re,
570 fft_data_valid => fft_data_valid,
573 fft_data_valid => fft_data_valid,
571 fft_ready => fft_ready);
574 fft_ready => fft_ready);
572
575
576 observation_vector_0(5 DOWNTO 0) <= fft_ready & --5
577 fft_data_valid & --4
578 fft_pong & --3
579 sample_load & --2
580 fft_read & --1
581 sample_valid; --0
582
583
573 -----------------------------------------------------------------------------
584 -----------------------------------------------------------------------------
574 PROCESS (clk, rstn)
585 PROCESS (clk, rstn)
575 BEGIN
586 BEGIN
576 IF rstn = '0' THEN
587 IF rstn = '0' THEN
577 state_fsm_load_MS_memory <= IDLE;
588 state_fsm_load_MS_memory <= IDLE;
578 current_fifo_load <= "00001";
589 current_fifo_load <= "00001";
579 ELSIF clk'EVENT AND clk = '1' THEN
590 ELSIF clk'EVENT AND clk = '1' THEN
580 CASE state_fsm_load_MS_memory IS
591 CASE state_fsm_load_MS_memory IS
581 WHEN IDLE =>
592 WHEN IDLE =>
582 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
593 IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
583 state_fsm_load_MS_memory <= LOAD_FIFO;
594 state_fsm_load_MS_memory <= LOAD_FIFO;
584 END IF;
595 END IF;
585 WHEN LOAD_FIFO =>
596 WHEN LOAD_FIFO =>
586 IF current_fifo_full = '1' THEN
597 IF current_fifo_full = '1' THEN
587 state_fsm_load_MS_memory <= TRASH_FFT;
598 state_fsm_load_MS_memory <= TRASH_FFT;
588 END IF;
599 END IF;
589 WHEN TRASH_FFT =>
600 WHEN TRASH_FFT =>
590 IF fft_ready = '0' THEN
601 IF fft_ready = '0' THEN
591 state_fsm_load_MS_memory <= IDLE;
602 state_fsm_load_MS_memory <= IDLE;
592 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
603 current_fifo_load <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
593 END IF;
604 END IF;
594 WHEN OTHERS => NULL;
605 WHEN OTHERS => NULL;
595 END CASE;
606 END CASE;
596
607
597 END IF;
608 END IF;
598 END PROCESS;
609 END PROCESS;
599
610
600 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
611 current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
601 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
612 MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
602 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
613 MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
603 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
614 MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
604 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
615 MEM_IN_SM_Empty(4); -- WHEN current_fifo_load(3) = '1' ELSE
605
616
606 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
617 current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
607 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
618 MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
608 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
619 MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
609 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
620 MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
610 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
621 MEM_IN_SM_Full(4); -- WHEN current_fifo_load(3) = '1' ELSE
611
622
612 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
623 current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
613 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
624 MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
614 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
625 MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
615 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
626 MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
616 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
627 MEM_IN_SM_locked(4); -- WHEN current_fifo_load(3) = '1' ELSE
617
628
618 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
629 fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
619
630
620 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
631 all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
621 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
632 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
622 AND state_fsm_load_MS_memory = LOAD_FIFO
633 AND state_fsm_load_MS_memory = LOAD_FIFO
623 AND current_fifo_load(I) = '1'
634 AND current_fifo_load(I) = '1'
624 ELSE '1';
635 ELSE '1';
625 END GENERATE all_fifo;
636 END GENERATE all_fifo;
626
637
627 PROCESS (clk, rstn)
638 PROCESS (clk, rstn)
628 BEGIN
639 BEGIN
629 IF rstn = '0' THEN
640 IF rstn = '0' THEN
630 MEM_IN_SM_wen <= (OTHERS => '1');
641 MEM_IN_SM_wen <= (OTHERS => '1');
631 ELSIF clk'EVENT AND clk = '1' THEN
642 ELSIF clk'EVENT AND clk = '1' THEN
632 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
643 MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
633 END IF;
644 END IF;
634 END PROCESS;
645 END PROCESS;
635
646
636 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
647 MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
637 (fft_data_im & fft_data_re) &
648 (fft_data_im & fft_data_re) &
638 (fft_data_im & fft_data_re) &
649 (fft_data_im & fft_data_re) &
639 (fft_data_im & fft_data_re) &
650 (fft_data_im & fft_data_re) &
640 (fft_data_im & fft_data_re);
651 (fft_data_im & fft_data_re);
652 -----------------------------------------------------------------------------
653
641
654
642 -----------------------------------------------------------------------------
655 -----------------------------------------------------------------------------
643 Mem_In_SpectralMatrix : lppFIFOxN
656 Mem_In_SpectralMatrix : lppFIFOxN
644 GENERIC MAP (
657 GENERIC MAP (
645 tech => 0,
658 tech => 0,
646 Mem_use => Mem_use,
659 Mem_use => Mem_use,
647 Data_sz => 32, --16,
660 Data_sz => 32, --16,
648 Addr_sz => 7, --8
661 Addr_sz => 7, --8
649 FifoCnt => 5)
662 FifoCnt => 5)
650 PORT MAP (
663 PORT MAP (
651 clk => clk,
664 clk => clk,
652 rstn => rstn,
665 rstn => rstn,
653
666
654 ReUse => MEM_IN_SM_ReUse,
667 ReUse => MEM_IN_SM_ReUse,
655
668
656 wen => MEM_IN_SM_wen,
669 wen => MEM_IN_SM_wen,
657 wdata => MEM_IN_SM_wData,
670 wdata => MEM_IN_SM_wData,
658
671
659 ren => MEM_IN_SM_ren,
672 ren => MEM_IN_SM_ren,
660 rdata => MEM_IN_SM_rData,
673 rdata => MEM_IN_SM_rData,
661 full => MEM_IN_SM_Full,
674 full => MEM_IN_SM_Full,
662 empty => MEM_IN_SM_Empty,
675 empty => MEM_IN_SM_Empty,
663 almost_full => OPEN);
676 almost_full => OPEN);
664
677
665 -----------------------------------------------------------------------------
678 -----------------------------------------------------------------------------
666 MS_control_1 : MS_control
679 MS_control_1 : MS_control
667 PORT MAP (
680 PORT MAP (
668 clk => clk,
681 clk => clk,
669 rstn => rstn,
682 rstn => rstn,
670
683
671 current_status_ms => status_MS_input,
684 current_status_ms => status_MS_input,
672
685
673 fifo_in_lock => MEM_IN_SM_locked,
686 fifo_in_lock => MEM_IN_SM_locked,
674 fifo_in_data => MEM_IN_SM_rdata,
687 fifo_in_data => MEM_IN_SM_rdata,
675 fifo_in_full => MEM_IN_SM_Full,
688 fifo_in_full => MEM_IN_SM_Full,
676 fifo_in_empty => MEM_IN_SM_Empty,
689 fifo_in_empty => MEM_IN_SM_Empty,
677 fifo_in_ren => MEM_IN_SM_ren,
690 fifo_in_ren => MEM_IN_SM_ren,
678 fifo_in_reuse => MEM_IN_SM_ReUse,
691 fifo_in_reuse => MEM_IN_SM_ReUse,
679
692
680 fifo_out_data => SM_in_data,
693 fifo_out_data => SM_in_data,
681 fifo_out_ren => SM_in_ren,
694 fifo_out_ren => SM_in_ren,
682 fifo_out_empty => SM_in_empty,
695 fifo_out_empty => SM_in_empty,
683
696
684 current_status_component => status_component,
697 current_status_component => status_component,
685
698
686 correlation_start => SM_correlation_start,
699 correlation_start => SM_correlation_start,
687 correlation_auto => SM_correlation_auto,
700 correlation_auto => SM_correlation_auto,
688 correlation_done => SM_correlation_done);
701 correlation_done => SM_correlation_done);
689
702
690
703
691 MS_calculation_1 : MS_calculation
704 MS_calculation_1 : MS_calculation
692 PORT MAP (
705 PORT MAP (
693 clk => clk,
706 clk => clk,
694 rstn => rstn,
707 rstn => rstn,
695
708
696 fifo_in_data => SM_in_data,
709 fifo_in_data => SM_in_data,
697 fifo_in_ren => SM_in_ren,
710 fifo_in_ren => SM_in_ren,
698 fifo_in_empty => SM_in_empty,
711 fifo_in_empty => SM_in_empty,
699
712
700 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
713 fifo_out_data => MEM_OUT_SM_Data_in_s, -- TODO
701 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
714 fifo_out_wen => MEM_OUT_SM_Write_s, -- TODO
702 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
715 fifo_out_full => MEM_OUT_SM_Full_s, -- TODO
703
716
704 correlation_start => SM_correlation_start,
717 correlation_start => SM_correlation_start,
705 correlation_auto => SM_correlation_auto,
718 correlation_auto => SM_correlation_auto,
706 correlation_begin => SM_correlation_begin,
719 correlation_begin => SM_correlation_begin,
707 correlation_done => SM_correlation_done);
720 correlation_done => SM_correlation_done);
708
721
709 -----------------------------------------------------------------------------
722 -----------------------------------------------------------------------------
710 PROCESS (clk, rstn)
723 PROCESS (clk, rstn)
711 BEGIN -- PROCESS
724 BEGIN -- PROCESS
712 IF rstn = '0' THEN -- asynchronous reset (active low)
725 IF rstn = '0' THEN -- asynchronous reset (active low)
713 current_matrix_write <= '0';
726 current_matrix_write <= '0';
714 current_matrix_wait_empty <= '1';
727 current_matrix_wait_empty <= '1';
715 status_component_fifo_0 <= (OTHERS => '0');
728 status_component_fifo_0 <= (OTHERS => '0');
716 status_component_fifo_1 <= (OTHERS => '0');
729 status_component_fifo_1 <= (OTHERS => '0');
717 status_component_fifo_0_end <= '0';
730 status_component_fifo_0_end <= '0';
718 status_component_fifo_1_end <= '0';
731 status_component_fifo_1_end <= '0';
719 SM_correlation_done_reg1 <= '0';
732 SM_correlation_done_reg1 <= '0';
720 SM_correlation_done_reg2 <= '0';
733 SM_correlation_done_reg2 <= '0';
721 SM_correlation_done_reg3 <= '0';
734 SM_correlation_done_reg3 <= '0';
722
735
723 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
736 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
724 SM_correlation_done_reg1 <= SM_correlation_done;
737 SM_correlation_done_reg1 <= SM_correlation_done;
725 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
738 SM_correlation_done_reg2 <= SM_correlation_done_reg1;
726 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
739 SM_correlation_done_reg3 <= SM_correlation_done_reg2;
727 status_component_fifo_0_end <= '0';
740 status_component_fifo_0_end <= '0';
728 status_component_fifo_1_end <= '0';
741 status_component_fifo_1_end <= '0';
729 IF SM_correlation_begin = '1' THEN
742 IF SM_correlation_begin = '1' THEN
730 IF current_matrix_write = '0' THEN
743 IF current_matrix_write = '0' THEN
731 status_component_fifo_0 <= status_component;
744 status_component_fifo_0 <= status_component;
732 ELSE
745 ELSE
733 status_component_fifo_1 <= status_component;
746 status_component_fifo_1 <= status_component;
734 END IF;
747 END IF;
735 END IF;
748 END IF;
736
749
737 IF SM_correlation_done_reg3 = '1' THEN
750 IF SM_correlation_done_reg3 = '1' THEN
738 IF current_matrix_write = '0' THEN
751 IF current_matrix_write = '0' THEN
739 status_component_fifo_0_end <= '1';
752 status_component_fifo_0_end <= '1';
740 ELSE
753 ELSE
741 status_component_fifo_1_end <= '1';
754 status_component_fifo_1_end <= '1';
742 END IF;
755 END IF;
743 current_matrix_wait_empty <= '1';
756 current_matrix_wait_empty <= '1';
744 current_matrix_write <= NOT current_matrix_write;
757 current_matrix_write <= NOT current_matrix_write;
745 END IF;
758 END IF;
746
759
747 IF current_matrix_wait_empty <= '1' THEN
760 IF current_matrix_wait_empty <= '1' THEN
748 IF current_matrix_write = '0' THEN
761 IF current_matrix_write = '0' THEN
749 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
762 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
750 ELSE
763 ELSE
751 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
764 current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
752 END IF;
765 END IF;
753 END IF;
766 END IF;
754
767
755 END IF;
768 END IF;
756 END PROCESS;
769 END PROCESS;
757
770
758 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
771 MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
759 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
772 '1' WHEN SM_correlation_done_reg1 = '1' ELSE
760 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
773 '1' WHEN SM_correlation_done_reg2 = '1' ELSE
761 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
774 '1' WHEN SM_correlation_done_reg3 = '1' ELSE
762 '1' WHEN current_matrix_wait_empty = '1' ELSE
775 '1' WHEN current_matrix_wait_empty = '1' ELSE
763 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
776 MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0' ELSE
764 MEM_OUT_SM_Full(1);
777 MEM_OUT_SM_Full(1);
765
778
766 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
779 MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
767 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
780 MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
768
781
769 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
782 MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
770 -----------------------------------------------------------------------------
783 -----------------------------------------------------------------------------
771
784
772 Mem_Out_SpectralMatrix : lppFIFOxN
785 Mem_Out_SpectralMatrix : lppFIFOxN
773 GENERIC MAP (
786 GENERIC MAP (
774 tech => 0,
787 tech => 0,
775 Mem_use => Mem_use,
788 Mem_use => Mem_use,
776 Data_sz => 32,
789 Data_sz => 32,
777 Addr_sz => 8,
790 Addr_sz => 8,
778 FifoCnt => 2)
791 FifoCnt => 2)
779 PORT MAP (
792 PORT MAP (
780 clk => clk,
793 clk => clk,
781 rstn => rstn,
794 rstn => rstn,
782
795
783 ReUse => (OTHERS => '0'),
796 ReUse => (OTHERS => '0'),
784
797
785 wen => MEM_OUT_SM_Write,
798 wen => MEM_OUT_SM_Write,
786 wdata => MEM_OUT_SM_Data_in,
799 wdata => MEM_OUT_SM_Data_in,
787
800
788 ren => MEM_OUT_SM_Read,
801 ren => MEM_OUT_SM_Read,
789 rdata => MEM_OUT_SM_Data_out,
802 rdata => MEM_OUT_SM_Data_out,
790
803
791 full => MEM_OUT_SM_Full,
804 full => MEM_OUT_SM_Full,
792 empty => MEM_OUT_SM_Empty,
805 empty => MEM_OUT_SM_Empty,
793 almost_full => OPEN);
806 almost_full => OPEN);
794
807
795 -----------------------------------------------------------------------------
808 -----------------------------------------------------------------------------
796 -- MEM_OUT_SM_Read <= "00";
809 -- MEM_OUT_SM_Read <= "00";
797 PROCESS (clk, rstn)
810 PROCESS (clk, rstn)
798 BEGIN
811 BEGIN
799 IF rstn = '0' THEN
812 IF rstn = '0' THEN
800 fifo_0_ready <= '0';
813 fifo_0_ready <= '0';
801 fifo_1_ready <= '0';
814 fifo_1_ready <= '0';
802 fifo_ongoing <= '0';
815 fifo_ongoing <= '0';
803 ELSIF clk'EVENT AND clk = '1' THEN
816 ELSIF clk'EVENT AND clk = '1' THEN
804 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
817 IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
805 fifo_ongoing <= '1';
818 fifo_ongoing <= '1';
806 fifo_0_ready <= '0';
819 fifo_0_ready <= '0';
807 ELSIF status_component_fifo_0_end = '1' THEN
820 ELSIF status_component_fifo_0_end = '1' THEN
808 fifo_0_ready <= '1';
821 fifo_0_ready <= '1';
809 END IF;
822 END IF;
810
823
811 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
824 IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
812 fifo_ongoing <= '0';
825 fifo_ongoing <= '0';
813 fifo_1_ready <= '0';
826 fifo_1_ready <= '0';
814 ELSIF status_component_fifo_1_end = '1' THEN
827 ELSIF status_component_fifo_1_end = '1' THEN
815 fifo_1_ready <= '1';
828 fifo_1_ready <= '1';
816 END IF;
829 END IF;
817
830
818 END IF;
831 END IF;
819 END PROCESS;
832 END PROCESS;
820
833
821 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
834 MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
822 '1' WHEN fifo_0_ready = '0' ELSE
835 '1' WHEN fifo_0_ready = '0' ELSE
823 FSM_DMA_fifo_ren;
836 FSM_DMA_fifo_ren;
824
837
825 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
838 MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
826 '1' WHEN fifo_1_ready = '0' ELSE
839 '1' WHEN fifo_1_ready = '0' ELSE
827 FSM_DMA_fifo_ren;
840 FSM_DMA_fifo_ren;
828
841
829 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
842 FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
830 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
843 MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
831 '1';
844 '1';
832
845
833 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
846 FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
834 status_component_fifo_1;
847 status_component_fifo_1;
835
848
836 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
849 FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
837 MEM_OUT_SM_Data_out(63 DOWNTO 32);
850 MEM_OUT_SM_Data_out(63 DOWNTO 32);
838
851
839 -----------------------------------------------------------------------------
852 -----------------------------------------------------------------------------
840 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
853 lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
841 PORT MAP (
854 PORT MAP (
842 HCLK => clk,
855 HCLK => clk,
843 HRESETn => rstn,
856 HRESETn => rstn,
844
857
845 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
858 fifo_matrix_type => FSM_DMA_fifo_status(5 DOWNTO 4),
846 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
859 fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
847 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
860 fifo_matrix_time => FSM_DMA_fifo_status(53 DOWNTO 6),
848 fifo_data => FSM_DMA_fifo_data,
861 fifo_data => FSM_DMA_fifo_data,
849 fifo_empty => FSM_DMA_fifo_empty,
862 fifo_empty => FSM_DMA_fifo_empty,
850 fifo_ren => FSM_DMA_fifo_ren,
863 fifo_ren => FSM_DMA_fifo_ren,
851
864
852 dma_addr => dma_addr,
865 dma_addr => dma_addr,
853 dma_data => dma_data,
866 dma_data => dma_data,
854 dma_valid => dma_valid,
867 dma_valid => dma_valid,
855 dma_valid_burst => dma_valid_burst,
868 dma_valid_burst => dma_valid_burst,
856 dma_ren => dma_ren,
869 dma_ren => dma_ren,
857 dma_done => dma_done,
870 dma_done => dma_done,
858
871
859 ready_matrix_f0 => ready_matrix_f0,
872 ready_matrix_f0 => ready_matrix_f0,
860 ready_matrix_f1 => ready_matrix_f1,
873 ready_matrix_f1 => ready_matrix_f1,
861 ready_matrix_f2 => ready_matrix_f2,
874 ready_matrix_f2 => ready_matrix_f2,
862
875
863 error_bad_component_error => error_bad_component_error,
876 error_bad_component_error => error_bad_component_error,
864 error_buffer_full => error_buffer_full,
877 error_buffer_full => error_buffer_full,
865
878
866 debug_reg => debug_reg,
879 debug_reg => debug_reg,
867 status_ready_matrix_f0 => status_ready_matrix_f0,
880 status_ready_matrix_f0 => status_ready_matrix_f0,
868 status_ready_matrix_f1 => status_ready_matrix_f1,
881 status_ready_matrix_f1 => status_ready_matrix_f1,
869 status_ready_matrix_f2 => status_ready_matrix_f2,
882 status_ready_matrix_f2 => status_ready_matrix_f2,
870
883
871 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
884 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
872 config_active_interruption_onError => config_active_interruption_onError,
885 config_active_interruption_onError => config_active_interruption_onError,
873
886
874 addr_matrix_f0 => addr_matrix_f0,
887 addr_matrix_f0 => addr_matrix_f0,
875 addr_matrix_f1 => addr_matrix_f1,
888 addr_matrix_f1 => addr_matrix_f1,
876 addr_matrix_f2 => addr_matrix_f2,
889 addr_matrix_f2 => addr_matrix_f2,
877
890
878 matrix_time_f0 => matrix_time_f0,
891 matrix_time_f0 => matrix_time_f0,
879 matrix_time_f1 => matrix_time_f1,
892 matrix_time_f1 => matrix_time_f1,
880 matrix_time_f2 => matrix_time_f2
893 matrix_time_f2 => matrix_time_f2
881 );
894 );
882 -----------------------------------------------------------------------------
895 -----------------------------------------------------------------------------
883
896
884
897
885
898
886
899
887
900
888 -----------------------------------------------------------------------------
901 -----------------------------------------------------------------------------
889 -- TIME MANAGMENT
902 -- TIME MANAGMENT
890 -----------------------------------------------------------------------------
903 -----------------------------------------------------------------------------
891 all_time <= coarse_time & fine_time;
904 all_time <= coarse_time & fine_time;
892 --
905 --
893 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
906 f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
894 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
907 f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
895 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
908 f_empty(2) <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
896 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
909 f_empty(3) <= '1' WHEN sample_f2_empty = "11111" ELSE '0';
897
910
898 all_time_reg: FOR I IN 0 TO 3 GENERATE
911 all_time_reg: FOR I IN 0 TO 3 GENERATE
899
912
900 PROCESS (clk, rstn)
913 PROCESS (clk, rstn)
901 BEGIN
914 BEGIN
902 IF rstn = '0' THEN
915 IF rstn = '0' THEN
903 f_empty_reg(I) <= '1';
916 f_empty_reg(I) <= '1';
904 ELSIF clk'event AND clk = '1' THEN
917 ELSIF clk'event AND clk = '1' THEN
905 f_empty_reg(I) <= f_empty(I);
918 f_empty_reg(I) <= f_empty(I);
906 END IF;
919 END IF;
907 END PROCESS;
920 END PROCESS;
908
921
909 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
922 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
910
923
911 s_m_t_m_f0_A : spectral_matrix_time_managment
924 s_m_t_m_f0_A : spectral_matrix_time_managment
912 PORT MAP (
925 PORT MAP (
913 clk => clk,
926 clk => clk,
914 rstn => rstn,
927 rstn => rstn,
915 time_in => all_time,
928 time_in => all_time,
916 update_1 => time_update_f(I),
929 update_1 => time_update_f(I),
917 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
930 time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
918 );
931 );
919
932
920 END GENERATE all_time_reg;
933 END GENERATE all_time_reg;
921
934
922 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
935 time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
923 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
936 time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
924 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
937 time_reg_f1 <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
925 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
938 time_reg_f2 <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
926
939
927 -----------------------------------------------------------------------------
940 -----------------------------------------------------------------------------
928
941
929 END Behavioral;
942 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,298 +1,299
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
36 USE lpp.lpp_dma_pkg.ALL;
37 LIBRARY techmap;
37 LIBRARY techmap;
38 USE techmap.gencomp.ALL;
38 USE techmap.gencomp.ALL;
39
39
40
40
41 ENTITY lpp_lfr_ms_fsmdma IS
41 ENTITY lpp_lfr_ms_fsmdma IS
42 PORT (
42 PORT (
43 -- AMBA AHB system signals
43 -- AMBA AHB system signals
44 HCLK : IN STD_ULOGIC;
44 HCLK : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
45 HRESETn : IN STD_ULOGIC;
46
46
47 ---------------------------------------------------------------------------
47 ---------------------------------------------------------------------------
48 -- FIFO - IN
48 -- FIFO - IN
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
49 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
51 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 fifo_empty : IN STD_LOGIC;
53 fifo_empty : IN STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
54 fifo_ren : OUT STD_LOGIC;
55
55
56 ---------------------------------------------------------------------------
56 ---------------------------------------------------------------------------
57 -- DMA - OUT
57 -- DMA - OUT
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
58 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
59 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
60 dma_valid : OUT STD_LOGIC;
60 dma_valid : OUT STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
61 dma_valid_burst : OUT STD_LOGIC;
62 dma_ren : IN STD_LOGIC;
62 dma_ren : IN STD_LOGIC;
63 dma_done : IN STD_LOGIC;
63 dma_done : IN STD_LOGIC;
64
64
65 ---------------------------------------------------------------------------
65 ---------------------------------------------------------------------------
66 -- Reg out
66 -- Reg out
67 ready_matrix_f0 : OUT STD_LOGIC;
67 ready_matrix_f0 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
68 ready_matrix_f1 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
69 ready_matrix_f2 : OUT STD_LOGIC;
70
70
71 error_bad_component_error : OUT STD_LOGIC;
71 error_bad_component_error : OUT STD_LOGIC;
72 error_buffer_full : OUT STD_LOGIC;
72 error_buffer_full : OUT STD_LOGIC;
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
74
74
75 -- Reg In
75 -- Reg In
76 status_ready_matrix_f0 : IN STD_LOGIC;
76 status_ready_matrix_f0 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
77 status_ready_matrix_f1 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
78 status_ready_matrix_f2 : IN STD_LOGIC;
79
79
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
80 config_active_interruption_onNewMatrix : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
81 config_active_interruption_onError : IN STD_LOGIC;
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85
85
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
86 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
87 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
88 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
89
89
90 );
90 );
91 END;
91 END;
92
92
93 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
93 ARCHITECTURE Behavioral OF lpp_lfr_ms_fsmdma IS
94 -----------------------------------------------------------------------------
94 -----------------------------------------------------------------------------
95 TYPE state_DMAWriteBurst IS (IDLE,
95 TYPE state_DMAWriteBurst IS (IDLE,
96 CHECK_COMPONENT_TYPE,
96 CHECK_COMPONENT_TYPE,
97 WRITE_COARSE_TIME,
97 WRITE_COARSE_TIME,
98 WRITE_FINE_TIME,
98 WRITE_FINE_TIME,
99 TRASH_FIFO,
99 TRASH_FIFO,
100 SEND_DATA,
100 SEND_DATA,
101 WAIT_DATA_ACK
101 WAIT_DATA_ACK
102 );
102 );
103 SIGNAL state : state_DMAWriteBurst;
103 SIGNAL state : state_DMAWriteBurst;
104
104
105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
105 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
106 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SIGNAL header_check_ok : STD_LOGIC;
108 SIGNAL header_check_ok : STD_LOGIC;
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
109 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
110 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 -----------------------------------------------------------------------------
111 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
113
114 SIGNAL component_send : STD_LOGIC;
114 SIGNAL component_send : STD_LOGIC;
115 SIGNAL component_send_ok : STD_LOGIC;
115 SIGNAL component_send_ok : STD_LOGIC;
116 -----------------------------------------------------------------------------
116 -----------------------------------------------------------------------------
117 SIGNAL fifo_ren_trash : STD_LOGIC;
117 SIGNAL fifo_ren_trash : STD_LOGIC;
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL debug_reg_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 SIGNAL log_empty_fifo : STD_LOGIC;
122 SIGNAL log_empty_fifo : STD_LOGIC;
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
124
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
125 SIGNAL matrix_buffer_ready : STD_LOGIC;
126 BEGIN
126 BEGIN
127
127
128 debug_reg <= debug_reg_s;
128 debug_reg <= debug_reg_s;
129
129
130
130
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
131 matrix_buffer_ready <= '1' WHEN matrix_type = "00" AND status_ready_matrix_f0 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
132 '1' WHEN matrix_type = "01" AND status_ready_matrix_f1 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
133 '1' WHEN matrix_type = "10" AND status_ready_matrix_f2 = '0' ELSE
134 '0';
134 '0';
135
135
136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
136 header_check_ok <= '0' WHEN component_type = "1111" ELSE -- ?? component_type_pre = "1111"
137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
137 '1' WHEN component_type = "0000" ELSE --AND component_type_pre = "0000" ELSE
138 '1' WHEN component_type = component_type_pre + "0001" ELSE
138 '1' WHEN component_type = component_type_pre + "0001" ELSE
139 '0';
139 '0';
140
140
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
141 address_matrix <= addr_matrix_f0 WHEN matrix_type = "00" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
142 addr_matrix_f1 WHEN matrix_type = "01" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
143 addr_matrix_f2 WHEN matrix_type = "10" ELSE
144 (OTHERS => '0');
144 (OTHERS => '0');
145
145
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
146 debug_reg_s(31 DOWNTO 15) <= (OTHERS => '0');
147 -----------------------------------------------------------------------------
147 -----------------------------------------------------------------------------
148 -- DMA control
148 -- DMA control
149 -----------------------------------------------------------------------------
149 -----------------------------------------------------------------------------
150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
150 DMAWriteFSM_p : PROCESS (HCLK, HRESETn)
151 BEGIN
151 BEGIN
152 IF HRESETn = '0' THEN
152 IF HRESETn = '0' THEN
153 matrix_type <= (OTHERS => '0');
153 matrix_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
154 component_type <= (OTHERS => '0');
155 state <= IDLE;
155 state <= IDLE;
156 ready_matrix_f0 <= '0';
156 ready_matrix_f0 <= '0';
157 ready_matrix_f1 <= '0';
157 ready_matrix_f1 <= '0';
158 ready_matrix_f2 <= '0';
158 ready_matrix_f2 <= '0';
159 error_bad_component_error <= '0';
159 error_bad_component_error <= '0';
160 error_buffer_full <= '0'; -- TODO
160 error_buffer_full <= '0'; -- TODO
161 component_type_pre <= "0000";
161 component_type_pre <= "0000";
162 fifo_ren_trash <= '1';
162 fifo_ren_trash <= '1';
163 component_send <= '0';
163 component_send <= '0';
164 address <= (OTHERS => '0');
164 address <= (OTHERS => '0');
165
165
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
166 debug_reg_s(2 DOWNTO 0) <= (OTHERS => '0');
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
167 debug_reg_s(5 DOWNTO 3) <= (OTHERS => '0');
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
168 debug_reg_s(8 DOWNTO 6) <= (OTHERS => '0');
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
169 debug_reg_s(10 DOWNTO 9) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
170 debug_reg_s(14 DOWNTO 11) <= (OTHERS => '0');
171
171
172 log_empty_fifo <= '0';
172 log_empty_fifo <= '0';
173
173
174 matrix_time_f0 <= (OTHERS => '0');
174 matrix_time_f0 <= (OTHERS => '0');
175 matrix_time_f1 <= (OTHERS => '0');
175 matrix_time_f1 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
176 matrix_time_f2 <= (OTHERS => '0');
177
177
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
178 ELSIF HCLK'EVENT AND HCLK = '1' THEN
179 --
179 --
180 debug_reg_s(3) <= status_ready_matrix_f0;
180 debug_reg_s(3) <= status_ready_matrix_f0;
181 debug_reg_s(4) <= status_ready_matrix_f1;
181 debug_reg_s(4) <= status_ready_matrix_f1;
182 debug_reg_s(5) <= status_ready_matrix_f2;
182 debug_reg_s(5) <= status_ready_matrix_f2;
183 debug_reg_s(6) <= '0';
183 debug_reg_s(6) <= '0';
184 debug_reg_s(7) <= '0';
184 debug_reg_s(7) <= '0';
185 debug_reg_s(8) <= '0';
185 debug_reg_s(8) <= '0';
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
186 debug_reg_s(10 DOWNTO 9) <= matrix_type;
187 debug_reg_s(14 DOWNTO 11) <= component_type;
187 debug_reg_s(14 DOWNTO 11) <= component_type;
188
188
189 --
189 --
190
190
191
191
192
192
193 ready_matrix_f0 <= '0';
193 ready_matrix_f0 <= '0';
194 ready_matrix_f1 <= '0';
194 ready_matrix_f1 <= '0';
195 ready_matrix_f2 <= '0';
195 ready_matrix_f2 <= '0';
196 error_bad_component_error <= '0';
196 error_bad_component_error <= '0';
197 error_buffer_full <= '0';
197 error_buffer_full <= '0';
198
198
199 CASE state IS
199 CASE state IS
200 WHEN IDLE =>
200 WHEN IDLE =>
201 debug_reg_s(2 DOWNTO 0) <= "000";
201 debug_reg_s(2 DOWNTO 0) <= "000";
202 IF fifo_empty = '0' THEN
202 IF fifo_empty = '0' THEN
203 state <= CHECK_COMPONENT_TYPE;
203 state <= CHECK_COMPONENT_TYPE;
204 matrix_type <= fifo_matrix_type;
204 matrix_type <= fifo_matrix_type;
205 component_type <= fifo_matrix_component;
205 component_type <= fifo_matrix_component;
206 component_type_pre <= component_type;
206 component_type_pre <= component_type;
207 END IF;
207 END IF;
208
208
209 log_empty_fifo <= '0';
209 log_empty_fifo <= '0';
210
210
211 WHEN CHECK_COMPONENT_TYPE =>
211 WHEN CHECK_COMPONENT_TYPE =>
212 debug_reg_s(2 DOWNTO 0) <= "001";
212 debug_reg_s(2 DOWNTO 0) <= "001";
213
213
214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
214 IF header_check_ok = '1' AND matrix_buffer_ready = '1'THEN
215 IF component_type = "0000" THEN
215 IF component_type = "0000" THEN
216 address <= address_matrix;
216 address <= address_matrix;
217 CASE matrix_type IS
217 CASE matrix_type IS
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
218 WHEN "00" => matrix_time_f0 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
219 WHEN "01" => matrix_time_f1 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
220 WHEN "10" => matrix_time_f2 <= fifo_matrix_time;
221 WHEN OTHERS => NULL;
221 WHEN OTHERS => NULL;
222 END CASE;
222 END CASE;
223 component_send <= '1';
223 component_send <= '1';
224 END IF;
224 END IF;
225 state <= SEND_DATA;
225 state <= SEND_DATA;
226 --
226 --
227 ELSE
227 ELSE
228 error_bad_component_error <= NOT header_check_ok;
228 error_bad_component_error <= NOT header_check_ok;
229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
229 error_buffer_full <= NOT matrix_buffer_ready; -- TODO
230 component_type_pre <= "0000";
230 component_type_pre <= "0000";
231 state <= TRASH_FIFO;
231 state <= TRASH_FIFO;
232 END IF;
232 END IF;
233
233
234 WHEN TRASH_FIFO =>
234 WHEN TRASH_FIFO =>
235 debug_reg_s(2 DOWNTO 0) <= "100";
235 debug_reg_s(2 DOWNTO 0) <= "100";
236
236
237 error_buffer_full <= '0';
237 error_bad_component_error <= '0';
238 error_bad_component_error <= '0';
238 IF fifo_empty = '1' THEN
239 IF fifo_empty = '1' THEN
239 state <= IDLE;
240 state <= IDLE;
240 fifo_ren_trash <= '1';
241 fifo_ren_trash <= '1';
241 ELSE
242 ELSE
242 fifo_ren_trash <= '0';
243 fifo_ren_trash <= '0';
243 END IF;
244 END IF;
244
245
245 WHEN SEND_DATA =>
246 WHEN SEND_DATA =>
246 debug_reg_s(2 DOWNTO 0) <= "010";
247 debug_reg_s(2 DOWNTO 0) <= "010";
247
248
248 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
249 IF fifo_empty = '1' OR log_empty_fifo = '1' THEN
249 state <= IDLE;
250 state <= IDLE;
250 IF component_type = "1110" THEN
251 IF component_type = "1110" THEN
251 CASE matrix_type IS
252 CASE matrix_type IS
252 WHEN "00" =>
253 WHEN "00" =>
253 ready_matrix_f0 <= '1';
254 ready_matrix_f0 <= '1';
254 debug_reg_s(6) <= '1';
255 debug_reg_s(6) <= '1';
255 WHEN "01" =>
256 WHEN "01" =>
256 ready_matrix_f1 <= '1';
257 ready_matrix_f1 <= '1';
257 debug_reg_s(7) <= '1';
258 debug_reg_s(7) <= '1';
258 WHEN "10" =>
259 WHEN "10" =>
259 ready_matrix_f2 <= '1';
260 ready_matrix_f2 <= '1';
260 debug_reg_s(8) <= '1';
261 debug_reg_s(8) <= '1';
261 WHEN OTHERS => NULL;
262 WHEN OTHERS => NULL;
262 END CASE;
263 END CASE;
263 END IF;
264 END IF;
264 ELSE
265 ELSE
265 component_send <= '1';
266 component_send <= '1';
266 address <= address;
267 address <= address;
267 state <= WAIT_DATA_ACK;
268 state <= WAIT_DATA_ACK;
268 END IF;
269 END IF;
269
270
270 WHEN WAIT_DATA_ACK =>
271 WHEN WAIT_DATA_ACK =>
271 log_empty_fifo <= fifo_empty OR log_empty_fifo;
272 log_empty_fifo <= fifo_empty OR log_empty_fifo;
272
273
273 debug_reg_s(2 DOWNTO 0) <= "011";
274 debug_reg_s(2 DOWNTO 0) <= "011";
274
275
275 IF dma_ren = '0' THEN
276 IF dma_ren = '0' THEN
276 component_send <= '0';
277 component_send <= '0';
277 END IF;
278 END IF;
278
279
279 IF component_send_ok = '1' THEN
280 IF component_send_ok = '1' THEN
280 address <= address + 64;
281 address <= address + 64;
281 state <= SEND_DATA;
282 state <= SEND_DATA;
282 END IF;
283 END IF;
283
284
284 WHEN OTHERS => NULL;
285 WHEN OTHERS => NULL;
285 END CASE;
286 END CASE;
286
287
287 END IF;
288 END IF;
288 END PROCESS DMAWriteFSM_p;
289 END PROCESS DMAWriteFSM_p;
289
290
290 dma_valid_burst <= component_send;
291 dma_valid_burst <= component_send;
291 dma_valid <= '0';
292 dma_valid <= '0';
292 dma_data <= fifo_data;
293 dma_data <= fifo_data;
293 dma_addr <= address;
294 dma_addr <= address;
294 fifo_ren <= dma_ren AND fifo_ren_trash;
295 fifo_ren <= dma_ren AND fifo_ren_trash;
295
296
296 component_send_ok <= dma_done;
297 component_send_ok <= dma_done;
297
298
298 END Behavioral;
299 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,406 +1,416
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16 -----------------------------------------------------------------------------
16 -----------------------------------------------------------------------------
17 -- TEMP
17 -- TEMP
18 -----------------------------------------------------------------------------
18 -----------------------------------------------------------------------------
19 COMPONENT lpp_lfr_ms_test
19 COMPONENT lpp_lfr_ms_test
20 GENERIC (
20 GENERIC (
21 Mem_use : INTEGER);
21 Mem_use : INTEGER);
22 PORT (
22 PORT (
23 clk : IN STD_LOGIC;
23 clk : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
24 rstn : IN STD_LOGIC;
25
25
26 -- TIME
26 -- TIME
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
27 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
28 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
29 --
29 --
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
30 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
31 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
32 --
32 --
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
33 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
34 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
35 --
35 --
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
36 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
37 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
38
38
39
39
40
40
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
42 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
43
43
44 --
44 --
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
45 --sample_ren : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 --sample_full : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 --sample_empty : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
49
49
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
50 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
51
51
52 -- IN
52 -- IN
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
53 MEM_IN_SM_locked : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
54
54
55 -----------------------------------------------------------------------------
55 -----------------------------------------------------------------------------
56
56
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
57 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
58 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
59 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
60 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61
61
62 SM_correlation_start : OUT STD_LOGIC;
62 SM_correlation_start : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
63 SM_correlation_auto : OUT STD_LOGIC;
64 SM_correlation_done : IN STD_LOGIC
64 SM_correlation_done : IN STD_LOGIC
65 );
65 );
66 END COMPONENT;
66 END COMPONENT;
67
67
68
68
69 -----------------------------------------------------------------------------
69 -----------------------------------------------------------------------------
70 COMPONENT lpp_lfr_ms
70 COMPONENT lpp_lfr_ms
71 GENERIC (
71 GENERIC (
72 Mem_use : INTEGER
72 Mem_use : INTEGER
73 );
73 );
74 PORT (
74 PORT (
75 clk : IN STD_LOGIC;
75 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
77
77
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
78 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
79 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
80
80
81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
81 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
82 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
83
83
84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
84 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
85 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
86
86
87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
87 sample_f2_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
88 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
89
89
90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
91 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 dma_valid : OUT STD_LOGIC;
92 dma_valid : OUT STD_LOGIC;
93 dma_valid_burst : OUT STD_LOGIC;
93 dma_valid_burst : OUT STD_LOGIC;
94 dma_ren : IN STD_LOGIC;
94 dma_ren : IN STD_LOGIC;
95 dma_done : IN STD_LOGIC;
95 dma_done : IN STD_LOGIC;
96
96
97 ready_matrix_f0 : OUT STD_LOGIC;
97 ready_matrix_f0 : OUT STD_LOGIC;
98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
98 -- ready_matrix_f0_1 : OUT STD_LOGIC;
99 ready_matrix_f1 : OUT STD_LOGIC;
99 ready_matrix_f1 : OUT STD_LOGIC;
100 ready_matrix_f2 : OUT STD_LOGIC;
100 ready_matrix_f2 : OUT STD_LOGIC;
101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
101 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
102 error_bad_component_error : OUT STD_LOGIC;
102 error_bad_component_error : OUT STD_LOGIC;
103 error_buffer_full : OUT STD_LOGIC;
103 error_buffer_full : OUT STD_LOGIC;
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
104 error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
105 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 --
107 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
108 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
109 -------------------------------------------------------------------------
106 status_ready_matrix_f0 : IN STD_LOGIC;
110 status_ready_matrix_f0 : IN STD_LOGIC;
107 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
111 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
108 status_ready_matrix_f1 : IN STD_LOGIC;
112 status_ready_matrix_f1 : IN STD_LOGIC;
109 status_ready_matrix_f2 : IN STD_LOGIC;
113 status_ready_matrix_f2 : IN STD_LOGIC;
110 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
114 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
111 -- status_error_bad_component_error : IN STD_LOGIC;
115 -- status_error_bad_component_error : IN STD_LOGIC;
112 config_active_interruption_onNewMatrix : IN STD_LOGIC;
116 config_active_interruption_onNewMatrix : IN STD_LOGIC;
113 config_active_interruption_onError : IN STD_LOGIC;
117 config_active_interruption_onError : IN STD_LOGIC;
114 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
118 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
115 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
119 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
116 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
117 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
118
122
119 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
123 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
120 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
124 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
121 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
125 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
122 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
126 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
123 END COMPONENT;
127 END COMPONENT;
124
128
125 COMPONENT lpp_lfr_ms_fsmdma
129 COMPONENT lpp_lfr_ms_fsmdma
126 PORT (
130 PORT (
127 HCLK : IN STD_ULOGIC;
131 HCLK : IN STD_ULOGIC;
128 HRESETn : IN STD_ULOGIC;
132 HRESETn : IN STD_ULOGIC;
129 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
133 fifo_matrix_type : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
130 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 fifo_matrix_component : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
131 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
135 fifo_matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
132 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 fifo_empty : IN STD_LOGIC;
137 fifo_empty : IN STD_LOGIC;
134 fifo_ren : OUT STD_LOGIC;
138 fifo_ren : OUT STD_LOGIC;
135 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
139 --data_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
136 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 --fifo_data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 --fifo_empty : IN STD_LOGIC;
141 --fifo_empty : IN STD_LOGIC;
138 --fifo_ren : OUT STD_LOGIC;
142 --fifo_ren : OUT STD_LOGIC;
139 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
143 --header : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 --header_val : IN STD_LOGIC;
144 --header_val : IN STD_LOGIC;
141 --header_ack : OUT STD_LOGIC;
145 --header_ack : OUT STD_LOGIC;
142 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
146 dma_addr : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
143 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
147 dma_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
144 dma_valid : OUT STD_LOGIC;
148 dma_valid : OUT STD_LOGIC;
145 dma_valid_burst : OUT STD_LOGIC;
149 dma_valid_burst : OUT STD_LOGIC;
146 dma_ren : IN STD_LOGIC;
150 dma_ren : IN STD_LOGIC;
147 dma_done : IN STD_LOGIC;
151 dma_done : IN STD_LOGIC;
148 ready_matrix_f0 : OUT STD_LOGIC;
152 ready_matrix_f0 : OUT STD_LOGIC;
149 -- ready_matrix_f0_1 : OUT STD_LOGIC;
153 -- ready_matrix_f0_1 : OUT STD_LOGIC;
150 ready_matrix_f1 : OUT STD_LOGIC;
154 ready_matrix_f1 : OUT STD_LOGIC;
151 ready_matrix_f2 : OUT STD_LOGIC;
155 ready_matrix_f2 : OUT STD_LOGIC;
152 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
156 -- error_anticipating_empty_fifo : OUT STD_LOGIC;
153 error_bad_component_error : OUT STD_LOGIC;
157 error_bad_component_error : OUT STD_LOGIC;
154 error_buffer_full : OUT STD_LOGIC;
158 error_buffer_full : OUT STD_LOGIC;
155 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
159 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 status_ready_matrix_f0 : IN STD_LOGIC;
160 status_ready_matrix_f0 : IN STD_LOGIC;
157 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
161 -- status_ready_matrix_f0_1 : IN STD_LOGIC;
158 status_ready_matrix_f1 : IN STD_LOGIC;
162 status_ready_matrix_f1 : IN STD_LOGIC;
159 status_ready_matrix_f2 : IN STD_LOGIC;
163 status_ready_matrix_f2 : IN STD_LOGIC;
160 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
164 -- status_error_anticipating_empty_fifo : IN STD_LOGIC;
161 -- status_error_bad_component_error : IN STD_LOGIC;
165 -- status_error_bad_component_error : IN STD_LOGIC;
162 config_active_interruption_onNewMatrix : IN STD_LOGIC;
166 config_active_interruption_onNewMatrix : IN STD_LOGIC;
163 config_active_interruption_onError : IN STD_LOGIC;
167 config_active_interruption_onError : IN STD_LOGIC;
164 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
168 addr_matrix_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
165 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
169 -- addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
166 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
167 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
171 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
168
172
169 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
173 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
170 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
174 -- matrix_time_f0_1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
171 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
175 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
172 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
176 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)
173 );
177 );
174 END COMPONENT;
178 END COMPONENT;
175
179
176 COMPONENT lpp_lfr_ms_FFT
180 COMPONENT lpp_lfr_ms_FFT
177 PORT (
181 PORT (
178 clk : IN STD_LOGIC;
182 clk : IN STD_LOGIC;
179 rstn : IN STD_LOGIC;
183 rstn : IN STD_LOGIC;
180 sample_valid : IN STD_LOGIC;
184 sample_valid : IN STD_LOGIC;
181 fft_read : IN STD_LOGIC;
185 fft_read : IN STD_LOGIC;
182 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
186 sample_data : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
183 sample_load : OUT STD_LOGIC;
187 sample_load : OUT STD_LOGIC;
184 fft_pong : OUT STD_LOGIC;
188 fft_pong : OUT STD_LOGIC;
185 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
189 fft_data_im : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
186 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
190 fft_data_re : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
187 fft_data_valid : OUT STD_LOGIC;
191 fft_data_valid : OUT STD_LOGIC;
188 fft_ready : OUT STD_LOGIC);
192 fft_ready : OUT STD_LOGIC);
189 END COMPONENT;
193 END COMPONENT;
190
194
191 COMPONENT lpp_lfr_filter
195 COMPONENT lpp_lfr_filter
192 GENERIC (
196 GENERIC (
193 Mem_use : INTEGER);
197 Mem_use : INTEGER);
194 PORT (
198 PORT (
195 sample : IN Samples(7 DOWNTO 0);
199 sample : IN Samples(7 DOWNTO 0);
196 sample_val : IN STD_LOGIC;
200 sample_val : IN STD_LOGIC;
197 clk : IN STD_LOGIC;
201 clk : IN STD_LOGIC;
198 rstn : IN STD_LOGIC;
202 rstn : IN STD_LOGIC;
199 data_shaping_SP0 : IN STD_LOGIC;
203 data_shaping_SP0 : IN STD_LOGIC;
200 data_shaping_SP1 : IN STD_LOGIC;
204 data_shaping_SP1 : IN STD_LOGIC;
201 data_shaping_R0 : IN STD_LOGIC;
205 data_shaping_R0 : IN STD_LOGIC;
202 data_shaping_R1 : IN STD_LOGIC;
206 data_shaping_R1 : IN STD_LOGIC;
203 sample_f0_val : OUT STD_LOGIC;
207 sample_f0_val : OUT STD_LOGIC;
204 sample_f1_val : OUT STD_LOGIC;
208 sample_f1_val : OUT STD_LOGIC;
205 sample_f2_val : OUT STD_LOGIC;
209 sample_f2_val : OUT STD_LOGIC;
206 sample_f3_val : OUT STD_LOGIC;
210 sample_f3_val : OUT STD_LOGIC;
207 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
211 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
208 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
212 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
209 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
213 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
210 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
214 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
211 END COMPONENT;
215 END COMPONENT;
212
216
213 COMPONENT lpp_lfr
217 COMPONENT lpp_lfr
214 GENERIC (
218 GENERIC (
215 Mem_use : INTEGER;
219 Mem_use : INTEGER;
216 nb_data_by_buffer_size : INTEGER;
220 nb_data_by_buffer_size : INTEGER;
217 nb_word_by_buffer_size : INTEGER;
221 nb_word_by_buffer_size : INTEGER;
218 nb_snapshot_param_size : INTEGER;
222 nb_snapshot_param_size : INTEGER;
219 delta_vector_size : INTEGER;
223 delta_vector_size : INTEGER;
220 delta_vector_size_f0_2 : INTEGER;
224 delta_vector_size_f0_2 : INTEGER;
221 pindex : INTEGER;
225 pindex : INTEGER;
222 paddr : INTEGER;
226 paddr : INTEGER;
223 pmask : INTEGER;
227 pmask : INTEGER;
224 pirq_ms : INTEGER;
228 pirq_ms : INTEGER;
225 pirq_wfp : INTEGER;
229 pirq_wfp : INTEGER;
226 hindex : INTEGER;
230 hindex : INTEGER;
227 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
231 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0)
228 );
232 );
229 PORT (
233 PORT (
230 clk : IN STD_LOGIC;
234 clk : IN STD_LOGIC;
231 rstn : IN STD_LOGIC;
235 rstn : IN STD_LOGIC;
232 sample_B : IN Samples(2 DOWNTO 0);
236 sample_B : IN Samples(2 DOWNTO 0);
233 sample_E : IN Samples(4 DOWNTO 0);
237 sample_E : IN Samples(4 DOWNTO 0);
234 sample_val : IN STD_LOGIC;
238 sample_val : IN STD_LOGIC;
235 apbi : IN apb_slv_in_type;
239 apbi : IN apb_slv_in_type;
236 apbo : OUT apb_slv_out_type;
240 apbo : OUT apb_slv_out_type;
237 ahbi : IN AHB_Mst_In_Type;
241 ahbi : IN AHB_Mst_In_Type;
238 ahbo : OUT AHB_Mst_Out_Type;
242 ahbo : OUT AHB_Mst_Out_Type;
239 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
243 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
240 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
244 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
241 data_shaping_BW : OUT STD_LOGIC;
245 data_shaping_BW : OUT STD_LOGIC;
246 --
247 observation_vector_0: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
248 observation_vector_1: OUT STD_LOGIC_VECTOR(11 DOWNTO 0);
242 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
249 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
243 );
250 );
244 END COMPONENT;
251 END COMPONENT;
245
252
246 -----------------------------------------------------------------------------
253 -----------------------------------------------------------------------------
247 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
254 -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
248 -----------------------------------------------------------------------------
255 -----------------------------------------------------------------------------
249 COMPONENT lpp_lfr_WFP_nMS
256 COMPONENT lpp_lfr_WFP_nMS
250 GENERIC (
257 GENERIC (
251 Mem_use : INTEGER;
258 Mem_use : INTEGER;
252 nb_data_by_buffer_size : INTEGER;
259 nb_data_by_buffer_size : INTEGER;
253 nb_word_by_buffer_size : INTEGER;
260 nb_word_by_buffer_size : INTEGER;
254 nb_snapshot_param_size : INTEGER;
261 nb_snapshot_param_size : INTEGER;
255 delta_vector_size : INTEGER;
262 delta_vector_size : INTEGER;
256 delta_vector_size_f0_2 : INTEGER;
263 delta_vector_size_f0_2 : INTEGER;
257 pindex : INTEGER;
264 pindex : INTEGER;
258 paddr : INTEGER;
265 paddr : INTEGER;
259 pmask : INTEGER;
266 pmask : INTEGER;
260 pirq_ms : INTEGER;
267 pirq_ms : INTEGER;
261 pirq_wfp : INTEGER;
268 pirq_wfp : INTEGER;
262 hindex : INTEGER;
269 hindex : INTEGER;
263 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
270 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
264 PORT (
271 PORT (
265 clk : IN STD_LOGIC;
272 clk : IN STD_LOGIC;
266 rstn : IN STD_LOGIC;
273 rstn : IN STD_LOGIC;
267 sample_B : IN Samples(2 DOWNTO 0);
274 sample_B : IN Samples(2 DOWNTO 0);
268 sample_E : IN Samples(4 DOWNTO 0);
275 sample_E : IN Samples(4 DOWNTO 0);
269 sample_val : IN STD_LOGIC;
276 sample_val : IN STD_LOGIC;
270 apbi : IN apb_slv_in_type;
277 apbi : IN apb_slv_in_type;
271 apbo : OUT apb_slv_out_type;
278 apbo : OUT apb_slv_out_type;
272 ahbi : IN AHB_Mst_In_Type;
279 ahbi : IN AHB_Mst_In_Type;
273 ahbo : OUT AHB_Mst_Out_Type;
280 ahbo : OUT AHB_Mst_Out_Type;
274 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
281 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
275 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
282 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
276 data_shaping_BW : OUT STD_LOGIC;
283 data_shaping_BW : OUT STD_LOGIC;
277 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
284 observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
278 END COMPONENT;
285 END COMPONENT;
279 -----------------------------------------------------------------------------
286 -----------------------------------------------------------------------------
280 COMPONENT lpp_lfr_apbreg
287 COMPONENT lpp_lfr_apbreg
281 GENERIC (
288 GENERIC (
282 nb_data_by_buffer_size : INTEGER;
289 nb_data_by_buffer_size : INTEGER;
283 nb_word_by_buffer_size : INTEGER;
290 nb_word_by_buffer_size : INTEGER;
284 nb_snapshot_param_size : INTEGER;
291 nb_snapshot_param_size : INTEGER;
285 delta_vector_size : INTEGER;
292 delta_vector_size : INTEGER;
286 delta_vector_size_f0_2 : INTEGER;
293 delta_vector_size_f0_2 : INTEGER;
287 pindex : INTEGER;
294 pindex : INTEGER;
288 paddr : INTEGER;
295 paddr : INTEGER;
289 pmask : INTEGER;
296 pmask : INTEGER;
290 pirq_ms : INTEGER;
297 pirq_ms : INTEGER;
291 pirq_wfp : INTEGER;
298 pirq_wfp : INTEGER;
292 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
299 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0));
293 PORT (
300 PORT (
294 HCLK : IN STD_ULOGIC;
301 HCLK : IN STD_ULOGIC;
295 HRESETn : IN STD_ULOGIC;
302 HRESETn : IN STD_ULOGIC;
296 apbi : IN apb_slv_in_type;
303 apbi : IN apb_slv_in_type;
297 apbo : OUT apb_slv_out_type;
304 apbo : OUT apb_slv_out_type;
298 run_ms : OUT STD_LOGIC;
305 run_ms : OUT STD_LOGIC;
299 ready_matrix_f0 : IN STD_LOGIC;
306 ready_matrix_f0 : IN STD_LOGIC;
300 ready_matrix_f1 : IN STD_LOGIC;
307 ready_matrix_f1 : IN STD_LOGIC;
301 ready_matrix_f2 : IN STD_LOGIC;
308 ready_matrix_f2 : IN STD_LOGIC;
302 error_bad_component_error : IN STD_LOGIC;
309 error_bad_component_error : IN STD_LOGIC;
303 error_buffer_full : in STD_LOGIC;
310 error_buffer_full : in STD_LOGIC;
304 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
311 error_input_fifo_write : in STD_LOGIC_VECTOR(2 DOWNTO 0);
305 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
312 --x debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
306 status_ready_matrix_f0 : OUT STD_LOGIC;
313 status_ready_matrix_f0 : OUT STD_LOGIC;
307 status_ready_matrix_f1 : OUT STD_LOGIC;
314 status_ready_matrix_f1 : OUT STD_LOGIC;
308 status_ready_matrix_f2 : OUT STD_LOGIC;
315 status_ready_matrix_f2 : OUT STD_LOGIC;
309 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
316 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
310 config_active_interruption_onError : OUT STD_LOGIC;
317 config_active_interruption_onError : OUT STD_LOGIC;
311 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
318 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
312 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
319 -- addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
313 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
320 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
315 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
322 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
316 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
323 -- matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
317 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
324 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
318 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
325 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
319 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
326 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
320 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
327 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
321 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
322 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
323 data_shaping_BW : OUT STD_LOGIC;
330 data_shaping_BW : OUT STD_LOGIC;
324 data_shaping_SP0 : OUT STD_LOGIC;
331 data_shaping_SP0 : OUT STD_LOGIC;
325 data_shaping_SP1 : OUT STD_LOGIC;
332 data_shaping_SP1 : OUT STD_LOGIC;
326 data_shaping_R0 : OUT STD_LOGIC;
333 data_shaping_R0 : OUT STD_LOGIC;
327 data_shaping_R1 : OUT STD_LOGIC;
334 data_shaping_R1 : OUT STD_LOGIC;
328 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
335 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
329 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
336 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
330 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
337 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
331 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
338 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
332 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
339 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
333 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
340 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
334 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
341 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
335 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
342 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
336 enable_f0 : OUT STD_LOGIC;
343 enable_f0 : OUT STD_LOGIC;
337 enable_f1 : OUT STD_LOGIC;
344 enable_f1 : OUT STD_LOGIC;
338 enable_f2 : OUT STD_LOGIC;
345 enable_f2 : OUT STD_LOGIC;
339 enable_f3 : OUT STD_LOGIC;
346 enable_f3 : OUT STD_LOGIC;
340 burst_f0 : OUT STD_LOGIC;
347 burst_f0 : OUT STD_LOGIC;
341 burst_f1 : OUT STD_LOGIC;
348 burst_f1 : OUT STD_LOGIC;
342 burst_f2 : OUT STD_LOGIC;
349 burst_f2 : OUT STD_LOGIC;
343 run : OUT STD_LOGIC;
350 run : OUT STD_LOGIC;
344 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
351 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
345 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
346 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
347 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
354 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
348 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
355 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
356
357 debug_signal : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
358
349 );
359 );
350 END COMPONENT;
360 END COMPONENT;
351
361
352
362
353
363
354 COMPONENT lpp_top_ms
364 COMPONENT lpp_top_ms
355 GENERIC (
365 GENERIC (
356 Mem_use : INTEGER;
366 Mem_use : INTEGER;
357 nb_burst_available_size : INTEGER;
367 nb_burst_available_size : INTEGER;
358 nb_snapshot_param_size : INTEGER;
368 nb_snapshot_param_size : INTEGER;
359 delta_snapshot_size : INTEGER;
369 delta_snapshot_size : INTEGER;
360 delta_f2_f0_size : INTEGER;
370 delta_f2_f0_size : INTEGER;
361 delta_f2_f1_size : INTEGER;
371 delta_f2_f1_size : INTEGER;
362 pindex : INTEGER;
372 pindex : INTEGER;
363 paddr : INTEGER;
373 paddr : INTEGER;
364 pmask : INTEGER;
374 pmask : INTEGER;
365 pirq_ms : INTEGER;
375 pirq_ms : INTEGER;
366 pirq_wfp : INTEGER;
376 pirq_wfp : INTEGER;
367 hindex_wfp : INTEGER;
377 hindex_wfp : INTEGER;
368 hindex_ms : INTEGER);
378 hindex_ms : INTEGER);
369 PORT (
379 PORT (
370 clk : IN STD_LOGIC;
380 clk : IN STD_LOGIC;
371 rstn : IN STD_LOGIC;
381 rstn : IN STD_LOGIC;
372 sample_B : IN Samples14v(2 DOWNTO 0);
382 sample_B : IN Samples14v(2 DOWNTO 0);
373 sample_E : IN Samples14v(4 DOWNTO 0);
383 sample_E : IN Samples14v(4 DOWNTO 0);
374 sample_val : IN STD_LOGIC;
384 sample_val : IN STD_LOGIC;
375 apbi : IN apb_slv_in_type;
385 apbi : IN apb_slv_in_type;
376 apbo : OUT apb_slv_out_type;
386 apbo : OUT apb_slv_out_type;
377 ahbi_ms : IN AHB_Mst_In_Type;
387 ahbi_ms : IN AHB_Mst_In_Type;
378 ahbo_ms : OUT AHB_Mst_Out_Type;
388 ahbo_ms : OUT AHB_Mst_Out_Type;
379 data_shaping_BW : OUT STD_LOGIC;
389 data_shaping_BW : OUT STD_LOGIC;
380 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
390 matrix_time_f0_0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
381 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
391 matrix_time_f0_1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
382 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
392 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
383 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
393 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
384
394
385 );
395 );
386 END COMPONENT;
396 END COMPONENT;
387
397
388 COMPONENT lpp_apbreg_ms_pointer
398 COMPONENT lpp_apbreg_ms_pointer
389 PORT (
399 PORT (
390 clk : IN STD_LOGIC;
400 clk : IN STD_LOGIC;
391 rstn : IN STD_LOGIC;
401 rstn : IN STD_LOGIC;
392 reg0_status_ready_matrix : IN STD_LOGIC;
402 reg0_status_ready_matrix : IN STD_LOGIC;
393 reg0_ready_matrix : OUT STD_LOGIC;
403 reg0_ready_matrix : OUT STD_LOGIC;
394 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
404 reg0_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
395 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
405 reg0_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
396 reg1_status_ready_matrix : IN STD_LOGIC;
406 reg1_status_ready_matrix : IN STD_LOGIC;
397 reg1_ready_matrix : OUT STD_LOGIC;
407 reg1_ready_matrix : OUT STD_LOGIC;
398 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
408 reg1_addr_matrix : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
399 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
409 reg1_matrix_time : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
400 ready_matrix : IN STD_LOGIC;
410 ready_matrix : IN STD_LOGIC;
401 status_ready_matrix : OUT STD_LOGIC;
411 status_ready_matrix : OUT STD_LOGIC;
402 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
412 addr_matrix : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
403 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
413 matrix_time : IN STD_LOGIC_VECTOR(47 DOWNTO 0));
404 END COMPONENT;
414 END COMPONENT;
405
415
406 END lpp_lfr_pkg;
416 END lpp_lfr_pkg;
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