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Update SDC for the MINI-LFR boards
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r560:8e5e2afea36a JC
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1 1 # Synplicity, Inc. constraint file
2 2 # /home/jiri/ibm/vhdl/grlib/boards/actel-coremp7-1000/default.sdc
3 3 # Written on Wed Aug 1 19:29:24 2007
4 4 # by Synplify Pro, Synplify Pro 8.8.0.4 Scope Editor
5 5
6 6 #
7 7 # Collections
8 8 #
9 9
10 10 #
11 11 # Clocks
12 12 #
13 13
14 14
15 define_clock {clk_50} -name {clk_50} -freq 100 -clockgroup default_clkgroup -route 5
16 define_clock {clk_49} -name {clk_49} -freq 49.152 -clockgroup default_clkgroup -route 5
15 define_clock -name {clk_50} -freq 100 -clockgroup default_clkgroup_50 -route 5
16 define_clock -name {clk_49} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
17 17
18 18 #
19 19 # Clock to Clock
20 20 #
21 21
22 22 #
23 23 # Inputs/Outputs
24 24 #
25 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
26 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
27 25
28 26
29 27 #
30 28 # Registers
31 29 #
32 30
33 31 #
34 32 # Multicycle Path
35 33 #
36 34
37 35 #
38 36 # False Path
39 37 #
38 set_false_path -from reset
40 39
41 40 #
42 41 # Path Delay
43 42 #
44 43
45 44 #
46 45 # Attributes
47 46 #
48 47 define_global_attribute syn_useioff {1}
49 48 define_global_attribute -disable syn_netlist_hierarchy {0}
50 define_attribute {etx_clk} syn_noclockbuf {1}
51 49
52 50 #
53 51 # I/O standards
54 52 #
55 53
56 54 #
57 55 # Compile Points
58 56 #
59 57
60 58 #
61 59 # Other Constraints
62 60 #
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 SIGNAL clk_24 : STD_LOGIC := '0';
119 119 -----------------------------------------------------------------------------
120 120 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 121 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
122 122 --
123 123 SIGNAL errorn : STD_LOGIC;
124 124 -- UART AHB ---------------------------------------------------------------
125 125 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
126 126 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
127 127
128 128 -- UART APB ---------------------------------------------------------------
129 129 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
130 130 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
131 131 --
132 132 SIGNAL I00_s : STD_LOGIC;
133 133
134 134 -- CONSTANTS
135 135 CONSTANT CFG_PADTECH : INTEGER := inferred;
136 136 --
137 137 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
138 138 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
139 139 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
140 140
141 141 SIGNAL apbi_ext : apb_slv_in_type;
142 142 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
143 143 SIGNAL ahbi_s_ext : ahb_slv_in_type;
144 144 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
145 145 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
146 146 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
147 147
148 148 -- Spacewire signals
149 149 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
150 150 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
151 151 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
152 152 SIGNAL spw_rxtxclk : STD_ULOGIC;
153 153 SIGNAL spw_rxclkn : STD_ULOGIC;
154 154 SIGNAL spw_clk : STD_LOGIC;
155 155 SIGNAL swni : grspw_in_type;
156 156 SIGNAL swno : grspw_out_type;
157 157 -- SIGNAL clkmn : STD_ULOGIC;
158 158 -- SIGNAL txclk : STD_ULOGIC;
159 159
160 160 --GPIO
161 161 SIGNAL gpioi : gpio_in_type;
162 162 SIGNAL gpioo : gpio_out_type;
163 163
164 164 -- AD Converter ADS7886
165 165 SIGNAL sample : Samples14v(7 DOWNTO 0);
166 166 SIGNAL sample_s : Samples(7 DOWNTO 0);
167 167 SIGNAL sample_val : STD_LOGIC;
168 168 SIGNAL ADC_nCS_sig : STD_LOGIC;
169 169 SIGNAL ADC_CLK_sig : STD_LOGIC;
170 170 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
171 171
172 172 SIGNAL bias_fail_sw_sig : STD_LOGIC;
173 173
174 174 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 175 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
176 176 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
177 177 -----------------------------------------------------------------------------
178 178
179 179 SIGNAL LFR_soft_rstn : STD_LOGIC;
180 180 SIGNAL LFR_rstn : STD_LOGIC;
181 181
182 182
183 183 SIGNAL rstn_25 : STD_LOGIC;
184 184 SIGNAL rstn_25_d1 : STD_LOGIC;
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 SIGNAL rstn_24 : STD_LOGIC;
189 SIGNAL rstn_24_d1 : STD_LOGIC;
190 SIGNAL rstn_24_d2 : STD_LOGIC;
191 SIGNAL rstn_24_d3 : STD_LOGIC;
192
188 193 SIGNAL rstn_50 : STD_LOGIC;
189 194 SIGNAL rstn_50_d1 : STD_LOGIC;
190 195 SIGNAL rstn_50_d2 : STD_LOGIC;
191 196 SIGNAL rstn_50_d3 : STD_LOGIC;
192 197
193 198 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
194 199 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
195 200
196 201 --
197 202 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
198 203
199 204 --
200 205 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
206 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 207
203 208 BEGIN -- beh
204 209
205 210 -----------------------------------------------------------------------------
206 211 -- CLK
207 212 -----------------------------------------------------------------------------
208 213
209 214 --PROCESS(clk_50)
210 215 --BEGIN
211 216 -- IF clk_50'EVENT AND clk_50 = '1' THEN
212 217 -- clk_50_s <= NOT clk_50_s;
213 218 -- END IF;
214 219 --END PROCESS;
215 220
216 221 --PROCESS(clk_50_s)
217 222 --BEGIN
218 223 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
219 224 -- clk_25 <= NOT clk_25;
220 225 -- END IF;
221 226 --END PROCESS;
222 227
223 228 --PROCESS(clk_49)
224 229 --BEGIN
225 230 -- IF clk_49'EVENT AND clk_49 = '1' THEN
226 231 -- clk_24 <= NOT clk_24;
227 232 -- END IF;
228 233 --END PROCESS;
229 234
230 235 --PROCESS(clk_25)
231 236 --BEGIN
232 237 -- IF clk_25'EVENT AND clk_25 = '1' THEN
233 238 -- rstn_25 <= reset;
234 239 -- END IF;
235 240 --END PROCESS;
236 241
237 242 PROCESS (clk_50, reset)
238 243 BEGIN -- PROCESS
239 244 IF reset = '0' THEN -- asynchronous reset (active low)
240 245 clk_50_s <= '0';
241 246 rstn_50 <= '0';
242 247 rstn_50_d1 <= '0';
243 248 rstn_50_d2 <= '0';
244 249 rstn_50_d3 <= '0';
245 250
246 251 ELSIF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
247 252 clk_50_s <= NOT clk_50_s;
248 253 rstn_50_d1 <= '1';
249 254 rstn_50_d2 <= rstn_50_d1;
250 255 rstn_50_d3 <= rstn_50_d2;
251 256 rstn_50 <= rstn_50_d3;
252 257 END IF;
253 258 END PROCESS;
254 259
255 260 PROCESS (clk_50_s, rstn_50)
256 261 BEGIN -- PROCESS
257 262 IF rstn_50 = '0' THEN -- asynchronous reset (active low)
258 263 clk_25 <= '0';
259 264 rstn_25 <= '0';
260 265 rstn_25_d1 <= '0';
261 266 rstn_25_d2 <= '0';
262 267 rstn_25_d3 <= '0';
263 268 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
264 269 clk_25 <= NOT clk_25;
265 270 rstn_25_d1 <= '1';
266 271 rstn_25_d2 <= rstn_25_d1;
267 272 rstn_25_d3 <= rstn_25_d2;
268 273 rstn_25 <= rstn_25_d3;
269 274 END IF;
270 275 END PROCESS;
271 276
272 277 PROCESS (clk_49, reset)
273 278 BEGIN -- PROCESS
274 279 IF reset = '0' THEN -- asynchronous reset (active low)
275 clk_24 <= '0';
280 clk_24 <= '0';
281 rstn_24_d1 <= '0';
282 rstn_24_d2 <= '0';
283 rstn_24_d3 <= '0';
284 rstn_24 <= '0';
276 285 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 clk_24 <= NOT clk_24;
286 clk_24 <= NOT clk_24;
287 rstn_24_d1 <= '1';
288 rstn_24_d2 <= rstn_24_d1;
289 rstn_24_d3 <= rstn_24_d2;
290 rstn_24 <= rstn_24_d3;
278 291 END IF;
279 292 END PROCESS;
280 293
281 294 -----------------------------------------------------------------------------
282 295
283 296 PROCESS (clk_25, rstn_25)
284 297 BEGIN -- PROCESS
285 298 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
286 299 LED0 <= '0';
287 300 LED1 <= '0';
288 301 LED2 <= '0';
289 302 --IO1 <= '0';
290 303 --IO2 <= '1';
291 304 --IO3 <= '0';
292 305 --IO4 <= '0';
293 306 --IO5 <= '0';
294 307 --IO6 <= '0';
295 308 --IO7 <= '0';
296 309 --IO8 <= '0';
297 310 --IO9 <= '0';
298 311 --IO10 <= '0';
299 312 --IO11 <= '0';
300 313 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
301 314 LED0 <= '0';
302 315 LED1 <= '1';
303 316 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
304 317 --IO1 <= '1';
305 318 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
306 319 --IO3 <= ADC_SDO(0);
307 320 --IO4 <= ADC_SDO(1);
308 321 --IO5 <= ADC_SDO(2);
309 322 --IO6 <= ADC_SDO(3);
310 323 --IO7 <= ADC_SDO(4);
311 324 --IO8 <= ADC_SDO(5);
312 325 --IO9 <= ADC_SDO(6);
313 326 --IO10 <= ADC_SDO(7);
314 327 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
315 328 END IF;
316 329 END PROCESS;
317 330
318 PROCESS (clk_24, rstn_25)
331 PROCESS (clk_24, rstn_24)
319 332 BEGIN -- PROCESS
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
333 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
321 334 I00_s <= '0';
322 335 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 336 I00_s <= NOT I00_s;
324 337 END IF;
325 338 END PROCESS;
326 339 -- IO0 <= I00_s;
327 340
328 341 --UARTs
329 342 nCTS1 <= '1';
330 343 nCTS2 <= '1';
331 344 nDCD2 <= '1';
332 345
333 346 --
334
347
335 348 leon3_soc_1 : leon3_soc
336 349 GENERIC MAP (
337 fabtech => apa3e,
338 memtech => apa3e,
339 padtech => inferred,
340 clktech => inferred,
341 disas => 0,
342 dbguart => 0,
343 pclow => 2,
344 clk_freq => 25000,
345 IS_RADHARD => 0,
346 NB_CPU => 1,
347 ENABLE_FPU => 1,
348 FPU_NETLIST => 0,
349 ENABLE_DSU => 1,
350 ENABLE_AHB_UART => 1,
351 ENABLE_APB_UART => 1,
352 ENABLE_IRQMP => 1,
353 ENABLE_GPT => 1,
354 NB_AHB_MASTER => NB_AHB_MASTER,
355 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 NB_APB_SLAVE => NB_APB_SLAVE,
357 ADDRESS_SIZE => 20,
350 fabtech => apa3e,
351 memtech => apa3e,
352 padtech => inferred,
353 clktech => inferred,
354 disas => 0,
355 dbguart => 0,
356 pclow => 2,
357 clk_freq => 25000,
358 IS_RADHARD => 0,
359 NB_CPU => 1,
360 ENABLE_FPU => 1,
361 FPU_NETLIST => 0,
362 ENABLE_DSU => 1,
363 ENABLE_AHB_UART => 1,
364 ENABLE_APB_UART => 1,
365 ENABLE_IRQMP => 1,
366 ENABLE_GPT => 1,
367 NB_AHB_MASTER => NB_AHB_MASTER,
368 NB_AHB_SLAVE => NB_AHB_SLAVE,
369 NB_APB_SLAVE => NB_APB_SLAVE,
370 ADDRESS_SIZE => 20,
358 371 USES_IAP_MEMCTRLR => 0)
359 372 PORT MAP (
360 clk => clk_25,
361 reset => rstn_25,
362 errorn => errorn,
363 ahbrxd => TXD1,
364 ahbtxd => RXD1,
365 urxd1 => TXD2,
366 utxd1 => RXD2,
367 address => SRAM_A,
368 data => SRAM_DQ,
369 nSRAM_BE0 => SRAM_nBE(0),
370 nSRAM_BE1 => SRAM_nBE(1),
371 nSRAM_BE2 => SRAM_nBE(2),
372 nSRAM_BE3 => SRAM_nBE(3),
373 nSRAM_WE => SRAM_nWE,
374 nSRAM_CE => SRAM_CE_s,
375 nSRAM_OE => SRAM_nOE,
373 clk => clk_25,
374 reset => rstn_25,
375 errorn => errorn,
376 ahbrxd => TXD1,
377 ahbtxd => RXD1,
378 urxd1 => TXD2,
379 utxd1 => RXD2,
380 address => SRAM_A,
381 data => SRAM_DQ,
382 nSRAM_BE0 => SRAM_nBE(0),
383 nSRAM_BE1 => SRAM_nBE(1),
384 nSRAM_BE2 => SRAM_nBE(2),
385 nSRAM_BE3 => SRAM_nBE(3),
386 nSRAM_WE => SRAM_nWE,
387 nSRAM_CE => SRAM_CE_s,
388 nSRAM_OE => SRAM_nOE,
376 389 nSRAM_READY => '0',
377 390 SRAM_MBE => OPEN,
378 apbi_ext => apbi_ext,
379 apbo_ext => apbo_ext,
380 ahbi_s_ext => ahbi_s_ext,
381 ahbo_s_ext => ahbo_s_ext,
382 ahbi_m_ext => ahbi_m_ext,
383 ahbo_m_ext => ahbo_m_ext);
391 apbi_ext => apbi_ext,
392 apbo_ext => apbo_ext,
393 ahbi_s_ext => ahbi_s_ext,
394 ahbo_s_ext => ahbo_s_ext,
395 ahbi_m_ext => ahbi_m_ext,
396 ahbo_m_ext => ahbo_m_ext);
384 397
385 398 SRAM_CE <= SRAM_CE_s(0);
386 399 -------------------------------------------------------------------------------
387 400 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
388 401 -------------------------------------------------------------------------------
389 402 apb_lfr_management_1 : apb_lfr_management
390 403 GENERIC MAP (
391 404 tech => apa3e,
392 405 pindex => 6,
393 406 paddr => 6,
394 407 pmask => 16#fff#,
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
408 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 409 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 410 PORT MAP (
398 clk25MHz => clk_25,
399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 resetn => rstn_25,
401 grspw_tick => swno.tickout,
402 apbi => apbi_ext,
403 apbo => apbo_ext(6),
404 HK_sample => sample_hk,
405 HK_val => sample_val,
406 HK_sel => HK_SEL,
407 DAC_SDO => OPEN,
408 DAC_SCK => OPEN,
409 DAC_SYNC => OPEN,
410 DAC_CAL_EN => OPEN,
411 coarse_time => coarse_time,
412 fine_time => fine_time,
413 LFR_soft_rstn => LFR_soft_rstn
411 clk25MHz => clk_25,
412 resetn_25MHz => rstn_25, -- TODO
413 clk24_576MHz => clk_24, -- 49.152MHz/2
414 resetn_24_576MHz => rstn_24, -- TODO
415 grspw_tick => swno.tickout,
416 apbi => apbi_ext,
417 apbo => apbo_ext(6),
418 HK_sample => sample_hk,
419 HK_val => sample_val,
420 HK_sel => HK_SEL,
421 DAC_SDO => OPEN,
422 DAC_SCK => OPEN,
423 DAC_SYNC => OPEN,
424 DAC_CAL_EN => OPEN,
425 coarse_time => coarse_time,
426 fine_time => fine_time,
427 LFR_soft_rstn => LFR_soft_rstn
414 428 );
415 429
416 430 -----------------------------------------------------------------------
417 431 --- SpaceWire --------------------------------------------------------
418 432 -----------------------------------------------------------------------
419 433
420 434 SPW_EN <= '1';
421 435
422 436 spw_clk <= clk_50_s;
423 437 spw_rxtxclk <= spw_clk;
424 438 spw_rxclkn <= NOT spw_rxtxclk;
425 439
426 440 -- PADS for SPW1
427 441 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
428 442 PORT MAP (SPW_NOM_DIN, dtmp(0));
429 443 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
430 444 PORT MAP (SPW_NOM_SIN, stmp(0));
431 445 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
432 446 PORT MAP (SPW_NOM_DOUT, swno.d(0));
433 447 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
434 448 PORT MAP (SPW_NOM_SOUT, swno.s(0));
435 449 -- PADS FOR SPW2
436 450 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
437 451 PORT MAP (SPW_RED_SIN, dtmp(1));
438 452 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
439 453 PORT MAP (SPW_RED_DIN, stmp(1));
440 454 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
441 455 PORT MAP (SPW_RED_DOUT, swno.d(1));
442 456 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
443 457 PORT MAP (SPW_RED_SOUT, swno.s(1));
444 458
445 459 -- GRSPW PHY
446 460 --spw1_input: if CFG_SPW_GRSPW = 1 generate
447 461 spw_inputloop : FOR j IN 0 TO 1 GENERATE
448 462 spw_phy0 : grspw_phy
449 463 GENERIC MAP(
450 464 tech => apa3e,
451 465 rxclkbuftype => 1,
452 466 scantest => 0)
453 467 PORT MAP(
454 468 rxrst => swno.rxrst,
455 469 di => dtmp(j),
456 470 si => stmp(j),
457 471 rxclko => spw_rxclk(j),
458 472 do => swni.d(j),
459 473 ndo => swni.nd(j*5+4 DOWNTO j*5),
460 474 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
461 475 END GENERATE spw_inputloop;
462 476
463 477 swni.rmapnodeaddr <= (OTHERS => '0');
464 478
465 479 -- SPW core
466 480 sw0 : grspwm GENERIC MAP(
467 481 tech => apa3e,
468 482 hindex => 1,
469 483 pindex => 5,
470 484 paddr => 5,
471 485 pirq => 11,
472 486 sysfreq => 25000, -- CPU_FREQ
473 487 rmap => 1,
474 488 rmapcrc => 1,
475 489 fifosize1 => 16,
476 490 fifosize2 => 16,
477 491 rxclkbuftype => 1,
478 492 rxunaligned => 0,
479 493 rmapbufs => 4,
480 494 ft => 0,
481 495 netlist => 0,
482 496 ports => 2,
483 497 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
484 498 memtech => apa3e,
485 499 destkey => 2,
486 500 spwcore => 1
487 501 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
488 502 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
489 503 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
490 504 )
491 505 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
492 506 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
493 507 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
494 508 swni, swno);
495 509
496 510 swni.tickin <= '0';
497 511 swni.rmapen <= '1';
498 512 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
499 513 swni.tickinraw <= '0';
500 514 swni.timein <= (OTHERS => '0');
501 515 swni.dcrstval <= (OTHERS => '0');
502 516 swni.timerrstval <= (OTHERS => '0');
503 517
504 518 -------------------------------------------------------------------------------
505 519 -- LFR ------------------------------------------------------------------------
506 520 -------------------------------------------------------------------------------
507 521
508 522
509 523 LFR_rstn <= LFR_soft_rstn AND rstn_25;
510 524 --LFR_rstn <= rstn_25;
511 525
512 526 lpp_lfr_1 : lpp_lfr
513 527 GENERIC MAP (
514 528 Mem_use => use_RAM,
515 529 nb_data_by_buffer_size => 32,
516 530 nb_snapshot_param_size => 32,
517 531 delta_vector_size => 32,
518 532 delta_vector_size_f0_2 => 7, -- log2(96)
519 533 pindex => 15,
520 534 paddr => 15,
521 535 pmask => 16#fff#,
522 536 pirq_ms => 6,
523 537 pirq_wfp => 14,
524 538 hindex => 2,
525 top_lfr_version => X"000143") -- aa.bb.cc version
539 top_lfr_version => X"000144") -- aa.bb.cc version
526 540 PORT MAP (
527 541 clk => clk_25,
528 542 rstn => LFR_rstn,
529 543 sample_B => sample_s(2 DOWNTO 0),
530 544 sample_E => sample_s(7 DOWNTO 3),
531 545 sample_val => sample_val,
532 546 apbi => apbi_ext,
533 547 apbo => apbo_ext(15),
534 548 ahbi => ahbi_m_ext,
535 549 ahbo => ahbo_m_ext(2),
536 550 coarse_time => coarse_time,
537 551 fine_time => fine_time,
538 552 data_shaping_BW => bias_fail_sw_sig,
539 553 debug_vector => lfr_debug_vector,
540 554 debug_vector_ms => lfr_debug_vector_ms
541 555 );
542 556
543 557 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
544 558 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
545 559 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
546 560 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
547 561 IO0 <= rstn_25;
548 562 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
549 563 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
550 564 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
551 565 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
552 566 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
553 567 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
554 568 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
555 569
556 570 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
557 571 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
558 572 END GENERATE all_sample;
559 573
560 574 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
561 575 GENERIC MAP(
562 576 ChannelCount => 8,
563 577 SampleNbBits => 14,
564 578 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
565 579 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
566 580 PORT MAP (
567 581 -- CONV
568 582 cnv_clk => clk_24,
569 cnv_rstn => rstn_25,
583 cnv_rstn => rstn_24,
570 584 cnv => ADC_nCS_sig,
571 585 -- DATA
572 586 clk => clk_25,
573 587 rstn => rstn_25,
574 588 sck => ADC_CLK_sig,
575 589 sdo => ADC_SDO_sig,
576 590 -- SAMPLE
577 591 sample => sample,
578 592 sample_val => sample_val);
579 593
580 594 --IO10 <= ADC_SDO_sig(5);
581 595 --IO9 <= ADC_SDO_sig(4);
582 596 --IO8 <= ADC_SDO_sig(3);
583 597
584 598 ADC_nCS <= ADC_nCS_sig;
585 599 ADC_CLK <= ADC_CLK_sig;
586 600 ADC_SDO_sig <= ADC_SDO;
587 601
588 602 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
589 603 "0010001000100010" WHEN HK_SEL = "01" ELSE
590 604 "0100010001000100" WHEN HK_SEL = "10" ELSE
591 605 (OTHERS => '0');
592
606
593 607
594 608 ----------------------------------------------------------------------
595 609 --- GPIO -----------------------------------------------------------
596 610 ----------------------------------------------------------------------
597 611
598 612 grgpio0 : grgpio
599 613 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
600 614 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
601 615
602 616 gpioi.sig_en <= (OTHERS => '0');
603 617 gpioi.sig_in <= (OTHERS => '0');
604 618 gpioi.din <= (OTHERS => '0');
605 619 --pio_pad_0 : iopad
606 620 -- GENERIC MAP (tech => CFG_PADTECH)
607 621 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
608 622 --pio_pad_1 : iopad
609 623 -- GENERIC MAP (tech => CFG_PADTECH)
610 624 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
611 625 --pio_pad_2 : iopad
612 626 -- GENERIC MAP (tech => CFG_PADTECH)
613 627 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
614 628 --pio_pad_3 : iopad
615 629 -- GENERIC MAP (tech => CFG_PADTECH)
616 630 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
617 631 --pio_pad_4 : iopad
618 632 -- GENERIC MAP (tech => CFG_PADTECH)
619 633 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
620 634 --pio_pad_5 : iopad
621 635 -- GENERIC MAP (tech => CFG_PADTECH)
622 636 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
623 637 --pio_pad_6 : iopad
624 638 -- GENERIC MAP (tech => CFG_PADTECH)
625 639 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
626 640 --pio_pad_7 : iopad
627 641 -- GENERIC MAP (tech => CFG_PADTECH)
628 642 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
629 643
630 644 PROCESS (clk_25, rstn_25)
631 645 BEGIN -- PROCESS
632 646 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
633 647 -- --IO0 <= '0';
634 648 -- IO1 <= '0';
635 649 -- IO2 <= '0';
636 650 -- IO3 <= '0';
637 651 -- IO4 <= '0';
638 652 -- IO5 <= '0';
639 653 -- IO6 <= '0';
640 654 -- IO7 <= '0';
641 655 IO8 <= '0';
642 656 IO9 <= '0';
643 657 IO10 <= '0';
644 658 IO11 <= '0';
645 659 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
646 660 CASE gpioo.dout(2 DOWNTO 0) IS
647 661 WHEN "011" =>
648 662 -- --IO0 <= observation_reg(0 );
649 663 -- IO1 <= observation_reg(1 );
650 664 -- IO2 <= observation_reg(2 );
651 665 -- IO3 <= observation_reg(3 );
652 666 -- IO4 <= observation_reg(4 );
653 667 -- IO5 <= observation_reg(5 );
654 668 -- IO6 <= observation_reg(6 );
655 669 -- IO7 <= observation_reg(7 );
656 670 IO8 <= observation_reg(8);
657 671 IO9 <= observation_reg(9);
658 672 IO10 <= observation_reg(10);
659 673 IO11 <= observation_reg(11);
660 674 WHEN "001" =>
661 675 -- --IO0 <= observation_reg(0 + 12);
662 676 -- IO1 <= observation_reg(1 + 12);
663 677 -- IO2 <= observation_reg(2 + 12);
664 678 -- IO3 <= observation_reg(3 + 12);
665 679 -- IO4 <= observation_reg(4 + 12);
666 680 -- IO5 <= observation_reg(5 + 12);
667 681 -- IO6 <= observation_reg(6 + 12);
668 682 -- IO7 <= observation_reg(7 + 12);
669 683 IO8 <= observation_reg(8 + 12);
670 684 IO9 <= observation_reg(9 + 12);
671 685 IO10 <= observation_reg(10 + 12);
672 686 IO11 <= observation_reg(11 + 12);
673 687 WHEN "010" =>
674 688 -- --IO0 <= observation_reg(0 + 12 + 12);
675 689 -- IO1 <= observation_reg(1 + 12 + 12);
676 690 -- IO2 <= observation_reg(2 + 12 + 12);
677 691 -- IO3 <= observation_reg(3 + 12 + 12);
678 692 -- IO4 <= observation_reg(4 + 12 + 12);
679 693 -- IO5 <= observation_reg(5 + 12 + 12);
680 694 -- IO6 <= observation_reg(6 + 12 + 12);
681 695 -- IO7 <= observation_reg(7 + 12 + 12);
682 696 IO8 <= '0';
683 697 IO9 <= '0';
684 698 IO10 <= '0';
685 699 IO11 <= '0';
686 700 WHEN "000" =>
687 701 -- --IO0 <= observation_vector_0(0 );
688 702 -- IO1 <= observation_vector_0(1 );
689 703 -- IO2 <= observation_vector_0(2 );
690 704 -- IO3 <= observation_vector_0(3 );
691 705 -- IO4 <= observation_vector_0(4 );
692 706 -- IO5 <= observation_vector_0(5 );
693 707 -- IO6 <= observation_vector_0(6 );
694 708 -- IO7 <= observation_vector_0(7 );
695 709 IO8 <= observation_vector_0(8);
696 710 IO9 <= observation_vector_0(9);
697 711 IO10 <= observation_vector_0(10);
698 712 IO11 <= observation_vector_0(11);
699 713 WHEN "100" =>
700 714 -- --IO0 <= observation_vector_1(0 );
701 715 -- IO1 <= observation_vector_1(1 );
702 716 -- IO2 <= observation_vector_1(2 );
703 717 -- IO3 <= observation_vector_1(3 );
704 718 -- IO4 <= observation_vector_1(4 );
705 719 -- IO5 <= observation_vector_1(5 );
706 720 -- IO6 <= observation_vector_1(6 );
707 721 -- IO7 <= observation_vector_1(7 );
708 722 IO8 <= observation_vector_1(8);
709 723 IO9 <= observation_vector_1(9);
710 724 IO10 <= observation_vector_1(10);
711 725 IO11 <= observation_vector_1(11);
712 726 WHEN OTHERS => NULL;
713 727 END CASE;
714 728
715 729 END IF;
716 730 END PROCESS;
717 731 -----------------------------------------------------------------------------
718 732 --
719 733 -----------------------------------------------------------------------------
720 734 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
721 735 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
722 736 apbo_ext(I) <= apb_none;
723 737 END GENERATE apbo_ext_not_used;
724 738 END GENERATE all_apbo_ext;
725 739
726 740
727 741 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
728 742 ahbo_s_ext(I) <= ahbs_none;
729 743 END GENERATE all_ahbo_ext;
730 744
731 745 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
732 746 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
733 747 ahbo_m_ext(I) <= ahbm_none;
734 748 END GENERATE ahbo_m_ext_not_used;
735 749 END GENERATE all_ahbo_m_ext;
736 750
737 751 END beh;
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@@ -1,52 +1,52
1 1 VHDLIB=../..
2 2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 4 TOP=MINI_LFR_top
5 5 BOARD=MINI-LFR
6 6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 10 EFFORT=high
11 11 XSTOPT=
12 12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 13 VHDLSYNFILES= MINI_LFR_top.vhd
14 14 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 21 CLEAN=soft-clean
22 22
23 23 TECHLIBS = proasic3e
24 24
25 25 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
26 26 tmtc openchip hynix ihp gleichmann micron usbhc
27 27
28 28 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
29 29 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
30 30 ./amba_lcd_16x2_ctrlr \
31 31 ./general_purpose/lpp_AMR \
32 32 ./general_purpose/lpp_balise \
33 33 ./general_purpose/lpp_delay \
34 34 ./lpp_bootloader \
35 35 ./lpp_uart \
36 36 ./lpp_usb \
37 37 ./dsp/lpp_fft_rtax \
38 38 ./lpp_sim/CY7C1061DV33 \
39 39
40 40 FILESKIP =i2cmst.vhd \
41 41 APB_MULTI_DIODE.vhd \
42 42 APB_SIMPLE_DIODE.vhd \
43 43 Top_MatrixSpec.vhd \
44 44 APB_FFT.vhd \
45 45 CoreFFT_simu.vhd \
46 46 lpp_lfr_apbreg_simu.vhd
47 47
48 48 include $(GRLIB)/bin/Makefile
49 49 include $(GRLIB)/software/leon3/Makefile
50 50
51 51 ################## project specific targets ##########################
52 52
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@@ -1,397 +1,393
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -- jean-christophe.pellion@easii-ic.com
22 22 ----------------------------------------------------------------------------
23 23
24 24 LIBRARY ieee;
25 25 USE ieee.std_logic_1164.ALL;
26 26 USE ieee.numeric_std.all;
27 27
28 28 LIBRARY lpp;
29 29 USE lpp.cic_pkg.ALL;
30 30 USE lpp.data_type_pkg.ALL;
31 31 USE lpp.iir_filter.ALL;
32 32
33 33 LIBRARY techmap;
34 34 USE techmap.gencomp.ALL;
35 35
36 36 ENTITY cic_lfr_r2 IS
37 37 GENERIC(
38 38 tech : INTEGER := 0;
39 39 use_RAM_nCEL : INTEGER := 0 -- 1 => RAM(tech) , 0 => RAM_CEL
40 40 );
41 41 PORT (
42 42 clk : IN STD_LOGIC;
43 43 rstn : IN STD_LOGIC;
44 44 run : IN STD_LOGIC;
45 45
46 46 param_r2 : IN STD_LOGIC;
47 47
48 48 data_in : IN sample_vector(7 DOWNTO 0,15 DOWNTO 0);
49 49 data_in_valid : IN STD_LOGIC;
50 50
51 51 data_out_16 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
52 52 data_out_16_valid : OUT STD_LOGIC;
53 53 data_out_256 : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
54 54 data_out_256_valid : OUT STD_LOGIC
55 55 );
56 56
57 57 END cic_lfr_r2;
58 58
59 59 ARCHITECTURE beh OF cic_lfr_r2 IS
60 60 --
61 61 SIGNAL sel_sample : STD_LOGIC_VECTOR(2 DOWNTO 0);
62 62 SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
63 63 SIGNAL sample : STD_LOGIC_VECTOR(15 DOWNTO 0);
64 64 --
65 65 SIGNAL sel_A : STD_LOGIC_VECTOR(1 DOWNTO 0);
66 66 SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
67 67 SIGNAL data_A : STD_LOGIC_VECTOR(15 DOWNTO 0);
68 68 --
69 69 SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
70 70 SIGNAL data_B : STD_LOGIC_VECTOR(15 DOWNTO 0);
71 71 SIGNAL data_B_reg : STD_LOGIC_VECTOR(15 DOWNTO 0);
72 72 SIGNAL data_out : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 73 SIGNAL data_in_Carry : STD_LOGIC;
74 74 SIGNAL data_out_Carry : STD_LOGIC;
75 75 --
76 76 CONSTANT S_parameter : INTEGER := 3;
77 77 SIGNAL carry_reg : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
78 78 --
79 79
80 80 SIGNAL OPERATION : STD_LOGIC_VECTOR(15 DOWNTO 0);
81 81 SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
82 82 SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
83 83
84 84 -----------------------------------------------------------------------------
85 85 TYPE ARRAY_OF_ADDR IS ARRAY (7 DOWNTO 0) OF STD_LOGIC_VECTOR(8 DOWNTO 0);
86 86 SIGNAL base_addr_INT : ARRAY_OF_ADDR;
87 87 CONSTANT base_addr_delta : INTEGER := 40;
88 88 SIGNAL addr_base_sel : STD_LOGIC_VECTOR(8 DOWNTO 0);
89 89 SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
90 90 SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
91 91 SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
92 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0);
93 92 SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
94 93 SIGNAL data_we: STD_LOGIC;
95 94 SIGNAL data_we_s: STD_LOGIC;
96 95 SIGNAL data_wen : STD_LOGIC;
97 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 96 -----------------------------------------------------------------------------
101 97 SIGNAL sample_out_reg16 : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
102 98 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
103 99 SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(8*2 DOWNTO 0);
104 100 SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
105 101 SIGNAL data_out_16_valid_s : STD_LOGIC;
106 102 SIGNAL data_out_256_valid_s : STD_LOGIC;
107 103 SIGNAL data_out_16_valid_s1 : STD_LOGIC;
108 104 SIGNAL data_out_256_valid_s1 : STD_LOGIC;
109 105 SIGNAL data_out_16_valid_s2 : STD_LOGIC;
110 106 SIGNAL data_out_256_valid_s2 : STD_LOGIC;
111 107 -----------------------------------------------------------------------------
112 108 SIGNAL sample_out_reg16_s : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
113 109 SIGNAL sample_out_reg256_s : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
114 110 -----------------------------------------------------------------------------
115 111
116 112
117 113 BEGIN
118 114
119 115
120 116 PROCESS (clk, rstn)
121 117 BEGIN -- PROCESS
122 118 IF rstn = '0' THEN -- asynchronous reset (active low)
123 119 data_B_reg <= (OTHERS => '0');
124 120 OPERATION_reg <= (OTHERS => '0');
125 121 OPERATION_reg2 <= (OTHERS => '0');
126 122 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
127 123 OPERATION_reg <= OPERATION;
128 124 OPERATION_reg2 <= OPERATION_reg;
129 125 data_B_reg <= data_B;
130 126 END IF;
131 127 END PROCESS;
132 128
133 129
134 130 -----------------------------------------------------------------------------
135 131 -- SEL_SAMPLE
136 132 -----------------------------------------------------------------------------
137 133 sel_sample <= OPERATION_reg(2 DOWNTO 0);
138 134
139 135 all_bit: FOR I IN 15 DOWNTO 0 GENERATE
140 136 sample_temp(0,I) <= data_in(0,I) WHEN sel_sample(0) = '0' ELSE data_in(1,I);
141 137 sample_temp(1,I) <= data_in(2,I) WHEN sel_sample(0) = '0' ELSE data_in(3,I);
142 138 sample_temp(2,I) <= data_in(4,I) WHEN sel_sample(0) = '0' ELSE data_in(5,I);
143 139 sample_temp(3,I) <= data_in(6,I) WHEN sel_sample(0) = '0' ELSE data_in(7,I);
144 140
145 141 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
146 142 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE sample_temp(3,I);
147 143
148 144 sample(I) <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
149 145 END GENERATE all_bit;
150 146
151 147 -----------------------------------------------------------------------------
152 148 -- SEL_DATA_IN_A
153 149 -----------------------------------------------------------------------------
154 150 sel_A <= OPERATION_reg(4 DOWNTO 3);
155 151
156 152 all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
157 153 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
158 154 data_A_temp(1,I) <= '0' WHEN sel_A(0) = '0' ELSE sample(15);
159 155 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
160 156 data_A(I) <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
161 157 END GENERATE all_data_mux_A;
162 158
163 159
164 160
165 161 -----------------------------------------------------------------------------
166 162 -- ALU
167 163 -----------------------------------------------------------------------------
168 164 ALU_OP <= OPERATION_reg(6 DOWNTO 5);
169 165
170 166 ALU: cic_lfr_add_sub
171 167 PORT MAP (
172 168 clk => clk,
173 169 rstn => rstn,
174 170 run => run,
175 171
176 172 OP => ALU_OP,
177 173
178 174 data_in_A => data_A,
179 175 data_in_B => data_B,
180 176 data_in_Carry => data_in_Carry,
181 177
182 178 data_out => data_out,
183 179 data_out_Carry => data_out_Carry);
184 180
185 181 -----------------------------------------------------------------------------
186 182 -- CARRY_MANAGER
187 183 -----------------------------------------------------------------------------
188 184 data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
189 185
190 186 -- CARRY_PUSH <= OPERATION_reg(7);
191 187 -- CARRY_POP <= OPERATION_reg(6);
192 188
193 189 PROCESS (clk, rstn)
194 190 BEGIN -- PROCESS
195 191 IF rstn = '0' THEN -- asynchronous reset (active low)
196 192 carry_reg <= (OTHERS => '0');
197 193 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
198 194 --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
199 195 carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
200 196 carry_reg(0) <= data_out_Carry;
201 197 --END IF;
202 198 END IF;
203 199 END PROCESS;
204 200
205 201 -----------------------------------------------------------------------------
206 202 -- MEMORY
207 203 -----------------------------------------------------------------------------
208 204 all_bit_base_ADDR: FOR J IN 8 DOWNTO 0 GENERATE
209 205 all_channel: FOR I IN 7 DOWNTO 0 GENERATE
210 206 base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
211 207 END GENERATE all_channel;
212 208 END GENERATE all_bit_base_ADDR;
213 209
214 210
215 211 addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
216 212
217 213 cic_lfr_address_gen_1: cic_lfr_address_gen
218 214 GENERIC MAP (
219 215 ADDR_SIZE => 9)
220 216 PORT MAP (
221 217 clk => clk,
222 218 rstn => rstn,
223 219 run => run,
224 220
225 221 addr_base => addr_base_sel,
226 222 addr_init => OPERATION(8),
227 223 addr_add_1 => OPERATION(9),
228 224 addr => addr_gen);
229 225
230 226
231 227 addr_read <= addr_gen WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
232 228 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,9)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
233 229 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,9)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
234 230 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,9)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
235 231 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+6,9)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
236 232 STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen ))+15,9));
237 233
238 234 PROCESS (clk, rstn)
239 235 BEGIN -- PROCESS
240 236 IF rstn = '0' THEN -- asynchronous reset (active low)
241 237 addr_write <= (OTHERS => '0');
242 238 data_we <= '0';
243 239 addr_write_s <= (OTHERS => '0');
244 240 data_we_s <= '0';
245 241 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
246 242 addr_write_s <= addr_read;
247 243 data_we_s <= OPERATION(13);
248 244 IF OPERATION_reg(15) = '0' THEN
249 245 addr_write <= addr_write_s;
250 246 ELSE
251 247 addr_write <= addr_read;
252 248 END IF;
253 249 data_we <= data_we_s;
254 250 END IF;
255 251 END PROCESS;
256 252
257 253 memCEL : IF use_RAM_nCEL = 0 GENERATE
258 254 data_wen <= NOT data_we;
259 255 RAMblk : RAM_CEL
260 256 GENERIC MAP(16, 9)
261 257 PORT MAP(
262 258 WD => data_out,
263 259 RD => data_B,
264 260 WEN => data_wen,
265 261 REN => '0',
266 262 WADDR => addr_write,
267 263 RADDR => addr_read,
268 264 RWCLK => clk,
269 265 RESET => rstn
270 266 ) ;
271 267 END GENERATE;
272 268
273 269 memRAM : IF use_RAM_nCEL = 1 GENERATE
274 270 SRAM : syncram_2p
275 271 GENERIC MAP(tech, 9, 16)
276 272 PORT MAP(clk, '1', addr_read, data_B,
277 273 clk, data_we, addr_write, data_out);
278 274 END GENERATE;
279 275
280 276 -----------------------------------------------------------------------------
281 277 -- CONTROL
282 278 -----------------------------------------------------------------------------
283 279 cic_lfr_control_1: cic_lfr_control_r2
284 280 PORT MAP (
285 281 clk => clk,
286 282 rstn => rstn,
287 283 run => run,
288 284 data_in_valid => data_in_valid,
289 285 data_out_16_valid => data_out_16_valid_s,
290 286 data_out_256_valid => data_out_256_valid_s,
291 287 OPERATION => OPERATION);
292 288
293 289 -----------------------------------------------------------------------------
294 290 PROCESS (clk, rstn)
295 291 BEGIN -- PROCESS
296 292 IF rstn = '0' THEN -- asynchronous reset (active low)
297 293 data_out_16_valid_s1 <= '0';
298 294 data_out_256_valid_s1 <= '0';
299 295 data_out_16_valid_s2 <= '0';
300 296 data_out_256_valid_s2 <= '0';
301 297 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
302 298 data_out_16_valid_s1 <= data_out_16_valid_s;
303 299 data_out_256_valid_s1 <= data_out_256_valid_s;
304 300 data_out_16_valid_s2 <= data_out_16_valid_s1;
305 301 data_out_256_valid_s2 <= data_out_256_valid_s1;
306 302 END IF;
307 303 END PROCESS;
308 304
309 305 PROCESS (clk, rstn)
310 306 BEGIN -- PROCESS
311 307 IF rstn = '0' THEN -- asynchronous reset (active low)
312 308 sample_valid_reg16 <= "00000" & "000000" & "000001";
313 309 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
314 310 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
315 311 IF run = '0' THEN
316 312 sample_valid_reg16 <= "00000" & "000000" & "000001";
317 313 sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
318 314 ELSE
319 315 IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(8*2) = '1' THEN
320 316 sample_valid_reg16 <= sample_valid_reg16(8*2-1 DOWNTO 0) & sample_valid_reg16(8*2);
321 317 END IF;
322 318 IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
323 319 sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
324 320 END IF;
325 321 END IF;
326 322 END IF;
327 323 END PROCESS;
328 324
329 325 data_out_16_valid <= sample_valid_reg16(8*2);
330 326 data_out_256_valid <= sample_valid_reg256(6*3);
331 327
332 328 -----------------------------------------------------------------------------
333 329
334 330 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
335 331 all_channel_out16: FOR I IN 8*2-1 DOWNTO 0 GENERATE
336 332 PROCESS (clk, rstn)
337 333 BEGIN -- PROCESS
338 334 IF rstn = '0' THEN -- asynchronous reset (active low)
339 335 sample_out_reg16(I,J) <= '0';
340 336 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
341 337 IF run = '0' THEN
342 338 sample_out_reg16(I,J) <= '0';
343 339 ELSE
344 340 IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
345 341 sample_out_reg16(I,J) <= data_out(J);
346 342 END IF;
347 343 END IF;
348 344 END IF;
349 345 END PROCESS;
350 346 END GENERATE all_channel_out16;
351 347
352 348 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
353 349 PROCESS (clk, rstn)
354 350 BEGIN -- PROCESS
355 351 IF rstn = '0' THEN -- asynchronous reset (active low)
356 352 sample_out_reg256(I,J) <= '0';
357 353 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
358 354 IF run = '0' THEN
359 355 sample_out_reg256(I,J) <= '0';
360 356 ELSE
361 357 IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
362 358 sample_out_reg256(I,J) <= data_out(J);
363 359 END IF;
364 360 END IF;
365 361 END IF;
366 362 END PROCESS;
367 363 END GENERATE all_channel_out256;
368 364 END GENERATE all_bits;
369 365
370 366
371 367 all_bits_16: FOR J IN 15 DOWNTO 0 GENERATE
372 368 all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
373 369 sample_out_reg16_s(0,J+(K*16)) <= sample_out_reg16(2*0+K,J);
374 370 sample_out_reg16_s(1,J+(K*16)) <= sample_out_reg16(2*1+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*6+K,J);
375 371 sample_out_reg16_s(2,J+(K*16)) <= sample_out_reg16(2*2+K,J) WHEN param_r2 = '1' ELSE sample_out_reg16(2*7+K,J);
376 372 sample_out_reg16_s(3,J+(K*16)) <= sample_out_reg16(2*3+K,J);
377 373 sample_out_reg16_s(4,J+(K*16)) <= sample_out_reg16(2*4+K,J);
378 374 sample_out_reg16_s(5,J+(K*16)) <= sample_out_reg16(2*5+K,J);
379 375 END GENERATE all_reg_16;
380 376 END GENERATE all_bits_16;
381 377
382 378 all_channel_out_256: FOR I IN 5 DOWNTO 0 GENERATE
383 379 all_bits_256: FOR J IN 15 DOWNTO 0 GENERATE
384 380 all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
385 381 sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
386 382 END GENERATE all_reg_256;
387 383 END GENERATE all_bits_256;
388 384 END GENERATE all_channel_out_256;
389 385
390 386 all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
391 387 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
392 388 data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
393 389 data_out_16(I,J) <= sample_out_reg16_s (I,J+16 -16+15);
394 390 END GENERATE all_bits;
395 391 END GENERATE all_channel_out_v;
396 392
397 END beh;
393 END beh; No newline at end of file
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
69 PORT (
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 PORT (
88 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 PORT (
110 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
127
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
152 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
165 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
184 SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
186 BEGIN
187
188 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
191 all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
201 END IF;
202 END IF;
203 END PROCESS;
204 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
206 all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
207 all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
208 sample_out_zero(I,J) <= '0';
209 END GENERATE all_bit;
210 END GENERATE all_channel_sample_out;
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 state_channel_selection <= IDLE;
216 CHANNEL_SEL <= '0';
217 sample_in_val <= '0';
218 sample_out1_val <= '0';
219 sample_out2_val <= '0';
220 sample_out1 <= sample_out_zero;
221 sample_out2 <= sample_out_zero;
222 channel_done <= "00";
223
224 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
226 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
229 sample_out1_val <= '0';
230 sample_out2_val <= '0';
231 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
240 END IF;
241 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
247 channel_done(0) <= '1';
248 END IF;
249 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
255 channel_done(1) <= '1';
256 END IF;
257 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
261 sample_out1_val <= '0';
262 sample_out2_val <= '0';
263 channel_done <= "00";
264
265 WHEN OTHERS => NULL;
266 END CASE;
267
268 END IF;
269 END PROCESS;
270
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
275
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
288 RAM_CTRLR_v2_1: RAM_CTRLR_v2
289 GENERIC MAP (
290 tech => tech,
291 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
293 PORT MAP (
294 clk => clk,
295 rstn => rstn,
296 ram_write => ram_write_1,
297 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
302 sample_out => ram_output_1);
303
304 RAM_CTRLR_v2_2: RAM_CTRLR_v2
305 GENERIC MAP (
306 tech => tech,
307 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
309 PORT MAP (
310 clk => clk,
311 rstn => rstn,
312 ram_write => ram_write_2,
313 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
318 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
320
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
328 rstn => rstn,
329 clk => clk,
330 virg_pos => virg_pos,
331 coefs => coefs,
332 --CTRL
333 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
335 --
336 ram_input => ram_input,
337 ram_output => ram_output,
338 --
339 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
343 --DATA
344 sample_in => sample_in_s,
345 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
347
348
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
354 PORT MAP (
355 rstn => rstn,
356 clk => clk,
357 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
361
362 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
365 ram_read => ram_read,
366 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
372
373 -----------------------------------------------------------------------------
374 -- SAMPLE IN
375 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
389 END IF;
390 END PROCESS;
391 END GENERATE loop_all_chanel;
392
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
395 END GENERATE loop_all_sample;
396
397 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
409 END PROCESS;
410
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
420 END IF;
421 END PROCESS;
422 END GENERATE chanel_HIGH;
423
424 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
435 END IF;
436 END PROCESS;
437 END GENERATE all_bit;
438 END GENERATE all_chanel;
439 END GENERATE chanel_more;
440
441 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
69 PORT (
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 PORT (
88 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 PORT (
110 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
127
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
152 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
165 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
184 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
186 BEGIN
187
188 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
191 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
196 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
201 END IF;
202 END IF;
203 END PROCESS;
204 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
206
207
208 PROCESS (clk, rstn)
209 BEGIN -- PROCESS
210 IF rstn = '0' THEN -- asynchronous reset (active low)
211 state_channel_selection <= IDLE;
212 CHANNEL_SEL <= '0';
213 sample_in_val <= '0';
214 sample_out1_val <= '0';
215 sample_out2_val <= '0';
216 all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
217 all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
218 sample_out1(I, J) <= '0';
219 sample_out2(I, J) <= '0';
220 END LOOP all_bit;
221 END LOOP all_channel_sample_out;
222 channel_done <= "00";
223
224 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
226 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
229 sample_out1_val <= '0';
230 sample_out2_val <= '0';
231 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
240 END IF;
241 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
247 channel_done(0) <= '1';
248 END IF;
249 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
255 channel_done(1) <= '1';
256 END IF;
257 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
261 sample_out1_val <= '0';
262 sample_out2_val <= '0';
263 channel_done <= "00";
264
265 WHEN OTHERS => NULL;
266 END CASE;
267
268 END IF;
269 END PROCESS;
270
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
275
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
288 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
289 GENERIC MAP (
290 tech => tech,
291 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
293 PORT MAP (
294 clk => clk,
295 rstn => rstn,
296 ram_write => ram_write_1,
297 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
302 sample_out => ram_output_1);
303
304 RAM_CTRLR_v2_2 : RAM_CTRLR_v2
305 GENERIC MAP (
306 tech => tech,
307 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
309 PORT MAP (
310 clk => clk,
311 rstn => rstn,
312 ram_write => ram_write_2,
313 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
318 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
320
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
328 rstn => rstn,
329 clk => clk,
330 virg_pos => virg_pos,
331 coefs => coefs,
332 --CTRL
333 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
335 --
336 ram_input => ram_input,
337 ram_output => ram_output,
338 --
339 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
343 --DATA
344 sample_in => sample_in_s,
345 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
347
348
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
354 PORT MAP (
355 rstn => rstn,
356 clk => clk,
357 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
361
362 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
365 ram_read => ram_read,
366 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
372
373 -----------------------------------------------------------------------------
374 -- SAMPLE IN
375 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
389 END IF;
390 END PROCESS;
391 END GENERATE loop_all_chanel;
392
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
395 END GENERATE loop_all_sample;
396
397 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
409 END PROCESS;
410
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
420 END IF;
421 END PROCESS;
422 END GENERATE chanel_HIGH;
423
424 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
435 END IF;
436 END PROCESS;
437 END GENERATE all_bit;
438 END GENERATE all_chanel;
439 END GENERATE chanel_more;
440
441 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
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@@ -1,68 +1,69
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe PELLION
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25
26 26 LIBRARY lpp;
27 27 USE lpp.general_purpose.ALL;
28 28
29 29 ENTITY SYNC_VALID_BIT IS
30 30 GENERIC (
31 31 NB_FF_OF_SYNC : INTEGER := 2);
32 32 PORT (
33 33 clk_in : IN STD_LOGIC;
34 clk_out : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 sin : IN STD_LOGIC;
37 sout : OUT STD_LOGIC);
34 rstn_in : IN STD_LOGIC;
35 clk_out : IN STD_LOGIC;
36 rstn_out : IN STD_LOGIC;
37 sin : IN STD_LOGIC;
38 sout : OUT STD_LOGIC);
38 39 END SYNC_VALID_BIT;
39 40
40 41 ARCHITECTURE beh OF SYNC_VALID_BIT IS
41 42 SIGNAL s_1 : STD_LOGIC;
42 43 SIGNAL s_2 : STD_LOGIC;
43 44 BEGIN -- beh
44 45
45 46 lpp_front_to_level_1: lpp_front_to_level
46 47 PORT MAP (
47 48 clk => clk_in,
48 rstn => rstn,
49 rstn => rstn_in,
49 50 sin => sin,
50 51 sout => s_1);
51 52
52 53 SYNC_FF_1: SYNC_FF
53 54 GENERIC MAP (
54 55 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
55 56 PORT MAP (
56 57 clk => clk_out,
57 rstn => rstn,
58 rstn => rstn_out,
58 59 A => s_1,
59 60 A_sync => s_2);
60 61
61 62 lpp_front_detection_1: lpp_front_detection
62 63 PORT MAP (
63 64 clk => clk_out,
64 rstn => rstn,
65 rstn => rstn_out,
65 66 sin => s_2,
66 67 sout => sout);
67 68
68 69 END beh;
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@@ -1,395 +1,407
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Alexis Jeandet
20 20 -- Mail : alexis.jeandet@lpp.polytechnique.fr
21 21 ----------------------------------------------------------------------------
22 22 --UPDATE
23 23 -------------------------------------------------------------------------------
24 24 -- 14-03-2013 - Jean-christophe Pellion
25 25 -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
26 26 -------------------------------------------------------------------------------
27 27
28 28 LIBRARY ieee;
29 29 USE ieee.std_logic_1164.ALL;
30 30 USE IEEE.NUMERIC_STD.ALL;
31 31
32 32
33 33
34 34 PACKAGE general_purpose IS
35 35
36 36 COMPONENT general_counter
37 37 GENERIC (
38 38 CYCLIC : STD_LOGIC;
39 39 NB_BITS_COUNTER : INTEGER;
40 40 RST_VALUE : INTEGER);
41 41 PORT (
42 42 clk : IN STD_LOGIC;
43 43 rstn : IN STD_LOGIC;
44 44 MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
45 45 set : IN STD_LOGIC;
46 46 set_value : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
47 47 add1 : IN STD_LOGIC;
48 48 counter : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
49 49 END COMPONENT;
50 50
51 51 COMPONENT Clk_divider IS
52 52 GENERIC(OSC_freqHz : INTEGER := 50000000;
53 53 TargetFreq_Hz : INTEGER := 50000);
54 54 PORT (clk : IN STD_LOGIC;
55 55 reset : IN STD_LOGIC;
56 56 clk_divided : OUT STD_LOGIC);
57 57 END COMPONENT;
58 58
59 59
60 60 COMPONENT Clk_divider2 IS
61 61 generic(N : integer := 16);
62 62 port(
63 63 clk_in : in std_logic;
64 64 clk_out : out std_logic);
65 65 END COMPONENT;
66 66
67 67 COMPONENT Adder IS
68 68 GENERIC(
69 69 Input_SZ_A : INTEGER := 16;
70 70 Input_SZ_B : INTEGER := 16
71 71
72 72 );
73 73 PORT(
74 74 clk : IN STD_LOGIC;
75 75 reset : IN STD_LOGIC;
76 76 clr : IN STD_LOGIC;
77 77 load : IN STD_LOGIC;
78 78 add : IN STD_LOGIC;
79 79 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
80 80 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
81 81 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
82 82 );
83 83 END COMPONENT;
84 84
85 85 COMPONENT Adder_V0 is
86 86 generic(
87 87 Input_SZ_A : integer := 16;
88 88 Input_SZ_B : integer := 16
89 89
90 90 );
91 91 port(
92 92 clk : in std_logic;
93 93 reset : in std_logic;
94 94 clr : in std_logic;
95 95 add : in std_logic;
96 96 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
97 97 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
98 98 RES : out std_logic_vector(Input_SZ_A-1 downto 0)
99 99 );
100 100 end COMPONENT;
101 101
102 102 COMPONENT ADDRcntr IS
103 103 PORT(
104 104 clk : IN STD_LOGIC;
105 105 reset : IN STD_LOGIC;
106 106 count : IN STD_LOGIC;
107 107 clr : IN STD_LOGIC;
108 108 Q : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
109 109 );
110 110 END COMPONENT;
111 111
112 112 COMPONENT ALU IS
113 113 GENERIC(
114 114 Arith_en : INTEGER := 1;
115 115 Logic_en : INTEGER := 1;
116 116 Input_SZ_1 : INTEGER := 16;
117 117 Input_SZ_2 : INTEGER := 9;
118 118 COMP_EN : INTEGER := 0 -- 1 => No Comp
119 119
120 120 );
121 121 PORT(
122 122 clk : IN STD_LOGIC;
123 123 reset : IN STD_LOGIC;
124 124 ctrl : IN STD_LOGIC_VECTOR(2 downto 0);
125 125 comp : IN STD_LOGIC_VECTOR(1 downto 0);
126 126 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
127 127 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
128 128 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
129 129 );
130 130 END COMPONENT;
131 131
132 132 COMPONENT ALU_V0 IS
133 133 GENERIC(
134 134 Arith_en : INTEGER := 1;
135 135 Logic_en : INTEGER := 1;
136 136 Input_SZ_1 : INTEGER := 16;
137 137 Input_SZ_2 : INTEGER := 9
138 138
139 139 );
140 140 PORT(
141 141 clk : IN STD_LOGIC;
142 142 reset : IN STD_LOGIC;
143 143 ctrl : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
144 144 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
145 145 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
146 146 RES : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
147 147 );
148 148 END COMPONENT;
149 149
150 150 COMPONENT MAC_V0 is
151 151 generic(
152 152 Input_SZ_A : integer := 8;
153 153 Input_SZ_B : integer := 8
154 154
155 155 );
156 156 port(
157 157 clk : in std_logic;
158 158 reset : in std_logic;
159 159 clr_MAC : in std_logic;
160 160 MAC_MUL_ADD : in std_logic_vector(1 downto 0);
161 161 OP1 : in std_logic_vector(Input_SZ_A-1 downto 0);
162 162 OP2 : in std_logic_vector(Input_SZ_B-1 downto 0);
163 163 RES : out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
164 164 );
165 165 end COMPONENT;
166 166
167 167 ---------------------------------------------------------
168 168 -------- // SΓ©lection grace a l'entrΓ©e "ctrl" \\ --------
169 169 ---------------------------------------------------------
170 170 Constant ctrl_IDLE : std_logic_vector(2 downto 0) := "000";
171 171 Constant ctrl_MAC : std_logic_vector(2 downto 0) := "001";
172 172 Constant ctrl_MULT : std_logic_vector(2 downto 0) := "010";
173 173 Constant ctrl_ADD : std_logic_vector(2 downto 0) := "011";
174 174 Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
175 175
176 176
177 177 Constant IDLE_V0 : std_logic_vector(3 downto 0) := "0000";
178 178 Constant MAC_op_V0 : std_logic_vector(3 downto 0) := "0001";
179 179 Constant MULT_V0 : std_logic_vector(3 downto 0) := "0010";
180 180 Constant ADD_V0 : std_logic_vector(3 downto 0) := "0011";
181 181 Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
182 182 ---------------------------------------------------------
183 183
184 184 COMPONENT MAC IS
185 185 GENERIC(
186 186 Input_SZ_A : INTEGER := 8;
187 187 Input_SZ_B : INTEGER := 8;
188 188 COMP_EN : INTEGER := 0 -- 1 => No Comp
189 189 );
190 190 PORT(
191 191 clk : IN STD_LOGIC;
192 192 reset : IN STD_LOGIC;
193 193 clr_MAC : IN STD_LOGIC;
194 194 MAC_MUL_ADD : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
195 195 Comp_2C : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
196 196 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
197 197 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
198 198 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
199 199 );
200 200 END COMPONENT;
201 201
202 202 COMPONENT TwoComplementer is
203 203 generic(
204 204 Input_SZ : integer := 16);
205 205 port(
206 206 clk : in std_logic; --! Horloge du composant
207 207 reset : in std_logic; --! Reset general du composant
208 208 clr : in std_logic; --! Un reset spΓ©cifique au programme
209 209 TwoComp : in std_logic; --! Autorise l'utilisation du complΓ©ment
210 210 OP : in std_logic_vector(Input_SZ-1 downto 0); --! OpΓ©rande d'entrΓ©e
211 211 RES : out std_logic_vector(Input_SZ-1 downto 0) --! RΓ©sultat, opΓ©rande complΓ©mentΓ© ou non
212 212 );
213 213 end COMPONENT;
214 214
215 215 COMPONENT MAC_CONTROLER IS
216 216 PORT(
217 217 ctrl : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
218 218 MULT : OUT STD_LOGIC;
219 219 ADD : OUT STD_LOGIC;
220 220 -- LOAD_ADDER : out std_logic;
221 221 MACMUX_sel : OUT STD_LOGIC;
222 222 MACMUX2_sel : OUT STD_LOGIC
223 223 );
224 224 END COMPONENT;
225 225
226 226 COMPONENT MAC_MUX IS
227 227 GENERIC(
228 228 Input_SZ_A : INTEGER := 16;
229 229 Input_SZ_B : INTEGER := 16
230 230
231 231 );
232 232 PORT(
233 233 sel : IN STD_LOGIC;
234 234 INA1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
235 235 INA2 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
236 236 INB1 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
237 237 INB2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
238 238 OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
239 239 OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
240 240 );
241 241 END COMPONENT;
242 242
243 243
244 244 COMPONENT MAC_MUX2 IS
245 245 GENERIC(Input_SZ : INTEGER := 16);
246 246 PORT(
247 247 sel : IN STD_LOGIC;
248 248 RES1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
249 249 RES2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
250 250 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
251 251 );
252 252 END COMPONENT;
253 253
254 254
255 255 COMPONENT MAC_REG IS
256 256 GENERIC(size : INTEGER := 16);
257 257 PORT(
258 258 reset : IN STD_LOGIC;
259 259 clk : IN STD_LOGIC;
260 260 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
261 261 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
262 262 );
263 263 END COMPONENT;
264 264
265 265
266 266 COMPONENT MUX2 IS
267 267 GENERIC(Input_SZ : INTEGER := 16);
268 268 PORT(
269 269 sel : IN STD_LOGIC;
270 270 IN1 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
271 271 IN2 : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
272 272 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
273 273 );
274 274 END COMPONENT;
275 275
276 276 TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
277 277 TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
278 278
279 279 COMPONENT MUXN
280 280 GENERIC (
281 281 Input_SZ : INTEGER;
282 282 NbStage : INTEGER);
283 283 PORT (
284 284 sel : IN STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
285 285 INPUT : IN MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
286 286 --INPUT : IN ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
287 287 RES : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
288 288 END COMPONENT;
289 289
290 290
291 291
292 292 COMPONENT Multiplier IS
293 293 GENERIC(
294 294 Input_SZ_A : INTEGER := 16;
295 295 Input_SZ_B : INTEGER := 16
296 296
297 297 );
298 298 PORT(
299 299 clk : IN STD_LOGIC;
300 300 reset : IN STD_LOGIC;
301 301 mult : IN STD_LOGIC;
302 302 OP1 : IN STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
303 303 OP2 : IN STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
304 304 RES : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
305 305 );
306 306 END COMPONENT;
307 307
308 308 COMPONENT REG IS
309 309 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
310 310 PORT(
311 311 reset : IN STD_LOGIC;
312 312 clk : IN STD_LOGIC;
313 313 D : IN STD_LOGIC_VECTOR(size-1 DOWNTO 0);
314 314 Q : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
315 315 );
316 316 END COMPONENT;
317 317
318 318
319 319
320 320 COMPONENT RShifter IS
321 321 GENERIC(
322 322 Input_SZ : INTEGER := 16;
323 323 shift_SZ : INTEGER := 4
324 324 );
325 325 PORT(
326 326 clk : IN STD_LOGIC;
327 327 reset : IN STD_LOGIC;
328 328 shift : IN STD_LOGIC;
329 329 OP : IN STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
330 330 cnt : IN STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
331 331 RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
332 332 );
333 333 END COMPONENT;
334 334
335 335 COMPONENT SYNC_FF
336 336 GENERIC (
337 337 NB_FF_OF_SYNC : INTEGER);
338 338 PORT (
339 339 clk : IN STD_LOGIC;
340 340 rstn : IN STD_LOGIC;
341 341 A : IN STD_LOGIC;
342 342 A_sync : OUT STD_LOGIC);
343 343 END COMPONENT;
344 344
345 345 COMPONENT lpp_front_to_level
346 346 PORT (
347 347 clk : IN STD_LOGIC;
348 348 rstn : IN STD_LOGIC;
349 349 sin : IN STD_LOGIC;
350 350 sout : OUT STD_LOGIC);
351 351 END COMPONENT;
352 352
353 353 COMPONENT lpp_front_detection
354 354 PORT (
355 355 clk : IN STD_LOGIC;
356 356 rstn : IN STD_LOGIC;
357 357 sin : IN STD_LOGIC;
358 358 sout : OUT STD_LOGIC);
359 359 END COMPONENT;
360 360
361 361 COMPONENT lpp_front_positive_detection
362 362 PORT (
363 363 clk : IN STD_LOGIC;
364 364 rstn : IN STD_LOGIC;
365 365 sin : IN STD_LOGIC;
366 366 sout : OUT STD_LOGIC);
367 367 END COMPONENT;
368 368
369 --COMPONENT SYNC_VALID_BIT
370 -- GENERIC (
371 -- NB_FF_OF_SYNC : INTEGER);
372 -- PORT (
373 -- clk_in : IN STD_LOGIC;
374 -- clk_out : IN STD_LOGIC;
375 -- rstn : IN STD_LOGIC;
376 -- sin : IN STD_LOGIC;
377 -- sout : OUT STD_LOGIC);
378 --END COMPONENT;
379
369 380 COMPONENT SYNC_VALID_BIT
370 381 GENERIC (
371 382 NB_FF_OF_SYNC : INTEGER);
372 383 PORT (
373 clk_in : IN STD_LOGIC;
374 clk_out : IN STD_LOGIC;
375 rstn : IN STD_LOGIC;
376 sin : IN STD_LOGIC;
377 sout : OUT STD_LOGIC);
384 clk_in : IN STD_LOGIC;
385 rstn_in : IN STD_LOGIC;
386 clk_out : IN STD_LOGIC;
387 rstn_out : IN STD_LOGIC;
388 sin : IN STD_LOGIC;
389 sout : OUT STD_LOGIC);
378 390 END COMPONENT;
379 391
380 392 COMPONENT RR_Arbiter_4
381 393 PORT (
382 394 clk : IN STD_LOGIC;
383 395 rstn : IN STD_LOGIC;
384 396 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
385 397 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
386 398 END COMPONENT;
387 399
388 400 COMPONENT Clock_Divider is
389 401 generic(N :integer := 10);
390 402 port(
391 403 clk, rst : in std_logic;
392 404 sclk : out std_logic);
393 405 end COMPONENT;
394 406
395 407 END;
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@@ -1,512 +1,517
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 11:17:05 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: apb_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 USE IEEE.NUMERIC_STD.ALL;
23 23 LIBRARY grlib;
24 24 USE grlib.amba.ALL;
25 25 USE grlib.stdlib.ALL;
26 26 USE grlib.devices.ALL;
27 27 LIBRARY lpp;
28 28 USE lpp.apb_devices_list.ALL;
29 29 USE lpp.general_purpose.ALL;
30 30 USE lpp.lpp_lfr_management.ALL;
31 31 USE lpp.lpp_lfr_management_apbreg_pkg.ALL;
32 32 USE lpp.lpp_cna.ALL;
33 33 LIBRARY techmap;
34 34 USE techmap.gencomp.ALL;
35 35
36 36
37 37 ENTITY apb_lfr_management IS
38 38
39 39 GENERIC(
40 40 tech : INTEGER := 0;
41 41 pindex : INTEGER := 0; --! APB slave index
42 42 paddr : INTEGER := 0; --! ADDR field of the APB BAR
43 43 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
44 44 FIRST_DIVISION : INTEGER := 374;
45 45 NB_SECOND_DESYNC : INTEGER := 60
46 46 );
47 47
48 48 PORT (
49 clk25MHz : IN STD_LOGIC; --! Clock
50 clk24_576MHz : IN STD_LOGIC; --! secondary clock
51 resetn : IN STD_LOGIC; --! Reset
49 clk25MHz : IN STD_LOGIC; --! Clock
50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 resetn_24_576MHz : IN STD_LOGIC; --! Reset
52 53
53 54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
54 55
55 56 apbi : IN apb_slv_in_type; --! APB slave input signals
56 57 apbo : OUT apb_slv_out_type; --! APB slave output signals
57 58 ---------------------------------------------------------------------------
58 59 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
59 60 HK_val : IN STD_LOGIC;
60 61 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
61 62 ---------------------------------------------------------------------------
62 63 DAC_SDO : OUT STD_LOGIC;
63 64 DAC_SCK : OUT STD_LOGIC;
64 65 DAC_SYNC : OUT STD_LOGIC;
65 66 DAC_CAL_EN : OUT STD_LOGIC;
66 67 ---------------------------------------------------------------------------
67 68 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
68 69 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0); --! fine TIME
69 70 ---------------------------------------------------------------------------
70 71 LFR_soft_rstn : OUT STD_LOGIC
71 72 );
72 73
73 74 END apb_lfr_management;
74 75
75 76 ARCHITECTURE Behavioral OF apb_lfr_management IS
76 77
77 78 CONSTANT REVISION : INTEGER := 1;
78 79 CONSTANT pconfig : apb_config_type := (
79 80 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_MANAGEMENT, 0, REVISION, 0),
80 81 1 => apb_iobar(paddr, pmask)
81 82 );
82 83
83 84 TYPE apb_lfr_time_management_Reg IS RECORD
84 85 ctrl : STD_LOGIC;
85 86 soft_reset : STD_LOGIC;
86 87 coarse_time_load : STD_LOGIC_VECTOR(30 DOWNTO 0);
87 88 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
88 89 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
89 90 LFR_soft_reset : STD_LOGIC;
90 91 HK_temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
91 92 HK_temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
92 93 HK_temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
93 94 END RECORD;
94 95 SIGNAL r : apb_lfr_time_management_Reg;
95 96
96 97 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 98 SIGNAL force_tick : STD_LOGIC;
98 99 SIGNAL previous_force_tick : STD_LOGIC;
99 100 SIGNAL soft_tick : STD_LOGIC;
100 101
101 102 SIGNAL coarsetime_reg_updated : STD_LOGIC;
102 103 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(30 DOWNTO 0);
103 104
104 105 --SIGNAL coarse_time_new : STD_LOGIC;
105 106 SIGNAL coarse_time_new_49 : STD_LOGIC;
106 107 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
107 108 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
108 109
109 110 --SIGNAL fine_time_new : STD_LOGIC;
110 111 --SIGNAL fine_time_new_temp : STD_LOGIC;
111 112 SIGNAL fine_time_new_49 : STD_LOGIC;
112 113 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
113 114 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
114 115 SIGNAL tick : STD_LOGIC;
115 116 SIGNAL new_timecode : STD_LOGIC;
116 117 SIGNAL new_coarsetime : STD_LOGIC;
117 118
118 119 SIGNAL time_new_49 : STD_LOGIC;
119 120 SIGNAL time_new : STD_LOGIC;
120 121
121 122 -----------------------------------------------------------------------------
122 123 SIGNAL force_reset : STD_LOGIC;
123 124 SIGNAL previous_force_reset : STD_LOGIC;
124 125 SIGNAL soft_reset : STD_LOGIC;
125 126 SIGNAL soft_reset_sync : STD_LOGIC;
126 127 -----------------------------------------------------------------------------
127 128 SIGNAL HK_sel_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
128 129
129 130 SIGNAL previous_fine_time_bit : STD_LOGIC;
130 131
131 132 SIGNAL rstn_LFR_TM : STD_LOGIC;
132 133
133 134 -----------------------------------------------------------------------------
134 135 -- DAC
135 136 -----------------------------------------------------------------------------
136 137 CONSTANT PRESZ : INTEGER := 8;
137 138 CONSTANT CPTSZ : INTEGER := 16;
138 139 CONSTANT datawidth : INTEGER := 18;
139 140 CONSTANT dacresolution : INTEGER := 12;
140 141 CONSTANT abits : INTEGER := 8;
141 142
142 143 SIGNAL pre : STD_LOGIC_VECTOR(PRESZ-1 DOWNTO 0);
143 144 SIGNAL N : STD_LOGIC_VECTOR(CPTSZ-1 DOWNTO 0);
144 145 SIGNAL Reload : STD_LOGIC;
145 146 SIGNAL DATA_IN : STD_LOGIC_VECTOR(datawidth-1 DOWNTO 0);
146 147 SIGNAL WEN : STD_LOGIC;
147 148 SIGNAL LOAD_ADDRESSN : STD_LOGIC;
148 149 SIGNAL ADDRESS_IN : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
149 150 SIGNAL ADDRESS_OUT : STD_LOGIC_VECTOR(abits-1 DOWNTO 0);
150 151 SIGNAL INTERLEAVED : STD_LOGIC;
151 152 SIGNAL DAC_CFG : STD_LOGIC_VECTOR(3 DOWNTO 0);
152 153 SIGNAL DAC_CAL_EN_s : STD_LOGIC;
153 154
154 155 BEGIN
155 156
156 157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
157 158
158 PROCESS(resetn, clk25MHz)
159 PROCESS(resetn_25MHz, clk25MHz)
159 160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
160 161 BEGIN
161 162
162 IF resetn = '0' THEN
163 IF resetn_25MHz = '0' THEN
163 164 Rdata <= (OTHERS => '0');
164 165 r.coarse_time_load <= (OTHERS => '0');
165 166 r.soft_reset <= '0';
166 167 r.ctrl <= '0';
167 168 r.LFR_soft_reset <= '1';
168 169
169 170 force_tick <= '0';
170 171 previous_force_tick <= '0';
171 172 soft_tick <= '0';
172 173
173 174 coarsetime_reg_updated <= '0';
174 175 --DAC
175 176 pre <= (OTHERS => '1');
176 177 N <= (OTHERS => '1');
177 178 Reload <= '1';
178 179 DATA_IN <= (OTHERS => '0');
179 180 WEN <= '1';
180 181 LOAD_ADDRESSN <= '1';
181 182 ADDRESS_IN <= (OTHERS => '1');
182 183 INTERLEAVED <= '0';
183 184 DAC_CFG <= (OTHERS => '0');
184 185 --
185 186 DAC_CAL_EN_s <= '0';
186 187 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
187 188 coarsetime_reg_updated <= '0';
188 189
189 190 force_tick <= r.ctrl;
190 191 previous_force_tick <= force_tick;
191 192 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
192 193 soft_tick <= '1';
193 194 ELSE
194 195 soft_tick <= '0';
195 196 END IF;
196 197
197 198 force_reset <= r.soft_reset;
198 199 previous_force_reset <= force_reset;
199 200 IF (previous_force_reset = '0') AND (force_reset = '1') THEN
200 201 soft_reset <= '1';
201 202 ELSE
202 203 soft_reset <= '0';
203 204 END IF;
204 205
205 206 paddr := "000000";
206 207 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
207 208 Rdata <= (OTHERS => '0');
208 209
209 210 LOAD_ADDRESSN <= '1';
210 211 WEN <= '1';
211 212
212 213 IF apbi.psel(pindex) = '1' THEN
213 214 --APB READ OP
214 215 CASE paddr(7 DOWNTO 2) IS
215 216 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
216 217 Rdata(0) <= r.ctrl;
217 218 Rdata(1) <= r.soft_reset;
218 219 Rdata(2) <= r.LFR_soft_reset;
219 220 Rdata(31 DOWNTO 3) <= (OTHERS => '0');
220 221 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
221 222 Rdata(30 DOWNTO 0) <= r.coarse_time_load(30 DOWNTO 0);
222 223 WHEN ADDR_LFR_MANAGMENT_TIME_COARSE =>
223 224 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
224 225 WHEN ADDR_LFR_MANAGMENT_TIME_FINE =>
225 226 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
226 227 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
227 228 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_0 =>
228 229 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
229 230 Rdata(15 DOWNTO 0) <= r.HK_temp_0;
230 231 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_1 =>
231 232 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
232 233 Rdata(15 DOWNTO 0) <= r.HK_temp_1;
233 234 WHEN ADDR_LFR_MANAGMENT_HK_TEMP_2 =>
234 235 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
235 236 Rdata(15 DOWNTO 0) <= r.HK_temp_2;
236 237 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
237 238 Rdata(3 DOWNTO 0) <= DAC_CFG;
238 239 Rdata(4) <= Reload;
239 240 Rdata(5) <= INTERLEAVED;
240 241 Rdata(6) <= DAC_CAL_EN_s;
241 242 Rdata(31 DOWNTO 7) <= (OTHERS => '0');
242 243 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
243 244 Rdata(PRESZ-1 DOWNTO 0) <= pre;
244 245 Rdata(31 DOWNTO PRESZ) <= (OTHERS => '0');
245 246 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
246 247 Rdata(CPTSZ-1 DOWNTO 0) <= N;
247 248 Rdata(31 DOWNTO CPTSZ) <= (OTHERS => '0');
248 249 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
249 250 Rdata(abits-1 DOWNTO 0) <= ADDRESS_OUT;
250 251 Rdata(31 DOWNTO abits) <= (OTHERS => '0');
251 252 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
252 253 Rdata(datawidth-1 DOWNTO 0) <= DATA_IN;
253 254 Rdata(31 DOWNTO datawidth) <= (OTHERS => '0');
254 255 WHEN OTHERS =>
255 256 Rdata(31 DOWNTO 0) <= (OTHERS => '0');
256 257 END CASE;
257 258
258 259 --APB Write OP
259 260 IF (apbi.pwrite AND apbi.penable) = '1' THEN
260 261 CASE paddr(7 DOWNTO 2) IS
261 262 WHEN ADDR_LFR_MANAGMENT_CONTROL =>
262 263 r.ctrl <= apbi.pwdata(0);
263 264 r.soft_reset <= apbi.pwdata(1);
264 265 r.LFR_soft_reset <= apbi.pwdata(2);
265 266 WHEN ADDR_LFR_MANAGMENT_TIME_LOAD =>
266 267 r.coarse_time_load <= apbi.pwdata(30 DOWNTO 0);
267 268 coarsetime_reg_updated <= '1';
268 269 WHEN ADDR_LFR_MANAGMENT_DAC_CONTROL =>
269 270 DAC_CFG <= apbi.pwdata(3 DOWNTO 0);
270 271 Reload <= apbi.pwdata(4);
271 272 INTERLEAVED <= apbi.pwdata(5);
272 273 DAC_CAL_EN_s <= apbi.pwdata(6);
273 274 WHEN ADDR_LFR_MANAGMENT_DAC_PRE =>
274 275 pre <= apbi.pwdata(PRESZ-1 DOWNTO 0);
275 276 WHEN ADDR_LFR_MANAGMENT_DAC_N =>
276 277 N <= apbi.pwdata(CPTSZ-1 DOWNTO 0);
277 278 WHEN ADDR_LFR_MANAGMENT_DAC_ADDRESS_OUT =>
278 279 ADDRESS_IN <= apbi.pwdata(abits-1 DOWNTO 0);
279 280 LOAD_ADDRESSN <= '0';
280 281 WHEN ADDR_LFR_MANAGMENT_DAC_DATA_IN =>
281 282 DATA_IN <= apbi.pwdata(datawidth-1 DOWNTO 0);
282 283 WEN <= '0';
283 284
284 285 WHEN OTHERS =>
285 286 NULL;
286 287 END CASE;
287 288 ELSE
288 289 IF r.ctrl = '1' THEN
289 290 r.ctrl <= '0';
290 291 END IF;
291 292 IF r.soft_reset = '1' THEN
292 293 r.soft_reset <= '0';
293 294 END IF;
294 295 END IF;
295 296
296 297 END IF;
297 298
298 299 END IF;
299 300 END PROCESS;
300 301
301 302 apbo.pirq <= (OTHERS => '0');
302 303 apbo.prdata <= Rdata;
303 304 apbo.pconfig <= pconfig;
304 305 apbo.pindex <= pindex;
305 306
306 307 -----------------------------------------------------------------------------
307 308 -- IN
308 309 coarse_time <= r.coarse_time;
309 310 fine_time <= r.fine_time;
310 311 coarsetime_reg <= r.coarse_time_load;
311 312 -----------------------------------------------------------------------------
312 313
313 314 -----------------------------------------------------------------------------
314 315 -- OUT
315 316 r.coarse_time <= coarse_time_s;
316 317 r.fine_time <= fine_time_s;
317 318 -----------------------------------------------------------------------------
318 319
319 320 -----------------------------------------------------------------------------
320 321 tick <= grspw_tick OR soft_tick;
321 322
322 323 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
323 324 GENERIC MAP (
324 325 NB_FF_OF_SYNC => 2)
325 326 PORT MAP (
326 327 clk_in => clk25MHz,
328 rstn_in => resetn_25MHz,
327 329 clk_out => clk24_576MHz,
328 rstn => resetn,
330 rstn_out => resetn_24_576MHz,
329 331 sin => tick,
330 332 sout => new_timecode);
331 333
332 334 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
333 335 GENERIC MAP (
334 336 NB_FF_OF_SYNC => 2)
335 337 PORT MAP (
336 338 clk_in => clk25MHz,
339 rstn_in => resetn_25MHz,
337 340 clk_out => clk24_576MHz,
338 rstn => resetn,
341 rstn_out => resetn_24_576MHz,
339 342 sin => coarsetime_reg_updated,
340 343 sout => new_coarsetime);
341 344
342 345 SYNC_VALID_BIT_3 : SYNC_VALID_BIT
343 346 GENERIC MAP (
344 347 NB_FF_OF_SYNC => 2)
345 348 PORT MAP (
346 349 clk_in => clk25MHz,
350 rstn_in => resetn_25MHz,
347 351 clk_out => clk24_576MHz,
348 rstn => resetn,
352 rstn_out => resetn_24_576MHz,
349 353 sin => soft_reset,
350 354 sout => soft_reset_sync);
351 355
352 356 -----------------------------------------------------------------------------
353 357 --SYNC_FF_1 : SYNC_FF
354 358 -- GENERIC MAP (
355 359 -- NB_FF_OF_SYNC => 2)
356 360 -- PORT MAP (
357 361 -- clk => clk25MHz,
358 362 -- rstn => resetn,
359 363 -- A => fine_time_new_49,
360 364 -- A_sync => fine_time_new_temp);
361 365
362 366 --lpp_front_detection_1 : lpp_front_detection
363 367 -- PORT MAP (
364 368 -- clk => clk25MHz,
365 369 -- rstn => resetn,
366 370 -- sin => fine_time_new_temp,
367 371 -- sout => fine_time_new);
368 372
369 373 --SYNC_VALID_BIT_4 : SYNC_VALID_BIT
370 374 -- GENERIC MAP (
371 375 -- NB_FF_OF_SYNC => 2)
372 376 -- PORT MAP (
373 377 -- clk_in => clk24_576MHz,
374 378 -- clk_out => clk25MHz,
375 379 -- rstn => resetn,
376 380 -- sin => coarse_time_new_49,
377 381 -- sout => coarse_time_new);
378 382
379 383 time_new_49 <= coarse_time_new_49 OR fine_time_new_49;
380 384
381 385 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
382 386 GENERIC MAP (
383 387 NB_FF_OF_SYNC => 2)
384 388 PORT MAP (
385 389 clk_in => clk24_576MHz,
390 rstn_in => resetn_24_576MHz,
386 391 clk_out => clk25MHz,
387 rstn => resetn,
392 rstn_out => resetn_25MHz,
388 393 sin => time_new_49,
389 394 sout => time_new);
390 395
391 396
392 397
393 PROCESS (clk25MHz, resetn)
398 PROCESS (clk25MHz, resetn_25MHz)
394 399 BEGIN -- PROCESS
395 IF resetn = '0' THEN -- asynchronous reset (active low)
400 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
396 401 fine_time_s <= (OTHERS => '0');
397 402 coarse_time_s <= (OTHERS => '0');
398 403 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
399 404 IF time_new = '1' THEN
400 405 fine_time_s <= fine_time_49;
401 406 coarse_time_s <= coarse_time_49;
402 407 END IF;
403 408 END IF;
404 409 END PROCESS;
405 410
406 411
407 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
412 rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
408 413 '0' WHEN soft_reset_sync = '1' ELSE
409 414 '1';
410 415
411 416
412 417 -----------------------------------------------------------------------------
413 418 -- LFR_TIME_MANAGMENT
414 419 -----------------------------------------------------------------------------
415 420 lfr_time_management_1 : lfr_time_management
416 421 GENERIC MAP (
417 422 FIRST_DIVISION => FIRST_DIVISION,
418 423 NB_SECOND_DESYNC => NB_SECOND_DESYNC)
419 424 PORT MAP (
420 425 clk => clk24_576MHz,
421 426 rstn => rstn_LFR_TM,
422 427
423 428 tick => new_timecode,
424 429 new_coarsetime => new_coarsetime,
425 430 coarsetime_reg => coarsetime_reg(30 DOWNTO 0),
426 431
427 432 fine_time => fine_time_49,
428 433 fine_time_new => fine_time_new_49,
429 434 coarse_time => coarse_time_49,
430 435 coarse_time_new => coarse_time_new_49);
431 436
432 437 -----------------------------------------------------------------------------
433 438 -- HK
434 439 -----------------------------------------------------------------------------
435 440
436 PROCESS (clk25MHz, resetn)
441 PROCESS (clk25MHz, resetn_25MHz)
437 442 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
438 -- for each HK, the update frequency is freq/3
439 --
440 -- for 14, the update frequency is
441 -- 4Hz and update for each
442 -- HK is 1.33Hz
443 -- for each HK, the update frequency is freq/3
444 --
445 -- for 14, the update frequency is
446 -- 4Hz and update for each
447 -- HK is 1.33Hz
443 448 BEGIN -- PROCESS
444 IF resetn = '0' THEN -- asynchronous reset (active low)
449 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
445 450
446 451 r.HK_temp_0 <= (OTHERS => '0');
447 452 r.HK_temp_1 <= (OTHERS => '0');
448 453 r.HK_temp_2 <= (OTHERS => '0');
449 454
450 455 HK_sel_s <= "00";
451 456
452 457 previous_fine_time_bit <= '0';
453 458
454 459 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
455 460
456 461 IF HK_val = '1' THEN
457 462 IF previous_fine_time_bit = NOT(fine_time_s(BIT_FREQUENCY_UPDATE)) THEN
458 463 previous_fine_time_bit <= fine_time_s(BIT_FREQUENCY_UPDATE);
459 464 CASE HK_sel_s IS
460 465 WHEN "00" =>
461 466 r.HK_temp_0 <= HK_sample;
462 HK_sel_s <= "01";
467 HK_sel_s <= "01";
463 468 WHEN "01" =>
464 469 r.HK_temp_1 <= HK_sample;
465 HK_sel_s <= "10";
470 HK_sel_s <= "10";
466 471 WHEN "10" =>
467 472 r.HK_temp_2 <= HK_sample;
468 HK_sel_s <= "00";
473 HK_sel_s <= "00";
469 474 WHEN OTHERS => NULL;
470 475 END CASE;
471 476 END IF;
472 477 END IF;
473 478
474 479 END IF;
475 480 END PROCESS;
476 481
477 482 HK_sel <= HK_sel_s;
478 483
479 484 -----------------------------------------------------------------------------
480 485 -- DAC
481 486 -----------------------------------------------------------------------------
482 487 cal : lfr_cal_driver
483 488 GENERIC MAP(
484 489 tech => tech,
485 490 PRESZ => PRESZ,
486 491 CPTSZ => CPTSZ,
487 492 datawidth => datawidth,
488 493 abits => abits
489 494 )
490 495 PORT MAP(
491 496 clk => clk25MHz,
492 rstn => resetn,
497 rstn => resetn_25MHz,
493 498
494 499 pre => pre,
495 500 N => N,
496 501 Reload => Reload,
497 502 DATA_IN => DATA_IN,
498 503 WEN => WEN,
499 504 LOAD_ADDRESSN => LOAD_ADDRESSN,
500 505 ADDRESS_IN => ADDRESS_IN,
501 506 ADDRESS_OUT => ADDRESS_OUT,
502 507 INTERLEAVED => INTERLEAVED,
503 508 DAC_CFG => DAC_CFG,
504 509
505 510 SYNC => DAC_SYNC,
506 511 DOUT => DAC_SDO,
507 512 SCLK => DAC_SCK,
508 513 SMPCLK => OPEN --DAC_SMPCLK
509 514 );
510 515
511 516 DAC_CAL_EN <= DAC_CAL_EN_s;
512 END Behavioral;
517 END Behavioral; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,110 +1,111
1 1 ----------------------------------------------------------------------------------
2 2 -- Company:
3 3 -- Engineer:
4 4 --
5 5 -- Create Date: 13:04:01 07/02/2012
6 6 -- Design Name:
7 7 -- Module Name: lpp_lfr_time_management - Behavioral
8 8 -- Project Name:
9 9 -- Target Devices:
10 10 -- Tool versions:
11 11 -- Description:
12 12 --
13 13 -- Dependencies:
14 14 --
15 15 -- Revision:
16 16 -- Revision 0.01 - File Created
17 17 -- Additional Comments:
18 18 --
19 19 ----------------------------------------------------------------------------------
20 20 LIBRARY IEEE;
21 21 USE IEEE.STD_LOGIC_1164.ALL;
22 22 LIBRARY grlib;
23 23 USE grlib.amba.ALL;
24 24 USE grlib.stdlib.ALL;
25 25 USE grlib.devices.ALL;
26 26
27 27 PACKAGE lpp_lfr_management IS
28 28
29 29 --***************************
30 30 -- APB_LFR_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_management
33 33 GENERIC (
34 34 tech : INTEGER;
35 35 pindex : INTEGER;
36 36 paddr : INTEGER;
37 37 pmask : INTEGER;
38 38 FIRST_DIVISION : INTEGER;
39 39 NB_SECOND_DESYNC : INTEGER);
40 40 PORT (
41 clk25MHz : IN STD_LOGIC;
42 clk24_576MHz : IN STD_LOGIC;
43 resetn : IN STD_LOGIC;
44 grspw_tick : IN STD_LOGIC;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48 HK_val : IN STD_LOGIC;
49 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 DAC_SDO : OUT STD_LOGIC;
51 DAC_SCK : OUT STD_LOGIC;
52 DAC_SYNC : OUT STD_LOGIC;
53 DAC_CAL_EN : OUT STD_LOGIC;
54 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
56 LFR_soft_rstn : OUT STD_LOGIC);
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 clk24_576MHz : IN STD_LOGIC;
44 resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
57 58 END COMPONENT;
58 59
59 60 COMPONENT lfr_time_management
60 61 GENERIC (
61 62 FIRST_DIVISION : INTEGER;
62 63 NB_SECOND_DESYNC : INTEGER);
63 64 PORT (
64 65 clk : IN STD_LOGIC;
65 66 rstn : IN STD_LOGIC;
66 67 tick : IN STD_LOGIC;
67 68 new_coarsetime : IN STD_LOGIC;
68 69 coarsetime_reg : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
69 70 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
70 71 fine_time_new : OUT STD_LOGIC;
71 72 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
72 73 coarse_time_new : OUT STD_LOGIC);
73 74 END COMPONENT;
74 75
75 76 COMPONENT coarse_time_counter
76 77 GENERIC (
77 NB_SECOND_DESYNC : INTEGER );
78 NB_SECOND_DESYNC : INTEGER);
78 79 PORT (
79 80 clk : IN STD_LOGIC;
80 81 rstn : IN STD_LOGIC;
81 82 tick : IN STD_LOGIC;
82 83 set_TCU : IN STD_LOGIC;
83 84 new_TCU : IN STD_LOGIC;
84 85 set_TCU_value : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
85 86 CT_add1 : IN STD_LOGIC;
86 87 fsm_desync : IN STD_LOGIC;
87 88 FT_max : IN STD_LOGIC;
88 89 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
89 90 coarse_time_new : OUT STD_LOGIC);
90 91 END COMPONENT;
91 92
92 93 COMPONENT fine_time_counter
93 94 GENERIC (
94 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
95 FIRST_DIVISION : INTEGER );
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
96 FIRST_DIVISION : INTEGER);
96 97 PORT (
97 98 clk : IN STD_LOGIC;
98 99 rstn : IN STD_LOGIC;
99 100 tick : IN STD_LOGIC;
100 101 fsm_transition : IN STD_LOGIC;
101 102 FT_max : OUT STD_LOGIC;
102 103 FT_half : OUT STD_LOGIC;
103 104 FT_wait : OUT STD_LOGIC;
104 105 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
105 106 fine_time_new : OUT STD_LOGIC);
106 107 END COMPONENT;
107 108
108 109
109 110 END lpp_lfr_management;
110 111
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