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Update SDC for the MINI-LFR boards
pellion -
r560:8e5e2afea36a JC
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@@ -12,8 +12,8
12 12 #
13 13
14 14
15 define_clock {clk_50} -name {clk_50} -freq 100 -clockgroup default_clkgroup -route 5
16 define_clock {clk_49} -name {clk_49} -freq 49.152 -clockgroup default_clkgroup -route 5
15 define_clock -name {clk_50} -freq 100 -clockgroup default_clkgroup_50 -route 5
16 define_clock -name {clk_49} -freq 49.152 -clockgroup default_clkgroup_49 -route 5
17 17
18 18 #
19 19 # Clock to Clock
@@ -22,8 +22,6 define_clock {clk_49} -name {clk_49} -
22 22 #
23 23 # Inputs/Outputs
24 24 #
25 define_output_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
26 define_input_delay -disable -default 5.00 -improve 0.00 -route 0.00 -ref {clk:r}
27 25
28 26
29 27 #
@@ -37,6 +35,7 define_input_delay -disable -defaul
37 35 #
38 36 # False Path
39 37 #
38 set_false_path -from reset
40 39
41 40 #
42 41 # Path Delay
@@ -47,7 +46,6 define_input_delay -disable -defaul
47 46 #
48 47 define_global_attribute syn_useioff {1}
49 48 define_global_attribute -disable syn_netlist_hierarchy {0}
50 define_attribute {etx_clk} syn_noclockbuf {1}
51 49
52 50 #
53 51 # I/O standards
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@@ -185,6 +185,11 ARCHITECTURE beh OF MINI_LFR_top IS
185 185 SIGNAL rstn_25_d2 : STD_LOGIC;
186 186 SIGNAL rstn_25_d3 : STD_LOGIC;
187 187
188 SIGNAL rstn_24 : STD_LOGIC;
189 SIGNAL rstn_24_d1 : STD_LOGIC;
190 SIGNAL rstn_24_d2 : STD_LOGIC;
191 SIGNAL rstn_24_d3 : STD_LOGIC;
192
188 193 SIGNAL rstn_50 : STD_LOGIC;
189 194 SIGNAL rstn_50_d1 : STD_LOGIC;
190 195 SIGNAL rstn_50_d2 : STD_LOGIC;
@@ -198,7 +203,7 ARCHITECTURE beh OF MINI_LFR_top IS
198 203
199 204 --
200 205 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
201 SIGNAL HK_SEL : STD_LOGIC_VECTOR( 1 DOWNTO 0);
206 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
202 207
203 208 BEGIN -- beh
204 209
@@ -272,9 +277,17 BEGIN -- beh
272 277 PROCESS (clk_49, reset)
273 278 BEGIN -- PROCESS
274 279 IF reset = '0' THEN -- asynchronous reset (active low)
275 clk_24 <= '0';
280 clk_24 <= '0';
281 rstn_24_d1 <= '0';
282 rstn_24_d2 <= '0';
283 rstn_24_d3 <= '0';
284 rstn_24 <= '0';
276 285 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
277 clk_24 <= NOT clk_24;
286 clk_24 <= NOT clk_24;
287 rstn_24_d1 <= '1';
288 rstn_24_d2 <= rstn_24_d1;
289 rstn_24_d3 <= rstn_24_d2;
290 rstn_24 <= rstn_24_d3;
278 291 END IF;
279 292 END PROCESS;
280 293
@@ -315,9 +328,9 BEGIN -- beh
315 328 END IF;
316 329 END PROCESS;
317 330
318 PROCESS (clk_24, rstn_25)
331 PROCESS (clk_24, rstn_24)
319 332 BEGIN -- PROCESS
320 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
333 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
321 334 I00_s <= '0';
322 335 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
323 336 I00_s <= NOT I00_s;
@@ -331,56 +344,56 BEGIN -- beh
331 344 nDCD2 <= '1';
332 345
333 346 --
334
347
335 348 leon3_soc_1 : leon3_soc
336 349 GENERIC MAP (
337 fabtech => apa3e,
338 memtech => apa3e,
339 padtech => inferred,
340 clktech => inferred,
341 disas => 0,
342 dbguart => 0,
343 pclow => 2,
344 clk_freq => 25000,
345 IS_RADHARD => 0,
346 NB_CPU => 1,
347 ENABLE_FPU => 1,
348 FPU_NETLIST => 0,
349 ENABLE_DSU => 1,
350 ENABLE_AHB_UART => 1,
351 ENABLE_APB_UART => 1,
352 ENABLE_IRQMP => 1,
353 ENABLE_GPT => 1,
354 NB_AHB_MASTER => NB_AHB_MASTER,
355 NB_AHB_SLAVE => NB_AHB_SLAVE,
356 NB_APB_SLAVE => NB_APB_SLAVE,
357 ADDRESS_SIZE => 20,
350 fabtech => apa3e,
351 memtech => apa3e,
352 padtech => inferred,
353 clktech => inferred,
354 disas => 0,
355 dbguart => 0,
356 pclow => 2,
357 clk_freq => 25000,
358 IS_RADHARD => 0,
359 NB_CPU => 1,
360 ENABLE_FPU => 1,
361 FPU_NETLIST => 0,
362 ENABLE_DSU => 1,
363 ENABLE_AHB_UART => 1,
364 ENABLE_APB_UART => 1,
365 ENABLE_IRQMP => 1,
366 ENABLE_GPT => 1,
367 NB_AHB_MASTER => NB_AHB_MASTER,
368 NB_AHB_SLAVE => NB_AHB_SLAVE,
369 NB_APB_SLAVE => NB_APB_SLAVE,
370 ADDRESS_SIZE => 20,
358 371 USES_IAP_MEMCTRLR => 0)
359 372 PORT MAP (
360 clk => clk_25,
361 reset => rstn_25,
362 errorn => errorn,
363 ahbrxd => TXD1,
364 ahbtxd => RXD1,
365 urxd1 => TXD2,
366 utxd1 => RXD2,
367 address => SRAM_A,
368 data => SRAM_DQ,
369 nSRAM_BE0 => SRAM_nBE(0),
370 nSRAM_BE1 => SRAM_nBE(1),
371 nSRAM_BE2 => SRAM_nBE(2),
372 nSRAM_BE3 => SRAM_nBE(3),
373 nSRAM_WE => SRAM_nWE,
374 nSRAM_CE => SRAM_CE_s,
375 nSRAM_OE => SRAM_nOE,
373 clk => clk_25,
374 reset => rstn_25,
375 errorn => errorn,
376 ahbrxd => TXD1,
377 ahbtxd => RXD1,
378 urxd1 => TXD2,
379 utxd1 => RXD2,
380 address => SRAM_A,
381 data => SRAM_DQ,
382 nSRAM_BE0 => SRAM_nBE(0),
383 nSRAM_BE1 => SRAM_nBE(1),
384 nSRAM_BE2 => SRAM_nBE(2),
385 nSRAM_BE3 => SRAM_nBE(3),
386 nSRAM_WE => SRAM_nWE,
387 nSRAM_CE => SRAM_CE_s,
388 nSRAM_OE => SRAM_nOE,
376 389 nSRAM_READY => '0',
377 390 SRAM_MBE => OPEN,
378 apbi_ext => apbi_ext,
379 apbo_ext => apbo_ext,
380 ahbi_s_ext => ahbi_s_ext,
381 ahbo_s_ext => ahbo_s_ext,
382 ahbi_m_ext => ahbi_m_ext,
383 ahbo_m_ext => ahbo_m_ext);
391 apbi_ext => apbi_ext,
392 apbo_ext => apbo_ext,
393 ahbi_s_ext => ahbi_s_ext,
394 ahbo_s_ext => ahbo_s_ext,
395 ahbi_m_ext => ahbi_m_ext,
396 ahbo_m_ext => ahbo_m_ext);
384 397
385 398 SRAM_CE <= SRAM_CE_s(0);
386 399 -------------------------------------------------------------------------------
@@ -392,25 +405,26 BEGIN -- beh
392 405 pindex => 6,
393 406 paddr => 6,
394 407 pmask => 16#fff#,
395 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
408 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
396 409 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
397 410 PORT MAP (
398 clk25MHz => clk_25,
399 clk24_576MHz => clk_24, -- 49.152MHz/2
400 resetn => rstn_25,
401 grspw_tick => swno.tickout,
402 apbi => apbi_ext,
403 apbo => apbo_ext(6),
404 HK_sample => sample_hk,
405 HK_val => sample_val,
406 HK_sel => HK_SEL,
407 DAC_SDO => OPEN,
408 DAC_SCK => OPEN,
409 DAC_SYNC => OPEN,
410 DAC_CAL_EN => OPEN,
411 coarse_time => coarse_time,
412 fine_time => fine_time,
413 LFR_soft_rstn => LFR_soft_rstn
411 clk25MHz => clk_25,
412 resetn_25MHz => rstn_25, -- TODO
413 clk24_576MHz => clk_24, -- 49.152MHz/2
414 resetn_24_576MHz => rstn_24, -- TODO
415 grspw_tick => swno.tickout,
416 apbi => apbi_ext,
417 apbo => apbo_ext(6),
418 HK_sample => sample_hk,
419 HK_val => sample_val,
420 HK_sel => HK_SEL,
421 DAC_SDO => OPEN,
422 DAC_SCK => OPEN,
423 DAC_SYNC => OPEN,
424 DAC_CAL_EN => OPEN,
425 coarse_time => coarse_time,
426 fine_time => fine_time,
427 LFR_soft_rstn => LFR_soft_rstn
414 428 );
415 429
416 430 -----------------------------------------------------------------------
@@ -522,7 +536,7 BEGIN -- beh
522 536 pirq_ms => 6,
523 537 pirq_wfp => 14,
524 538 hindex => 2,
525 top_lfr_version => X"000143") -- aa.bb.cc version
539 top_lfr_version => X"000144") -- aa.bb.cc version
526 540 PORT MAP (
527 541 clk => clk_25,
528 542 rstn => LFR_rstn,
@@ -566,7 +580,7 BEGIN -- beh
566 580 PORT MAP (
567 581 -- CONV
568 582 cnv_clk => clk_24,
569 cnv_rstn => rstn_25,
583 cnv_rstn => rstn_24,
570 584 cnv => ADC_nCS_sig,
571 585 -- DATA
572 586 clk => clk_25,
@@ -589,7 +603,7 BEGIN -- beh
589 603 "0010001000100010" WHEN HK_SEL = "01" ELSE
590 604 "0100010001000100" WHEN HK_SEL = "10" ELSE
591 605 (OTHERS => '0');
592
606
593 607
594 608 ----------------------------------------------------------------------
595 609 --- GPIO -----------------------------------------------------------
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@@ -15,7 +15,7 VHDLSIMFILES= testbench.vhd
15 15 SIMTOP=testbench
16 16 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
17 17 ##SDC=$(VHDLIB)/boards/$(BOARD)/default.sdc
18 ##SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
18 SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc
19 19 SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc
20 20 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
21 21 CLEAN=soft-clean
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@@ -89,14 +89,10 ARCHITECTURE beh OF cic_lfr_r2 IS
89 89 SIGNAL addr_gen: STD_LOGIC_VECTOR(8 DOWNTO 0);
90 90 SIGNAL addr_read: STD_LOGIC_VECTOR(8 DOWNTO 0);
91 91 SIGNAL addr_write: STD_LOGIC_VECTOR(8 DOWNTO 0);
92 SIGNAL addr_write_mux: STD_LOGIC_VECTOR(8 DOWNTO 0);
93 92 SIGNAL addr_write_s: STD_LOGIC_VECTOR(8 DOWNTO 0);
94 93 SIGNAL data_we: STD_LOGIC;
95 94 SIGNAL data_we_s: STD_LOGIC;
96 95 SIGNAL data_wen : STD_LOGIC;
97 -- SIGNAL data_write : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 -- SIGNAL data_read : STD_LOGIC_VECTOR(15 DOWNTO 0);
99 -- SIGNAL data_read_pre : STD_LOGIC_VECTOR(15 DOWNTO 0);
100 96 -----------------------------------------------------------------------------
101 97 SIGNAL sample_out_reg16 : sample_vector(8*2-1 DOWNTO 0, 15 DOWNTO 0);
102 98 SIGNAL sample_out_reg256 : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
@@ -394,4 +390,4 BEGIN
394 390 END GENERATE all_bits;
395 391 END GENERATE all_channel_out_v;
396 392
397 END beh;
393 END beh; No newline at end of file
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@@ -1,442 +1,442
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
69 PORT (
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 PORT (
88 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 PORT (
110 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
127
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
152 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
165 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
184 SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
186 BEGIN
187
188 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
191 all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
196 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
201 END IF;
202 END IF;
203 END PROCESS;
204 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
206 all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
207 all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
208 sample_out_zero(I,J) <= '0';
209 END GENERATE all_bit;
210 END GENERATE all_channel_sample_out;
211
212 PROCESS (clk, rstn)
213 BEGIN -- PROCESS
214 IF rstn = '0' THEN -- asynchronous reset (active low)
215 state_channel_selection <= IDLE;
216 CHANNEL_SEL <= '0';
217 sample_in_val <= '0';
218 sample_out1_val <= '0';
219 sample_out2_val <= '0';
220 sample_out1 <= sample_out_zero;
221 sample_out2 <= sample_out_zero;
222 channel_done <= "00";
223
224 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
226 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
229 sample_out1_val <= '0';
230 sample_out2_val <= '0';
231 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
240 END IF;
241 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
247 channel_done(0) <= '1';
248 END IF;
249 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
255 channel_done(1) <= '1';
256 END IF;
257 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
261 sample_out1_val <= '0';
262 sample_out2_val <= '0';
263 channel_done <= "00";
264
265 WHEN OTHERS => NULL;
266 END CASE;
267
268 END IF;
269 END PROCESS;
270
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
275
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
288 RAM_CTRLR_v2_1: RAM_CTRLR_v2
289 GENERIC MAP (
290 tech => tech,
291 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
293 PORT MAP (
294 clk => clk,
295 rstn => rstn,
296 ram_write => ram_write_1,
297 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
302 sample_out => ram_output_1);
303
304 RAM_CTRLR_v2_2: RAM_CTRLR_v2
305 GENERIC MAP (
306 tech => tech,
307 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
309 PORT MAP (
310 clk => clk,
311 rstn => rstn,
312 ram_write => ram_write_2,
313 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
318 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
320
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
328 rstn => rstn,
329 clk => clk,
330 virg_pos => virg_pos,
331 coefs => coefs,
332 --CTRL
333 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
335 --
336 ram_input => ram_input,
337 ram_output => ram_output,
338 --
339 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
343 --DATA
344 sample_in => sample_in_s,
345 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
347
348
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
354 PORT MAP (
355 rstn => rstn,
356 clk => clk,
357 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
361
362 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
365 ram_read => ram_read,
366 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
372
373 -----------------------------------------------------------------------------
374 -- SAMPLE IN
375 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
389 END IF;
390 END PROCESS;
391 END GENERATE loop_all_chanel;
392
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
395 END GENERATE loop_all_sample;
396
397 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
409 END PROCESS;
410
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
420 END IF;
421 END PROCESS;
422 END GENERATE chanel_HIGH;
423
424 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
435 END IF;
436 END PROCESS;
437 END GENERATE all_bit;
438 END GENERATE all_chanel;
439 END GENERATE chanel_more;
440
441 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22
23 LIBRARY IEEE;
24 USE IEEE.numeric_std.ALL;
25 USE IEEE.std_logic_1164.ALL;
26
27 LIBRARY techmap;
28 USE techmap.gencomp.ALL;
29
30 LIBRARY lpp;
31 USE lpp.iir_filter.ALL;
32 USE lpp.general_purpose.ALL;
33
34 ENTITY IIR_CEL_CTRLR_v3 IS
35 GENERIC (
36 tech : INTEGER := 0;
37 Mem_use : INTEGER := use_RAM;
38 Sample_SZ : INTEGER := 18;
39 Coef_SZ : INTEGER := 9;
40 Coef_Nb : INTEGER := 25;
41 Coef_sel_SZ : INTEGER := 5;
42 Cels_count : INTEGER := 5;
43 ChanelsCount : INTEGER := 8);
44 PORT (
45 rstn : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47
48 virg_pos : IN INTEGER;
49 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
50
51 sample_in1_val : IN STD_LOGIC;
52 sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
53 sample_in2_val : IN STD_LOGIC;
54 sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
55
56 sample_out1_val : OUT STD_LOGIC;
57 sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
58 sample_out2_val : OUT STD_LOGIC;
59 sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0));
60 END IIR_CEL_CTRLR_v3;
61
62 ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS
63
64 COMPONENT RAM_CTRLR_v2
65 GENERIC (
66 tech : INTEGER;
67 Input_SZ_1 : INTEGER;
68 Mem_use : INTEGER);
69 PORT (
70 rstn : IN STD_LOGIC;
71 clk : IN STD_LOGIC;
72 ram_write : IN STD_LOGIC;
73 ram_read : IN STD_LOGIC;
74 raddr_rst : IN STD_LOGIC;
75 raddr_add1 : IN STD_LOGIC;
76 waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
77 sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
78 sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0));
79 END COMPONENT;
80
81 COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW
82 GENERIC (
83 Sample_SZ : INTEGER;
84 Coef_SZ : INTEGER;
85 Coef_Nb : INTEGER;
86 Coef_sel_SZ : INTEGER);
87 PORT (
88 rstn : IN STD_LOGIC;
89 clk : IN STD_LOGIC;
90 virg_pos : IN INTEGER;
91 coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0);
92 in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
93 ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
94 ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
95 ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
96 alu_sel_input : IN STD_LOGIC;
97 alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
98 alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);
99 alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
100 sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
101 sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0));
102 END COMPONENT;
103
104 COMPONENT IIR_CEL_CTRLR_v2_CONTROL
105 GENERIC (
106 Coef_sel_SZ : INTEGER;
107 Cels_count : INTEGER;
108 ChanelsCount : INTEGER);
109 PORT (
110 rstn : IN STD_LOGIC;
111 clk : IN STD_LOGIC;
112 sample_in_val : IN STD_LOGIC;
113 sample_in_rot : OUT STD_LOGIC;
114 sample_out_val : OUT STD_LOGIC;
115 sample_out_rot : OUT STD_LOGIC;
116 in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
117 ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
118 ram_write : OUT STD_LOGIC;
119 ram_read : OUT STD_LOGIC;
120 raddr_rst : OUT STD_LOGIC;
121 raddr_add1 : OUT STD_LOGIC;
122 waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
123 alu_sel_input : OUT STD_LOGIC;
124 alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
125 alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0));
126 END COMPONENT;
127
128 SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0);
129 SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0);
130 SIGNAL ram_write : STD_LOGIC;
131 SIGNAL ram_read : STD_LOGIC;
132 SIGNAL raddr_rst : STD_LOGIC;
133 SIGNAL raddr_add1 : STD_LOGIC;
134 SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0);
135 SIGNAL alu_sel_input : STD_LOGIC;
136 SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0);
137 SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0);
138
139 SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
140 SIGNAL sample_in_rotate : STD_LOGIC;
141 SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
142 SIGNAL sample_out_val_s : STD_LOGIC;
143 SIGNAL sample_out_val_s2 : STD_LOGIC;
144 SIGNAL sample_out_rot_s : STD_LOGIC;
145 SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
146
147 SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
148
149 SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
150 SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
151 --
152 SIGNAL sample_in_val : STD_LOGIC;
153 SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
154 SIGNAL sample_out_val : STD_LOGIC;
155 SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
156
157 -----------------------------------------------------------------------------
158 --
159 -----------------------------------------------------------------------------
160 SIGNAL CHANNEL_SEL : STD_LOGIC;
161
162 SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
163 SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0);
164
165 SIGNAL ram_write_1 : STD_LOGIC;
166 SIGNAL ram_read_1 : STD_LOGIC;
167 SIGNAL raddr_rst_1 : STD_LOGIC;
168 SIGNAL raddr_add1_1 : STD_LOGIC;
169 SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
170
171 SIGNAL ram_write_2 : STD_LOGIC;
172 SIGNAL ram_read_2 : STD_LOGIC;
173 SIGNAL raddr_rst_2 : STD_LOGIC;
174 SIGNAL raddr_add1_2 : STD_LOGIC;
175 SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0);
176 -----------------------------------------------------------------------------
177 SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0);
178 SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0);
179 SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0);
180 -----------------------------------------------------------------------------
181 TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE);
182 SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION;
183
184 --SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0);
185
186 BEGIN
187
188 -----------------------------------------------------------------------------
189 channel_val(0) <= sample_in1_val;
190 channel_val(1) <= sample_in2_val;
191 all_channel_input_valid : FOR I IN 1 DOWNTO 0 GENERATE
192 PROCESS (clk, rstn)
193 BEGIN -- PROCESS
194 IF rstn = '0' THEN -- asynchronous reset (active low)
195 channel_ready(I) <= '0';
196 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
197 IF channel_val(I) = '1' THEN
198 channel_ready(I) <= '1';
199 ELSIF channel_done(I) = '1' THEN
200 channel_ready(I) <= '0';
201 END IF;
202 END IF;
203 END PROCESS;
204 END GENERATE all_channel_input_valid;
205 -----------------------------------------------------------------------------
206
207
208 PROCESS (clk, rstn)
209 BEGIN -- PROCESS
210 IF rstn = '0' THEN -- asynchronous reset (active low)
211 state_channel_selection <= IDLE;
212 CHANNEL_SEL <= '0';
213 sample_in_val <= '0';
214 sample_out1_val <= '0';
215 sample_out2_val <= '0';
216 all_channel_sample_out : FOR I IN ChanelsCount-1 DOWNTO 0 LOOP
217 all_bit : FOR J IN Sample_SZ-1 DOWNTO 0 LOOP
218 sample_out1(I, J) <= '0';
219 sample_out2(I, J) <= '0';
220 END LOOP all_bit;
221 END LOOP all_channel_sample_out;
222 channel_done <= "00";
223
224 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
225 CASE state_channel_selection IS
226 WHEN IDLE =>
227 CHANNEL_SEL <= '0';
228 sample_in_val <= '0';
229 sample_out1_val <= '0';
230 sample_out2_val <= '0';
231 channel_done <= "00";
232 IF channel_ready(0) = '1' THEN
233 state_channel_selection <= ONGOING_1;
234 CHANNEL_SEL <= '0';
235 sample_in_val <= '1';
236 ELSIF channel_ready(1) = '1' THEN
237 state_channel_selection <= ONGOING_2;
238 CHANNEL_SEL <= '1';
239 sample_in_val <= '1';
240 END IF;
241 WHEN ONGOING_1 =>
242 sample_in_val <= '0';
243 IF sample_out_val = '1' THEN
244 state_channel_selection <= WAIT_STATE;
245 sample_out1 <= sample_out;
246 sample_out1_val <= '1';
247 channel_done(0) <= '1';
248 END IF;
249 WHEN ONGOING_2 =>
250 sample_in_val <= '0';
251 IF sample_out_val = '1' THEN
252 state_channel_selection <= WAIT_STATE;
253 sample_out2 <= sample_out;
254 sample_out2_val <= '1';
255 channel_done(1) <= '1';
256 END IF;
257 WHEN WAIT_STATE =>
258 state_channel_selection <= IDLE;
259 CHANNEL_SEL <= '0';
260 sample_in_val <= '0';
261 sample_out1_val <= '0';
262 sample_out2_val <= '0';
263 channel_done <= "00";
264
265 WHEN OTHERS => NULL;
266 END CASE;
267
268 END IF;
269 END PROCESS;
270
271 sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2;
272 -----------------------------------------------------------------------------
273 ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE
274 ram_output_2;
275
276 ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0';
277 ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0';
278 raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1';
279 raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0';
280 waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00";
281
282 ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0';
283 ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0';
284 raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1';
285 raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0';
286 waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00";
287
288 RAM_CTRLR_v2_1 : RAM_CTRLR_v2
289 GENERIC MAP (
290 tech => tech,
291 Input_SZ_1 => Sample_SZ,
292 Mem_use => Mem_use)
293 PORT MAP (
294 clk => clk,
295 rstn => rstn,
296 ram_write => ram_write_1,
297 ram_read => ram_read_1,
298 raddr_rst => raddr_rst_1,
299 raddr_add1 => raddr_add1_1,
300 waddr_previous => waddr_previous_1,
301 sample_in => ram_input,
302 sample_out => ram_output_1);
303
304 RAM_CTRLR_v2_2 : RAM_CTRLR_v2
305 GENERIC MAP (
306 tech => tech,
307 Input_SZ_1 => Sample_SZ,
308 Mem_use => Mem_use)
309 PORT MAP (
310 clk => clk,
311 rstn => rstn,
312 ram_write => ram_write_2,
313 ram_read => ram_read_2,
314 raddr_rst => raddr_rst_2,
315 raddr_add1 => raddr_add1_2,
316 waddr_previous => waddr_previous_2,
317 sample_in => ram_input,
318 sample_out => ram_output_2);
319 -----------------------------------------------------------------------------
320
321 IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW
322 GENERIC MAP (
323 Sample_SZ => Sample_SZ,
324 Coef_SZ => Coef_SZ,
325 Coef_Nb => Coef_Nb,
326 Coef_sel_SZ => Coef_sel_SZ)
327 PORT MAP (
328 rstn => rstn,
329 clk => clk,
330 virg_pos => virg_pos,
331 coefs => coefs,
332 --CTRL
333 in_sel_src => in_sel_src,
334 ram_sel_Wdata => ram_sel_Wdata,
335 --
336 ram_input => ram_input,
337 ram_output => ram_output,
338 --
339 alu_sel_input => alu_sel_input,
340 alu_sel_coeff => alu_sel_coeff,
341 alu_ctrl => alu_ctrl,
342 alu_comp => "00",
343 --DATA
344 sample_in => sample_in_s,
345 sample_out => sample_out_s);
346 -----------------------------------------------------------------------------
347
348
349 IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL
350 GENERIC MAP (
351 Coef_sel_SZ => Coef_sel_SZ,
352 Cels_count => Cels_count,
353 ChanelsCount => ChanelsCount)
354 PORT MAP (
355 rstn => rstn,
356 clk => clk,
357 sample_in_val => sample_in_val,
358 sample_in_rot => sample_in_rotate,
359 sample_out_val => sample_out_val_s,
360 sample_out_rot => sample_out_rot_s,
361
362 in_sel_src => in_sel_src,
363 ram_sel_Wdata => ram_sel_Wdata,
364 ram_write => ram_write,
365 ram_read => ram_read,
366 raddr_rst => raddr_rst,
367 raddr_add1 => raddr_add1,
368 waddr_previous => waddr_previous,
369 alu_sel_input => alu_sel_input,
370 alu_sel_coeff => alu_sel_coeff,
371 alu_ctrl => alu_ctrl);
372
373 -----------------------------------------------------------------------------
374 -- SAMPLE IN
375 -----------------------------------------------------------------------------
376 loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE
377
378 loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE
379 PROCESS (clk, rstn)
380 BEGIN -- PROCESS
381 IF rstn = '0' THEN -- asynchronous reset (active low)
382 sample_in_buf(I, J) <= '0';
383 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
384 IF sample_in_val = '1' THEN
385 sample_in_buf(I, J) <= sample_in(I, J);
386 ELSIF sample_in_rotate = '1' THEN
387 sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J);
388 END IF;
389 END IF;
390 END PROCESS;
391 END GENERATE loop_all_chanel;
392
393 sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J);
394
395 END GENERATE loop_all_sample;
396
397 -----------------------------------------------------------------------------
398 -- SAMPLE OUT
399 -----------------------------------------------------------------------------
400 PROCESS (clk, rstn)
401 BEGIN -- PROCESS
402 IF rstn = '0' THEN -- asynchronous reset (active low)
403 sample_out_val <= '0';
404 sample_out_val_s2 <= '0';
405 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
406 sample_out_val <= sample_out_val_s2;
407 sample_out_val_s2 <= sample_out_val_s;
408 END IF;
409 END PROCESS;
410
411 chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
412 PROCESS (clk, rstn)
413 BEGIN -- PROCESS
414 IF rstn = '0' THEN -- asynchronous reset (active low)
415 sample_out_s2(ChanelsCount-1, I) <= '0';
416 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
417 IF sample_out_rot_s = '1' THEN
418 sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I);
419 END IF;
420 END IF;
421 END PROCESS;
422 END GENERATE chanel_HIGH;
423
424 chanel_more : IF ChanelsCount > 1 GENERATE
425 all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE
426 all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 sample_out_s2(J-1, I) <= '0';
431 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
432 IF sample_out_rot_s = '1' THEN
433 sample_out_s2(J-1, I) <= sample_out_s2(J, I);
434 END IF;
435 END IF;
436 END PROCESS;
437 END GENERATE all_bit;
438 END GENERATE all_chanel;
439 END GENERATE chanel_more;
440
441 sample_out <= sample_out_s2;
442 END ar_IIR_CEL_CTRLR_v3;
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@@ -31,10 +31,11 ENTITY SYNC_VALID_BIT IS
31 31 NB_FF_OF_SYNC : INTEGER := 2);
32 32 PORT (
33 33 clk_in : IN STD_LOGIC;
34 clk_out : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 sin : IN STD_LOGIC;
37 sout : OUT STD_LOGIC);
34 rstn_in : IN STD_LOGIC;
35 clk_out : IN STD_LOGIC;
36 rstn_out : IN STD_LOGIC;
37 sin : IN STD_LOGIC;
38 sout : OUT STD_LOGIC);
38 39 END SYNC_VALID_BIT;
39 40
40 41 ARCHITECTURE beh OF SYNC_VALID_BIT IS
@@ -45,7 +46,7 BEGIN -- beh
45 46 lpp_front_to_level_1: lpp_front_to_level
46 47 PORT MAP (
47 48 clk => clk_in,
48 rstn => rstn,
49 rstn => rstn_in,
49 50 sin => sin,
50 51 sout => s_1);
51 52
@@ -54,14 +55,14 BEGIN -- beh
54 55 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
55 56 PORT MAP (
56 57 clk => clk_out,
57 rstn => rstn,
58 rstn => rstn_out,
58 59 A => s_1,
59 60 A_sync => s_2);
60 61
61 62 lpp_front_detection_1: lpp_front_detection
62 63 PORT MAP (
63 64 clk => clk_out,
64 rstn => rstn,
65 rstn => rstn_out,
65 66 sin => s_2,
66 67 sout => sout);
67 68
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@@ -366,15 +366,27 Constant CLR_MAC_V0 : std_logic_vector(3
366 366 sout : OUT STD_LOGIC);
367 367 END COMPONENT;
368 368
369 --COMPONENT SYNC_VALID_BIT
370 -- GENERIC (
371 -- NB_FF_OF_SYNC : INTEGER);
372 -- PORT (
373 -- clk_in : IN STD_LOGIC;
374 -- clk_out : IN STD_LOGIC;
375 -- rstn : IN STD_LOGIC;
376 -- sin : IN STD_LOGIC;
377 -- sout : OUT STD_LOGIC);
378 --END COMPONENT;
379
369 380 COMPONENT SYNC_VALID_BIT
370 381 GENERIC (
371 382 NB_FF_OF_SYNC : INTEGER);
372 383 PORT (
373 clk_in : IN STD_LOGIC;
374 clk_out : IN STD_LOGIC;
375 rstn : IN STD_LOGIC;
376 sin : IN STD_LOGIC;
377 sout : OUT STD_LOGIC);
384 clk_in : IN STD_LOGIC;
385 rstn_in : IN STD_LOGIC;
386 clk_out : IN STD_LOGIC;
387 rstn_out : IN STD_LOGIC;
388 sin : IN STD_LOGIC;
389 sout : OUT STD_LOGIC);
378 390 END COMPONENT;
379 391
380 392 COMPONENT RR_Arbiter_4
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@@ -46,9 +46,10 ENTITY apb_lfr_management IS
46 46 );
47 47
48 48 PORT (
49 clk25MHz : IN STD_LOGIC; --! Clock
50 clk24_576MHz : IN STD_LOGIC; --! secondary clock
51 resetn : IN STD_LOGIC; --! Reset
49 clk25MHz : IN STD_LOGIC; --! Clock
50 resetn_25MHz : IN STD_LOGIC; --! Reset
51 clk24_576MHz : IN STD_LOGIC; --! secondary clock
52 resetn_24_576MHz : IN STD_LOGIC; --! Reset
52 53
53 54 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
54 55
@@ -155,11 +156,11 BEGIN
155 156
156 157 LFR_soft_rstn <= NOT r.LFR_soft_reset;
157 158
158 PROCESS(resetn, clk25MHz)
159 PROCESS(resetn_25MHz, clk25MHz)
159 160 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
160 161 BEGIN
161 162
162 IF resetn = '0' THEN
163 IF resetn_25MHz = '0' THEN
163 164 Rdata <= (OTHERS => '0');
164 165 r.coarse_time_load <= (OTHERS => '0');
165 166 r.soft_reset <= '0';
@@ -324,8 +325,9 BEGIN
324 325 NB_FF_OF_SYNC => 2)
325 326 PORT MAP (
326 327 clk_in => clk25MHz,
328 rstn_in => resetn_25MHz,
327 329 clk_out => clk24_576MHz,
328 rstn => resetn,
330 rstn_out => resetn_24_576MHz,
329 331 sin => tick,
330 332 sout => new_timecode);
331 333
@@ -334,8 +336,9 BEGIN
334 336 NB_FF_OF_SYNC => 2)
335 337 PORT MAP (
336 338 clk_in => clk25MHz,
339 rstn_in => resetn_25MHz,
337 340 clk_out => clk24_576MHz,
338 rstn => resetn,
341 rstn_out => resetn_24_576MHz,
339 342 sin => coarsetime_reg_updated,
340 343 sout => new_coarsetime);
341 344
@@ -344,8 +347,9 BEGIN
344 347 NB_FF_OF_SYNC => 2)
345 348 PORT MAP (
346 349 clk_in => clk25MHz,
350 rstn_in => resetn_25MHz,
347 351 clk_out => clk24_576MHz,
348 rstn => resetn,
352 rstn_out => resetn_24_576MHz,
349 353 sin => soft_reset,
350 354 sout => soft_reset_sync);
351 355
@@ -383,16 +387,17 BEGIN
383 387 NB_FF_OF_SYNC => 2)
384 388 PORT MAP (
385 389 clk_in => clk24_576MHz,
390 rstn_in => resetn_24_576MHz,
386 391 clk_out => clk25MHz,
387 rstn => resetn,
392 rstn_out => resetn_25MHz,
388 393 sin => time_new_49,
389 394 sout => time_new);
390 395
391 396
392 397
393 PROCESS (clk25MHz, resetn)
398 PROCESS (clk25MHz, resetn_25MHz)
394 399 BEGIN -- PROCESS
395 IF resetn = '0' THEN -- asynchronous reset (active low)
400 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
396 401 fine_time_s <= (OTHERS => '0');
397 402 coarse_time_s <= (OTHERS => '0');
398 403 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
@@ -404,7 +409,7 BEGIN
404 409 END PROCESS;
405 410
406 411
407 rstn_LFR_TM <= '0' WHEN resetn = '0' ELSE
412 rstn_LFR_TM <= '0' WHEN resetn_24_576MHz = '0' ELSE
408 413 '0' WHEN soft_reset_sync = '1' ELSE
409 414 '1';
410 415
@@ -433,15 +438,15 BEGIN
433 438 -- HK
434 439 -----------------------------------------------------------------------------
435 440
436 PROCESS (clk25MHz, resetn)
441 PROCESS (clk25MHz, resetn_25MHz)
437 442 CONSTANT BIT_FREQUENCY_UPDATE : INTEGER := 14; -- freq = 2^(16-BIT)
438 -- for each HK, the update frequency is freq/3
439 --
440 -- for 14, the update frequency is
441 -- 4Hz and update for each
442 -- HK is 1.33Hz
443 -- for each HK, the update frequency is freq/3
444 --
445 -- for 14, the update frequency is
446 -- 4Hz and update for each
447 -- HK is 1.33Hz
443 448 BEGIN -- PROCESS
444 IF resetn = '0' THEN -- asynchronous reset (active low)
449 IF resetn_25MHz = '0' THEN -- asynchronous reset (active low)
445 450
446 451 r.HK_temp_0 <= (OTHERS => '0');
447 452 r.HK_temp_1 <= (OTHERS => '0');
@@ -459,13 +464,13 BEGIN
459 464 CASE HK_sel_s IS
460 465 WHEN "00" =>
461 466 r.HK_temp_0 <= HK_sample;
462 HK_sel_s <= "01";
467 HK_sel_s <= "01";
463 468 WHEN "01" =>
464 469 r.HK_temp_1 <= HK_sample;
465 HK_sel_s <= "10";
470 HK_sel_s <= "10";
466 471 WHEN "10" =>
467 472 r.HK_temp_2 <= HK_sample;
468 HK_sel_s <= "00";
473 HK_sel_s <= "00";
469 474 WHEN OTHERS => NULL;
470 475 END CASE;
471 476 END IF;
@@ -489,7 +494,7 BEGIN
489 494 )
490 495 PORT MAP(
491 496 clk => clk25MHz,
492 rstn => resetn,
497 rstn => resetn_25MHz,
493 498
494 499 pre => pre,
495 500 N => N,
@@ -509,4 +514,4 BEGIN
509 514 );
510 515
511 516 DAC_CAL_EN <= DAC_CAL_EN_s;
512 END Behavioral;
517 END Behavioral; No newline at end of file
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@@ -38,22 +38,23 PACKAGE lpp_lfr_management IS
38 38 FIRST_DIVISION : INTEGER;
39 39 NB_SECOND_DESYNC : INTEGER);
40 40 PORT (
41 clk25MHz : IN STD_LOGIC;
42 clk24_576MHz : IN STD_LOGIC;
43 resetn : IN STD_LOGIC;
44 grspw_tick : IN STD_LOGIC;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
48 HK_val : IN STD_LOGIC;
49 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
50 DAC_SDO : OUT STD_LOGIC;
51 DAC_SCK : OUT STD_LOGIC;
52 DAC_SYNC : OUT STD_LOGIC;
53 DAC_CAL_EN : OUT STD_LOGIC;
54 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
55 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
56 LFR_soft_rstn : OUT STD_LOGIC);
41 clk25MHz : IN STD_LOGIC;
42 resetn_25MHz : IN STD_LOGIC;
43 clk24_576MHz : IN STD_LOGIC;
44 resetn_24_576MHz : IN STD_LOGIC;
45 grspw_tick : IN STD_LOGIC;
46 apbi : IN apb_slv_in_type;
47 apbo : OUT apb_slv_out_type;
48 HK_sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
49 HK_val : IN STD_LOGIC;
50 HK_sel : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
51 DAC_SDO : OUT STD_LOGIC;
52 DAC_SCK : OUT STD_LOGIC;
53 DAC_SYNC : OUT STD_LOGIC;
54 DAC_CAL_EN : OUT STD_LOGIC;
55 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
56 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
57 LFR_soft_rstn : OUT STD_LOGIC);
57 58 END COMPONENT;
58 59
59 60 COMPONENT lfr_time_management
@@ -74,7 +75,7 PACKAGE lpp_lfr_management IS
74 75
75 76 COMPONENT coarse_time_counter
76 77 GENERIC (
77 NB_SECOND_DESYNC : INTEGER );
78 NB_SECOND_DESYNC : INTEGER);
78 79 PORT (
79 80 clk : IN STD_LOGIC;
80 81 rstn : IN STD_LOGIC;
@@ -91,8 +92,8 PACKAGE lpp_lfr_management IS
91 92
92 93 COMPONENT fine_time_counter
93 94 GENERIC (
94 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
95 FIRST_DIVISION : INTEGER );
95 WAITING_TIME : STD_LOGIC_VECTOR(15 DOWNTO 0);
96 FIRST_DIVISION : INTEGER);
96 97 PORT (
97 98 clk : IN STD_LOGIC;
98 99 rstn : IN STD_LOGIC;
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