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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_dac_Driver -llpp_apb_functions
25 INPUTFILE=main.c
26 EXEC=BenchDAC_CAL.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_dac_Driver.h"
4
5 int main()
6 {
7 printf("\nDebut Main\n\n");
8 int i;
9 int tablo CAL_SignalData
10
11 DAC_Device* dac0 = openDAC(0);
12
13 printf("\nSTART\n\n");
14
15 while(1)
16 {
17 for (i = 0 ; i < 251 ; i++)
18 {
19 while(!((dac0->ConfigReg & DAC_ready) == DAC_ready));
20 dac0->DataReg = tablo[i];
21 while((dac0->ConfigReg & DAC_ready) == DAC_ready);
22 }
23 }
24 return 0;
25 }
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1 #
2 # Automatically generated make config: don't edit
3 #
4
5 #
6 # Synthesis
7 #
8 # CONFIG_SYN_INFERRED is not set
9 # CONFIG_SYN_STRATIX is not set
10 # CONFIG_SYN_STRATIXII is not set
11 # CONFIG_SYN_STRATIXIII is not set
12 # CONFIG_SYN_CYCLONEIII is not set
13 # CONFIG_SYN_ALTERA is not set
14 # CONFIG_SYN_AXCEL is not set
15 # CONFIG_SYN_PROASIC is not set
16 # CONFIG_SYN_PROASICPLUS is not set
17 CONFIG_SYN_PROASIC3=y
18 # CONFIG_SYN_UT025CRH is not set
19 # CONFIG_SYN_ATC18 is not set
20 # CONFIG_SYN_ATC18RHA is not set
21 # CONFIG_SYN_CUSTOM1 is not set
22 # CONFIG_SYN_EASIC90 is not set
23 # CONFIG_SYN_IHP25 is not set
24 # CONFIG_SYN_IHP25RH is not set
25 # CONFIG_SYN_LATTICE is not set
26 # CONFIG_SYN_ECLIPSE is not set
27 # CONFIG_SYN_PEREGRINE is not set
28 # CONFIG_SYN_RH_LIB18T is not set
29 # CONFIG_SYN_RHUMC is not set
30 # CONFIG_SYN_SMIC13 is not set
31 # CONFIG_SYN_SPARTAN2 is not set
32 # CONFIG_SYN_SPARTAN3 is not set
33 # CONFIG_SYN_SPARTAN3E is not set
34 # CONFIG_SYN_VIRTEX is not set
35 # CONFIG_SYN_VIRTEXE is not set
36 # CONFIG_SYN_VIRTEX2 is not set
37 # CONFIG_SYN_VIRTEX4 is not set
38 # CONFIG_SYN_VIRTEX5 is not set
39 # CONFIG_SYN_UMC is not set
40 # CONFIG_SYN_TSMC90 is not set
41 # CONFIG_SYN_INFER_RAM is not set
42 # CONFIG_SYN_INFER_PADS is not set
43 # CONFIG_SYN_NO_ASYNC is not set
44 # CONFIG_SYN_SCAN is not set
45
46 #
47 # Clock generation
48 #
49 # CONFIG_CLK_INFERRED is not set
50 # CONFIG_CLK_HCLKBUF is not set
51 # CONFIG_CLK_ALTDLL is not set
52 # CONFIG_CLK_LATDLL is not set
53 CONFIG_CLK_PRO3PLL=y
54 # CONFIG_CLK_LIB18T is not set
55 # CONFIG_CLK_RHUMC is not set
56 # CONFIG_CLK_CLKDLL is not set
57 # CONFIG_CLK_DCM is not set
58 CONFIG_CLK_MUL=2
59 CONFIG_CLK_DIV=8
60 CONFIG_OCLK_DIV=2
61 # CONFIG_PCI_SYSCLK is not set
62 CONFIG_LEON3=y
63 CONFIG_PROC_NUM=1
64
65 #
66 # Processor
67 #
68
69 #
70 # Integer unit
71 #
72 CONFIG_IU_NWINDOWS=8
73 # CONFIG_IU_V8MULDIV is not set
74 # CONFIG_IU_SVT is not set
75 CONFIG_IU_LDELAY=1
76 CONFIG_IU_WATCHPOINTS=0
77 # CONFIG_PWD is not set
78 CONFIG_IU_RSTADDR=00000
79
80 #
81 # Floating-point unit
82 #
83 # CONFIG_FPU_ENABLE is not set
84
85 #
86 # Cache system
87 #
88 CONFIG_ICACHE_ENABLE=y
89 CONFIG_ICACHE_ASSO1=y
90 # CONFIG_ICACHE_ASSO2 is not set
91 # CONFIG_ICACHE_ASSO3 is not set
92 # CONFIG_ICACHE_ASSO4 is not set
93 # CONFIG_ICACHE_SZ1 is not set
94 # CONFIG_ICACHE_SZ2 is not set
95 CONFIG_ICACHE_SZ4=y
96 # CONFIG_ICACHE_SZ8 is not set
97 # CONFIG_ICACHE_SZ16 is not set
98 # CONFIG_ICACHE_SZ32 is not set
99 # CONFIG_ICACHE_SZ64 is not set
100 # CONFIG_ICACHE_SZ128 is not set
101 # CONFIG_ICACHE_SZ256 is not set
102 # CONFIG_ICACHE_LZ16 is not set
103 CONFIG_ICACHE_LZ32=y
104 CONFIG_DCACHE_ENABLE=y
105 CONFIG_DCACHE_ASSO1=y
106 # CONFIG_DCACHE_ASSO2 is not set
107 # CONFIG_DCACHE_ASSO3 is not set
108 # CONFIG_DCACHE_ASSO4 is not set
109 # CONFIG_DCACHE_SZ1 is not set
110 # CONFIG_DCACHE_SZ2 is not set
111 CONFIG_DCACHE_SZ4=y
112 # CONFIG_DCACHE_SZ8 is not set
113 # CONFIG_DCACHE_SZ16 is not set
114 # CONFIG_DCACHE_SZ32 is not set
115 # CONFIG_DCACHE_SZ64 is not set
116 # CONFIG_DCACHE_SZ128 is not set
117 # CONFIG_DCACHE_SZ256 is not set
118 # CONFIG_DCACHE_LZ16 is not set
119 CONFIG_DCACHE_LZ32=y
120 # CONFIG_DCACHE_SNOOP is not set
121 CONFIG_CACHE_FIXED=0
122
123 #
124 # MMU
125 #
126 CONFIG_MMU_ENABLE=y
127 # CONFIG_MMU_COMBINED is not set
128 CONFIG_MMU_SPLIT=y
129 # CONFIG_MMU_REPARRAY is not set
130 CONFIG_MMU_REPINCREMENT=y
131 # CONFIG_MMU_I2 is not set
132 # CONFIG_MMU_I4 is not set
133 CONFIG_MMU_I8=y
134 # CONFIG_MMU_I16 is not set
135 # CONFIG_MMU_I32 is not set
136 # CONFIG_MMU_D2 is not set
137 # CONFIG_MMU_D4 is not set
138 CONFIG_MMU_D8=y
139 # CONFIG_MMU_D16 is not set
140 # CONFIG_MMU_D32 is not set
141 CONFIG_MMU_FASTWB=y
142 CONFIG_MMU_PAGE_4K=y
143 # CONFIG_MMU_PAGE_8K is not set
144 # CONFIG_MMU_PAGE_16K is not set
145 # CONFIG_MMU_PAGE_32K is not set
146 # CONFIG_MMU_PAGE_PROG is not set
147
148 #
149 # Debug Support Unit
150 #
151 # CONFIG_DSU_ENABLE is not set
152
153 #
154 # Fault-tolerance
155 #
156
157 #
158 # VHDL debug settings
159 #
160 # CONFIG_IU_DISAS is not set
161 # CONFIG_DEBUG_PC32 is not set
162
163 #
164 # AMBA configuration
165 #
166 CONFIG_AHB_DEFMST=0
167 CONFIG_AHB_RROBIN=y
168 # CONFIG_AHB_SPLIT is not set
169 CONFIG_AHB_IOADDR=FFF
170 CONFIG_APB_HADDR=800
171 # CONFIG_AHB_MON is not set
172
173 #
174 # Debug Link
175 #
176 CONFIG_DSU_UART=y
177 # CONFIG_DSU_JTAG is not set
178
179 #
180 # Peripherals
181 #
182
183 #
184 # Memory controllers
185 #
186
187 #
188 # 8/32-bit PROM/SRAM controller
189 #
190 CONFIG_SRCTRL=y
191 # CONFIG_SRCTRL_8BIT is not set
192 CONFIG_SRCTRL_PROMWS=3
193 CONFIG_SRCTRL_RAMWS=0
194 CONFIG_SRCTRL_IOWS=0
195 # CONFIG_SRCTRL_RMW is not set
196 CONFIG_SRCTRL_SRBANKS1=y
197 # CONFIG_SRCTRL_SRBANKS2 is not set
198 # CONFIG_SRCTRL_SRBANKS3 is not set
199 # CONFIG_SRCTRL_SRBANKS4 is not set
200 # CONFIG_SRCTRL_SRBANKS5 is not set
201 # CONFIG_SRCTRL_BANKSZ0 is not set
202 # CONFIG_SRCTRL_BANKSZ1 is not set
203 # CONFIG_SRCTRL_BANKSZ2 is not set
204 # CONFIG_SRCTRL_BANKSZ3 is not set
205 # CONFIG_SRCTRL_BANKSZ4 is not set
206 # CONFIG_SRCTRL_BANKSZ5 is not set
207 # CONFIG_SRCTRL_BANKSZ6 is not set
208 # CONFIG_SRCTRL_BANKSZ7 is not set
209 # CONFIG_SRCTRL_BANKSZ8 is not set
210 # CONFIG_SRCTRL_BANKSZ9 is not set
211 # CONFIG_SRCTRL_BANKSZ10 is not set
212 # CONFIG_SRCTRL_BANKSZ11 is not set
213 # CONFIG_SRCTRL_BANKSZ12 is not set
214 # CONFIG_SRCTRL_BANKSZ13 is not set
215 CONFIG_SRCTRL_ROMASEL=19
216
217 #
218 # Leon2 memory controller
219 #
220 CONFIG_MCTRL_LEON2=y
221 # CONFIG_MCTRL_8BIT is not set
222 # CONFIG_MCTRL_16BIT is not set
223 # CONFIG_MCTRL_5CS is not set
224 # CONFIG_MCTRL_SDRAM is not set
225
226 #
227 # PC133 SDRAM controller
228 #
229 # CONFIG_SDCTRL is not set
230
231 #
232 # On-chip RAM/ROM
233 #
234 # CONFIG_AHBROM_ENABLE is not set
235 # CONFIG_AHBRAM_ENABLE is not set
236
237 #
238 # Ethernet
239 #
240 # CONFIG_GRETH_ENABLE is not set
241
242 #
243 # CAN
244 #
245 # CONFIG_CAN_ENABLE is not set
246
247 #
248 # PCI
249 #
250 # CONFIG_PCI_SIMPLE_TARGET is not set
251 # CONFIG_PCI_MASTER_TARGET is not set
252 # CONFIG_PCI_ARBITER is not set
253 # CONFIG_PCI_TRACE is not set
254
255 #
256 # Spacewire
257 #
258 # CONFIG_SPW_ENABLE is not set
259
260 #
261 # UARTs, timers and irq control
262 #
263 CONFIG_UART1_ENABLE=y
264 # CONFIG_UA1_FIFO1 is not set
265 # CONFIG_UA1_FIFO2 is not set
266 CONFIG_UA1_FIFO4=y
267 # CONFIG_UA1_FIFO8 is not set
268 # CONFIG_UA1_FIFO16 is not set
269 # CONFIG_UA1_FIFO32 is not set
270 # CONFIG_UART2_ENABLE is not set
271 CONFIG_IRQ3_ENABLE=y
272 # CONFIG_IRQ3_SEC is not set
273 CONFIG_GPT_ENABLE=y
274 CONFIG_GPT_NTIM=2
275 CONFIG_GPT_SW=8
276 CONFIG_GPT_TW=32
277 CONFIG_GPT_IRQ=8
278 CONFIG_GPT_SEPIRQ=y
279 CONFIG_GPT_WDOGEN=y
280 CONFIG_GPT_WDOG=FFFF
281 CONFIG_GRGPIO_ENABLE=y
282 CONFIG_GRGPIO_WIDTH=8
283 CONFIG_GRGPIO_IMASK=0000
284
285 #
286 # VHDL Debugging
287 #
288 # CONFIG_DEBUG_UART is not set
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1 #GRLIB=../..
2 VHDLIB=../..
3 SCRIPTSDIR=$(VHDLIB)/scripts/
4 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
5 TOP=leon3mp
6 BOARD=em-LeonLPP-A3PE3kL-v3-core1
7 include $(GRLIB)/boards/$(BOARD)/Makefile.inc
8 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
9 UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
10 QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
11 EFFORT=high
12 XSTOPT=
13 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
14 #VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
15 VHDLSYNFILES=config.vhd leon3mp.vhd
16 #VHDLSIMFILES=testbench.vhd
17 #SIMTOP=testbench
18 #SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
19 #SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
20 PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
21 BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
22 CLEAN=soft-clean
23
24 TECHLIBS = proasic3e
25
26 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
27 tmtc openchip hynix ihp gleichmann micron usbhc
28
29 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
30 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
31 ./amba_lcd_16x2_ctrlr \
32 ./general_purpose/lpp_AMR \
33 ./general_purpose/lpp_balise \
34 ./general_purpose/lpp_delay \
35 ./lpp_bootloader \
36 ./lpp_cna \
37 ./lpp_uart \
38 ./lpp_usb \
39
40 FILESKIP = i2cmst.vhd \
41 lpp_lfr_ms.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_MULTI_DIODE.vhd \
44 Top_MatrixSpec.vhd \
45 APB_FFT.vhd
46
47 include $(GRLIB)/bin/Makefile
48 include $(GRLIB)/software/leon3/Makefile
49
50 ################## project specific targets ##########################
51
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (3);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181
182 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
45 ENTITY leon3mp IS
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
54 );
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
60 errorn : OUT STD_ULOGIC;
61
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC; -- JCPE --TODO
91
92 -- ADC --------------------------------------------------------------------
93 bias_fail_sw : OUT STD_LOGIC;
94 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
95 ADC_smpclk : OUT STD_LOGIC;
96 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
97
98 ---------------------------------------------------------------------------
99 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
100 );
101 END;
102
103 ARCHITECTURE Behavioral OF leon3mp IS
104
105 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
106 -- CFG_GRETH+CFG_AHB_JTAG;
107 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
108 CFG_AHB_UART
109 +2;
110 -- 1 is for the SpaceWire module grspw, which is a master
111 -- 1 is for the LFR
112
113 CONSTANT maxahbm : INTEGER := maxahbmsp;
114
115 --Clk & Rst g�n�
116 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL resetnl : STD_ULOGIC;
119 SIGNAL clk2x : STD_ULOGIC;
120 SIGNAL lclk2x : STD_ULOGIC;
121 SIGNAL lclk25MHz : STD_ULOGIC;
122 SIGNAL lclk50MHz : STD_ULOGIC;
123 SIGNAL lclk100MHz : STD_ULOGIC;
124 SIGNAL clkm : STD_ULOGIC;
125 SIGNAL rstn : STD_ULOGIC;
126 SIGNAL rstraw : STD_ULOGIC;
127 SIGNAL pciclk : STD_ULOGIC;
128 SIGNAL sdclkl : STD_ULOGIC;
129 SIGNAL cgi : clkgen_in_type;
130 SIGNAL cgo : clkgen_out_type;
131 --- AHB / APB
132 SIGNAL apbi : apb_slv_in_type;
133 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
134 SIGNAL ahbsi : ahb_slv_in_type;
135 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
136 SIGNAL ahbmi : ahb_mst_in_type;
137 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
138 --UART
139 SIGNAL ahbuarti : uart_in_type;
140 SIGNAL ahbuarto : uart_out_type;
141 SIGNAL apbuarti : uart_in_type;
142 SIGNAL apbuarto : uart_out_type;
143 --MEM CTRLR
144 SIGNAL memi : memory_in_type;
145 SIGNAL memo : memory_out_type;
146 SIGNAL wpo : wprot_out_type;
147 SIGNAL sdo : sdram_out_type;
148 SIGNAL ramcs : STD_ULOGIC;
149 --IRQ
150 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
151 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
152 --Timer
153 SIGNAL gpti : gptimer_in_type;
154 SIGNAL gpto : gptimer_out_type;
155 --GPIO
156 SIGNAL gpioi : gpio_in_type;
157 SIGNAL gpioo : gpio_out_type;
158 --DSU
159 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
160 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
161 SIGNAL dsui : dsu_in_type;
162 SIGNAL dsuo : dsu_out_type;
163
164 ---------------------------------------------------------------------
165 --- AJOUT TEST ------------------------Signaux----------------------
166 ---------------------------------------------------------------------
167
168 ---------------------------------------------------------------------
169 CONSTANT IOAEN : INTEGER := CFG_CAN;
170 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
171
172 -- time management signal
173 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
174 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
175
176 -- Spacewire signals
177 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
178 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
179 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
180 SIGNAL spw_rxtxclk : STD_ULOGIC;
181 SIGNAL spw_rxclkn : STD_ULOGIC;
182 SIGNAL spw_clk : STD_LOGIC;
183 SIGNAL swni : grspw_in_type; -- PLE
184 SIGNAL swno : grspw_out_type; -- PLE
185 SIGNAL clkmn : STD_ULOGIC; -- PLE
186 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
187
188 -- AD Converter RHF1401
189 SIGNAL sample : Samples14v(7 DOWNTO 0);
190 SIGNAL sample_val : STD_LOGIC;
191 -----------------------------------------------------------------------------
192 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(7 DOWNTO 0);
193
194 BEGIN
195
196
197 ----------------------------------------------------------------------
198 --- Reset and Clock generation -------------------------------------
199 ----------------------------------------------------------------------
200
201 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
202 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
203
204 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
205
206
207 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
208
209 clkgen0 : clkgen -- clock generator
210 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
211 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
212 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
213
214 PROCESS(lclk100MHz)
215 BEGIN
216 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
217 lclk50MHz <= NOT lclk50MHz;
218 END IF;
219 END PROCESS;
220
221 PROCESS(lclk50MHz)
222 BEGIN
223 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
224 lclk25MHz <= NOT lclk25MHz;
225 END IF;
226 END PROCESS;
227
228 lclk2x <= lclk50MHz;
229 spw_clk <= lclk50MHz;
230
231 ----------------------------------------------------------------------
232 --- LEON3 processor / DSU / IRQ ------------------------------------
233 ----------------------------------------------------------------------
234
235 l3 : IF CFG_LEON3 = 1 GENERATE
236 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
237 u0 : leon3s -- LEON3 processor
238 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
239 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
240 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
241 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
242 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
243 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
244 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
245 irqi(i), irqo(i), dbgi(i), dbgo(i));
246 END GENERATE;
247 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
248
249 dsugen : IF CFG_DSU = 1 GENERATE
250 dsu0 : dsu3 -- LEON3 Debug Support Unit
251 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
252 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
253 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
254 dsui.enable <= '1';
255 dsui.break <= '0';
256 led(2) <= dsuo.active;
257 END GENERATE;
258 END GENERATE;
259
260 nodsu : IF CFG_DSU = 0 GENERATE
261 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
262 END GENERATE;
263
264 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
265 irqctrl0 : irqmp -- interrupt controller
266 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
267 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
268 END GENERATE;
269 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
270 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
271 irqi(i).irl <= "0000";
272 END GENERATE;
273 apbo(2) <= apb_none;
274 END GENERATE;
275
276 ----------------------------------------------------------------------
277 --- Memory controllers ---------------------------------------------
278 ----------------------------------------------------------------------
279 memctrlr : mctrl GENERIC MAP (
280 hindex => 0,
281 pindex => 0,
282 paddr => 0,
283 srbanks => 1
284 )
285 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
286
287 memi.brdyn <= '1';
288 memi.bexcn <= '1';
289 memi.writen <= '1';
290 memi.wrn <= "1111";
291 memi.bwidth <= "10";
292
293 bdr : FOR i IN 0 TO 3 GENERATE
294 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
295 PORT MAP (
296 data(31-i*8 DOWNTO 24-i*8),
297 memo.data(31-i*8 DOWNTO 24-i*8),
298 memo.bdrive(i),
299 memi.data(31-i*8 DOWNTO 24-i*8));
300 END GENERATE;
301
302 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
303 PORT MAP (address, memo.address(21 DOWNTO 2));
304
305 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
306 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
307 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
308 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
309 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
310 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
311 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
312
313 ----------------------------------------------------------------------
314 --- AHB CONTROLLER -------------------------------------------------
315 ----------------------------------------------------------------------
316 ahb0 : ahbctrl -- AHB arbiter/multiplexer
317 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
318 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
319 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
320 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
321
322 ----------------------------------------------------------------------
323 --- AHB UART -------------------------------------------------------
324 ----------------------------------------------------------------------
325 dcomgen : IF CFG_AHB_UART = 1 GENERATE
326 dcom0 : ahbuart
327 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
328 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
329 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
330 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
331 led(0) <= NOT ahbuarti.rxd;
332 led(1) <= NOT ahbuarto.txd;
333 END GENERATE;
334 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
335
336 ----------------------------------------------------------------------
337 --- APB Bridge -----------------------------------------------------
338 ----------------------------------------------------------------------
339 apb0 : apbctrl -- AHB/APB bridge
340 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
341 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
342
343 ----------------------------------------------------------------------
344 --- GPT Timer ------------------------------------------------------
345 ----------------------------------------------------------------------
346 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
347 timer0 : gptimer -- timer unit
348 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
349 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
350 nbits => CFG_GPT_TW)
351 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
352 gpti.dhalt <= dsuo.tstop;
353 gpti.extclk <= '0';
354 END GENERATE;
355 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
356
357
358 ----------------------------------------------------------------------
359 --- APB UART -------------------------------------------------------
360 ----------------------------------------------------------------------
361 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
362 uart1 : apbuart -- UART 1
363 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
364 fifosize => CFG_UART1_FIFO)
365 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
366 apbuarti.rxd <= urxd1;
367 apbuarti.extclk <= '0';
368 utxd1 <= apbuarto.txd;
369 apbuarti.ctsn <= '0';
370 END GENERATE;
371 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
372
373 -------------------------------------------------------------------------------
374 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
375 -------------------------------------------------------------------------------
376 apb_lfr_time_management_1: apb_lfr_time_management
377 GENERIC MAP (
378 pindex => 6,
379 paddr => 6,
380 pmask => 16#fff#,
381 pirq => 12)
382 PORT MAP (
383 clk25MHz => clkm,
384 clk49_152MHz => clk49_152MHz,
385 resetn => rstn,
386 grspw_tick => swno.tickout,
387 apbi => apbi,
388 apbo => apbo(6),
389 coarse_time => coarse_time,
390 fine_time => fine_time);
391
392 -----------------------------------------------------------------------
393 --- SpaceWire --------------------------------------------------------
394 -----------------------------------------------------------------------
395
396 spw_rxtxclk <= spw_clk;
397 spw_rxclkn <= NOT spw_rxtxclk;
398
399 -- PADS for SPW1
400 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw1_din, dtmp(0));
402 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw1_sin, stmp(0));
404 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw1_dout, swno.d(0));
406 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
407 PORT MAP (spw1_sout, swno.s(0));
408 -- PADS FOR SPW2
409 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
410 PORT MAP (spw2_din, dtmp(1));
411 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
412 PORT MAP (spw2_sin, stmp(1));
413 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
414 PORT MAP (spw2_dout, swno.d(1));
415 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
416 PORT MAP (spw2_sout, swno.s(1));
417
418 -- GRSPW PHY
419 --spw1_input: if CFG_SPW_GRSPW = 1 generate
420 spw_inputloop : FOR j IN 0 TO 1 GENERATE
421 spw_phy0 : grspw_phy
422 GENERIC MAP(
423 tech => fabtech,
424 rxclkbuftype => 1,
425 scantest => 0)
426 PORT MAP(
427 rxrst => swno.rxrst,
428 di => dtmp(j),
429 si => stmp(j),
430 rxclko => spw_rxclk(j),
431 do => swni.d(j),
432 ndo => swni.nd(j*5+4 DOWNTO j*5),
433 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
434 END GENERATE spw_inputloop;
435
436 -- SPW core
437 sw0 : grspwm
438 GENERIC MAP(
439 tech => apa3e,
440 hindex => 1,
441 pindex => 5,
442 paddr => 5,
443 pirq => 11,
444 sysfreq => 25000, -- CPU_FREQ
445 rmap => 1,
446 rmapcrc => 1,
447 fifosize1 => 16,
448 fifosize2 => 16,
449 rxclkbuftype => 1,
450 rxunaligned => 0,
451 rmapbufs => 4,
452 ft => 0,
453 netlist => 0,
454 ports => 2,
455 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
456 memtech => apa3e,
457 destkey => 2,
458 spwcore => 1
459 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
460 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
461 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
462 )
463 PORT MAP(rstn, clkm, spw_rxclk(0),
464 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
465 ahbmi, ahbmo(1), apbi, apbo(5),
466 swni, swno);
467
468 swni.tickin <= '0';
469 swni.rmapen <= '1';
470 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
471 swni.tickinraw <= '0';
472 swni.timein <= (OTHERS => '0');
473 swni.dcrstval <= (OTHERS => '0');
474 swni.timerrstval <= (OTHERS => '0');
475
476 -------------------------------------------------------------------------------
477 -- LFR
478 -------------------------------------------------------------------------------
479 lpp_lfr_1 : lpp_lfr
480 GENERIC MAP (
481 Mem_use => use_RAM,
482 nb_data_by_buffer_size => 32,
483 nb_word_by_buffer_size => 30,
484 nb_snapshot_param_size => 32,
485 delta_vector_size => 32,
486 delta_vector_size_f0_2 => 7, -- log2(96)
487 pindex => 15,
488 paddr => 15,
489 pmask => 16#fff#,
490 pirq_ms => 6,
491 pirq_wfp => 14,
492 hindex => 2,
493 top_lfr_version => X"00000005")
494 PORT MAP (
495 clk => clkm,
496 rstn => rstn,
497 sample_B => sample(2 DOWNTO 0),
498 sample_E => sample(7 DOWNTO 3),
499 sample_val => sample_val,
500 apbi => apbi,
501 apbo => apbo(15),
502 ahbi => ahbmi,
503 ahbo => ahbmo(2),
504 coarse_time => coarse_time,
505 fine_time => fine_time,
506 data_shaping_BW => bias_fail_sw);
507
508 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
509 GENERIC MAP (
510 ChanelCount => 8,
511 ncycle_cnv_high => 79,
512 ncycle_cnv => 500)
513 PORT MAP (
514 cnv_clk => clk49_152MHz,
515 cnv_rstn => rstn,
516 cnv => ADC_smpclk,
517 clk => clkm,
518 rstn => rstn,
519 ADC_data => ADC_data,
520 ADC_nOE => ADC_OEB_bar_CH,
521 sample => sample,
522 sample_val => sample_val);
523
524 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
38 USE work.config.ALL;
39 LIBRARY lpp;
40 USE lpp.lpp_memory.ALL;
41 USE lpp.lpp_ad_conv.ALL;
42 USE lpp.lpp_lfr_pkg.ALL;
43 USE lpp.iir_filter.ALL;
44 USE lpp.general_purpose.ALL;
45 USE lpp.lpp_lfr_time_management.ALL;
46
47 ENTITY MINI_LFR_top IS
48
49 PORT (
50 clk_50 : IN STD_LOGIC;
51 clk_49 : IN STD_LOGIC;
52 reset : IN STD_LOGIC;
53 --BPs
54 BP0 : IN STD_LOGIC;
55 BP1 : IN STD_LOGIC;
56 --LEDs
57 LED0 : OUT STD_LOGIC;
58 LED1 : OUT STD_LOGIC;
59 LED2 : OUT STD_LOGIC;
60 --UARTs
61 TXD1 : IN STD_LOGIC;
62 RXD1 : OUT STD_LOGIC;
63 nCTS1 : OUT STD_LOGIC;
64 nRTS1 : IN STD_LOGIC;
65
66 TXD2 : IN STD_LOGIC;
67 RXD2 : OUT STD_LOGIC;
68 nCTS2 : OUT STD_LOGIC;
69 nDTR2 : IN STD_LOGIC;
70 nRTS2 : IN STD_LOGIC;
71 nDCD2 : OUT STD_LOGIC;
72
73 --EXT CONNECTOR
74 IO0 : INOUT STD_LOGIC;
75 IO1 : INOUT STD_LOGIC;
76 IO2 : INOUT STD_LOGIC;
77 IO3 : INOUT STD_LOGIC;
78 IO4 : INOUT STD_LOGIC;
79 IO5 : INOUT STD_LOGIC;
80 IO6 : INOUT STD_LOGIC;
81 IO7 : INOUT STD_LOGIC;
82 IO8 : INOUT STD_LOGIC;
83 IO9 : INOUT STD_LOGIC;
84 IO10 : INOUT STD_LOGIC;
85 IO11 : INOUT STD_LOGIC;
86
87 --SPACE WIRE
88 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_SOUT : OUT STD_LOGIC;
97 -- MINI LFR ADC INPUTS
98 ADC_nCS : OUT STD_LOGIC;
99 ADC_CLK : OUT STD_LOGIC;
100 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101
102 -- SRAM
103 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_CE : OUT STD_LOGIC;
105 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 );
110
111 END MINI_LFR_top;
112
113
114 ARCHITECTURE beh OF MINI_LFR_top IS
115
116 COMPONENT leon3_soc
117 GENERIC (
118 fabtech : INTEGER;
119 memtech : INTEGER;
120 padtech : INTEGER;
121 clktech : INTEGER;
122 disas : INTEGER;
123 dbguart : INTEGER;
124 pclow : INTEGER);
125 PORT (
126 clk100MHz : IN STD_ULOGIC;
127 clk49_152MHz : IN STD_ULOGIC;
128 reset : IN STD_ULOGIC;
129 errorn : OUT STD_ULOGIC;
130 ahbrxd : IN STD_ULOGIC;
131 ahbtxd : OUT STD_ULOGIC;
132 urxd1 : IN STD_ULOGIC;
133 utxd1 : OUT STD_ULOGIC;
134 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
135 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 nSRAM_BE0 : OUT STD_LOGIC;
137 nSRAM_BE1 : OUT STD_LOGIC;
138 nSRAM_BE2 : OUT STD_LOGIC;
139 nSRAM_BE3 : OUT STD_LOGIC;
140 nSRAM_WE : OUT STD_LOGIC;
141 nSRAM_CE : OUT STD_LOGIC;
142 nSRAM_OE : OUT STD_LOGIC;
143 spw1_din : IN STD_LOGIC;
144 spw1_sin : IN STD_LOGIC;
145 spw1_dout : OUT STD_LOGIC;
146 spw1_sout : OUT STD_LOGIC;
147 spw2_din : IN STD_LOGIC;
148 spw2_sin : IN STD_LOGIC;
149 spw2_dout : OUT STD_LOGIC;
150 spw2_sout : OUT STD_LOGIC;
151 apbi_wfp : OUT apb_slv_in_type;
152 apbo_wfp : IN apb_slv_out_type;
153 ahbi_wfp : OUT AHB_Mst_In_Type;
154 ahbo_wfp : IN AHB_Mst_Out_Type;
155 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0));
157 END COMPONENT;
158
159 BEGIN -- beh
160
161 PROCESS (clk_50, reset)
162 BEGIN -- PROCESS
163 IF reset = '0' THEN -- asynchronous reset (active low)
164 LED0 <= '0';
165 LED1 <= '0';
166 LED2 <= '0';
167 ELSIF clk_50'event AND clk_50 = '1' THEN -- rising clock edge
168 LED0 <= '0';
169 LED1 <= '1';
170 LED2 <= BP0;
171 END IF;
172 END PROCESS;
173
174 --UARTs
175 RXD1 <= '0';
176 nCTS1 <= '0';
177 RXD2 <= '0';
178 nCTS2 <= '0';
179 nDCD2 <= '0';
180
181 --EXT CONNECTOR
182 IO0 <= clk_49;
183 IO1 <= clk_50;
184
185 IO2 <= SPW_NOM_DIN OR
186 SPW_NOM_SIN OR
187 SPW_RED_DIN OR
188 SPW_RED_SIN;
189
190 IO3 <= ADC_SDO(0);
191 IO4 <= ADC_SDO(1);
192 IO5 <= ADC_SDO(2);
193 IO6 <= ADC_SDO(3);
194 IO7 <= ADC_SDO(4);
195 IO8 <= ADC_SDO(5);
196 IO9 <= ADC_SDO(6);
197 IO10 <= ADC_SDO(7);
198 IO11 <= BP1 OR TXD1 OR TXD2 OR nDTR2 OR nRTS2 OR nRTS1;
199
200 --SPACE WIRE
201 SPW_EN <= '0'; -- 0 => off
202 SPW_NOM_DOUT <= '0';
203 SPW_NOM_SOUT <= '0';
204 SPW_RED_DOUT <= '0';
205 SPW_RED_SOUT <= '0';
206 ADC_nCS <= '0';
207 ADC_CLK <= '0';
208
209 -- SRAM
210 SRAM_nWE <= '1';
211 SRAM_CE <= '0';
212 SRAM_nOE <= '1';
213 SRAM_nBE <= (OTHERS => '1');
214 SRAM_A <= (OTHERS => '0');
215 SRAM_DQ <= (OTHERS => '0');
216
217
218 leon3mp_1: leon3_soc
219 GENERIC MAP (
220 fabtech => fabtech,
221 memtech => memtech,
222 padtech => padtech,
223 clktech => clktech,
224 disas => disas,
225 dbguart => dbguart,
226 pclow => pclow)
227 PORT MAP (
228 clk100MHz => clk100MHz,
229 clk49_152MHz => clk49_152MHz,
230 reset => reset,
231 errorn => errorn,
232 ahbrxd => ahbrxd,
233 ahbtxd => ahbtxd,
234 urxd1 => urxd1,
235 utxd1 => utxd1,
236 address => address,
237 data => data,
238 nSRAM_BE0 => nSRAM_BE0,
239 nSRAM_BE1 => nSRAM_BE1,
240 nSRAM_BE2 => nSRAM_BE2,
241 nSRAM_BE3 => nSRAM_BE3,
242 nSRAM_WE => nSRAM_WE,
243 nSRAM_CE => nSRAM_CE,
244 nSRAM_OE => nSRAM_OE,
245 spw1_din => spw1_din,
246 spw1_sin => spw1_sin,
247 spw1_dout => spw1_dout,
248 spw1_sout => spw1_sout,
249 spw2_din => spw2_din,
250 spw2_sin => spw2_sin,
251 spw2_dout => spw2_dout,
252 spw2_sout => spw2_sout,
253 apbi_wfp => apbi_wfp,
254 apbo_wfp => apbo_wfp,
255 ahbi_wfp => ahbi_wfp,
256 ahbo_wfp => ahbo_wfp,
257 coarse_time => coarse_time,
258 fine_time => fine_time);
259
260
261 END beh;
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1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd \
14 config.vhd \
15 leon3_soc.vhd
16
17 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
18 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
19 CLEAN=soft-clean
20
21 TECHLIBS = proasic3e
22
23 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
24 tmtc openchip hynix ihp gleichmann micron usbhc
25
26 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
27 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
28 ./amba_lcd_16x2_ctrlr \
29 ./general_purpose/lpp_AMR \
30 ./general_purpose/lpp_balise \
31 ./general_purpose/lpp_delay \
32 ./dsp/lpp_fft \
33 ./lpp_bootloader \
34 ./lpp_cna \
35 ./lpp_demux \
36 ./lpp_matrix \
37 ./lpp_uart \
38 ./lpp_usb \
39 ./lpp_Header \
40
41 FILESKIP = i2cmst.vhd \
42 APB_MULTI_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd
44
45 include $(GRLIB)/bin/Makefile
46 include $(GRLIB)/software/leon3/Makefile
47
48 ################## project specific targets ##########################
49
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design test bench configuration
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 ------------------------------------------------------------------------------
15
16
17 library techmap;
18 use techmap.gencomp.all;
19
20 package config is
21
22
23 -- Technology and synthesis options
24 constant CFG_FABTECH : integer := apa3e;
25 constant CFG_MEMTECH : integer := apa3e;
26 constant CFG_PADTECH : integer := inferred;
27 constant CFG_NOASYNC : integer := 0;
28 constant CFG_SCAN : integer := 0;
29
30 -- Clock generator
31 constant CFG_CLKTECH : integer := inferred;
32 constant CFG_CLKMUL : integer := (1);
33 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
34 constant CFG_OCLKDIV : integer := (1);
35 constant CFG_PCIDLL : integer := 0;
36 constant CFG_PCISYSCLK: integer := 0;
37 constant CFG_CLK_NOFB : integer := 0;
38
39 -- LEON3 processor core
40 constant CFG_LEON3 : integer := 1;
41 constant CFG_NCPU : integer := (1);
42 --constant CFG_NWIN : integer := (7); -- PLE
43 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
44 constant CFG_V8 : integer := 0;
45 constant CFG_MAC : integer := 0;
46 constant CFG_SVT : integer := 0;
47 constant CFG_RSTADDR : integer := 16#00000#;
48 constant CFG_LDDEL : integer := (1);
49 constant CFG_NWP : integer := (0);
50 constant CFG_PWD : integer := 1*2;
51 constant CFG_FPU : integer := 8 + 16 * 0; -- 8 => grfpu-light, + 16 * 1 => netlist
52 --constant CFG_FPU : integer := 8 + 16 * 1; -- previous value 0 + 16*0 PLE
53 constant CFG_GRFPUSH : integer := 0;
54 constant CFG_ICEN : integer := 1;
55 constant CFG_ISETS : integer := 1;
56 constant CFG_ISETSZ : integer := 4;
57 constant CFG_ILINE : integer := 4;
58 constant CFG_IREPL : integer := 0;
59 constant CFG_ILOCK : integer := 0;
60 constant CFG_ILRAMEN : integer := 0;
61 constant CFG_ILRAMADDR: integer := 16#8E#;
62 constant CFG_ILRAMSZ : integer := 1;
63 constant CFG_DCEN : integer := 1;
64 constant CFG_DSETS : integer := 1;
65 constant CFG_DSETSZ : integer := 4;
66 constant CFG_DLINE : integer := 4;
67 constant CFG_DREPL : integer := 0;
68 constant CFG_DLOCK : integer := 0;
69 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
70 constant CFG_DFIXED : integer := 16#00F3#;
71 constant CFG_DLRAMEN : integer := 0;
72 constant CFG_DLRAMADDR: integer := 16#8F#;
73 constant CFG_DLRAMSZ : integer := 1;
74 constant CFG_MMUEN : integer := 0;
75 constant CFG_ITLBNUM : integer := 2;
76 constant CFG_DTLBNUM : integer := 2;
77 constant CFG_TLB_TYPE : integer := 1 + 0*2;
78 constant CFG_TLB_REP : integer := 1;
79 constant CFG_DSU : integer := 1;
80 constant CFG_ITBSZ : integer := 0;
81 constant CFG_ATBSZ : integer := 0;
82 constant CFG_LEON3FT_EN : integer := 0;
83 constant CFG_IUFT_EN : integer := 0;
84 constant CFG_FPUFT_EN : integer := 0;
85 constant CFG_RF_ERRINJ : integer := 0;
86 constant CFG_CACHE_FT_EN : integer := 0;
87 constant CFG_CACHE_ERRINJ : integer := 0;
88 constant CFG_LEON3_NETLIST: integer := 0;
89 constant CFG_DISAS : integer := 0 + 0;
90 constant CFG_PCLOW : integer := 2;
91
92 -- AMBA settings
93 constant CFG_DEFMST : integer := (0);
94 constant CFG_RROBIN : integer := 1;
95 constant CFG_SPLIT : integer := 0;
96 constant CFG_AHBIO : integer := 16#FFF#;
97 constant CFG_APBADDR : integer := 16#800#;
98 constant CFG_AHB_MON : integer := 0;
99 constant CFG_AHB_MONERR : integer := 0;
100 constant CFG_AHB_MONWAR : integer := 0;
101
102 -- DSU UART
103 constant CFG_AHB_UART : integer := 1;
104
105 -- JTAG based DSU interface
106 constant CFG_AHB_JTAG : integer := 0;
107
108 -- Ethernet DSU
109 constant CFG_DSU_ETH : integer := 0 + 0;
110 constant CFG_ETH_BUF : integer := 1;
111 constant CFG_ETH_IPM : integer := 16#C0A8#;
112 constant CFG_ETH_IPL : integer := 16#0033#;
113 constant CFG_ETH_ENM : integer := 16#00007A#;
114 constant CFG_ETH_ENL : integer := 16#CC0001#;
115
116 -- LEON2 memory controller
117 constant CFG_MCTRL_LEON2 : integer := 1;
118 constant CFG_MCTRL_RAM8BIT : integer := 0;
119 constant CFG_MCTRL_RAM16BIT : integer := 0;
120 constant CFG_MCTRL_5CS : integer := 0;
121 constant CFG_MCTRL_SDEN : integer := 0;
122 constant CFG_MCTRL_SEPBUS : integer := 0;
123 constant CFG_MCTRL_INVCLK : integer := 0;
124 constant CFG_MCTRL_SD64 : integer := 0;
125 constant CFG_MCTRL_PAGE : integer := 0 + 0;
126
127 -- SSRAM controller
128 constant CFG_SSCTRL : integer := 0;
129 constant CFG_SSCTRLP16 : integer := 0;
130
131 -- AHB ROM
132 constant CFG_AHBROMEN : integer := 0;
133 constant CFG_AHBROPIP : integer := 0;
134 constant CFG_AHBRODDR : integer := 16#000#;
135 constant CFG_ROMADDR : integer := 16#000#;
136 constant CFG_ROMMASK : integer := 16#E00# + 16#000#;
137
138 -- AHB RAM
139 constant CFG_AHBRAMEN : integer := 0;
140 constant CFG_AHBRSZ : integer := 1;
141 constant CFG_AHBRADDR : integer := 16#A00#;
142
143 -- Gaisler Ethernet core
144 constant CFG_GRETH : integer := 0;
145 constant CFG_GRETH1G : integer := 0;
146 constant CFG_ETH_FIFO : integer := 8;
147
148 -- CAN 2.0 interface
149 constant CFG_CAN : integer := 0;
150 constant CFG_CANIO : integer := 16#0#;
151 constant CFG_CANIRQ : integer := 0;
152 constant CFG_CANLOOP : integer := 0;
153 constant CFG_CAN_SYNCRST : integer := 0;
154 constant CFG_CANFT : integer := 0;
155
156 -- UART 1
157 constant CFG_UART1_ENABLE : integer := 1;
158 constant CFG_UART1_FIFO : integer := 1;
159
160 -- LEON3 interrupt controller
161 constant CFG_IRQ3_ENABLE : integer := 1;
162
163 -- Modular timer
164 constant CFG_GPT_ENABLE : integer := 1;
165 constant CFG_GPT_NTIM : integer := (2);
166 constant CFG_GPT_SW : integer := (8);
167 constant CFG_GPT_TW : integer := (32);
168 constant CFG_GPT_IRQ : integer := (8);
169 constant CFG_GPT_SEPIRQ : integer := 1;
170 constant CFG_GPT_WDOGEN : integer := 0;
171 constant CFG_GPT_WDOG : integer := 16#0#;
172
173 -- GPIO port
174 constant CFG_GRGPIO_ENABLE : integer := 1;
175 constant CFG_GRGPIO_IMASK : integer := 16#0000#;
176 constant CFG_GRGPIO_WIDTH : integer := (7);
177
178 -- GRLIB debugging
179 constant CFG_DUART : integer := 0;
180
181 -- SPACEWIRE
182 constant CFG_SPW_ENABLE : integer := 0;
183
184
185 end;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
36 USE work.config.ALL;
37 LIBRARY lpp;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.iir_filter.ALL;
42 USE lpp.general_purpose.ALL;
43 USE lpp.lpp_lfr_time_management.ALL;
44
45 ENTITY leon3_soc IS
46 GENERIC (
47 fabtech : INTEGER := CFG_FABTECH;
48 memtech : INTEGER := CFG_MEMTECH;
49 padtech : INTEGER := CFG_PADTECH;
50 clktech : INTEGER := CFG_CLKTECH;
51 disas : INTEGER := CFG_DISAS; -- Enable disassembly to console
52 dbguart : INTEGER := CFG_DUART; -- Print UART on console
53 pclow : INTEGER := CFG_PCLOW
54 );
55 PORT (
56 clk100MHz : IN STD_ULOGIC;
57 clk49_152MHz : IN STD_ULOGIC;
58 reset : IN STD_ULOGIC;
59
60 errorn : OUT STD_ULOGIC;
61
62 -- UART AHB ---------------------------------------------------------------
63 ahbrxd : IN STD_ULOGIC; -- DSU rx data
64 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
65
66 -- UART APB ---------------------------------------------------------------
67 urxd1 : IN STD_ULOGIC; -- UART1 rx data
68 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
69
70 -- RAM --------------------------------------------------------------------
71 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
72 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
73 nSRAM_BE0 : OUT STD_LOGIC;
74 nSRAM_BE1 : OUT STD_LOGIC;
75 nSRAM_BE2 : OUT STD_LOGIC;
76 nSRAM_BE3 : OUT STD_LOGIC;
77 nSRAM_WE : OUT STD_LOGIC;
78 nSRAM_CE : OUT STD_LOGIC;
79 nSRAM_OE : OUT STD_LOGIC;
80
81 -- SPW --------------------------------------------------------------------
82 spw1_din : IN STD_LOGIC; -- PLE
83 spw1_sin : IN STD_LOGIC; -- PLE
84 spw1_dout : OUT STD_LOGIC; -- PLE
85 spw1_sout : OUT STD_LOGIC; -- PLE
86
87 spw2_din : IN STD_LOGIC; -- JCPE --TODO
88 spw2_sin : IN STD_LOGIC; -- JCPE --TODO
89 spw2_dout : OUT STD_LOGIC; -- JCPE --TODO
90 spw2_sout : OUT STD_LOGIC;
91
92 -- WAVEFORM PICKER --------------------------------------------------------
93 apbi_wfp : OUT apb_slv_in_type;
94 apbo_wfp : IN apb_slv_out_type;
95 ahbi_wfp : OUT AHB_Mst_In_Type;
96 ahbo_wfp : IN AHB_Mst_Out_Type;
97 -- TIME -------------------------------------------------------------------
98 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
99 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
100
101 );
102 END;
103
104 ARCHITECTURE Behavioral OF leon3_soc IS
105
106 --constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
107 -- CFG_GRETH+CFG_AHB_JTAG;
108 CONSTANT maxahbmsp : INTEGER := CFG_NCPU+
109 CFG_AHB_UART
110 +2;
111 -- 1 is for the SpaceWire module grspw, which is a master
112 -- 1 is for the LFR
113
114 CONSTANT maxahbm : INTEGER := maxahbmsp;
115
116 --Clk & Rst g�n�
117 SIGNAL vcc : STD_LOGIC_VECTOR(4 DOWNTO 0);
118 SIGNAL gnd : STD_LOGIC_VECTOR(4 DOWNTO 0);
119 SIGNAL resetnl : STD_ULOGIC;
120 SIGNAL clk2x : STD_ULOGIC;
121 SIGNAL lclk2x : STD_ULOGIC;
122 SIGNAL lclk25MHz : STD_ULOGIC;
123 SIGNAL lclk50MHz : STD_ULOGIC;
124 SIGNAL lclk100MHz : STD_ULOGIC;
125 SIGNAL clkm : STD_ULOGIC;
126 SIGNAL rstn : STD_ULOGIC;
127 SIGNAL rstraw : STD_ULOGIC;
128 SIGNAL pciclk : STD_ULOGIC;
129 SIGNAL sdclkl : STD_ULOGIC;
130 SIGNAL cgi : clkgen_in_type;
131 SIGNAL cgo : clkgen_out_type;
132 --- AHB / APB
133 SIGNAL apbi : apb_slv_in_type;
134 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
135 SIGNAL ahbsi : ahb_slv_in_type;
136 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
137 SIGNAL ahbmi : ahb_mst_in_type;
138 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
139 --UART
140 SIGNAL ahbuarti : uart_in_type;
141 SIGNAL ahbuarto : uart_out_type;
142 SIGNAL apbuarti : uart_in_type;
143 SIGNAL apbuarto : uart_out_type;
144 --MEM CTRLR
145 SIGNAL memi : memory_in_type;
146 SIGNAL memo : memory_out_type;
147 SIGNAL wpo : wprot_out_type;
148 SIGNAL sdo : sdram_out_type;
149 SIGNAL ramcs : STD_ULOGIC;
150 --IRQ
151 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
152 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
153 --Timer
154 SIGNAL gpti : gptimer_in_type;
155 SIGNAL gpto : gptimer_out_type;
156 --GPIO
157 SIGNAL gpioi : gpio_in_type;
158 SIGNAL gpioo : gpio_out_type;
159 --DSU
160 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
161 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
162 SIGNAL dsui : dsu_in_type;
163 SIGNAL dsuo : dsu_out_type;
164
165 ---------------------------------------------------------------------
166 --- AJOUT TEST ------------------------Signaux----------------------
167 ---------------------------------------------------------------------
168
169 ---------------------------------------------------------------------
170 CONSTANT IOAEN : INTEGER := CFG_CAN;
171 CONSTANT boardfreq : INTEGER := 25000; -- the board frequency (lclk) is 50 MHz
172
173 -- Spacewire signals
174 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
175 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
176 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0); -- PLE
177 SIGNAL spw_rxtxclk : STD_ULOGIC;
178 SIGNAL spw_rxclkn : STD_ULOGIC;
179 SIGNAL spw_clk : STD_LOGIC;
180 SIGNAL swni : grspw_in_type; -- PLE
181 SIGNAL swno : grspw_out_type; -- PLE
182 SIGNAL clkmn : STD_ULOGIC; -- PLE
183 SIGNAL txclk : STD_ULOGIC; -- PLE 2013 02 14
184 -----------------------------------------------------------------------------
185
186 BEGIN
187
188
189 ----------------------------------------------------------------------
190 --- Reset and Clock generation -------------------------------------
191 ----------------------------------------------------------------------
192
193 vcc <= (OTHERS => '1'); gnd <= (OTHERS => '0');
194 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
195
196 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
197
198
199 clk_pad : clkpad GENERIC MAP (tech => padtech) PORT MAP (clk100MHz, lclk100MHz);
200
201 clkgen0 : clkgen -- clock generator
202 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
203 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
204 PORT MAP (lclk25MHz, lclk25MHz, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
205
206 PROCESS(lclk100MHz)
207 BEGIN
208 IF lclk100MHz'EVENT AND lclk100MHz = '1' THEN
209 lclk50MHz <= NOT lclk50MHz;
210 END IF;
211 END PROCESS;
212
213 PROCESS(lclk50MHz)
214 BEGIN
215 IF lclk50MHz'EVENT AND lclk50MHz = '1' THEN
216 lclk25MHz <= NOT lclk25MHz;
217 END IF;
218 END PROCESS;
219
220 lclk2x <= lclk50MHz;
221 spw_clk <= lclk50MHz;
222
223 ----------------------------------------------------------------------
224 --- LEON3 processor / DSU / IRQ ------------------------------------
225 ----------------------------------------------------------------------
226
227 l3 : IF CFG_LEON3 = 1 GENERATE
228 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
229 u0 : leon3s -- LEON3 processor
230 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
231 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
232 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
233 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
234 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
235 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
236 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
237 irqi(i), irqo(i), dbgi(i), dbgo(i));
238 END GENERATE;
239 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
240
241 dsugen : IF CFG_DSU = 1 GENERATE
242 dsu0 : dsu3 -- LEON3 Debug Support Unit
243 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
244 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
245 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
246 dsui.enable <= '1';
247 dsui.break <= '0';
248 END GENERATE;
249 END GENERATE;
250
251 nodsu : IF CFG_DSU = 0 GENERATE
252 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
253 END GENERATE;
254
255 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
256 irqctrl0 : irqmp -- interrupt controller
257 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
258 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
259 END GENERATE;
260 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
261 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
262 irqi(i).irl <= "0000";
263 END GENERATE;
264 apbo(2) <= apb_none;
265 END GENERATE;
266
267 ----------------------------------------------------------------------
268 --- Memory controllers ---------------------------------------------
269 ----------------------------------------------------------------------
270 memctrlr : mctrl GENERIC MAP (
271 hindex => 0,
272 pindex => 0,
273 paddr => 0,
274 srbanks => 1
275 )
276 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
277
278 memi.brdyn <= '1';
279 memi.bexcn <= '1';
280 memi.writen <= '1';
281 memi.wrn <= "1111";
282 memi.bwidth <= "10";
283
284 bdr : FOR i IN 0 TO 3 GENERATE
285 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
286 PORT MAP (
287 data(31-i*8 DOWNTO 24-i*8),
288 memo.data(31-i*8 DOWNTO 24-i*8),
289 memo.bdrive(i),
290 memi.data(31-i*8 DOWNTO 24-i*8));
291 END GENERATE;
292
293 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
294 PORT MAP (address, memo.address(21 DOWNTO 2));
295
296 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
297 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
298 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
299 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
300 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
301 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
302 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
303
304 ----------------------------------------------------------------------
305 --- AHB CONTROLLER -------------------------------------------------
306 ----------------------------------------------------------------------
307 ahb0 : ahbctrl -- AHB arbiter/multiplexer
308 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
309 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
310 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
311 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
312
313 ----------------------------------------------------------------------
314 --- AHB UART -------------------------------------------------------
315 ----------------------------------------------------------------------
316 dcomgen : IF CFG_AHB_UART = 1 GENERATE
317 dcom0 : ahbuart
318 GENERIC MAP (hindex => 3, pindex => 4, paddr => 4)
319 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(3));
320 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
321 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
322 END GENERATE;
323 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
324
325 ----------------------------------------------------------------------
326 --- APB Bridge -----------------------------------------------------
327 ----------------------------------------------------------------------
328 apb0 : apbctrl -- AHB/APB bridge
329 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
330 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
331
332 ----------------------------------------------------------------------
333 --- GPT Timer ------------------------------------------------------
334 ----------------------------------------------------------------------
335 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
336 timer0 : gptimer -- timer unit
337 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
338 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
339 nbits => CFG_GPT_TW)
340 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
341 gpti.dhalt <= dsuo.tstop;
342 gpti.extclk <= '0';
343 END GENERATE;
344 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
345
346
347 ----------------------------------------------------------------------
348 --- APB UART -------------------------------------------------------
349 ----------------------------------------------------------------------
350 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
351 uart1 : apbuart -- UART 1
352 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
353 fifosize => CFG_UART1_FIFO)
354 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
355 apbuarti.rxd <= urxd1;
356 apbuarti.extclk <= '0';
357 utxd1 <= apbuarto.txd;
358 apbuarti.ctsn <= '0';
359 END GENERATE;
360 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
361
362 -------------------------------------------------------------------------------
363 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
364 -------------------------------------------------------------------------------
365 apb_lfr_time_management_1: apb_lfr_time_management
366 GENERIC MAP (
367 pindex => 6,
368 paddr => 6,
369 pmask => 16#fff#,
370 pirq => 12)
371 PORT MAP (
372 clk25MHz => clkm,
373 clk49_152MHz => clk49_152MHz,
374 resetn => rstn,
375 grspw_tick => swno.tickout,
376 apbi => apbi,
377 apbo => apbo(6),
378 coarse_time => coarse_time,
379 fine_time => fine_time);
380
381 -----------------------------------------------------------------------
382 --- SpaceWire --------------------------------------------------------
383 -----------------------------------------------------------------------
384
385 spw_rxtxclk <= spw_clk;
386 spw_rxclkn <= NOT spw_rxtxclk;
387
388 -- PADS for SPW1
389 spw1_rxd_pad : inpad GENERIC MAP (tech => padtech)
390 PORT MAP (spw1_din, dtmp(0));
391 spw1_rxs_pad : inpad GENERIC MAP (tech => padtech)
392 PORT MAP (spw1_sin, stmp(0));
393 spw1_txd_pad : outpad GENERIC MAP (tech => padtech)
394 PORT MAP (spw1_dout, swno.d(0));
395 spw1_txs_pad : outpad GENERIC MAP (tech => padtech)
396 PORT MAP (spw1_sout, swno.s(0));
397 -- PADS FOR SPW2
398 spw2_rxd_pad : inpad GENERIC MAP (tech => padtech)
399 PORT MAP (spw2_din, dtmp(1));
400 spw2_rxs_pad : inpad GENERIC MAP (tech => padtech)
401 PORT MAP (spw2_sin, stmp(1));
402 spw2_txd_pad : outpad GENERIC MAP (tech => padtech)
403 PORT MAP (spw2_dout, swno.d(1));
404 spw2_txs_pad : outpad GENERIC MAP (tech => padtech)
405 PORT MAP (spw2_sout, swno.s(1));
406
407 -- GRSPW PHY
408 --spw1_input: if CFG_SPW_GRSPW = 1 generate
409 spw_inputloop : FOR j IN 0 TO 1 GENERATE
410 spw_phy0 : grspw_phy
411 GENERIC MAP(
412 tech => fabtech,
413 rxclkbuftype => 1,
414 scantest => 0)
415 PORT MAP(
416 rxrst => swno.rxrst,
417 di => dtmp(j),
418 si => stmp(j),
419 rxclko => spw_rxclk(j),
420 do => swni.d(j),
421 ndo => swni.nd(j*5+4 DOWNTO j*5),
422 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
423 END GENERATE spw_inputloop;
424
425 -- SPW core
426 sw0 : grspwm
427 GENERIC MAP(
428 tech => apa3e,
429 hindex => 1,
430 pindex => 5,
431 paddr => 5,
432 pirq => 11,
433 sysfreq => 25000, -- CPU_FREQ
434 rmap => 1,
435 rmapcrc => 1,
436 fifosize1 => 16,
437 fifosize2 => 16,
438 rxclkbuftype => 1,
439 rxunaligned => 0,
440 rmapbufs => 4,
441 ft => 0,
442 netlist => 0,
443 ports => 2,
444 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
445 memtech => apa3e,
446 destkey => 2,
447 spwcore => 1
448 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
449 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
450 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
451 )
452 PORT MAP(rstn, clkm, spw_rxclk(0),
453 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
454 ahbmi, ahbmo(1), apbi, apbo(5),
455 swni, swno);
456
457 swni.tickin <= '0';
458 swni.rmapen <= '1';
459 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
460 swni.tickinraw <= '0';
461 swni.timein <= (OTHERS => '0');
462 swni.dcrstval <= (OTHERS => '0');
463 swni.timerrstval <= (OTHERS => '0');
464
465 -------------------------------------------------------------------------------
466 -- LFR
467 -------------------------------------------------------------------------------
468 apbi_wfp <= apbi;
469 apbo(15) <= apbo_wfp;
470 ahbi_wfp <= ahbmi;
471 ahbmo(2) <= ahbo_wfp;
472
473 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 ENTITY RR_Arbiter_4 IS
27
28 GENERIC (
29 NB_INPUT : INTEGER := 4);
30
31 PORT (
32 clk : IN STD_LOGIC;
33 rstn : IN STD_LOGIC;
34 in_valid : IN STD_LOGIC_VECTOR(NB_INPUT DOWNTO 0);
35 out_grant : OUT STD_LOGIC_VECTOR(NB_INPUT DOWNTO 0)
36 );
37
38 END RR_Arbiter;
39
40 ARCHITECTURE beh OF RR_Arbiter IS
41
42 SIGNAL grant_vector : STD_LOGIC_VECTOR(NB_INPUT DOWNTO 0);
43
44 BEGIN -- beh
45
46
47
48 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 ENTITY RR_Arbiter_4 IS
27
28 PORT (
29 clk : IN STD_LOGIC;
30 rstn : IN STD_LOGIC;
31 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
32 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
33 );
34
35 END RR_Arbiter_4;
36
37 ARCHITECTURE beh OF RR_Arbiter_4 IS
38
39 SIGNAL out_grant_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
40 SIGNAL grant_sel : STD_LOGIC_VECTOR(1 DOWNTO 0);
41
42 BEGIN -- beh
43
44 out_grant <= out_grant_s;
45
46 out_grant_s <= "0001" WHEN grant_sel = "00" AND in_valid(0) = '1' ELSE
47 "0010" WHEN grant_sel = "00" AND in_valid(1) = '1' ELSE
48 "0100" WHEN grant_sel = "00" AND in_valid(2) = '1' ELSE
49 "1000" WHEN grant_sel = "00" AND in_valid(3) = '1' ELSE
50 "0010" WHEN grant_sel = "01" AND in_valid(1) = '1' ELSE
51 "0100" WHEN grant_sel = "01" AND in_valid(2) = '1' ELSE
52 "1000" WHEN grant_sel = "01" AND in_valid(3) = '1' ELSE
53 "0001" WHEN grant_sel = "01" AND in_valid(0) = '1' ELSE
54 "0100" WHEN grant_sel = "10" AND in_valid(2) = '1' ELSE
55 "1000" WHEN grant_sel = "10" AND in_valid(3) = '1' ELSE
56 "0001" WHEN grant_sel = "10" AND in_valid(0) = '1' ELSE
57 "0010" WHEN grant_sel = "10" AND in_valid(1) = '1' ELSE
58 "1000" WHEN grant_sel = "11" AND in_valid(3) = '1' ELSE
59 "0001" WHEN grant_sel = "11" AND in_valid(0) = '1' ELSE
60 "0010" WHEN grant_sel = "11" AND in_valid(1) = '1' ELSE
61 "0100" WHEN grant_sel = "11" AND in_valid(2) = '1' ELSE
62 "0000";
63
64 PROCESS (clk, rstn)
65 BEGIN -- PROCESS
66 IF rstn = '0' THEN -- asynchronous reset (active low)
67 grant_sel <= "00";
68 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
69 CASE out_grant_s IS
70 WHEN "0001" => grant_sel <= "01";
71 WHEN "0010" => grant_sel <= "10";
72 WHEN "0100" => grant_sel <= "11";
73 WHEN "1000" => grant_sel <= "00";
74 WHEN OTHERS => grant_sel <= grant_sel;
75 END CASE;
76 END IF;
77 END PROCESS;
78
79 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
25
26 LIBRARY lpp;
27 USE lpp.general_purpose.ALL;
28
29 ENTITY SYNC_VALID_BIT IS
30 GENERIC (
31 NB_FF_OF_SYNC : INTEGER := 2);
32 PORT (
33 clk_in : IN STD_LOGIC;
34 clk_out : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
36 sin : IN STD_LOGIC;
37 sout : OUT STD_LOGIC);
38 END SYNC_VALID_BIT;
39
40 ARCHITECTURE beh OF SYNC_VALID_BIT IS
41 SIGNAL s_1 : STD_LOGIC;
42 SIGNAL s_2 : STD_LOGIC;
43 BEGIN -- beh
44
45 lpp_front_to_level_1: lpp_front_to_level
46 PORT MAP (
47 clk => clk_in,
48 rstn => rstn,
49 sin => sin,
50 sout => s_1);
51
52 SYNC_FF_1: SYNC_FF
53 GENERIC MAP (
54 NB_FF_OF_SYNC => NB_FF_OF_SYNC)
55 PORT MAP (
56 clk => clk_out,
57 rstn => rstn,
58 A => s_1,
59 A_sync => s_2);
60
61 lpp_front_detection_1: lpp_front_detection
62 PORT MAP (
63 clk => clk_out,
64 rstn => rstn,
65 sin => s_2,
66 sout => sout);
67
68 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_detection IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_detection;
34
35 ARCHITECTURE beh OF lpp_front_detection IS
36
37 SIGNAL reg : STD_LOGIC;
38 SIGNAL sout_reg : STD_LOGIC;
39
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = NOT reg THEN
50 sout_reg <= '1';
51 ELSE
52 sout_reg <= '0';
53 END IF;
54 END IF;
55 END PROCESS;
56
57 sout <= sout_reg;
58
59 END beh;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ----------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.STD_LOGIC_1164.ALL;
24
25 ENTITY lpp_front_to_level IS
26
27 PORT (
28 clk : IN STD_LOGIC;
29 rstn : IN STD_LOGIC;
30 sin : IN STD_LOGIC;
31 sout : OUT STD_LOGIC);
32
33 END lpp_front_to_level;
34
35 ARCHITECTURE beh OF lpp_front_to_level IS
36
37 SIGNAL reg : STD_LOGIC;
38
39 SIGNAL sout_reg : STD_LOGIC;
40 BEGIN -- beh
41
42 PROCESS (clk, rstn)
43 BEGIN -- PROCESS
44 IF rstn = '0' THEN -- asynchronous reset (active low)
45 reg <= '0';
46 sout_reg <= '0';
47 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
48 reg <= sin;
49 IF sin = '1' AND reg = '0' THEN
50 sout_reg <= NOT sout_reg;
51 END IF;
52 END IF;
53 END PROCESS;
54
55 sout <= sout_reg;
56
57 END beh;
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1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19
20
21 library ieee;
22 use ieee.std_logic_1164.all;
23 library grlib;
24 use grlib.amba.all;
25 use grlib.stdlib.all;
26 library techmap;
27 use techmap.gencomp.all;
28 library gaisler;
29 use gaisler.memctrl.all;
30 use gaisler.leon3.all;
31 use gaisler.uart.all;
32 use gaisler.misc.all;
33 library esa;
34 use esa.memoryctrl.all;
35 use work.config.all;
36 library lpp;
37 use lpp.lpp_amba.all;
38 use lpp.lpp_memory.all;
39 use lpp.lpp_uart.all;
40 use lpp.lpp_matrix.all;
41 use lpp.lpp_delay.all;
42 use lpp.lpp_fft.all;
43 use lpp.fft_components.all;
44 use lpp.lpp_ad_conv.all;
45 use lpp.iir_filter.all;
46 use lpp.general_purpose.all;
47 use lpp.Filtercfg.all;
48 use lpp.lpp_cna.all;
49
50 entity leon3mp is
51 generic (
52 fabtech : integer := CFG_FABTECH;
53 memtech : integer := CFG_MEMTECH;
54 padtech : integer := CFG_PADTECH;
55 clktech : integer := CFG_CLKTECH;
56 disas : integer := CFG_DISAS; -- Enable disassembly to console
57 dbguart : integer := CFG_DUART; -- Print UART on console
58 pclow : integer := CFG_PCLOW
59 );
60 port (
61 clk50MHz : in std_ulogic;
62 reset : in std_ulogic;
63 ramclk : out std_logic;
64
65 ahbrxd : in std_ulogic; -- DSU rx data
66 ahbtxd : out std_ulogic; -- DSU tx data
67 dsubre : in std_ulogic;
68 dsuact : out std_ulogic;
69 urxd1 : in std_ulogic; -- UART1 rx data
70 utxd1 : out std_ulogic; -- UART1 tx data
71 errorn : out std_ulogic;
72
73 address : out std_logic_vector(18 downto 0);
74 data : inout std_logic_vector(31 downto 0);
75 gpio : inout std_logic_vector(6 downto 0); -- I/O port
76
77 nBWa : out std_logic;
78 nBWb : out std_logic;
79 nBWc : out std_logic;
80 nBWd : out std_logic;
81 nBWE : out std_logic;
82 nADSC : out std_logic;
83 nADSP : out std_logic;
84 nADV : out std_logic;
85 nGW : out std_logic;
86 nCE1 : out std_logic;
87 CE2 : out std_logic;
88 nCE3 : out std_logic;
89 nOE : out std_logic;
90 MODE : out std_logic;
91 SSRAM_CLK : out std_logic;
92 ZZ : out std_logic;
93 ---------------------------------------------------------------------
94 --- AJOUT TEST ------------------------In/Out-----------------------
95 ---------------------------------------------------------------------
96 -- DAC
97 DAC_EN : out std_logic;
98 DAC_SYNC : out std_logic;
99 DAC_SCLK : out std_logic;
100 DAC_DATA : out std_logic;
101 -- UART
102 UART_RXD : in std_logic;
103 UART_TXD : out std_logic;
104 ---------------------------------------------------------------------
105 led : out std_logic_vector(1 downto 0)
106 );
107 end;
108
109 architecture Behavioral of leon3mp is
110
111 constant maxahbmsp : integer := CFG_NCPU+CFG_AHB_UART+
112 CFG_GRETH+CFG_AHB_JTAG;
113 constant maxahbm : integer := maxahbmsp;
114
115 --Clk & Rst g�n�
116 signal vcc : std_logic_vector(4 downto 0);
117 signal gnd : std_logic_vector(4 downto 0);
118 signal resetnl : std_ulogic;
119 signal clk2x : std_ulogic;
120 signal lclk : std_ulogic;
121 signal lclk2x : std_ulogic;
122 signal clkm : std_ulogic;
123 signal rstn : std_ulogic;
124 signal rstraw : std_ulogic;
125 signal pciclk : std_ulogic;
126 signal sdclkl : std_ulogic;
127 signal cgi : clkgen_in_type;
128 signal cgo : clkgen_out_type;
129 --- AHB / APB
130 signal apbi : apb_slv_in_type;
131 signal apbo : apb_slv_out_vector := (others => apb_none);
132 signal ahbsi : ahb_slv_in_type;
133 signal ahbso : ahb_slv_out_vector := (others => ahbs_none);
134 signal ahbmi : ahb_mst_in_type;
135 signal ahbmo : ahb_mst_out_vector := (others => ahbm_none);
136 --UART
137 signal ahbuarti : uart_in_type;
138 signal ahbuarto : uart_out_type;
139 signal apbuarti : uart_in_type;
140 signal apbuarto : uart_out_type;
141 --MEM CTRLR
142 signal memi : memory_in_type;
143 signal memo : memory_out_type;
144 signal wpo : wprot_out_type;
145 signal sdo : sdram_out_type;
146 --IRQ
147 signal irqi : irq_in_vector(0 to CFG_NCPU-1);
148 signal irqo : irq_out_vector(0 to CFG_NCPU-1);
149 --Timer
150 signal gpti : gptimer_in_type;
151 signal gpto : gptimer_out_type;
152 --GPIO
153 signal gpioi : gpio_in_type;
154 signal gpioo : gpio_out_type;
155 --DSU
156 signal dbgi : l3_debug_in_vector(0 to CFG_NCPU-1);
157 signal dbgo : l3_debug_out_vector(0 to CFG_NCPU-1);
158 signal dsui : dsu_in_type;
159 signal dsuo : dsu_out_type;
160
161 ---------------------------------------------------------------------
162 --- AJOUT TEST ------------------------Signaux----------------------
163 ---------------------------------------------------------------------
164
165 ---------------------------------------------------------------------
166 constant IOAEN : integer := CFG_CAN;
167 constant boardfreq : integer := 50000;
168
169 begin
170
171 ---------------------------------------------------------------------
172 --- AJOUT TEST -------------------------------------IPs-------------
173 ---------------------------------------------------------------------
174
175 -- apbo not free : 0 1 2 3 7 11
176
177 --- DAC -------------------------------------------------------------
178
179 CAL0 : APB_CNA
180 generic map (pindex => 4, paddr => 4)
181 port map(clkm,rstn,apbi,apbo(4),DAC_EN,DAC_SYNC,DAC_SCLK,DAC_DATA);
182
183
184 --- UART -------------------------------------------------------------
185
186 COM0 : APB_UART
187 generic map (pindex => 5, paddr => 5)
188 port map (clkm,rstn,apbi,apbo(5),UART_TXD,UART_RXD);
189
190
191 --- FIFO -------------------------------------------------------------
192
193 Memtest : APB_FIFO
194 generic map (pindex => 6, paddr => 6, FifoCnt => 5, Data_sz => 16, Addr_sz => 8, Enable_ReUse => '1', R => 1, W => 1)
195 port map (clkm,rstn,clkm,clkm,(others => '0'),(others => '1'),(others => '1'),open,open,open,(others => '0'),open,open,apbi,apbo(6));
196
197
198 ----------------------------------------------------------------------
199 --- Reset and Clock generation -------------------------------------
200 ----------------------------------------------------------------------
201
202 vcc <= (others => '1'); gnd <= (others => '0');
203 cgi.pllctrl <= "00"; cgi.pllrst <= rstraw;
204
205 rst0 : rstgen port map (reset, clkm, cgo.clklock, rstn, rstraw);
206
207
208 clk_pad : clkpad generic map (tech => padtech) port map (clk50MHz, lclk2x);
209
210 clkgen0 : clkgen -- clock generator
211 generic map (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
212 CFG_CLK_NOFB, 0, 0, 0, boardfreq, 0, 0, CFG_OCLKDIV)
213 port map (lclk, lclk, clkm, open, clk2x, sdclkl, pciclk, cgi, cgo);
214
215 ramclk <= clkm;
216 process(lclk2x)
217 begin
218 if lclk2x'event and lclk2x = '1' then
219 lclk <= not lclk;
220 end if;
221 end process;
222
223 ----------------------------------------------------------------------
224 --- LEON3 processor / DSU / IRQ ------------------------------------
225 ----------------------------------------------------------------------
226
227 l3 : if CFG_LEON3 = 1 generate
228 cpu : for i in 0 to CFG_NCPU-1 generate
229 u0 : leon3s -- LEON3 processor
230 generic map (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
231 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
232 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
233 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
234 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
235 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
236 port map (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
237 irqi(i), irqo(i), dbgi(i), dbgo(i));
238 end generate;
239 errorn_pad : outpad generic map (tech => padtech) port map (errorn, dbgo(0).error);
240
241 dsugen : if CFG_DSU = 1 generate
242 dsu0 : dsu3 -- LEON3 Debug Support Unit
243 generic map (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
244 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
245 port map (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
246 -- dsuen_pad : inpad generic map (tech => padtech) port map (dsuen, dsui.enable);
247 dsui.enable <= '1';
248 dsubre_pad : inpad generic map (tech => padtech) port map (dsubre, dsui.break);
249 dsuact_pad : outpad generic map (tech => padtech) port map (dsuact, dsuo.active);
250 end generate;
251 end generate;
252
253 nodsu : if CFG_DSU = 0 generate
254 ahbso(2) <= ahbs_none; dsuo.tstop <= '0'; dsuo.active <= '0';
255 end generate;
256
257 irqctrl : if CFG_IRQ3_ENABLE /= 0 generate
258 irqctrl0 : irqmp -- interrupt controller
259 generic map (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
260 port map (rstn, clkm, apbi, apbo(2), irqo, irqi);
261 end generate;
262 irq3 : if CFG_IRQ3_ENABLE = 0 generate
263 x : for i in 0 to CFG_NCPU-1 generate
264 irqi(i).irl <= "0000";
265 end generate;
266 apbo(2) <= apb_none;
267 end generate;
268
269 ----------------------------------------------------------------------
270 --- Memory controllers ---------------------------------------------
271 ----------------------------------------------------------------------
272
273 memctrlr : mctrl generic map (hindex => 0,pindex => 0, paddr => 0)
274 port map (rstn, clkm, memi, memo, ahbsi, ahbso(0),apbi,apbo(0),wpo, sdo);
275
276 memi.brdyn <= '1'; memi.bexcn <= '1';
277 memi.writen <= '1'; memi.wrn <= "1111"; memi.bwidth <= "10";
278
279 bdr : for i in 0 to 3 generate
280 data_pad : iopadv generic map (tech => padtech, width => 8)
281 port map (data(31-i*8 downto 24-i*8), memo.data(31-i*8 downto 24-i*8),
282 memo.bdrive(i), memi.data(31-i*8 downto 24-i*8));
283 end generate;
284
285
286 addr_pad : outpadv generic map (width => 19, tech => padtech)
287 port map (address, memo.address(20 downto 2));
288
289
290 SSRAM_0:entity ssram_plugin
291 generic map (tech => padtech)
292 port map
293 (lclk2x,memo,SSRAM_CLK,nBWa,nBWb,nBWc,nBWd,nBWE,nADSC,nADSP,nADV,nGW,nCE1,CE2,nCE3,nOE,MODE,ZZ);
294
295 ----------------------------------------------------------------------
296 --- AHB CONTROLLER -------------------------------------------------
297 ----------------------------------------------------------------------
298
299 ahb0 : ahbctrl -- AHB arbiter/multiplexer
300 generic map (defmast => CFG_DEFMST, split => CFG_SPLIT,
301 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
302 ioen => IOAEN, nahbm => maxahbm, nahbs => 8)
303 port map (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
304
305 ----------------------------------------------------------------------
306 --- AHB UART -------------------------------------------------------
307 ----------------------------------------------------------------------
308
309 dcomgen : if CFG_AHB_UART = 1 generate
310 dcom0: ahbuart -- Debug UART
311 generic map (hindex => CFG_NCPU, pindex => 7, paddr => 7)
312 port map (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(7), ahbmi, ahbmo(CFG_NCPU));
313 dsurx_pad : inpad generic map (tech => padtech) port map (ahbrxd, ahbuarti.rxd);
314 dsutx_pad : outpad generic map (tech => padtech) port map (ahbtxd, ahbuarto.txd);
315 -- led(0) <= not ahbuarti.rxd; led(1) <= not ahbuarto.txd;
316 end generate;
317 nouah : if CFG_AHB_UART = 0 generate apbo(7) <= apb_none; end generate;
318
319 ----------------------------------------------------------------------
320 --- APB Bridge -----------------------------------------------------
321 ----------------------------------------------------------------------
322
323 apb0 : apbctrl -- AHB/APB bridge
324 generic map (hindex => 1, haddr => CFG_APBADDR)
325 port map (rstn, clkm, ahbsi, ahbso(1), apbi, apbo );
326
327 ----------------------------------------------------------------------
328 --- GPT Timer ------------------------------------------------------
329 ----------------------------------------------------------------------
330
331 gpt : if CFG_GPT_ENABLE /= 0 generate
332 timer0 : gptimer -- timer unit
333 generic map (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
334 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
335 nbits => CFG_GPT_TW)
336 port map (rstn, clkm, apbi, apbo(3), gpti, gpto);
337 gpti.dhalt <= dsuo.tstop; gpti.extclk <= '0';
338 -- led(4) <= gpto.wdog;
339 end generate;
340 notim : if CFG_GPT_ENABLE = 0 generate apbo(3) <= apb_none; end generate;
341
342
343 ----------------------------------------------------------------------
344 --- APB UART -------------------------------------------------------
345 ----------------------------------------------------------------------
346
347 ua1 : if CFG_UART1_ENABLE /= 0 generate
348 uart1 : apbuart -- UART 1
349 generic map (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
350 fifosize => CFG_UART1_FIFO)
351 port map (rstn, clkm, apbi, apbo(1), ahbuarti, apbuarto);
352 apbuarti.rxd <= urxd1; apbuarti.extclk <= '0'; utxd1 <= apbuarto.txd;
353 apbuarti.ctsn <= '0'; --rtsn1 <= apbuarto.rtsn;
354 -- led(0) <= not apbuarti.rxd; led(1) <= not apbuarto.txd;
355 end generate;
356 noua0 : if CFG_UART1_ENABLE = 0 generate apbo(1) <= apb_none; end generate;
357
358 ----------------------------------------------------------------------
359 --- GPIO -----------------------------------------------------------
360 ----------------------------------------------------------------------
361 led(0) <= gpio(0); led(1) <= gpio(1);
362
363 gpio0 : if CFG_GRGPIO_ENABLE /= 0 generate -- GR GPIO unit
364 grgpio0: grgpio
365 generic map( pindex => 11, paddr => 11, imask => CFG_GRGPIO_IMASK, nbits => 7)
366 port map( rstn, clkm, apbi, apbo(11), gpioi, gpioo);
367
368 pio_pads : for i in 0 to 6 generate
369 pio_pad : iopad generic map (tech => padtech)
370 port map (gpio(i), gpioo.dout(i), gpioo.oen(i), gpioi.din(i));
371 end generate;
372 end generate;
373
374
375 end Behavioral; No newline at end of file
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1 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
3 USE IEEE.NUMERIC_STD.ALL;
4
5 ENTITY lpp_counter IS
6
7 GENERIC (
8 nb_wait_period : INTEGER := 750;
9 nb_bit_of_data : INTEGER := 16
10 );
11 PORT (
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 clear : IN STD_LOGIC;
15 full : OUT STD_LOGIC;
16 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
17 new_data : OUT STD_LOGIC
18 );
19
20 END lpp_counter;
21
22 ARCHITECTURE beh OF lpp_counter IS
23
24 SIGNAL counter_wait : INTEGER;
25 SIGNAL counter_data : INTEGER;
26
27 SIGNAL new_data_s : STD_LOGIC;
28 BEGIN -- beh
29
30 PROCESS (clk, rstn)
31 BEGIN -- PROCESS
32 IF rstn = '0' THEN -- asynchronous reset (active low)
33 counter_wait <= 0;
34 counter_data <= 0;
35 full <= '0';
36 new_data_s <= '0';
37 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
38 IF clear = '1' THEN
39 counter_wait <= 0;
40 counter_data <= 0;
41 full <= '0';
42 new_data_s <= NOT new_data_s;
43 ELSE
44 IF counter_wait = nb_wait_period-1 THEN
45 counter_wait <= 0;
46 new_data_s <= NOT new_data_s;
47 IF counter_data = (2**nb_bit_of_data)-1 THEN
48 full <= '1';
49 counter_data <= 0;
50 ELSE
51 full <= '0';
52 counter_data <= counter_data +1;
53 END IF;
54 ELSE
55 full <= '0';
56 counter_wait <= counter_wait +1;
57 END IF;
58 END IF;
59 END IF;
60 END PROCESS;
61
62 data <= STD_LOGIC_VECTOR(to_unsigned(counter_data,nb_bit_of_data));
63 new_data <= new_data_s;
64
65 END beh;
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@@ -0,0 +1,125
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_cna.all;
32
33 --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba
34
35 entity APB_DAC is
36 generic (
37 pindex : integer := 0;
38 paddr : integer := 0;
39 pmask : integer := 16#fff#;
40 pirq : integer := 0;
41 abits : integer := 8);
42 port (
43 clk : in std_logic; --! Horloge du composant
44 rst : in std_logic; --! Reset general du composant
45 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
46 apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus
47 Cal_EN : out std_logic; --! Signal Enable du multiplex pour la CAL
48 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
49 SCLK : out std_logic; --! Horloge systeme du convertisseur
50 DATA : out std_logic --! Donn�e num�rique s�rialis�
51 );
52 end entity;
53
54 --! @details Les deux registres (apbi,apbo) permettent de g�rer la communication sur le bus
55 --! et les sorties seront cabl�es vers le convertisseur.
56
57 architecture ar_APB_DAC of APB_DAC is
58
59 constant REVISION : integer := 1;
60
61 constant pconfig : apb_config_type := (
62 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0),
63 1 => apb_iobar(paddr, pmask));
64
65 signal enable : std_logic;
66 signal flag_sd : std_logic;
67
68 type DAC_ctrlr_Reg is record
69 DAC_Cfg : std_logic_vector(1 downto 0);
70 DAC_Data : std_logic_vector(15 downto 0);
71 end record;
72
73 signal Rec : DAC_ctrlr_Reg;
74 signal Rdata : std_logic_vector(31 downto 0);
75
76 begin
77
78 enable <= Rec.DAC_Cfg(0);
79 Rec.DAC_Cfg(1) <= flag_sd;
80
81 CONV0 : DacDriver
82 port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data);
83
84
85 process(rst,clk)
86 begin
87 if(rst='0')then
88 Rec.DAC_Data <= (others => '0');
89
90 elsif(clk'event and clk='1')then
91
92
93 --APB Write OP
94 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
95 case apbi.paddr(abits-1 downto 2) is
96 when "000000" =>
97 Rec.DAC_Cfg(0) <= apbi.pwdata(0);
98 when "000001" =>
99 Rec.DAC_Data <= apbi.pwdata(15 downto 0);
100 when others =>
101 null;
102 end case;
103 end if;
104
105 --APB Read OP
106 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
107 case apbi.paddr(abits-1 downto 2) is
108 when "000000" =>
109 Rdata(31 downto 2) <= X"ABCDEF5" & "00";
110 Rdata(1 downto 0) <= Rec.DAC_Cfg;
111 when "000001" =>
112 Rdata(31 downto 16) <= X"FD18";
113 Rdata(15 downto 0) <= Rec.DAC_Data;
114 when others =>
115 Rdata <= (others => '0');
116 end case;
117 end if;
118
119 end if;
120 apbo.pconfig <= pconfig;
121 end process;
122
123 apbo.prdata <= Rdata when apbi.penable = '1';
124 Cal_EN <= enable;
125 end architecture;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 use work.Convertisseur_config.all;
26 use lpp.lpp_cna.all;
27
28 --! Programme du Convertisseur Num�rique/Analogique
29
30 entity DacDriver is
31 port(
32 clk : in std_logic; --! Horloge du composant
33 rst : in std_logic; --! Reset general du composant
34 enable : in std_logic; --! Autorise ou non l'utilisation du composant
35 Data_C : in std_logic_vector(15 downto 0); --! Donn�e Num�rique d'entr�e sur 16 bits
36 SYNC : out std_logic; --! Signal de synchronisation du convertisseur
37 SCLK : out std_logic; --! Horloge systeme du convertisseur
38 flag_sd : out std_logic; --! Flag, signale la fin de la s�rialisation d'une donn�e
39 Data : out std_logic --! Donn�e num�rique s�rialis�
40 );
41 end entity;
42
43 --! @details Un driver C va permettre de g�nerer un tableau de donn�es sur 16 bits,
44 --! qui seront s�rialis� pour �tre ensuite dirig�es vers le convertisseur.
45
46 architecture ar_DacDriver of DacDriver is
47
48 signal s_SCLK : std_logic;
49 signal OKAI_send : std_logic;
50
51 begin
52
53 SystemCLK : Systeme_Clock
54 generic map (nb_serial)
55 port map (clk,rst,s_SCLK);
56
57
58 Signal_sync : Gene_SYNC
59 port map (s_SCLK,rst,enable,OKAI_send,SYNC);
60
61
62 Serial : serialize
63 port map (clk,rst,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
64
65
66 SCLK <= s_SCLK;
67
68 end architecture; No newline at end of file
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_multiSource IS
46 GENERIC (
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
49 );
50 PORT (
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
66 );
67 END;
68
69 ARCHITECTURE Behavioral OF lpp_dma_multiSource IS
70 -----------------------------------------------------------------------------
71 SIGNAL DMAIn : DMA_In_Type;
72 SIGNAL DMAOut : DMA_OUt_Type;
73 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
75 -- CONTROL
76 SIGNAL single_send : STD_LOGIC;
77 SIGNAL burst_send : STD_LOGIC;
78
79 -----------------------------------------------------------------------------
80 -- SEND SINGLE MODULE
81 SIGNAL single_dmai : DMA_In_Type;
82 SIGNAL single_send : STD_LOGIC;
83 SIGNAL single_send_ok : STD_LOGIC;
84 SIGNAL single_send_ko : STD_LOGIC;
85 -----------------------------------------------------------------------------
86 -- SEND SINGLE MODULE
87 SIGNAL burst_dmai : DMA_In_Type;
88 SIGNAL burst_send : STD_LOGIC;
89 SIGNAL burst_send_ok : STD_LOGIC;
90 SIGNAL burst_send_ko : STD_LOGIC;
91 SIGNAL burst_ren : STD_LOGIC;
92 -----------------------------------------------------------------------------
93 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
94 BEGIN
95
96 -----------------------------------------------------------------------------
97 -- DMA to AHB interface
98 DMA2AHB_1 : DMA2AHB
99 GENERIC MAP (
100 hindex => hindex,
101 vendorid => VENDOR_LPP,
102 deviceid => 10,
103 version => 0,
104 syncrst => 1,
105 boundary => 1) -- FIX 11/01/2013
106 PORT MAP (
107 HCLK => HCLK,
108 HRESETn => HRESETn,
109 DMAIn => DMAIn,
110 DMAOut => DMAOut,
111
112 AHBIn => AHB_Master_In,
113 AHBOut => AHB_Master_Out);
114 -----------------------------------------------------------------------------
115
116 single_send <= send WHEN valid_burst = '0' ELSE '0';
117 burst_send <= send WHEN valid_burst = '1' ELSE '0';
118 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
119
120 done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
121 burst_send_ok OR burst_send_ko;
122
123 ren <= burst_fifo_ren WHEN valid_burst = '1' ELSE
124 NOT single_send_ok;
125
126 -----------------------------------------------------------------------------
127 -- SEND 1 word by DMA
128 -----------------------------------------------------------------------------
129 lpp_dma_send_1word_1 : lpp_dma_send_1word
130 PORT MAP (
131 HCLK => HCLK,
132 HRESETn => HRESETn,
133 DMAIn => single_dmai,
134 DMAOut => DMAOut,
135
136 send => single_send,
137 address => address,
138 data => data,
139
140 send_ok => single_send_ok, -- TODO
141 send_ko => single_send_ko -- TODO
142 );
143
144 -----------------------------------------------------------------------------
145 -- SEND 16 word by DMA (in burst mode)
146 -----------------------------------------------------------------------------
147 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
148
149 lpp_dma_send_16word_1 : lpp_dma_send_16word
150 PORT MAP (
151 HCLK => HCLK,
152 HRESETn => HRESETn,
153 DMAIn => burst_dmai,
154 DMAOut => DMAOut,
155
156 send => burst_send,
157 address => address,
158 data => data_2_halfword,
159 ren => burst_ren,
160
161 send_ok => burst_send_ok,
162 send_ko => burst_send_ko);
163
164 END Behavioral;
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1
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
10 --
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
15 --
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
43
44
45 ENTITY lpp_dma_singleOrBurst IS
46 GENERIC (
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
49 );
50 PORT (
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
66 );
67 END;
68
69 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
70 -----------------------------------------------------------------------------
71 SIGNAL DMAIn : DMA_In_Type;
72 SIGNAL DMAOut : DMA_OUt_Type;
73 -----------------------------------------------------------------------------
74 -----------------------------------------------------------------------------
75 -- CONTROL
76 SIGNAL single_send : STD_LOGIC;
77 SIGNAL burst_send : STD_LOGIC;
78
79 -----------------------------------------------------------------------------
80 -- SEND SINGLE MODULE
81 SIGNAL single_dmai : DMA_In_Type;
82
83 SIGNAL single_send_ok : STD_LOGIC;
84 SIGNAL single_send_ko : STD_LOGIC;
85 SIGNAL single_ren : STD_LOGIC;
86 -----------------------------------------------------------------------------
87 -- SEND SINGLE MODULE
88 SIGNAL burst_dmai : DMA_In_Type;
89
90 SIGNAL burst_send_ok : STD_LOGIC;
91 SIGNAL burst_send_ko : STD_LOGIC;
92 SIGNAL burst_ren : STD_LOGIC;
93 -----------------------------------------------------------------------------
94 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
95 BEGIN
96
97 -----------------------------------------------------------------------------
98 -- DMA to AHB interface
99 DMA2AHB_1 : DMA2AHB
100 GENERIC MAP (
101 hindex => hindex,
102 vendorid => VENDOR_LPP,
103 deviceid => 10,
104 version => 0,
105 syncrst => 1,
106 boundary => 1) -- FIX 11/01/2013
107 PORT MAP (
108 HCLK => HCLK,
109 HRESETn => HRESETn,
110 DMAIn => DMAIn,
111 DMAOut => DMAOut,
112
113 AHBIn => AHB_Master_In,
114 AHBOut => AHB_Master_Out);
115 -----------------------------------------------------------------------------
116
117 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 -- LE PROBLEME EST LA !!!!!
120 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122 -- C'est le signal valid_burst qui n'est pas assez long.
123 -----------------------------------------------------------------------------
124 single_send <= send WHEN valid_burst = '0' ELSE '0';
125 burst_send <= send WHEN valid_burst = '1' ELSE '0';
126 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
127
128 -- TODO : verifier
129 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
130 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
131 -- burst_send_ok OR burst_send_ko;
132
133 --ren <= burst_ren WHEN valid_burst = '1' ELSE
134 -- NOT single_send_ok;
135 ren <= burst_ren AND single_ren;
136
137 -----------------------------------------------------------------------------
138 -- SEND 1 word by DMA
139 -----------------------------------------------------------------------------
140 lpp_dma_send_1word_1 : lpp_dma_send_1word
141 PORT MAP (
142 HCLK => HCLK,
143 HRESETn => HRESETn,
144 DMAIn => single_dmai,
145 DMAOut => DMAOut,
146
147 send => single_send,
148 address => address,
149 data => data_2_halfword,
150 ren => single_ren,
151
152 send_ok => single_send_ok, -- TODO
153 send_ko => single_send_ko -- TODO
154 );
155
156 -----------------------------------------------------------------------------
157 -- SEND 16 word by DMA (in burst mode)
158 -----------------------------------------------------------------------------
159 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
160
161 lpp_dma_send_16word_1 : lpp_dma_send_16word
162 PORT MAP (
163 HCLK => HCLK,
164 HRESETn => HRESETn,
165 DMAIn => burst_dmai,
166 DMAOut => DMAOut,
167
168 send => burst_send,
169 address => address,
170 data => data_2_halfword,
171 ren => burst_ren,
172
173 send_ok => burst_send_ok,
174 send_ko => burst_send_ko);
175
176 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 -- 1.0 - initial version
24 -------------------------------------------------------------------------------
25
26 LIBRARY ieee;
27 USE ieee.std_logic_1164.ALL;
28 USE ieee.numeric_std.ALL;
29
30
31 ENTITY lpp_waveform_dma_genvalid IS
32 PORT (
33 HCLK : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
35 run : IN STD_LOGIC;
36
37 valid_in : IN STD_LOGIC;
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
39
40 ack_in : IN STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
43 error : OUT STD_LOGIC
44 );
45 END;
46
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
48 TYPE state_fsm IS (IDLE, VALID);
49 SIGNAL state : state_fsm;
50 BEGIN
51
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
53 BEGIN
54 IF HRESETn = '0' THEN
55 state <= IDLE;
56 valid_out <= '0';
57 error <= '0';
58 time_out <= (OTHERS => '0');
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
60 CASE state IS
61 WHEN IDLE =>
62
63 valid_out <= '0';
64 error <= '0';
65 IF run = '1' AND valid_in = '1' THEN
66 state <= VALID;
67 valid_out <= '1';
68 time_out <= time_in;
69 END IF;
70
71 WHEN VALID =>
72 IF run = '0' THEN
73 state <= IDLE;
74 valid_out <= '0';
75 error <= '0';
76 ELSE
77 IF valid_in = '1' THEN
78 IF ack_in = '1' THEN
79 state <= VALID;
80 valid_out <= '1';
81 time_out <= time_in;
82 ELSE
83 state <= IDLE;
84 error <= '1';
85 valid_out <= '0';
86 END IF;
87 ELSIF ack_in = '1' THEN
88 state <= IDLE;
89 valid_out <= '0';
90 END IF;
91 END IF;
92
93 WHEN OTHERS => NULL;
94 END CASE;
95 END IF;
96 END PROCESS FSM_SELECT_ADDRESS;
97
98 END Behavioral;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
29
30 ENTITY lpp_waveform_fifo_arbiter_reg IS
31 GENERIC(
32 data_size : INTEGER;
33 data_nb : INTEGER
34 );
35 PORT(
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
40
41 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
42
43 enable : IN STD_LOGIC;
44 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
45
46 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
47 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
48 );
49 END ENTITY;
50
51
52 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
53
54 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
55 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
56
57 SIGNAL reg_sel : INTEGER;
58 SIGNAL reg_sel_s : INTEGER;
59
60 BEGIN
61
62 all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE
63 PROCESS (clk, rstn)
64 BEGIN -- PROCESS
65 IF rstn = '0' THEN -- asynchronous reset (active low)
66 reg(I) <= 0;
67 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
68 IF run = '0' THEN
69 reg(I) <= 0;
70 ELSE
71 IF sel(I) = '1' THEN
72 reg(I) <= reg_sel_s;
73 END IF;
74 END IF;
75 END IF;
76 END PROCESS;
77 END GENERATE all_reg;
78
79 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
80 reg(1) WHEN sel(1) = '1' ELSE
81 reg(2) WHEN sel(2) = '1' ELSE
82 reg(3);
83
84 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
85 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
86 0;
87
88 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size));
89 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size));
90
91 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_waveform_fifo_latencyCorrection IS
34 GENERIC(
35 tech : INTEGER := 0
36 );
37 PORT(
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
42
43 ---------------------------------------------------------------------------
44 empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b
45 empty : OUT STD_LOGIC;
46 data_ren : IN STD_LOGIC;
47 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 ---------------------------------------------------------------------------
49 empty_almost_fifo : IN STD_LOGIC;
50 empty_fifo : IN STD_LOGIC;
51 data_ren_fifo : OUT STD_LOGIC;
52 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 );
54 END ENTITY;
55
56
57 ARCHITECTURE ar_lpp_waveform_fifo_latencyCorrection OF lpp_waveform_fifo_latencyCorrection IS
58 SIGNAL data_ren_fifo_s : STD_LOGIC;
59 -- SIGNAL rdata_s : STD_LOGIC;
60
61 SIGNAL reg_full : STD_LOGIC;
62 SIGNAL empty_almost_reg : STD_LOGIC;
63 BEGIN
64
65 PROCESS (clk, rstn)
66 BEGIN -- PROCESS
67 IF rstn = '0' THEN -- asynchronous reset (active low)
68 empty_almost_reg <= '1';
69 empty <= '1';
70 data_ren_fifo_s <= '1';
71 rdata <= (OTHERS => '0');
72 reg_full <= '0';
73 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
74 IF run = '0' THEN
75 empty_almost_reg <= '1';
76 empty <= '1';
77 data_ren_fifo_s <= '1';
78 rdata <= (OTHERS => '0');
79 reg_full <= '0';
80 ELSE
81
82 IF data_ren_fifo_s = '0' THEN
83 reg_full <= '1';
84 ELSIF data_ren = '0' THEN
85 reg_full <= '0';
86 END IF;
87
88 IF data_ren_fifo_s = '0' THEN
89 rdata <= rdata_fifo;
90 END IF;
91
92 IF (reg_full = '0' OR data_ren = '0') AND empty_fifo = '0' THEN
93 data_ren_fifo_s <= '0';
94 ELSE
95 data_ren_fifo_s <= '1';
96 END IF;
97
98 IF empty_fifo = '1' AND ((reg_full = '0') OR ( data_ren = '0')) THEN
99 empty <= '1';
100 ELSE
101 empty <= '0';
102 END IF;
103
104 IF empty_almost_reg = '0' AND data_ren = '0' AND empty_almost_fifo = '1' THEN
105 empty_almost_reg <= '1';
106 ELSIF empty_almost_reg = '1' AND empty_almost_fifo = '0' THEN
107 empty_almost_reg <= '0';
108 END IF;
109
110 END IF;
111 END IF;
112 END PROCESS;
113
114 empty_almost <= empty_almost_reg;
115 data_ren_fifo <= data_ren_fifo_s;
116
117 END ARCHITECTURE;
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
25 LIBRARY lpp;
26 USE lpp.lpp_memory.ALL;
27 USE lpp.iir_filter.ALL;
28 USE lpp.lpp_waveform_pkg.ALL;
29
30 LIBRARY techmap;
31 USE techmap.gencomp.ALL;
32
33 ENTITY lpp_waveform_fifo_withoutLatency IS
34 GENERIC(
35 tech : INTEGER := 0
36 );
37 PORT(
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40 ---------------------------------------------------------------------------
41 run : IN STD_LOGIC;
42
43 ---------------------------------------------------------------------------
44 empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b
45 empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
46 data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
47 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
48 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
50 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
51
52 ---------------------------------------------------------------------------
53 full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
54 full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
55 data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
56 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
57 );
58 END ENTITY;
59
60
61 ARCHITECTURE ar_lpp_waveform_fifo_withoutLatency OF lpp_waveform_fifo_withoutLatency IS
62 SIGNAL empty_almost_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
63 SIGNAL empty_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
64 SIGNAL data_ren_s : STD_LOGIC_VECTOR( 3 DOWNTO 0);
65 SIGNAL rdata_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
66
67 BEGIN
68
69
70
71
72 lpp_waveform_fifo_latencyCorrection_0: lpp_waveform_fifo_latencyCorrection
73 GENERIC MAP (
74 tech => tech)
75 PORT MAP (
76 clk => clk,
77 rstn => rstn,
78 run => run,
79
80 empty_almost => empty_almost(0),
81 empty => empty(0),
82 data_ren => data_ren(0),
83 rdata => rdata_0,
84
85 empty_almost_fifo => empty_almost_s(0),
86 empty_fifo => empty_s(0),
87 data_ren_fifo => data_ren_s(0),
88 rdata_fifo => rdata_s);
89
90 lpp_waveform_fifo_latencyCorrection_1: lpp_waveform_fifo_latencyCorrection
91 GENERIC MAP (
92 tech => tech)
93 PORT MAP (
94 clk => clk,
95 rstn => rstn,
96 run => run,
97
98 empty_almost => empty_almost(1),
99 empty => empty(1),
100 data_ren => data_ren(1),
101 rdata => rdata_1,
102
103 empty_almost_fifo => empty_almost_s(1),
104 empty_fifo => empty_s(1),
105 data_ren_fifo => data_ren_s(1),
106 rdata_fifo => rdata_s);
107
108 lpp_waveform_fifo_latencyCorrection_2: lpp_waveform_fifo_latencyCorrection
109 GENERIC MAP (
110 tech => tech)
111 PORT MAP (
112 clk => clk,
113 rstn => rstn,
114 run => run,
115
116 empty_almost => empty_almost(2),
117 empty => empty(2),
118 data_ren => data_ren(2),
119 rdata => rdata_2,
120
121 empty_almost_fifo => empty_almost_s(2),
122 empty_fifo => empty_s(2),
123 data_ren_fifo => data_ren_s(2),
124 rdata_fifo => rdata_s);
125
126 lpp_waveform_fifo_latencyCorrection_3: lpp_waveform_fifo_latencyCorrection
127 GENERIC MAP (
128 tech => tech)
129 PORT MAP (
130 clk => clk,
131 rstn => rstn,
132 run => run,
133
134 empty_almost => empty_almost(3),
135 empty => empty(3),
136 data_ren => data_ren(3),
137 rdata => rdata_3,
138
139 empty_almost_fifo => empty_almost_s(3),
140 empty_fifo => empty_s(3),
141 data_ren_fifo => data_ren_s(3),
142 rdata_fifo => rdata_s);
143
144 lpp_waveform_fifo_1: lpp_waveform_fifo
145 GENERIC MAP (
146 tech => tech)
147 PORT MAP (
148 clk => clk,
149 rstn => rstn,
150 run => run,
151
152 empty_almost => empty_almost_s,
153 empty => empty_s,
154 data_ren => data_ren_s,
155 rdata => rdata_s,
156
157 full_almost => full_almost,
158 full => full,
159 data_wen => data_wen,
160 wdata => wdata);
161
162 END ARCHITECTURE;
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@@ -0,0 +1,255
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress IS
40
41 GENERIC (
42 nb_data_by_buffer_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
52 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
54 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
55 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
56 -------------------------------------------------------------------------
57 -- CTRL
58 -------------------------------------------------------------------------
59 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
61 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
62
63 -------------------------------------------------------------------------
64 -- STATUS
65 -------------------------------------------------------------------------
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
68 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
69
70 -------------------------------------------------------------------------
71 -- ADDR DATA OUT
72 -------------------------------------------------------------------------
73 data_f0_data_out_valid_burst : OUT STD_LOGIC;
74 data_f1_data_out_valid_burst : OUT STD_LOGIC;
75 data_f2_data_out_valid_burst : OUT STD_LOGIC;
76 data_f3_data_out_valid_burst : OUT STD_LOGIC;
77
78 data_f0_data_out_valid : OUT STD_LOGIC;
79 data_f1_data_out_valid : OUT STD_LOGIC;
80 data_f2_data_out_valid : OUT STD_LOGIC;
81 data_f3_data_out_valid : OUT STD_LOGIC;
82
83 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
87
88 );
89
90 END lpp_waveform_genaddress;
91
92 ARCHITECTURE beh OF lpp_waveform_genaddress IS
93 SIGNAL addr_data_f0_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
94 SIGNAL addr_data_f1_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
95 SIGNAL addr_data_f2_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
96 SIGNAL addr_data_f3_s : STD_LOGIC_VECTOR(29 DOWNTO 0);
97 -----------------------------------------------------------------------------
98 -- Valid gen
99 -----------------------------------------------------------------------------
100 SIGNAL addr_burst_avail : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL data_out_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
102 SIGNAL data_out_valid_burst : STD_LOGIC_VECTOR(3 DOWNTO 0);
103
104 -----------------------------------------------------------------------------
105 -- Register
106 -----------------------------------------------------------------------------
107 SIGNAL data_addr_v_pre : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
108 SIGNAL data_addr_v_reg : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
109 SIGNAL data_addr_v_base : Data_Vector(3 DOWNTO 0, 29 DOWNTO 0);
110 SIGNAL data_addr_pre : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
111 SIGNAL data_addr_reg : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
112 SIGNAL data_addr_base : STD_LOGIC_VECTOR(29 DOWNTO 0); -- TODO
113
114 -----------------------------------------------------------------------------
115 --
116 -----------------------------------------------------------------------------
117 SIGNAL status_full_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
118
119 TYPE addr_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(29 DOWNTO 0);
120 SIGNAL addr_v_p : addr_VECTOR(3 DOWNTO 0);
121 SIGNAL addr_v_b : addr_VECTOR(3 DOWNTO 0);
122
123 SIGNAL addr_avail: addr_VECTOR(3 DOWNTO 0);
124
125 BEGIN -- beh
126
127 -----------------------------------------------------------------------------
128 -- valid gen
129 -----------------------------------------------------------------------------
130 data_f0_data_out_valid <= data_out_valid(0);
131 data_f1_data_out_valid <= data_out_valid(1);
132 data_f2_data_out_valid <= data_out_valid(2);
133 data_f3_data_out_valid <= data_out_valid(3);
134
135 data_f0_data_out_valid_burst <= data_out_valid_burst(0);
136 data_f1_data_out_valid_burst <= data_out_valid_burst(1);
137 data_f2_data_out_valid_burst <= data_out_valid_burst(2);
138 data_f3_data_out_valid_burst <= data_out_valid_burst(3);
139
140
141
142 all_bit_data_valid_out : FOR I IN 3 DOWNTO 0 GENERATE
143 addr_avail(I) <= (addr_v_b(I) + nb_data_by_buffer - addr_v_p(I));
144
145 addr_burst_avail(I) <= '1' WHEN (addr_v_p(I)(3 DOWNTO 0) = "0000")
146 AND (UNSIGNED(addr_avail(I)) > 15)
147 ELSE '0';
148
149 data_out_valid(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
150 '0' WHEN empty(I) = '1' ELSE
151 '0' WHEN addr_burst_avail(I) = '1' ELSE
152 '0' WHEN (run = '0') ELSE
153 '1';
154
155 data_out_valid_burst(I) <= '0' WHEN (status_full_s(I) = '1' AND status_full_ack(I) = '0') ELSE
156 '0' WHEN empty(I) = '1' ELSE
157 '0' WHEN addr_burst_avail(I) = '0' ELSE
158 '0' WHEN empty_almost(I) = '1' ELSE
159 '0' WHEN (run = '0') ELSE
160 '1';
161 END GENERATE all_bit_data_valid_out;
162
163 -----------------------------------------------------------------------------
164 -- Register
165 -----------------------------------------------------------------------------
166 all_data_bit : FOR J IN 29 DOWNTO 0 GENERATE
167 all_data_addr : FOR I IN 3 DOWNTO 0 GENERATE
168 PROCESS (clk, rstn)
169 BEGIN -- PROCESS
170 IF rstn = '0' THEN -- asynchronous reset (active low)
171 data_addr_v_reg(I, J) <= '0';
172 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
173 IF run = '1' AND status_full_ack(I) = '0' THEN
174 data_addr_v_reg(I, J) <= data_addr_v_pre(I, J);
175 ELSE
176 data_addr_v_reg(I, J) <= data_addr_v_base(I, J);
177 END IF;
178 END IF;
179 END PROCESS;
180
181 data_addr_v_pre(I, J) <= data_addr_v_reg(I, J) WHEN data_ren(I) = '1' ELSE data_addr_pre(J);
182
183 END GENERATE all_data_addr;
184
185 data_addr_reg(J) <= data_addr_v_reg(0, J) WHEN data_ren(0) = '0' ELSE
186 data_addr_v_reg(1, J) WHEN data_ren(1) = '0' ELSE
187 data_addr_v_reg(2, J) WHEN data_ren(2) = '0' ELSE
188 data_addr_v_reg(3, J);
189
190 data_addr_v_base(0, J) <= addr_data_f0_s(J);
191 data_addr_v_base(1, J) <= addr_data_f1_s(J);
192 data_addr_v_base(2, J) <= addr_data_f2_s(J);
193 data_addr_v_base(3, J) <= addr_data_f3_s(J);
194
195 data_f0_addr_out(J+2) <= data_addr_v_reg(0, J) ;
196 data_f1_addr_out(J+2) <= data_addr_v_reg(1, J) ;
197 data_f2_addr_out(J+2) <= data_addr_v_reg(2, J) ;
198 data_f3_addr_out(J+2) <= data_addr_v_reg(3, J) ;
199
200 END GENERATE all_data_bit;
201
202 addr_data_f0_s <= addr_data_f0(31 DOWNTO 2);
203 addr_data_f1_s <= addr_data_f1(31 DOWNTO 2);
204 addr_data_f2_s <= addr_data_f2(31 DOWNTO 2);
205 addr_data_f3_s <= addr_data_f3(31 DOWNTO 2);
206
207 data_f0_addr_out(1 DOWNTO 0) <= "00";
208 data_f1_addr_out(1 DOWNTO 0) <= "00";
209 data_f2_addr_out(1 DOWNTO 0) <= "00";
210 data_f3_addr_out(1 DOWNTO 0) <= "00";
211
212
213
214
215 -----------------------------------------------------------------------------
216 -- ADDER
217 -----------------------------------------------------------------------------
218
219 data_addr_pre <= data_addr_reg + 1;
220
221 -----------------------------------------------------------------------------
222 -- FULL STATUS
223 -----------------------------------------------------------------------------
224 all_status : FOR I IN 3 DOWNTO 0 GENERATE
225 all_bit_addr : FOR J IN 29 DOWNTO 0 GENERATE
226 addr_v_p(I)(J) <= data_addr_v_pre(I, J);
227 addr_v_b(I)(J) <= data_addr_v_base(I, J);
228 END GENERATE all_bit_addr;
229
230 PROCESS (clk, rstn)
231 BEGIN -- PROCESS
232 IF rstn = '0' THEN -- asynchronous reset (active low)
233 status_full_s(I) <= '0';
234 status_full_err(I) <= '0';
235 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
236 IF run = '1' AND status_full_ack(I) = '0' THEN
237 IF addr_v_p(I) = addr_v_b(I) + nb_data_by_buffer THEN
238 status_full_s(I) <= '1';
239 IF status_full_s(I) = '1' AND data_ren(I) = '0' THEN
240 status_full_err(I) <= '1';
241 END IF;
242 END IF;
243 ELSE
244 status_full_s(I) <= '0';
245 status_full_err(I) <= '0';
246 END IF;
247 END IF;
248 END PROCESS;
249
250 END GENERATE all_status;
251
252 status_full <= status_full_s;
253
254
255 END beh;
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@@ -0,0 +1,97
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
26
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
35
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
38
39 ENTITY lpp_waveform_genaddress_single IS
40
41 GENERIC (
42 nb_burst_available_size : INTEGER);
43
44 PORT (
45 clk : IN STD_LOGIC;
46 rstn : IN STD_LOGIC;
47 run : IN STD_LOGIC;
48 -------------------------------------------------------------------------
49 -- CONFIG
50 -------------------------------------------------------------------------
51 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
52 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 -------------------------------------------------------------------------
54 -- CTRL
55 -------------------------------------------------------------------------
56 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
57 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
58 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
59 --burst : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
60
61 -------------------------------------------------------------------------
62 -- STATUS
63 -------------------------------------------------------------------------
64 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
65 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
66 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67
68 -------------------------------------------------------------------------
69 -- ADDR DATA OUT
70 -------------------------------------------------------------------------
71 data_f0_data_out_valid_burst : OUT STD_LOGIC;
72 data_f1_data_out_valid_burst : OUT STD_LOGIC;
73 data_f2_data_out_valid_burst : OUT STD_LOGIC;
74 data_f3_data_out_valid_burst : OUT STD_LOGIC;
75
76 data_f0_data_out_valid : OUT STD_LOGIC;
77 data_f1_data_out_valid : OUT STD_LOGIC;
78 data_f2_data_out_valid : OUT STD_LOGIC;
79 data_f3_data_out_valid : OUT STD_LOGIC;
80
81 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
85
86 );
87
88 END lpp_waveform_genaddress_single;
89
90 ARCHITECTURE beh OF lpp_waveform_genaddress_single IS
91
92 BEGIN -- beh
93
94
95
96
97 END beh;
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@@ -5,3 +5,6 3ff0c20d32174922de6010a36c07697fe229dc4c
5 3ff0c20d32174922de6010a36c07697fe229dc4c em-2013-07-25-vhdlib210
5 3ff0c20d32174922de6010a36c07697fe229dc4c em-2013-07-25-vhdlib210
6 3ff0c20d32174922de6010a36c07697fe229dc4c em-2013-07-24-vhdlib210
6 3ff0c20d32174922de6010a36c07697fe229dc4c em-2013-07-24-vhdlib210
7 0000000000000000000000000000000000000000 em-2013-07-24-vhdlib210
7 0000000000000000000000000000000000000000 em-2013-07-24-vhdlib210
8 3d6676b65e410dacd88dfaa9ded82c581ee2f148 LPP-LFR-em-WaveFormPicker-0-0-2
9 7e0d5f5f88e746f017656ffd6728655cc88f817a LPP-LFR-em-WaveFormPicker-0-0-3
10 af3a90f3ec47b27bb56cf2c603238cc7bd9d180e LPP-LFR-em-WaveFormPicker-0-0-5
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@@ -27,4 +27,5 all:
27 make all -C BenchFFT
27 make all -C BenchFFT
28 make all -C BenchGPIO
28 make all -C BenchGPIO
29 make all -C BenchMatrix
29 make all -C BenchMatrix
30 make all -C BenchFFT+Matrix No newline at end of file
30 make all -C BenchFFT+Matrix
31 make all -C BenchDAC_CAL No newline at end of file
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@@ -1,34 +1,42
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_CNA_DRIVER_H
22 #ifndef APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
24
24
25 #define DAC_ready 3
25 #define DAC_ready 3
26 #define DAC_enable 1
26 #define DAC_enable 1
27 #define DAC_disable 0
27 #define DAC_disable 0
28
29
28
30 /*===================================================
29 #define CAL_SignalData [251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,\
31 T Y P E S D E F
30 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,\
31 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,\
32 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,\
33 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,\
34 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,\
35 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
36 //Sinus (10Khz + 625hz)
37
38 /*===================================================
39 T Y P E S D E F
32 ====================================================*/
40 ====================================================*/
33
41
34 /** Structure repr�sentant le registre du CNA */
42 /** Structure repr�sentant le registre du CNA */
@@ -40,21 +48,12 struct DAC_Driver
40
48
41 typedef volatile struct DAC_Driver DAC_Device;
49 typedef volatile struct DAC_Driver DAC_Device;
42
50
43 /*===================================================
51 /*===================================================
44 F U N C T I O N S
52 F U N C T I O N S
45 ====================================================*/
53 ====================================================*/
46
54
47 /** Ouvre l'acc� au CNA */
55 /** Ouvre l'acc� au CNA */
48 DAC_Device* DacOpen(int count);
56 DAC_Device* openDAC(int count);
49
50 //DAC_Device* DacClose(int count);
51
52 /** Les donn�es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
53 int DacTable();
54
55 /** Les donn�es sont entr�e par l'utilisateur, la conversion se fait a chaque nouvelle donn�e */
56 int DacConst();
57
58
57
59
58
60 #endif
59 #endif
Show file before | Show file after | Hide comments
@@ -24,55 +24,15
24 #include <stdio.h>
24 #include <stdio.h>
25
25
26
26
27 DAC_Device* DacOpen(int count)
27 DAC_Device* openDAC(int count)
28 {
28 {
29 DAC_Device* dac0;
29 DAC_Device* dac0;
30 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
30 dac0 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
31 dac0->configReg = DAC_enable;
31 dac0->ConfigReg = DAC_enable;
32 return dac0;
32 return dac0;
33 }
33 }
34
34
35 /*
35 /*int DacConst()
36 DAC_Device* DacClose(int count)
37 {
38 DAC_Device* dac1;
39 dac1 = (DAC_Device*) apbgetdevice(LPP_CNA,VENDOR_LPP,count);
40 dac1->configReg = DAC_disable;
41 return dac1;
42 }
43 */
44
45
46 int DacTable()
47 {
48 int i;
49 DAC_Device* dac2;
50 int tablo[251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,
51 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,
52 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,
53 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,
54 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,
55 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,
56 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
57 dac2 = (DAC_Device*)0x80000800;
58 dac2->configReg = DAC_enable;
59 dac2->dataReg = tablo[0];
60
61 while(1)
62 {
63 for (i = 0 ; i < 251 ; i++)
64 {
65 while(!((dac2->configReg & DAC_ready) == DAC_ready));
66 dac2->dataReg = tablo[i];
67 while((dac2->configReg & DAC_ready) == DAC_ready);
68 }
69 }
70 return 0;
71 }
72
73
74
75 int DacConst()
76 {
36 {
77 DAC_Device* dac3;
37 DAC_Device* dac3;
78 int Value = 0x1FFF;
38 int Value = 0x1FFF;
@@ -85,5 +45,5 int DacConst()
85 dac3->dataReg = Value;
45 dac3->dataReg = Value;
86 }
46 }
87 return 0;
47 return 0;
88 }
48 } */
89
49
Show file before | Show file after | Hide comments
@@ -1,34 +1,42
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_CNA_DRIVER_H
22 #ifndef APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
23 #define APB_CNA_DRIVER_H
24
24
25 #define DAC_ready 3
25 #define DAC_ready 3
26 #define DAC_enable 1
26 #define DAC_enable 1
27 #define DAC_disable 0
27 #define DAC_disable 0
28
29
28
30 /*===================================================
29 #define CAL_SignalData [251] = {0x9555,0x1800,0x19AA,0x1B15,0x1C0A,0x1C66,0x1C1F,0x1B44,0x19FC,0x187F,0x170F,0x15EA,0x1542,0x1537,0x15CE,0x16F2,0x187A,0x1A2B,0x1BC2,0x1D04,0x1DBF,0x1DDB,0x1D56,0x1C49,0x1AE3,0x195F,0x1800,0x1700,0x168D,0x16BA,0x1785,0x18D0,0x1A69,0x1C12,0x1D8A,0x1E98,0x1F13,\
31 T Y P E S D E F
30 0x1EEB,0x1E28,0x1CEC,0x1FFF,0x19E8,0x189F,0x17C8,0x1788,0x17EA,0x18E2,0x1A48,0x1BE7,0x1D7C,0x1ECA,0x1F9C,0x1FD2,0x1F64,0x1E66,0x1D00,0x1B6E,0x19EF,0x18C1,0x1817,0x180A,0x189D,0x19BA,0x1B33,0x1CCC,0x1E44,0x1F5F,0x1FEE,0x1FDC,0x1F2B,0x1DF6,0x1C6E,0x1AD1,0x1960,0x1855,0x17D9,0x1800,\
31 0x18C1,0x19FD,0x1B80,0x1D0A,0x1E5C,0x1F3D,0x1F87,0x1F2E,0x1E3E,0x1CDA,0x1B39,0x199C,0x1842,0x1760,0x1717,0x1771,0x185D,0x19B1,0x1B36,0x1CAA,0x1DCF,0x1E73,0x1E79,0x1DDD,0x1CB4,0x1B2B,0x197C,0x17EA,0x16B1,0x15FF,0x15EE,0x167C,0x178F,0x18F7,0x1A78,0x1BCF,0x1CC4,0x1D2A,0x1CED,0x1C14,\
32 0x1ABC,0x191A,0x176B,0x15F0,0x14E2,0x1467,0x1490,0x1552,0x1689,0x1800,0x1977,0x1AAE,0x1B70,0x1B99,0x1B1E,0x1A10,0x1895,0x16E6,0x1544,0x13EC,0x1313,0x12D6,0x133C,0x1431,0x1588,0x1709,0x1871,0x1984,0x1A12,0x1A01,0x194F,0x1816,0x1684,0x14D5,0x134C,0x1223,0x1187,0x118D,0x1231,0x1356,\
33 0x14CA,0x164F,0x17A3,0x188F,0x18E9,0x18A0,0x17BE,0x1664,0x14C7,0x1326,0x11C2,0x10D2,0x1079,0x10C3,0x11A4,0x12F6,0x1480,0x1603,0x173F,0x1800,0x1827,0x17AB,0x16A0,0x152F,0x1392,0x120A,0x10D5,0x1024,0x1012,0x10A1,0x11BC,0x1334,0x14CD,0x1646,0x1763,0x17F6,0x17E9,0x173F,0x1611,0x1492,\
34 0x1300,0x119A,0x109C,0x102E,0x1064,0x1136,0x1284,0x1419,0x15B8,0x171E,0x1816,0x1878,0x1838,0x1761,0x1618,0x1494,0x1314,0x11D8,0x1115,0x10ED,0x1168,0x1276,0x13EE,0x1597,0x1730,0x187B,0x1946,0x1973,0x1900,0x1800,0x16A1,0x151D,0x13B7,0x12AA,0x1225,0x1241,0x12FC,0x143E,0x15D5,0x1786,\
35 0x190E,0x1A32,0x1AC9,0x1ABE,0x1A16,0x18F1,0x1781,0x1604,0x14BC,0x13E1,0x139A,0x13F6,0x14EB,0x1656};
36 //Sinus (10Khz + 625hz)
37
38 /*===================================================
39 T Y P E S D E F
32 ====================================================*/
40 ====================================================*/
33
41
34 /** Structure repr�sentant le registre du CNA */
42 /** Structure repr�sentant le registre du CNA */
@@ -40,21 +48,12 struct DAC_Driver
40
48
41 typedef volatile struct DAC_Driver DAC_Device;
49 typedef volatile struct DAC_Driver DAC_Device;
42
50
43 /*===================================================
51 /*===================================================
44 F U N C T I O N S
52 F U N C T I O N S
45 ====================================================*/
53 ====================================================*/
46
54
47 /** Ouvre l'acc� au CNA */
55 /** Ouvre l'acc� au CNA */
48 DAC_Device* DacOpen(int count);
56 DAC_Device* openDAC(int count);
49
50 //DAC_Device* DacClose(int count);
51
52 /** Les donn�es sont lus a partir d'un tableau pour obtenir le signal de CAL (10Khz + 625hz) */
53 int DacTable();
54
55 /** Les donn�es sont entr�e par l'utilisateur, la conversion se fait a chaque nouvelle donn�e */
56 int DacConst();
57
58
57
59
58
60 #endif
59 #endif
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@@ -1,23 +1,23
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./dsp/iir_filter
3 ./dsp/lpp_downsampling
4 ./dsp/lpp_fft
5 ./general_purpose
2 ./general_purpose
6 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
7 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
8 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 ./lfr_time_management
10 ./lfr_time_management
10 ./lpp_ad_Conv
11 ./lpp_ad_Conv
11 ./lpp_amba
12 ./lpp_bootloader
12 ./lpp_bootloader
13 ./lpp_cna
13 ./lpp_cna
14 ./lpp_demux
14 ./lpp_demux
15 ./lpp_dma
16 ./lpp_Header
15 ./lpp_Header
17 ./lpp_matrix
16 ./lpp_matrix
18 ./lpp_memory
17 ./lpp_memory
19 ./lpp_top_lfr
18 ./lpp_dma
20 ./lpp_uart
19 ./lpp_uart
21 ./lpp_usb
20 ./lpp_usb
22 ./lpp_waveform
21 ./lpp_waveform
23 ./Rocket_PCM_Encoder
22 ./lpp_top_lfr
23 ./lpp_Header
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@@ -1,19 +1,8
1 APB_IIR_CEL.vhd
1 iir_filter.vhd
2 APB_IIR_Filter.vhd
3 FILTERcfg.vhd
2 FILTERcfg.vhd
4 FilterCTRLR.vhd
3 RAM.vhd
5 FILTER_RAM_CTRLR.vhd
4 RAM_CEL.vhd
6 FILTER.vhd
5 RAM_CTRLR_v2.vhd
7 IIR_CEL_CTRLR_v2_CONTROL.vhd
6 IIR_CEL_CTRLR_v2_CONTROL.vhd
8 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
7 IIR_CEL_CTRLR_v2_DATAFLOW.vhd
9 IIR_CEL_CTRLR_v2.vhd
8 IIR_CEL_CTRLR_v2.vhd
10 IIR_CEL_CTRLR.vhd
11 IIR_CEL_FILTER.vhd
12 iir_filter.vhd
13 RAM_CEL_N.vhd
14 RAM_CEL.vhd
15 RAM_CTRLR2.vhd
16 RAM_CTRLR_v2.vhd
17 RAM.vhd
18 Top_Filtre_IIR.vhd
19 Top_IIR.vhd
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@@ -1,11 +1,16
1 APB_FFT_half.vhd
1 lpp_fft.vhd
2 APB_FFT.vhd
2 actar.vhd
3 Driver_FFT.vhd
3 actram.vhd
4 FFTamont.vhd
4 CoreFFT.vhd
5 FFTaval.vhd
5 fft_components.vhd
6 FFT.vhd
6 fftDp.vhd
7 FFT.vhd.bak
7 fftSm.vhd
8 Flag_Extremum.vhd
8 primitives.vhd
9 Flag_Extremum.vhd.bak
9 twiddle.vhd
10 Linker_FFT.vhd
10 APB_FFT.vhd
11 lpp_fft.vhd
11 Driver_FFT.vhd
12 FFT.vhd
13 FFTamont.vhd
14 FFTaval.vhd
15 Flag_Extremum.vhd
16 Linker_FFT.vhd
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@@ -328,4 +328,47 Constant CLR_MAC_V0 : std_logic_vector(3
328 A_sync : OUT STD_LOGIC);
328 A_sync : OUT STD_LOGIC);
329 END COMPONENT;
329 END COMPONENT;
330
330
331 COMPONENT lpp_front_to_level
332 PORT (
333 clk : IN STD_LOGIC;
334 rstn : IN STD_LOGIC;
335 sin : IN STD_LOGIC;
336 sout : OUT STD_LOGIC);
337 END COMPONENT;
338
339 COMPONENT lpp_front_detection
340 PORT (
341 clk : IN STD_LOGIC;
342 rstn : IN STD_LOGIC;
343 sin : IN STD_LOGIC;
344 sout : OUT STD_LOGIC);
345 END COMPONENT;
346
347 COMPONENT lpp_front_positive_detection
348 PORT (
349 clk : IN STD_LOGIC;
350 rstn : IN STD_LOGIC;
351 sin : IN STD_LOGIC;
352 sout : OUT STD_LOGIC);
353 END COMPONENT;
354
355 COMPONENT SYNC_VALID_BIT
356 GENERIC (
357 NB_FF_OF_SYNC : INTEGER);
358 PORT (
359 clk_in : IN STD_LOGIC;
360 clk_out : IN STD_LOGIC;
361 rstn : IN STD_LOGIC;
362 sin : IN STD_LOGIC;
363 sout : OUT STD_LOGIC);
364 END COMPONENT;
365
366 COMPONENT RR_Arbiter_4
367 PORT (
368 clk : IN STD_LOGIC;
369 rstn : IN STD_LOGIC;
370 in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
371 out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
372 END COMPONENT;
373
331 END;
374 END;
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@@ -1,24 +1,23
1 Adder_V0.vhd
1 general_purpose.vhd
2 Adder.vhd
3 ADDRcntr.vhd
2 ADDRcntr.vhd
4 ALU_V0.vhd
5 ALU_V0.vhd~
6 ALU.vhd
3 ALU.vhd
4 Adder.vhd
7 Clk_Divider2.vhd
5 Clk_Divider2.vhd
8 Clk_Divider2.vhd~
9 Clk_divider.vhd
6 Clk_divider.vhd
10 general_purpose.vhd
7 MAC.vhd
11 general_purpose.vhd~
12 MAC_CONTROLER.vhd
8 MAC_CONTROLER.vhd
13 MAC_MUX2.vhd
14 MAC_MUX.vhd
9 MAC_MUX.vhd
10 MAC_MUX2.vhd
15 MAC_REG.vhd
11 MAC_REG.vhd
16 MAC_V0.vhd
17 MAC.vhd
18 Multiplier.vhd
19 MUX2.vhd
12 MUX2.vhd
20 MUXN.vhd
13 MUXN.vhd
14 Multiplier.vhd
21 REG.vhd
15 REG.vhd
16 SYNC_FF.vhd
22 Shifter.vhd
17 Shifter.vhd
23 SYNC_FF.vhd
24 TwoComplementer.vhd
18 TwoComplementer.vhd
19 lpp_front_to_level.vhd
20 lpp_front_detection.vhd
21 lpp_front_positive_detection.vhd
22 SYNC_VALID_BIT.vhd
23 RR_Arbiter_4.vhd
Show file before | Show file after | Hide comments
@@ -26,29 +26,28 USE grlib.stdlib.ALL;
26 USE grlib.devices.ALL;
26 USE grlib.devices.ALL;
27 LIBRARY lpp;
27 LIBRARY lpp;
28 USE lpp.apb_devices_list.ALL;
28 USE lpp.apb_devices_list.ALL;
29 USE lpp.general_purpose.ALL;
29 USE lpp.lpp_lfr_time_management.ALL;
30 USE lpp.lpp_lfr_time_management.ALL;
30
31
31 ENTITY apb_lfr_time_management IS
32 ENTITY apb_lfr_time_management IS
32
33
33 GENERIC(
34 GENERIC(
34 pindex : INTEGER := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
37 pirq : INTEGER := 0; --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0 --! 2 consecutive IRQ lines are used
38 masterclk : INTEGER := 25000000; --! master clock in Hz
39 timeclk : INTEGER := 49152000; --! other clock in Hz
40 finetimeclk : INTEGER := 65536 --! divided clock used for the fine time counter
41 );
39 );
42
40
43 PORT (
41 PORT (
44 clk25MHz : IN STD_LOGIC; --! Clock
42 clk25MHz : IN STD_LOGIC; --! Clock
45 clk49_152MHz : IN STD_LOGIC; --! secondary clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
46 resetn : IN STD_LOGIC; --! Reset
44 resetn : IN STD_LOGIC; --! Reset
47 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45
48 apbi : IN apb_slv_in_type; --! APB slave input signals
46 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbo : OUT apb_slv_out_type; --! APB slave output signals
47 apbi : IN apb_slv_in_type; --! APB slave input signals
50 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
48 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0) --! fine time
49 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
50 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
52 );
51 );
53
52
54 END apb_lfr_time_management;
53 END apb_lfr_time_management;
@@ -56,91 +55,83 END apb_lfr_time_management;
56 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
55 ARCHITECTURE Behavioral OF apb_lfr_time_management IS
57
56
58 CONSTANT REVISION : INTEGER := 1;
57 CONSTANT REVISION : INTEGER := 1;
59
60 --! the following types are defined in the grlib amba package
61 --! subtype amba_config_word is std_logic_vector(31 downto 0);
62 --! type apb_config_type is array (0 to NAPBCFG-1) of amba_config_word;
63 CONSTANT pconfig : apb_config_type := (
58 CONSTANT pconfig : apb_config_type := (
64 --! 0 => ahb_device_reg (VENDOR_LPP, LPP_ROTARY, 0, REVISION, 0),
65 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
59 0 => ahb_device_reg (VENDOR_LPP, 14, 0, REVISION, pirq),
66 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask)
61 );
67
62
68 TYPE apb_lfr_time_management_Reg IS RECORD
63 TYPE apb_lfr_time_management_Reg IS RECORD
69 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 ctrl : STD_LOGIC_VECTOR(31 DOWNTO 0);
70 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
72 fine_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
67 fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
73 next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
74 END RECORD;
68 END RECORD;
75
69
76 SIGNAL r : apb_lfr_time_management_Reg;
70 SIGNAL r : apb_lfr_time_management_Reg;
77 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
71 SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
78 SIGNAL force_tick : STD_LOGIC;
72 SIGNAL force_tick : STD_LOGIC;
79 SIGNAL previous_force_tick : STD_LOGIC;
73 SIGNAL previous_force_tick : STD_LOGIC;
80 SIGNAL soft_tick : STD_LOGIC;
74 SIGNAL soft_tick : STD_LOGIC;
81 -- SIGNAL reset_next_commutation : STD_LOGIC;
75
82
83 SIGNAL irq1 : STD_LOGIC;
76 SIGNAL irq1 : STD_LOGIC;
84 SIGNAL irq2 : STD_LOGIC;
77 SIGNAL irq2 : STD_LOGIC;
85
78
86 BEGIN
79 SIGNAL coarsetime_reg_updated : STD_LOGIC;
80 SIGNAL coarsetime_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
87
81
88 lfrtimemanagement0 : lfr_time_management
82 SIGNAL coarse_time_new : STD_LOGIC;
89 GENERIC MAP(
83 SIGNAL coarse_time_new_49 : STD_LOGIC;
90 masterclk => masterclk,
84 SIGNAL coarse_time_49 : STD_LOGIC_VECTOR(31 DOWNTO 0);
91 timeclk => timeclk,
85 SIGNAL coarse_time_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
92 finetimeclk => finetimeclk,
86
93 nb_clk_div_ticks => 1)
87 SIGNAL fine_time_new : STD_LOGIC;
94 PORT MAP(
88 SIGNAL fine_time_new_temp : STD_LOGIC;
95 master_clock => clk25MHz,
89 SIGNAL fine_time_new_49 : STD_LOGIC;
96 time_clock => clk49_152MHz,
90 SIGNAL fine_time_49 : STD_LOGIC_VECTOR(15 DOWNTO 0);
97 resetn => resetn,
91 SIGNAL fine_time_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
98 grspw_tick => grspw_tick,
92 SIGNAL tick : STD_LOGIC;
99 soft_tick => soft_tick,
93 SIGNAL new_timecode : STD_LOGIC;
100 coarse_time_load => r.coarse_time_load,
94 SIGNAL new_coarsetime : STD_LOGIC;
101 coarse_time => r.coarse_time,
95
102 fine_time => r.fine_time,
96 BEGIN
103 next_commutation => r.next_commutation,
97 -----------------------------------------------------------------------------
104 -- reset_next_commutation => reset_next_commutation,
98 -- TODO
105 irq1 => irq1,--apbo.pirq(pirq),
99 -- IRQ 1 & 2
106 irq2 => irq2);--apbo.pirq(pirq+1));
100 -----------------------------------------------------------------------------
101 irq2 <= '0';
102 irq1 <= '0';
107
103
108 --apbo.pirq <= (OTHERS => '0');
104
105 --all_irq_gen : FOR I IN 15 DOWNTO 0 GENERATE
106 --irq1_gen : IF I = pirq GENERATE
107 apbo.pirq(pirq) <= irq1;
108 --END GENERATE irq1_gen;
109 --irq2_gen : IF I = pirq+1 GENERATE
110 apbo.pirq(pirq+1) <= irq2;
111 -- END GENERATE irq2_gen;
112 -- others_irq : IF (I < pirq) OR (I > (pirq + 1)) GENERATE
113 -- apbo.pirq(I) <= '0';
114 -- END GENERATE others_irq;
115 --END GENERATE all_irq_gen;
109
116
110 all_irq_gen: FOR I IN 15 DOWNTO 0 GENERATE
117 PROCESS(resetn, clk25MHz)
111 irq1_gen: IF I = pirq GENERATE
112 apbo.pirq(I) <= irq1;
113 END GENERATE irq1_gen;
114 irq2_gen: IF I = pirq+1 GENERATE
115 apbo.pirq(I) <= irq2;
116 END GENERATE irq2_gen;
117 others_irq: IF (I < pirq) OR (I > (pirq + 1)) GENERATE
118 apbo.pirq(I) <= '0';
119 END GENERATE others_irq;
120 END GENERATE all_irq_gen;
121
122 --all_irq_sig: FOR I IN 31 DOWNTO 0 GENERATE
123 --END GENERATE all_irq_sig;
124
125 PROCESS(resetn, clk25MHz)--, reset_next_commutation)
126 BEGIN
118 BEGIN
127
119
128 IF resetn = '0' THEN
120 IF resetn = '0' THEN
129 Rdata <= (OTHERS => '0');
121 Rdata <= (OTHERS => '0');
130 r.coarse_time_load <= x"80000000";
122 r.coarse_time_load <= x"80000000";
131 r.ctrl <= x"00000000";
123 r.ctrl <= x"00000000";
132 r.next_commutation <= x"ffffffff";
133 force_tick <= '0';
124 force_tick <= '0';
134 previous_force_tick <= '0';
125 previous_force_tick <= '0';
135 soft_tick <= '0';
126 soft_tick <= '0';
136
127
137 --ELSIF reset_next_commutation = '1' THEN
128 coarsetime_reg_updated <= '0';
138 -- r.next_commutation <= x"ffffffff";
139
129
140 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
130 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN
131 coarsetime_reg_updated <= '0';
141
132
133 force_tick <= r.ctrl(0);
142 previous_force_tick <= force_tick;
134 previous_force_tick <= force_tick;
143 force_tick <= r.ctrl(0);
144 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
135 IF (previous_force_tick = '0') AND (force_tick = '1') THEN
145 soft_tick <= '1';
136 soft_tick <= '1';
146 ELSE
137 ELSE
@@ -154,10 +145,8 BEGIN
154 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
145 r.ctrl <= apbi.pwdata(31 DOWNTO 0);
155 WHEN "000001" =>
146 WHEN "000001" =>
156 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
147 r.coarse_time_load <= apbi.pwdata(31 DOWNTO 0);
157 WHEN "000100" =>
148 coarsetime_reg_updated <= '1';
158 r.next_commutation <= apbi.pwdata(31 DOWNTO 0);
159 WHEN OTHERS =>
149 WHEN OTHERS =>
160 r.coarse_time_load <= x"00000000";
161 END CASE;
150 END CASE;
162 ELSIF r.ctrl(0) = '1' THEN
151 ELSIF r.ctrl(0) = '1' THEN
163 r.ctrl(0) <= '0';
152 r.ctrl(0) <= '0';
@@ -167,30 +156,14 BEGIN
167 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
156 IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
168 CASE apbi.paddr(7 DOWNTO 2) IS
157 CASE apbi.paddr(7 DOWNTO 2) IS
169 WHEN "000000" =>
158 WHEN "000000" =>
170 Rdata(31 DOWNTO 24) <= r.ctrl(31 DOWNTO 24);
159 Rdata(31 DOWNTO 0) <= r.ctrl(31 DOWNTO 0);
171 Rdata(23 DOWNTO 16) <= r.ctrl(23 DOWNTO 16);
172 Rdata(15 DOWNTO 8) <= r.ctrl(15 DOWNTO 8);
173 Rdata(7 DOWNTO 0) <= r.ctrl(7 DOWNTO 0);
174 WHEN "000001" =>
160 WHEN "000001" =>
175 Rdata(31 DOWNTO 24) <= r.coarse_time_load(31 DOWNTO 24);
161 Rdata(31 DOWNTO 0) <= r.coarse_time_load(31 DOWNTO 0);
176 Rdata(23 DOWNTO 16) <= r.coarse_time_load(23 DOWNTO 16);
177 Rdata(15 DOWNTO 8) <= r.coarse_time_load(15 DOWNTO 8);
178 Rdata(7 DOWNTO 0) <= r.coarse_time_load(7 DOWNTO 0);
179 WHEN "000010" =>
162 WHEN "000010" =>
180 Rdata(31 DOWNTO 24) <= r.coarse_time(31 DOWNTO 24);
163 Rdata(31 DOWNTO 0) <= r.coarse_time(31 DOWNTO 0);
181 Rdata(23 DOWNTO 16) <= r.coarse_time(23 DOWNTO 16);
182 Rdata(15 DOWNTO 8) <= r.coarse_time(15 DOWNTO 8);
183 Rdata(7 DOWNTO 0) <= r.coarse_time(7 DOWNTO 0);
184 WHEN "000011" =>
164 WHEN "000011" =>
185 Rdata(31 DOWNTO 24) <= r.fine_time(31 DOWNTO 24);
165 Rdata(31 DOWNTO 16) <= (OTHERS => '0');
186 Rdata(23 DOWNTO 16) <= r.fine_time(23 DOWNTO 16);
166 Rdata(15 DOWNTO 0) <= r.fine_time(15 DOWNTO 0);
187 Rdata(15 DOWNTO 8) <= r.fine_time(15 DOWNTO 8);
188 Rdata(7 DOWNTO 0) <= r.fine_time(7 DOWNTO 0);
189 WHEN "000100" =>
190 Rdata(31 DOWNTO 24) <= r.next_commutation(31 DOWNTO 24);
191 Rdata(23 DOWNTO 16) <= r.next_commutation(23 DOWNTO 16);
192 Rdata(15 DOWNTO 8) <= r.next_commutation(15 DOWNTO 8);
193 Rdata(7 DOWNTO 0) <= r.next_commutation(7 DOWNTO 0);
194 WHEN OTHERS =>
167 WHEN OTHERS =>
195 Rdata(31 DOWNTO 0) <= x"00000000";
168 Rdata(31 DOWNTO 0) <= x"00000000";
196 END CASE;
169 END CASE;
@@ -199,10 +172,115 BEGIN
199 END IF;
172 END IF;
200 END PROCESS;
173 END PROCESS;
201
174
202 apbo.prdata <= Rdata ;--WHEN apbi.penable = '1';
175 apbo.prdata <= Rdata;
176 apbo.pconfig <= pconfig;
177 apbo.pindex <= pindex;
178
203 coarse_time <= r.coarse_time;
179 coarse_time <= r.coarse_time;
204 fine_time <= r.fine_time;
180 fine_time <= r.fine_time;
205 apbo.pconfig <= pconfig;
181 -----------------------------------------------------------------------------
206 apbo.pindex <= pindex;
182
183 coarsetime_reg <= r.coarse_time_load;
184 r.coarse_time <= coarse_time_s;
185 r.fine_time <= fine_time_s;
186 -----------------------------------------------------------------------------
187 -- IN coarsetime_reg_updated
188 -- IN coarsetime_reg
189
190 -- OUT coarse_time_s -- ok
191 -- OUT fine_time_s -- ok
192 -----------------------------------------------------------------------------
193
194 tick <= grspw_tick OR soft_tick;
195
196 SYNC_VALID_BIT_1 : SYNC_VALID_BIT
197 GENERIC MAP (
198 NB_FF_OF_SYNC => 2)
199 PORT MAP (
200 clk_in => clk25MHz,
201 clk_out => clk49_152MHz,
202 rstn => resetn,
203 sin => tick,
204 sout => new_timecode);
205
206 SYNC_VALID_BIT_2 : SYNC_VALID_BIT
207 GENERIC MAP (
208 NB_FF_OF_SYNC => 2)
209 PORT MAP (
210 clk_in => clk25MHz,
211 clk_out => clk49_152MHz,
212 rstn => resetn,
213 sin => coarsetime_reg_updated,
214 sout => new_coarsetime);
215
216 --SYNC_VALID_BIT_3 : SYNC_VALID_BIT
217 -- GENERIC MAP (
218 -- NB_FF_OF_SYNC => 2)
219 -- PORT MAP (
220 -- clk_in => clk49_152MHz,
221 -- clk_out => clk25MHz,
222 -- rstn => resetn,
223 -- sin => 9,
224 -- sout => );
225
226 SYNC_FF_1: SYNC_FF
227 GENERIC MAP (
228 NB_FF_OF_SYNC => 2)
229 PORT MAP (
230 clk => clk25MHz,
231 rstn => resetn,
232 A => fine_time_new_49,
233 A_sync => fine_time_new_temp);
234
235 lpp_front_detection_1: lpp_front_detection
236 PORT MAP (
237 clk => clk25MHz,
238 rstn => resetn,
239 sin => fine_time_new_temp,
240 sout => fine_time_new);
241
242 SYNC_VALID_BIT_4 : SYNC_VALID_BIT
243 GENERIC MAP (
244 NB_FF_OF_SYNC => 2)
245 PORT MAP (
246 clk_in => clk49_152MHz,
247 clk_out => clk25MHz,
248 rstn => resetn,
249 sin => coarse_time_new_49,
250 sout => coarse_time_new);
251
252 PROCESS (clk25MHz, resetn)
253 BEGIN -- PROCESS
254 IF resetn = '0' THEN -- asynchronous reset (active low)
255 fine_time_s <= (OTHERS => '0');
256 coarse_time_s <= (OTHERS => '0');
257 ELSIF clk25MHz'EVENT AND clk25MHz = '1' THEN -- rising clock edge
258 IF fine_time_new = '1' THEN
259 fine_time_s <= fine_time_49;
260 END IF;
261 IF coarse_time_new = '1' THEN
262 coarse_time_s <= coarse_time_49;
263 END IF;
264 END IF;
265 END PROCESS;
266
267 -----------------------------------------------------------------------------
268 -- LFR_TIME_MANAGMENT
269 -----------------------------------------------------------------------------
270 lfr_time_management_1 : lfr_time_management
271 GENERIC MAP (
272 nb_time_code_missing_limit => 60)
273 PORT MAP (
274 clk => clk49_152MHz,
275 rstn => resetn,
276
277 new_timecode => new_timecode,
278 new_coarsetime => new_coarsetime,
279 coarsetime_reg => coarsetime_reg,
280
281 fine_time => fine_time_49,
282 fine_time_new => fine_time_new_49,
283 coarse_time => coarse_time_49,
284 coarse_time_new => coarse_time_new_49);
207
285
208 END Behavioral;
286 END Behavioral;
Show file before | Show file after | Hide comments
@@ -21,247 +21,91 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
22 USE IEEE.NUMERIC_STD.ALL;
23 LIBRARY lpp;
23 LIBRARY lpp;
24 USE lpp.general_purpose.Clk_divider;
24 USE lpp.lpp_lfr_time_management.ALL;
25
25
26 ENTITY lfr_time_management IS
26 ENTITY lfr_time_management IS
27 GENERIC (
27 GENERIC (
28 masterclk : INTEGER := 25000000; -- master clock in Hz
28 nb_time_code_missing_limit : INTEGER := 60
29 timeclk : INTEGER := 49152000; -- 2nd clock in Hz
30 finetimeclk : INTEGER := 65536; -- divided clock used for the fine time counter
31 nb_clk_div_ticks : INTEGER := 1 -- nb ticks before commutation to AUTO state
32 );
29 );
33 PORT (
30 PORT (
34 master_clock : IN STD_LOGIC; --! Clock -- 25MHz
31 clk : IN STD_LOGIC;
35 time_clock : IN STD_LOGIC; --! 2nd Clock -- 49MHz
32 rstn : IN STD_LOGIC;
36 resetn : IN STD_LOGIC; --! Reset
33
37 grspw_tick : IN STD_LOGIC;
34 new_timecode : IN STD_LOGIC; -- transition signal information
38 soft_tick : IN STD_LOGIC; --! soft tick, load the coarse_time value -- 25MHz
35 new_coarsetime : IN STD_LOGIC; -- transition signal information
39 coarse_time_load : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
36 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
37
41 fine_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
38 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
42 next_commutation : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- 25MHz
39 fine_time_new : OUT STD_LOGIC;
43 -- reset_next_commutation : OUT STD_LOGIC;
40 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
44 irq1 : OUT STD_LOGIC; -- 25MHz
41 coarse_time_new : OUT STD_LOGIC
45 irq2 : OUT STD_LOGIC -- 25MHz
46 );
42 );
47 END lfr_time_management;
43 END lfr_time_management;
48
44
49 ARCHITECTURE Behavioral OF lfr_time_management IS
45 ARCHITECTURE Behavioral OF lfr_time_management IS
50
46
51 SIGNAL resetn_clk_div : STD_LOGIC;
47 SIGNAL counter_clear : STD_LOGIC;
52 SIGNAL clk_div : STD_LOGIC;
48 SIGNAL counter_full : STD_LOGIC;
53 --
49
54 SIGNAL flag : STD_LOGIC;
50 SIGNAL nb_time_code_missing : INTEGER;
55 SIGNAL s_coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
51 SIGNAL coarse_time_s : INTEGER;
56 SIGNAL previous_coarse_time_load : STD_LOGIC_VECTOR(31 DOWNTO 0);
57 SIGNAL cpt : INTEGER RANGE 0 TO 100000;
58 SIGNAL secondary_cpt : INTEGER RANGE 0 TO 72000;
59 --
60 SIGNAL sirq1 : STD_LOGIC;
61 SIGNAL sirq2 : STD_LOGIC;
62 SIGNAL cpt_next_commutation : INTEGER RANGE 0 TO 100000;
63 SIGNAL p_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
64 SIGNAL latched_next_commutation : STD_LOGIC_VECTOR(31 DOWNTO 0);
65 SIGNAL p_clk_div : STD_LOGIC;
66 --
67 TYPE state_type IS (auto, slave);
68 SIGNAL state : state_type;
69 TYPE timer_type IS (idle, engaged);
70 SIGNAL commutation_timer : timer_type;
71
52
53 SIGNAL new_coarsetime_s : STD_LOGIC;
54
72 BEGIN
55 BEGIN
73
56
74 --*******************************************
57 lpp_counter_1 : lpp_counter
75 -- COMMUTATION TIMER AND INTERRUPT GENERATION
58 GENERIC MAP (
76 PROCESS(master_clock, resetn)
59 nb_wait_period => 750,
77 BEGIN
60 nb_bit_of_data => 16)
61 PORT MAP (
62 clk => clk,
63 rstn => rstn,
64 clear => counter_clear,
65 full => counter_full,
66 data => fine_time,
67 new_data => fine_time_new);
78
68
79 IF resetn = '0' THEN
69 PROCESS (clk, rstn)
80 commutation_timer <= idle;
70 BEGIN -- PROCESS
81 cpt_next_commutation <= 0;
71 IF rstn = '0' THEN -- asynchronous reset (active low)
82 sirq1 <= '0';
72 nb_time_code_missing <= 0;
83 sirq2 <= '0';
73 counter_clear <= '0';
84 latched_next_commutation <= x"ffffffff";
74 coarse_time_s <= 0;
85 p_next_commutation <= (others => '0');
75 coarse_time_new <= '0';
86 p_clk_div <= '0';
76 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
87 ELSIF master_clock'EVENT AND master_clock = '1' THEN
77 IF new_coarsetime = '1' THEN
78 new_coarsetime_s <= '1';
79 ELSIF new_timecode = '1' THEN
80 new_coarsetime_s <= '0';
81 END IF;
88
82
89 CASE commutation_timer IS
83 IF new_timecode = '1' THEN
90
84 coarse_time_new <= '1';
91 WHEN idle =>
85 IF new_coarsetime_s = '1' THEN
92 sirq1 <= '0';
86 coarse_time_s <= to_integer(unsigned(coarsetime_reg));
93 sirq2 <= '0';
87 ELSE
94 IF s_coarse_time = latched_next_commutation THEN
88 coarse_time_s <= coarse_time_s + 1;
95 commutation_timer <= engaged; -- transition to state "engaged"
89 END IF;
96 sirq1 <= '1'; -- start the pulse on sirq1
90 nb_time_code_missing <= 0;
97 latched_next_commutation <= x"ffffffff";
91 counter_clear <= '1';
98 ELSIF NOT(p_next_commutation = next_commutation) THEN -- next_commutation has changed
92 ELSE
99 latched_next_commutation <= next_commutation; -- latch the value
93 coarse_time_new <= '0';
94 counter_clear <= '0';
95 IF counter_full = '1' THEN
96 coarse_time_new <= '1';
97 coarse_time_s <= coarse_time_s + 1;
98 IF nb_time_code_missing = nb_time_code_missing_limit THEN
99 nb_time_code_missing <= nb_time_code_missing_limit;
100 ELSE
100 ELSE
101 commutation_timer <= idle;
101 nb_time_code_missing <= nb_time_code_missing + 1;
102 END IF;
102 END IF;
103
103 END IF;
104 WHEN engaged =>
104 END IF;
105 sirq1 <= '0'; -- stop the pulse on sirq1
106 IF NOT(p_clk_div = clk_div) AND clk_div = '1' THEN -- detect a clk_div raising edge
107 IF cpt_next_commutation = 65536 THEN
108 cpt_next_commutation <= 0;
109 commutation_timer <= idle;
110 sirq2 <= '1'; -- start the pulse on sirq2
111 ELSE
112 cpt_next_commutation <= cpt_next_commutation + 1;
113 END IF;
114 END IF;
115
116 WHEN OTHERS =>
117 commutation_timer <= idle;
118
119 END CASE;
120
121 p_next_commutation <= next_commutation;
122 p_clk_div <= clk_div;
123
124 END IF;
105 END IF;
125
126 END PROCESS;
106 END PROCESS;
127
107
128 irq1 <= sirq1;
108 coarse_time(30 DOWNTO 0) <= STD_LOGIC_VECTOR(to_unsigned(coarse_time_s,31));
129 irq2 <= sirq2;
109 coarse_time(31) <= '1' WHEN nb_time_code_missing = nb_time_code_missing_limit ELSE '0';
130 -- reset_next_commutation <= '0';
110
131
132 --
133 --*******************************************
134
135 --**********************
136 -- synchronization stage
137 PROCESS(master_clock, resetn) -- resynchronisation with clk
138 BEGIN
139
140 IF resetn = '0' THEN
141 coarse_time(31 DOWNTO 0) <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
142
143 ELSIF master_clock'EVENT AND master_clock = '1' THEN
144 coarse_time(31 DOWNTO 0) <= s_coarse_time(31 DOWNTO 0); -- coarse_time is changed synchronously with clk
145 END IF;
146
147 END PROCESS;
148 --
149 --**********************
150
151
152 -- PROCESS(clk_div, resetn, grspw_tick, soft_tick, flag, coarse_time_load) -- JC
153 PROCESS(clk_div, resetn) -- JC
154 BEGIN
155
156 IF resetn = '0' THEN
157 flag <= '0';
158 cpt <= 0;
159 secondary_cpt <= 0;
160 s_coarse_time <= x"80000000"; -- set the most significant bit of the coarse time to 1 on reset
161 previous_coarse_time_load <= x"80000000";
162 state <= auto;
163
164 --ELSIF grspw_tick = '1' OR soft_tick = '1' THEN
165 -- --IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
166 -- -- s_coarse_time <= coarse_time_load;
167 -- -- flag <= '0';
168 -- --ELSE -- if coarse_time_load has not changed, increment the value autonomously
169 -- -- s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
170 -- --END IF;
171
172 -- cpt <= 0;
173 -- secondary_cpt <= 0;
174 -- state <= slave;
175
176 ELSIF clk_div'EVENT AND clk_div = '1' THEN
177
178 CASE state IS
179
180 WHEN auto =>
181 IF grspw_tick = '1' OR soft_tick = '1' THEN
182 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
183 s_coarse_time <= coarse_time_load;
184 ELSE -- if coarse_time_load has not changed, increment the value autonomously
185 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
186 END IF;
187 flag <= '0';
188 cpt <= 0;
189 secondary_cpt <= 0;
190 state <= slave;
191 ELSE
192 IF cpt = 65535 THEN
193 IF flag = '1' THEN
194 s_coarse_time <= coarse_time_load;
195 flag <= '0';
196 ELSE
197 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
198 END IF;
199 cpt <= 0;
200 secondary_cpt <= secondary_cpt + 1;
201 ELSE
202 cpt <= cpt + 1;
203 END IF;
204 END IF;
205
206 WHEN slave =>
207 IF grspw_tick = '1' OR soft_tick = '1' THEN
208 IF flag = '1' THEN -- coarse_time_load shall change at least 1/65536 s before the timecode
209 s_coarse_time <= coarse_time_load;
210 ELSE -- if coarse_time_load has not changed, increment the value autonomously
211 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
212 END IF;
213 flag <= '0';
214 cpt <= 0;
215 secondary_cpt <= 0;
216 state <= slave;
217 ELSE
218 IF cpt = 65536 + nb_clk_div_ticks THEN -- 1 / 65536 = 15.259 us
219 state <= auto; -- commutation to AUTO state
220 IF flag = '1' THEN
221 s_coarse_time <= coarse_time_load;
222 flag <= '0';
223 ELSE
224 s_coarse_time <= STD_LOGIC_VECTOR(UNSIGNED(s_coarse_time) + 1);
225 END IF;
226 cpt <= nb_clk_div_ticks; -- reset cpt at nb_clk_div_ticks
227 secondary_cpt <= secondary_cpt + 1;
228 ELSE
229 cpt <= cpt + 1;
230 END IF;
231 END IF;
232
233 WHEN OTHERS =>
234 state <= auto;
235
236 END CASE;
237
238 IF secondary_cpt > 60 THEN
239 s_coarse_time(31) <= '1';
240 END IF;
241
242 IF NOT(previous_coarse_time_load = coarse_time_load) THEN
243 flag <= '1';
244 END IF;
245
246 previous_coarse_time_load <= coarse_time_load;
247
248 END IF;
249
250 END PROCESS;
251
252 fine_time <= STD_LOGIC_VECTOR(to_unsigned(cpt, 32));
253
254 -- resetn grspw_tick soft_tick resetn_clk_div
255 -- 0 0 0 0
256 -- 0 0 1 0
257 -- 0 1 0 0
258 -- 0 1 1 0
259 -- 1 0 0 1
260 -- 1 0 1 0
261 -- 1 1 0 0
262 -- 1 1 1 0
263 resetn_clk_div <= '1' WHEN ((resetn = '1') AND (grspw_tick = '0') AND (soft_tick = '0')) ELSE '0';
264 Clk_divider0 : Clk_divider -- the target frequency is 65536 Hz
265 GENERIC MAP (timeclk, finetimeclk) PORT MAP (time_clock, resetn_clk_div, clk_div);
266
267 END Behavioral;
111 END Behavioral;
Show file before | Show file after | Hide comments
@@ -17,67 +17,68
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 library IEEE;
20 LIBRARY IEEE;
21 use IEEE.STD_LOGIC_1164.all;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 library grlib;
22 LIBRARY grlib;
23 use grlib.amba.all;
23 USE grlib.amba.ALL;
24 use grlib.stdlib.all;
24 USE grlib.stdlib.ALL;
25 use grlib.devices.all;
25 USE grlib.devices.ALL;
26
26
27 package lpp_lfr_time_management is
27 PACKAGE lpp_lfr_time_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_TIME_MANAGEMENT
31
31
32 component apb_lfr_time_management is
32 COMPONENT apb_lfr_time_management IS
33
33
34 generic(
34 GENERIC(
35 pindex : integer := 0; --! APB slave index
35 pindex : INTEGER := 0; --! APB slave index
36 paddr : integer := 0; --! ADDR field of the APB BAR
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : integer := 16#fff#; --! MASK field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : integer := 0; --! 2 consecutive IRQ lines are used
38 pirq : INTEGER := 0
39 masterclk : integer := 25000000; --! master clock in Hz
39 );
40 timeclk : integer := 49152000; --! other clock in Hz
41 finetimeclk : integer := 65536 --! divided clock used for the fine time counter
42 );
43
40
44 Port (
41 PORT (
45 clk25MHz : in STD_LOGIC; --! Clock
42 clk25MHz : IN STD_LOGIC; --! Clock
46 clk49_152MHz : in STD_LOGIC; --! secondary clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
47 resetn : in STD_LOGIC; --! Reset
44 resetn : IN STD_LOGIC; --! Reset
48 grspw_tick : in STD_LOGIC; --! grspw signal asserted when a valid time-code is received
45 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
49 apbi : in apb_slv_in_type; --! APB slave input signals
46 apbi : IN apb_slv_in_type; --! APB slave input signals
50 apbo : out apb_slv_out_type; --! APB slave output signals
47 apbo : OUT apb_slv_out_type; --! APB slave output signals
51 coarse_time : out std_logic_vector(31 downto 0); --! coarse time
48 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
52 fine_time : out std_logic_vector(31 downto 0) --! fine time
49 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
53 );
50 );
54
51
55 end component;
52 END COMPONENT;
56
53
57 component lfr_time_management is
54 COMPONENT lfr_time_management
55 GENERIC (
56 nb_time_code_missing_limit : INTEGER);
57 PORT (
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 new_timecode : IN STD_LOGIC;
61 new_coarsetime : IN STD_LOGIC;
62 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
64 fine_time_new : OUT STD_LOGIC;
65 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_new : OUT STD_LOGIC
67 );
68 END COMPONENT;
58
69
59 generic (
70 COMPONENT lpp_counter
60 masterclk : integer := 25000000; -- master clock in Hz
71 GENERIC (
61 timeclk : integer := 49152000; -- 2nd clock in Hz
72 nb_wait_period : INTEGER;
62 finetimeclk : integer := 65536; -- divided clock used for the fine time counter
73 nb_bit_of_data : INTEGER);
63 nb_clk_div_ticks : integer := 1 -- nb ticks before commutation to AUTO state
74 PORT (
64 );
75 clk : IN STD_LOGIC;
65 Port (
76 rstn : IN STD_LOGIC;
66 master_clock : in std_logic; --! Clock
77 clear : IN STD_LOGIC;
67 time_clock : in std_logic; --! 2nd Clock
78 full : OUT STD_LOGIC;
68 resetn : in std_logic; --! Reset
79 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
69 grspw_tick : in std_logic;
80 new_data : OUT STD_LOGIC );
70 soft_tick : in std_logic; --! soft tick, load the coarse_time value
81 END COMPONENT;
71 coarse_time_load : in std_logic_vector(31 downto 0);
72 coarse_time : out std_logic_vector(31 downto 0);
73 fine_time : out std_logic_vector(31 downto 0);
74 next_commutation : in std_logic_vector(31 downto 0);
75 -- reset_next_commutation: out std_logic;
76 irq1 : out std_logic;
77 irq2 : out std_logic
78 );
79
80 end component;
81
82
82 end lpp_lfr_time_management;
83 END lpp_lfr_time_management;
83
84
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@@ -1,3 +1,4
1 apb_lfr_time_management.vhd
1 apb_lfr_time_management.vhd
2 lpp_counter.vhd
2 lfr_time_management.vhd
3 lfr_time_management.vhd
3 lpp_lfr_time_management.vhd
4 lpp_lfr_time_management.vhd
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@@ -30,7 +30,6 entity HeaderBuilder is
30 clkm : in std_logic;
30 clkm : in std_logic;
31 rstn : in std_logic;
31 rstn : in std_logic;
32
32
33 pong : in std_logic;
34 Statu : in std_logic_vector(3 downto 0);
33 Statu : in std_logic_vector(3 downto 0);
35 Matrix_Type : in std_logic_vector(1 downto 0);
34 Matrix_Type : in std_logic_vector(1 downto 0);
36 Matrix_Write : in std_logic;
35 Matrix_Write : in std_logic;
@@ -57,7 +56,6 signal Matrix_Param : std_logic_vect
57 signal Write_reg : std_logic;
56 signal Write_reg : std_logic;
58 signal Data_cpt : integer;
57 signal Data_cpt : integer;
59 signal MAX : integer;
58 signal MAX : integer;
60 signal pong_reg : std_logic;
61
59
62 type etat is (idle0,idle1,pong0,pong1);
60 type etat is (idle0,idle1,pong0,pong1);
63 signal ect : etat;
61 signal ect : etat;
@@ -69,7 +67,6 begin
69 if(rstn='0')then
67 if(rstn='0')then
70 ect <= idle0;
68 ect <= idle0;
71 Valid <= '0';
69 Valid <= '0';
72 pong_reg <= '0';
73 header_val <= '0';
70 header_val <= '0';
74 header(5 downto 0) <= (others => '0');
71 header(5 downto 0) <= (others => '0');
75 Write_reg <= '0';
72 Write_reg <= '0';
@@ -79,7 +76,6 begin
79
76
80 elsif(clkm' event and clkm='1')then
77 elsif(clkm' event and clkm='1')then
81 Write_reg <= Matrix_Write;
78 Write_reg <= Matrix_Write;
82 pong_reg <= pong;
83
79
84 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
80 if(Statu="0001" or Statu="0011" or Statu="0110" or Statu="1010" or Statu="1111")then
85 MAX <= 128;
81 MAX <= 128;
@@ -87,17 +83,6 begin
87 MAX <= 256;
83 MAX <= 256;
88 end if;
84 end if;
89
85
90 -- if(Write_reg = '0' and Matrix_Write = '1')then
91 -- if(Data_cpt = MAX)then
92 -- Data_cpt <= 0;
93 -- Valid <= '1';
94 -- header_val <= '1';
95 -- else
96 -- Data_cpt <= Data_cpt + 1;
97 -- Valid <= '0';
98 -- end if;
99 -- end if;
100
101 if(Write_reg = '0' and Matrix_Write = '1')then
86 if(Write_reg = '0' and Matrix_Write = '1')then
102 Data_cpt <= Data_cpt + 1;
87 Data_cpt <= Data_cpt + 1;
103 Valid <= '0';
88 Valid <= '0';
@@ -107,19 +92,7 begin
107 header_val <= '1';
92 header_val <= '1';
108 else
93 else
109 Valid <= '0';
94 Valid <= '0';
110 end if;
95 end if;
111
112 -- if(header_ack = '1')then
113 -- header_val <= '0';
114 -- end if;
115
116 -- if(emptyIN = "10")then
117 -- ping <= '0';
118 -- elsif(emptyIN = "01")then
119 -- ping <= '1';
120 -- else
121 -- ping <= ping;
122 -- end if;
123
96
124
97
125 case ect is
98 case ect is
@@ -127,11 +100,7 begin
127 when idle0 =>
100 when idle0 =>
128 if(header_ack = '1')then
101 if(header_ack = '1')then
129 header_val <= '0';
102 header_val <= '0';
130 --if(pong = '1')then
103 ect <= pong0;
131 ect <= pong0;
132 --elsif(pong = '0')then
133 --ect <= pong1;
134 --end if;
135 end if;
104 end if;
136
105
137 when pong0 =>
106 when pong0 =>
@@ -160,8 +129,6 begin
160
129
161 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
130 Matrix_Param <= std_logic_vector(to_unsigned(to_integer(unsigned(Statu))-1,4));
162
131
163 --header(1 downto 0) <= Matrix_Type;
164 --header(5 downto 2) <= Matrix_Param;
165 header(31 downto 6) <= (others => '0');
132 header(31 downto 6) <= (others => '0');
166
133
167 with ect select
134 with ect select
Show file before | Show file after | Hide comments
@@ -38,7 +38,6 component HeaderBuilder is
38 clkm : in std_logic;
38 clkm : in std_logic;
39 rstn : in std_logic;
39 rstn : in std_logic;
40
40
41 pong : in std_logic;
42 Statu : in std_logic_vector(3 downto 0);
41 Statu : in std_logic_vector(3 downto 0);
43 Matrix_Type : in std_logic_vector(1 downto 0);
42 Matrix_Type : in std_logic_vector(1 downto 0);
44 Matrix_Write : in std_logic;
43 Matrix_Write : in std_logic;
Show file before | Show file after | Hide comments
@@ -50,6 +50,78 PACKAGE lpp_ad_conv IS
50
50
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
51 TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
52
52
53 -----------------------------------------------------------------------------
54 -----------------------------------------------------------------------------
55 SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
56
57 SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
58
59 SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
60
61 SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
62
63 SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
64
65 SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
66
67 TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
68
69 TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
70
71 TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
72
73 TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
74
75 TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
76
77 TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
78
79 COMPONENT RHF1401_drvr IS
80 GENERIC(
81 ChanelCount : INTEGER := 8);
82 PORT (
83 cnv_clk : IN STD_LOGIC;
84 clk : IN STD_LOGIC;
85 rstn : IN STD_LOGIC;
86 ADC_data : IN Samples14;
87 --ADC_smpclk : OUT STD_LOGIC;
88 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
89 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
90 sample_val : OUT STD_LOGIC
91 );
92 END COMPONENT;
93
94 COMPONENT top_ad_conv_RHF1401
95 GENERIC (
96 ChanelCount : INTEGER;
97 ncycle_cnv_high : INTEGER := 79;
98 ncycle_cnv : INTEGER := 500);
99 PORT (
100 cnv_clk : IN STD_LOGIC;
101 cnv_rstn : IN STD_LOGIC;
102 cnv : OUT STD_LOGIC;
103 clk : IN STD_LOGIC;
104 rstn : IN STD_LOGIC;
105 ADC_data : IN Samples14;
106 ADC_nOE : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
107 sample : OUT Samples14v(ChanelCount-1 DOWNTO 0);
108 sample_val : OUT STD_LOGIC);
109 END COMPONENT;
110
111 COMPONENT TestModule_RHF1401
112 GENERIC (
113 freq : INTEGER;
114 amplitude : INTEGER;
115 impulsion : INTEGER);
116 PORT (
117 ADC_smpclk : IN STD_LOGIC;
118 ADC_OEB_bar : IN STD_LOGIC;
119 ADC_data : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
120 END COMPONENT;
121
122 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124
53 COMPONENT ADS7886_drvr
125 COMPONENT ADS7886_drvr
54 GENERIC (
126 GENERIC (
55 ChanelCount : INTEGER;
127 ChanelCount : INTEGER;
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@@ -1,19 +1,4
1 AD7688_drvr_sync.vhd
2 AD7688_drvr.vhd
3 AD7688_drvr.vhd.orig
4 AD7688_spi_if.vhd
5 ADS1274_drvr.vhd
6 ADS1274_drvr.vhd~
7 ADS1278_drvr.vhd
8 ADS1278_drvr.vhd~
9 ADS7886_drvr.vhd
10 dual_ADS1278_drvr.vhd
11 dual_ADS1278_drvr.vhd~
12 lpp_ad_Conv.vhd
1 lpp_ad_Conv.vhd
13 lpp_ad_Conv.vhd~
14 lpp_ad_Conv.vhd.orig
15 lpp_apb_ad_conv.vhd
16 RHF1401.vhd
2 RHF1401.vhd
17 top_ad_conv_RHF1401.vhd
3 top_ad_conv_RHF1401.vhd
18 top_ad_conv.vhd
4 TestModule_RHF1401.vhd
19 WriteGen_ADC.vhd
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@@ -6,34 +6,36
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 library ieee;
9 LIBRARY ieee;
10 use ieee.std_logic_1164.all;
10 USE ieee.std_logic_1164.ALL;
11 library grlib;
11 LIBRARY grlib;
12 use grlib.amba.all;
12 USE grlib.amba.ALL;
13 use std.textio.all;
13 USE std.textio.ALL;
14
14
15
15
16 package apb_devices_list is
16 PACKAGE apb_devices_list IS
17
17
18
18
19 constant VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
21 constant ROCKET_TM : amba_device_type := 16#1#;
22 constant otherCore : amba_device_type := 16#2#;
23 constant LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 constant LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 constant LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 constant LPP_UART : amba_device_type := 16#6#;
27 constant LPP_CNA : amba_device_type := 16#7#;
28 constant LPP_APB_ADC : amba_device_type := 16#8#;
29 constant LPP_CHENILLARD : amba_device_type := 16#9#;
30 constant LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 constant LPP_FIFO_PID : amba_device_type := 16#11#;
32 constant LPP_FFT : amba_device_type := 16#12#;
33 constant LPP_MATRIX : amba_device_type := 16#13#;
34 constant LPP_DELAY : amba_device_type := 16#14#;
35 constant LPP_USB : amba_device_type := 16#15#;
36 constant LPP_BALISE : amba_device_type := 16#16#;
37
20
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
38
40
39 end;
41 END;
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@@ -1,4 +1,2
1 apb_devices_list.vhd
1 apb_devices_list.vhd
2 APB_MULTI_DIODE.vhd
3 APB_SIMPLE_DIODE.vhd
4 lpp_amba.vhd
2 lpp_amba.vhd
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@@ -31,7 +31,7 use lpp.lpp_amba.all;
31
31
32 package lpp_cna is
32 package lpp_cna is
33
33
34 component APB_CNA is
34 component APB_DAC is
35 generic (
35 generic (
36 pindex : integer := 0;
36 pindex : integer := 0;
37 paddr : integer := 0;
37 paddr : integer := 0;
@@ -43,6 +43,7 component APB_CNA is
43 rst : in std_logic;
43 rst : in std_logic;
44 apbi : in apb_slv_in_type;
44 apbi : in apb_slv_in_type;
45 apbo : out apb_slv_out_type;
45 apbo : out apb_slv_out_type;
46 Cal_EN : out std_logic;
46 SYNC : out std_logic;
47 SYNC : out std_logic;
47 SCLK : out std_logic;
48 SCLK : out std_logic;
48 DATA : out std_logic
49 DATA : out std_logic
@@ -50,9 +51,9 component APB_CNA is
50 end component;
51 end component;
51
52
52
53
53 component CNA_TabloC is
54 component DacDriver is
54 port(
55 port(
55 clock : in std_logic;
56 clk : in std_logic;
56 rst : in std_logic;
57 rst : in std_logic;
57 enable : in std_logic;
58 enable : in std_logic;
58 Data_C : in std_logic_vector(15 downto 0);
59 Data_C : in std_logic_vector(15 downto 0);
Show file before | Show file after | Hide comments
@@ -110,17 +110,17 ARCHITECTURE Behavioral OF lpp_dma_ip IS
110 WAIT_DATA_ACK,
110 WAIT_DATA_ACK,
111 CHECK_LENGTH
111 CHECK_LENGTH
112 );
112 );
113 SIGNAL state : state_DMAWriteBurst := IDLE;
113 SIGNAL state : state_DMAWriteBurst;-- := IDLE;
114
114
115 SIGNAL nbSend : INTEGER;
115 -- SIGNAL nbSend : INTEGER;
116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
116 SIGNAL matrix_type : STD_LOGIC_VECTOR(1 DOWNTO 0);
117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL component_type : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL component_type_pre : STD_LOGIC_VECTOR(3 DOWNTO 0);
119 SIGNAL header_check_ok : STD_LOGIC;
119 SIGNAL header_check_ok : STD_LOGIC;
120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL address_matrix : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL send_matrix : STD_LOGIC;
121 SIGNAL send_matrix : STD_LOGIC;
122 SIGNAL request : STD_LOGIC;
122 -- SIGNAL request : STD_LOGIC;
123 SIGNAL remaining_data_request : INTEGER;
123 -- SIGNAL remaining_data_request : INTEGER;
124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
124 SIGNAL Address : STD_LOGIC_VECTOR(31 DOWNTO 0);
125 -----------------------------------------------------------------------------
125 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
@@ -362,4 +362,4 BEGIN
362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
362 DMAIn <= header_dmai WHEN header_select = '1' ELSE component_dmai;
363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
363 fifo_ren <= fifo_ren_trash WHEN header_select = '1' ELSE component_fifo_ren;
364
364
365 END Behavioral;
365 END Behavioral; No newline at end of file
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@@ -131,6 +131,7 PACKAGE lpp_dma_pkg IS
131 send : IN STD_LOGIC;
131 send : IN STD_LOGIC;
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 ren : OUT STD_LOGIC;
134 send_ok : OUT STD_LOGIC;
135 send_ok : OUT STD_LOGIC;
135 send_ko : OUT STD_LOGIC);
136 send_ko : OUT STD_LOGIC);
136 END COMPONENT;
137 END COMPONENT;
@@ -196,5 +197,23 PACKAGE lpp_dma_pkg IS
196 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
197 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
198 END COMPONENT;
199 END COMPONENT;
200
201 COMPONENT lpp_dma_singleOrBurst
202 GENERIC (
203 tech : INTEGER;
204 hindex : INTEGER);
205 PORT (
206 HCLK : IN STD_ULOGIC;
207 HRESETn : IN STD_ULOGIC;
208 run : IN STD_LOGIC;
209 AHB_Master_In : IN AHB_Mst_In_Type;
210 AHB_Master_Out : OUT AHB_Mst_Out_Type;
211 send : IN STD_LOGIC;
212 valid_burst : IN STD_LOGIC;
213 done : OUT STD_LOGIC;
214 ren : OUT STD_LOGIC;
215 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
217 END COMPONENT;
199
218
200 END;
219 END;
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@@ -167,8 +167,10 BEGIN -- beh
167
167
168 DMAIn.Data <= data;
168 DMAIn.Data <= data;
169
169
170 ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
170 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
171 '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
171 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
172 -- '1';
173 ren <= '0' WHEN state = SEND_DATA ELSE
172 '1';
174 '1';
173
175
174 END beh; No newline at end of file
176 END beh;
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@@ -49,6 +49,7 ENTITY lpp_dma_send_1word IS
49 send : IN STD_LOGIC;
49 send : IN STD_LOGIC;
50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
50 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 ren : OUT STD_LOGIC;
52 --
53 --
53 send_ok : OUT STD_LOGIC;
54 send_ok : OUT STD_LOGIC;
54 send_ko : OUT STD_LOGIC
55 send_ko : OUT STD_LOGIC
@@ -78,7 +79,9 BEGIN -- beh
78 send_ok <= '0';
79 send_ok <= '0';
79 send_ko <= '0';
80 send_ko <= '0';
80 DMAIn.Lock <= '0';
81 DMAIn.Lock <= '0';
82 ren <= '1';
81 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
83 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
84 ren <= '1';
82 CASE state IS
85 CASE state IS
83 WHEN IDLE =>
86 WHEN IDLE =>
84 DMAIn.Store <= '1';
87 DMAIn.Store <= '1';
@@ -96,6 +99,7 BEGIN -- beh
96 DMAIn.Request <= '0';
99 DMAIn.Request <= '0';
97 DMAIn.Store <= '0';
100 DMAIn.Store <= '0';
98 state <= SEND_DATA;
101 state <= SEND_DATA;
102 ren <= '0';
99 END IF;
103 END IF;
100 WHEN SEND_DATA =>
104 WHEN SEND_DATA =>
101 IF DMAOut.Fault = '1' THEN
105 IF DMAOut.Fault = '1' THEN
@@ -105,9 +109,9 BEGIN -- beh
105 ELSIF DMAOut.Ready = '1' THEN
109 ELSIF DMAOut.Ready = '1' THEN
106 DMAIn.Request <= '0';
110 DMAIn.Request <= '0';
107 DMAIn.Store <= '0';
111 DMAIn.Store <= '0';
108 send_ok <= '1';
112 send_ok <= '1';
109 send_ko <= '0';
113 send_ko <= '0';
110 state <= IDLE;
114 state <= IDLE;
111 END IF;
115 END IF;
112 WHEN ERROR0 =>
116 WHEN ERROR0 =>
113 state <= ERROR1;
117 state <= ERROR1;
Show file before | Show file after | Hide comments
@@ -1,8 +1,7
1 lpp_dma_pkg.vhd
1 fifo_latency_correction.vhd
2 fifo_latency_correction.vhd
2 lpp_dma_apbreg.vhd
3 lpp_dma.vhd
3 lpp_dma_fsm.vhd
4 lpp_dma_ip.vhd
4 lpp_dma_ip.vhd
5 lpp_dma_pkg.vhd
6 lpp_dma_send_16word.vhd
5 lpp_dma_send_16word.vhd
7 lpp_dma_send_1word.vhd
6 lpp_dma_send_1word.vhd
8 lpp_dma.vhd
7 lpp_dma_singleOrBurst.vhd
Show file before | Show file after | Hide comments
@@ -29,14 +29,12 generic(
29 port(
29 port(
30 clk : in std_logic;
30 clk : in std_logic;
31 reset : in std_logic;
31 reset : in std_logic;
32 Acq : in std_logic;
32 Ack : in std_logic;
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
33 Data : in std_logic_vector(Data_SZ-1 downto 0);
34 Write : in std_logic;
34 Write : in std_logic;
35 Valid : in std_logic;
35 Valid : in std_logic;
36 -- Full : in std_logic_vector(1 downto 0);
37 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
36 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
38 FifoWrite : out std_logic_vector(1 downto 0);
37 FifoWrite : out std_logic_vector(1 downto 0);
39 Pong : out std_logic;
40 Error : out std_logic
38 Error : out std_logic
41 );
39 );
42 end entity;
40 end entity;
@@ -47,15 +45,14 architecture ar_Dispatch of Dispatch is
47 type etat is (eX,e0,e1,e2);
45 type etat is (eX,e0,e1,e2);
48 signal ect : etat;
46 signal ect : etat;
49
47
50 signal Pong_int : std_logic;
48 signal Pong : std_logic;
51 --signal FifoCpt : integer range 0 to 1 := 0;
52
49
53 begin
50 begin
54
51
55 process (clk,reset)
52 process (clk,reset)
56 begin
53 begin
57 if(reset='0')then
54 if(reset='0')then
58 Pong_int <= '0';
55 Pong <= '0';
59 Error <= '0';
56 Error <= '0';
60 ect <= e0;
57 ect <= e0;
61
58
@@ -64,14 +61,13 begin
64 case ect is
61 case ect is
65
62
66 when e0 =>
63 when e0 =>
67 -- if(Full(FifoCpt) = '1')then
68 if(Valid = '1')then
64 if(Valid = '1')then
69 Pong_int <= not Pong_int;
65 Pong <= not Pong;
70 ect <= e1;
66 ect <= e1;
71 end if;
67 end if;
72
68
73 when e1 =>
69 when e1 =>
74 if(Acq = '0')then
70 if(Ack = '0')then
75 Error <= '1';
71 Error <= '1';
76 ect <= e1;
72 ect <= e1;
77 else
73 else
@@ -80,7 +76,7 begin
80 end if;
76 end if;
81
77
82 when others =>
78 when others =>
83 null;
79 null;
84
80
85 end case;
81 end case;
86
82
@@ -88,10 +84,6 begin
88 end process;
84 end process;
89
85
90 FifoData <= Data & Data;
86 FifoData <= Data & Data;
91 Pong <= Pong_int;
87 FifoWrite <= '1' & not Write when Pong='0' else not Write & '1';
92
93 --FifoCpt <= 0 when Pong_int='0' else 1;
94
95 FifoWrite <= '1' & not Write when Pong_int='0' else not Write & '1';
96
88
97 end architecture; No newline at end of file
89 end architecture;
Show file before | Show file after | Hide comments
@@ -35,13 +35,11 entity MatriceSpectrale is
35
35
36 FifoIN_Full : in std_logic_vector(4 downto 0);
36 FifoIN_Full : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
37 SetReUse : in std_logic_vector(4 downto 0);
38 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
39 Valid : in std_logic;
38 Valid : in std_logic;
40 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
39 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
41 ACQ : in std_logic;
40 ACK : in std_logic;
42 SM_Write : out std_logic;
41 SM_Write : out std_logic;
43 FlagError : out std_logic;
42 FlagError : out std_logic;
44 Pong : out std_logic;
45 Statu : out std_logic_vector(3 downto 0);
43 Statu : out std_logic_vector(3 downto 0);
46 Write : out std_logic_vector(1 downto 0);
44 Write : out std_logic_vector(1 downto 0);
47 Read : out std_logic_vector(4 downto 0);
45 Read : out std_logic_vector(4 downto 0);
@@ -78,7 +76,7 begin
78
76
79 DISP : Dispatch
77 DISP : Dispatch
80 generic map(Result_SZ)
78 generic map(Result_SZ)
81 port map(clkm,rstn,ACQ,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,Pong,FlagError);
79 port map(clkm,rstn,ACK,Matrix_Result,Matrix_Write,Valid,Data_OUT,Write,FlagError);
82
80
83 Statu <= TopSM_Statu;
81 Statu <= TopSM_Statu;
84 SM_Write <= Matrix_Write;
82 SM_Write <= Matrix_Write;
Show file before | Show file after | Hide comments
@@ -66,13 +66,11 component MatriceSpectrale is
66
66
67 FifoIN_Full : in std_logic_vector(4 downto 0);
67 FifoIN_Full : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
68 SetReUse : in std_logic_vector(4 downto 0);
69 -- FifoOUT_Full : in std_logic_vector(1 downto 0);
70 Valid : in std_logic;
69 Valid : in std_logic;
71 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
70 Data_IN : in std_logic_vector((5*Input_SZ)-1 downto 0);
72 ACQ : in std_logic;
71 ACK : in std_logic;
73 SM_Write : out std_logic;
72 SM_Write : out std_logic;
74 FlagError : out std_logic;
73 FlagError : out std_logic;
75 Pong : out std_logic;
76 Statu : out std_logic_vector(3 downto 0);
74 Statu : out std_logic_vector(3 downto 0);
77 Write : out std_logic_vector(1 downto 0);
75 Write : out std_logic_vector(1 downto 0);
78 Read : out std_logic_vector(4 downto 0);
76 Read : out std_logic_vector(4 downto 0);
@@ -199,14 +197,12 generic(
199 port(
197 port(
200 clk : in std_logic;
198 clk : in std_logic;
201 reset : in std_logic;
199 reset : in std_logic;
202 Acq : in std_logic;
200 Ack : in std_logic;
203 Data : in std_logic_vector(Data_SZ-1 downto 0);
201 Data : in std_logic_vector(Data_SZ-1 downto 0);
204 Write : in std_logic;
202 Write : in std_logic;
205 Valid : in std_logic;
203 Valid : in std_logic;
206 -- Full : in std_logic_vector(1 downto 0);
207 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
204 FifoData : out std_logic_vector(2*Data_SZ-1 downto 0);
208 FifoWrite : out std_logic_vector(1 downto 0);
205 FifoWrite : out std_logic_vector(1 downto 0);
209 Pong : out std_logic;
210 Error : out std_logic
206 Error : out std_logic
211 );
207 );
212 end component;
208 end component;
Show file before | Show file after | Hide comments
@@ -1,17 +1,14
1 ALU_Driver.vhd
1 ALU_Driver.vhd
2 ALU_Driver.vhd.bak
3 APB_Matrix.vhd
2 APB_Matrix.vhd
3 ReUse_CTRLR.vhd
4 Dispatch.vhd
4 Dispatch.vhd
5 DriveInputs.vhd
5 DriveInputs.vhd
6 GetResult.vhd
6 GetResult.vhd
7 lpp_matrix.vhd
8 MatriceSpectrale.vhd
7 MatriceSpectrale.vhd
9 MatriceSpectrale.vhd.bak
10 Matrix.vhd
8 Matrix.vhd
11 ReUse_CTRLR.vhd
12 SpectralMatrix.vhd
9 SpectralMatrix.vhd
13 SpectralMatrix.vhd.bak
14 Starter.vhd
10 Starter.vhd
15 TopMatrix_PDR.vhd
11 TopMatrix_PDR.vhd
12 TopSpecMatrix.vhd
16 Top_MatrixSpec.vhd
13 Top_MatrixSpec.vhd
17 TopSpecMatrix.vhd
14 lpp_matrix.vhd
Show file before | Show file after | Hide comments
@@ -104,7 +104,7 BEGIN
104 END IF;
104 END IF;
105 END PROCESS;
105 END PROCESS;
106
106
107 --nclk <= NOT clk;
107 --nclk <= NOT clk;
108 ssram_clk_pad : outpad GENERIC MAP (tech => tech)
108 ssram_clk_pad : outpad GENERIC MAP (tech => tech)
109 PORT MAP (SSRAM_CLK, NOT clk);
109 PORT MAP (SSRAM_CLK, NOT clk);
110
110
@@ -184,4 +184,4 BEGIN
184 ZZ_pad : outpad GENERIC MAP (tech => tech)
184 ZZ_pad : outpad GENERIC MAP (tech => tech)
185 PORT MAP (ZZ, '0');
185 PORT MAP (ZZ, '0');
186
186
187 END ARCHITECTURE;
187 END ARCHITECTURE; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,66 +1,65
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library IEEE;
22 library IEEE;
23 use IEEE.std_logic_1164.all;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
24 use IEEE.numeric_std.all;
25 library lpp;
25 library lpp;
26 use lpp.lpp_memory.all;
26 use lpp.lpp_memory.all;
27 use lpp.iir_filter.all;
27 use lpp.iir_filter.all;
28 library techmap;
28 library techmap;
29 use techmap.gencomp.all;
29 use techmap.gencomp.all;
30
30
31 entity lppFIFOxN is
31 entity lppFIFOxN is
32 generic(
32 generic(
33 tech : integer := 0;
33 tech : integer := 0;
34 Mem_use : integer := use_RAM;
34 Mem_use : integer := use_RAM;
35 Data_sz : integer range 1 to 32 := 8;
35 Data_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 1 to 32 := 8;
36 Addr_sz : integer range 2 to 12 := 8;
37 FifoCnt : integer := 1;
37 FifoCnt : integer := 1;
38 Enable_ReUse : std_logic := '0'
38 Enable_ReUse : std_logic := '0'
39 );
39 );
40 port(
40 port(
41 rst : in std_logic;
41 rstn : in std_logic;
42 wclk : in std_logic;
42 wclk : in std_logic;
43 rclk : in std_logic;
43 rclk : in std_logic;
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
44 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
45 wen : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
46 ren : in std_logic_vector(FifoCnt-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
47 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
48 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
49 full : out std_logic_vector(FifoCnt-1 downto 0);
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
50 empty : out std_logic_vector(FifoCnt-1 downto 0)
51 );
51 );
52 end entity;
52 end entity;
53
53
54
54
55 architecture ar_lppFIFOxN of lppFIFOxN is
55 architecture ar_lppFIFOxN of lppFIFOxN is
56
56
57 begin
57 begin
58
58
59 fifos: for i in 0 to FifoCnt-1 generate
59 fifos: for i in 0 to FifoCnt-1 generate
60 FIFO0 : lpp_fifo
60 FIFO0 : lpp_fifo
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
61 generic map (tech,Mem_use,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
62 port map(rstn,ReUse(i),rclk,ren(i),rdata((i+1)*Data_sz-1 downto i*Data_sz),empty(i),open,wclk,wen(i),wdata((i+1)*Data_sz-1 downto i*Data_sz),full(i),open);
63 end generate;
63 end generate;
64
64
65 end architecture;
65 end architecture;
66
Show file before | Show file after | Hide comments
@@ -34,7 +34,7 generic(
34 Mem_use : integer := use_RAM;
34 Mem_use : integer := use_RAM;
35 Enable_ReUse : std_logic := '0';
35 Enable_ReUse : std_logic := '0';
36 DataSz : integer range 1 to 32 := 8;
36 DataSz : integer range 1 to 32 := 8;
37 abits : integer range 2 to 12 := 8
37 AddrSz : integer range 2 to 12 := 8
38 );
38 );
39 port(
39 port(
40 rstn : in std_logic;
40 rstn : in std_logic;
@@ -43,12 +43,12 port(
43 ren : in std_logic;
43 ren : in std_logic;
44 rdata : out std_logic_vector(DataSz-1 downto 0);
44 rdata : out std_logic_vector(DataSz-1 downto 0);
45 empty : out std_logic;
45 empty : out std_logic;
46 raddr : out std_logic_vector(abits-1 downto 0);
46 raddr : out std_logic_vector(AddrSz-1 downto 0);
47 wclk : in std_logic;
47 wclk : in std_logic;
48 wen : in std_logic;
48 wen : in std_logic;
49 wdata : in std_logic_vector(DataSz-1 downto 0);
49 wdata : in std_logic_vector(DataSz-1 downto 0);
50 full : out std_logic;
50 full : out std_logic;
51 waddr : out std_logic_vector(abits-1 downto 0)
51 waddr : out std_logic_vector(AddrSz-1 downto 0)
52 );
52 );
53 end entity;
53 end entity;
54
54
@@ -65,10 +65,10 signal sWEN : std_logic;
65 signal sRE : std_logic;
65 signal sRE : std_logic;
66 signal sWE : std_logic;
66 signal sWE : std_logic;
67
67
68 signal Waddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
68 signal Waddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
69 signal Raddr_vect : std_logic_vector(abits-1 downto 0):=(others =>'0');
69 signal Raddr_vect : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
70 signal Waddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
70 signal Waddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
71 signal Raddr_vect_s : std_logic_vector(abits-1 downto 0):=(others =>'0');
71 signal Raddr_vect_s : std_logic_vector(AddrSz-1 downto 0):=(others =>'0');
72
72
73 begin
73 begin
74
74
@@ -78,13 +78,13 begin
78 --==================================================================================
78 --==================================================================================
79 memRAM : IF Mem_use = use_RAM GENERATE
79 memRAM : IF Mem_use = use_RAM GENERATE
80 SRAM : syncram_2p
80 SRAM : syncram_2p
81 generic map(tech,abits,DataSz)
81 generic map(tech,AddrSz,DataSz)
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
82 port map(RCLK,sRE,Raddr_vect,rdata,WCLK,sWE,Waddr_vect,wdata);
83 END GENERATE;
83 END GENERATE;
84 --==================================================================================
84 --==================================================================================
85 memCEL : IF Mem_use = use_CEL GENERATE
85 memCEL : IF Mem_use = use_CEL GENERATE
86 CRAM : RAM_CEL
86 CRAM : RAM_CEL
87 generic map(DataSz,abits)
87 generic map(DataSz,AddrSz)
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
88 port map(wdata, rdata, sWEN, sREN, Waddr_vect, Raddr_vect, WCLK, rstn);
89 END GENERATE;
89 END GENERATE;
90 --==================================================================================
90 --==================================================================================
@@ -177,4 +177,3 end architecture;
177
177
178
178
179
179
180
Show file before | Show file after | Hide comments
@@ -1,186 +1,186
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.iir_filter.all;
29 use lpp.iir_filter.all;
30 library gaisler;
30 library gaisler;
31 use gaisler.misc.all;
31 use gaisler.misc.all;
32 use gaisler.memctrl.all;
32 use gaisler.memctrl.all;
33 library techmap;
33 library techmap;
34 use techmap.gencomp.all;
34 use techmap.gencomp.all;
35
35
36 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
36 --! Package contenant tous les programmes qui forment le composant int�gr� dans le l�on
37
37
38 package lpp_memory is
38 package lpp_memory is
39
39
40 component APB_FIFO is
40 component APB_FIFO is
41 generic (
41 generic (
42 tech : integer := apa3;
42 tech : integer := apa3;
43 pindex : integer := 0;
43 pindex : integer := 0;
44 paddr : integer := 0;
44 paddr : integer := 0;
45 pmask : integer := 16#fff#;
45 pmask : integer := 16#fff#;
46 pirq : integer := 0;
46 pirq : integer := 0;
47 abits : integer := 8;
47 abits : integer := 8;
48 FifoCnt : integer := 2;
48 FifoCnt : integer := 2;
49 Data_sz : integer := 16;
49 Data_sz : integer := 16;
50 Addr_sz : integer := 9;
50 Addr_sz : integer := 9;
51 Enable_ReUse : std_logic := '0';
51 Enable_ReUse : std_logic := '0';
52 Mem_use : integer := use_RAM;
52 Mem_use : integer := use_RAM;
53 R : integer := 1;
53 R : integer := 1;
54 W : integer := 1
54 W : integer := 1
55 );
55 );
56 port (
56 port (
57 clk : in std_logic; --! Horloge du composant
57 clk : in std_logic; --! Horloge du composant
58 rst : in std_logic; --! Reset general du composant
58 rst : in std_logic; --! Reset general du composant
59 rclk : in std_logic;
59 rclk : in std_logic;
60 wclk : in std_logic;
60 wclk : in std_logic;
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
61 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
62 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en m�moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
63 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'�criture en m�moire
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
64 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire vide
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
65 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, M�moire pleine
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
66 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en entr�e
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
67 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donn�es en sortie
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
68 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (�criture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
69 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
70 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
70 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
71 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
72 );
72 );
73 end component;
73 end component;
74
74
75 component FIFO_pipeline is
75 component FIFO_pipeline is
76 generic(
76 generic(
77 tech : integer := 0;
77 tech : integer := 0;
78 Mem_use : integer := use_RAM;
78 Mem_use : integer := use_RAM;
79 fifoCount : integer range 2 to 32 := 8;
79 fifoCount : integer range 2 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
80 DataSz : integer range 1 to 32 := 8;
81 abits : integer range 2 to 12 := 8
81 abits : integer range 2 to 12 := 8
82 );
82 );
83 port(
83 port(
84 rstn : in std_logic;
84 rstn : in std_logic;
85 ReUse : in std_logic;
85 ReUse : in std_logic;
86 rclk : in std_logic;
86 rclk : in std_logic;
87 ren : in std_logic;
87 ren : in std_logic;
88 rdata : out std_logic_vector(DataSz-1 downto 0);
88 rdata : out std_logic_vector(DataSz-1 downto 0);
89 empty : out std_logic;
89 empty : out std_logic;
90 raddr : out std_logic_vector(abits-1 downto 0);
90 raddr : out std_logic_vector(abits-1 downto 0);
91 wclk : in std_logic;
91 wclk : in std_logic;
92 wen : in std_logic;
92 wen : in std_logic;
93 wdata : in std_logic_vector(DataSz-1 downto 0);
93 wdata : in std_logic_vector(DataSz-1 downto 0);
94 full : out std_logic;
94 full : out std_logic;
95 waddr : out std_logic_vector(abits-1 downto 0)
95 waddr : out std_logic_vector(abits-1 downto 0)
96 );
96 );
97 end component;
97 end component;
98
98
99 component lpp_fifo is
99 component lpp_fifo is
100 generic(
100 generic(
101 tech : integer := 0;
101 tech : integer := 0;
102 Mem_use : integer := use_RAM;
102 Mem_use : integer := use_RAM;
103 Enable_ReUse : std_logic := '0';
103 Enable_ReUse : std_logic := '0';
104 DataSz : integer range 1 to 32 := 8;
104 DataSz : integer range 1 to 32 := 8;
105 abits : integer range 2 to 12 := 8
105 AddrSz : integer range 2 to 12 := 8
106 );
106 );
107 port(
107 port(
108 rstn : in std_logic;
108 rstn : in std_logic;
109 ReUse : in std_logic; --27/01/12
109 ReUse : in std_logic; --27/01/12
110 rclk : in std_logic;
110 rclk : in std_logic;
111 ren : in std_logic;
111 ren : in std_logic;
112 rdata : out std_logic_vector(DataSz-1 downto 0);
112 rdata : out std_logic_vector(DataSz-1 downto 0);
113 empty : out std_logic;
113 empty : out std_logic;
114 raddr : out std_logic_vector(abits-1 downto 0);
114 raddr : out std_logic_vector(AddrSz-1 downto 0);
115 wclk : in std_logic;
115 wclk : in std_logic;
116 wen : in std_logic;
116 wen : in std_logic;
117 wdata : in std_logic_vector(DataSz-1 downto 0);
117 wdata : in std_logic_vector(DataSz-1 downto 0);
118 full : out std_logic;
118 full : out std_logic;
119 waddr : out std_logic_vector(abits-1 downto 0)
119 waddr : out std_logic_vector(AddrSz-1 downto 0)
120 );
120 );
121 end component;
121 end component;
122
122
123
123
124 component lppFIFOxN is
124 component lppFIFOxN is
125 generic(
125 generic(
126 tech : integer := 0;
126 tech : integer := 0;
127 Mem_use : integer := use_RAM;
127 Mem_use : integer := use_RAM;
128 Data_sz : integer range 1 to 32 := 8;
128 Data_sz : integer range 1 to 32 := 8;
129 Addr_sz : integer range 1 to 32 := 8;
129 Addr_sz : integer range 1 to 32 := 8;
130 FifoCnt : integer := 1;
130 FifoCnt : integer := 1;
131 Enable_ReUse : std_logic := '0'
131 Enable_ReUse : std_logic := '0'
132 );
132 );
133 port(
133 port(
134 rst : in std_logic;
134 rstn : in std_logic;
135 wclk : in std_logic;
135 wclk : in std_logic;
136 rclk : in std_logic;
136 rclk : in std_logic;
137 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
137 ReUse : in std_logic_vector(FifoCnt-1 downto 0);
138 wen : in std_logic_vector(FifoCnt-1 downto 0);
138 wen : in std_logic_vector(FifoCnt-1 downto 0);
139 ren : in std_logic_vector(FifoCnt-1 downto 0);
139 ren : in std_logic_vector(FifoCnt-1 downto 0);
140 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
140 wdata : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
141 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
141 rdata : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0);
142 full : out std_logic_vector(FifoCnt-1 downto 0);
142 full : out std_logic_vector(FifoCnt-1 downto 0);
143 empty : out std_logic_vector(FifoCnt-1 downto 0)
143 empty : out std_logic_vector(FifoCnt-1 downto 0)
144 );
144 );
145 end component;
145 end component;
146
146
147 component FillFifo is
147 component FillFifo is
148 generic(
148 generic(
149 Data_sz : integer range 1 to 32 := 16;
149 Data_sz : integer range 1 to 32 := 16;
150 Fifo_cnt : integer range 1 to 8 := 5
150 Fifo_cnt : integer range 1 to 8 := 5
151 );
151 );
152 port(
152 port(
153 clk : in std_logic;
153 clk : in std_logic;
154 raz : in std_logic;
154 raz : in std_logic;
155 write : out std_logic_vector(Fifo_cnt-1 downto 0);
155 write : out std_logic_vector(Fifo_cnt-1 downto 0);
156 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
156 reuse : out std_logic_vector(Fifo_cnt-1 downto 0);
157 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
157 data : out std_logic_vector(Fifo_cnt*Data_sz-1 downto 0)
158 );
158 );
159 end component;
159 end component;
160
160
161 component ssram_plugin is
161 component ssram_plugin is
162 generic (tech : integer := 0);
162 generic (tech : integer := 0);
163 port
163 port
164 (
164 (
165 clk : in std_logic;
165 clk : in std_logic;
166 mem_ctrlr_o : in memory_out_type;
166 mem_ctrlr_o : in memory_out_type;
167 SSRAM_CLK : out std_logic;
167 SSRAM_CLK : out std_logic;
168 nBWa : out std_logic;
168 nBWa : out std_logic;
169 nBWb : out std_logic;
169 nBWb : out std_logic;
170 nBWc : out std_logic;
170 nBWc : out std_logic;
171 nBWd : out std_logic;
171 nBWd : out std_logic;
172 nBWE : out std_logic;
172 nBWE : out std_logic;
173 nADSC : out std_logic;
173 nADSC : out std_logic;
174 nADSP : out std_logic;
174 nADSP : out std_logic;
175 nADV : out std_logic;
175 nADV : out std_logic;
176 nGW : out std_logic;
176 nGW : out std_logic;
177 nCE1 : out std_logic;
177 nCE1 : out std_logic;
178 CE2 : out std_logic;
178 CE2 : out std_logic;
179 nCE3 : out std_logic;
179 nCE3 : out std_logic;
180 nOE : out std_logic;
180 nOE : out std_logic;
181 MODE : out std_logic;
181 MODE : out std_logic;
182 ZZ : out std_logic
182 ZZ : out std_logic
183 );
183 );
184 end component;
184 end component;
185
185
186 end;
186 end; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,11 +1,8
1 lpp_memory.vhd
2 lpp_FIFO.vhd
3 FillFifo.vhd
1 APB_FIFO.vhd
4 APB_FIFO.vhd
2 APB_FIFO.vhd.bak
5 Bridge.vhd
3 FIFO_pipeline.vhd
6 SSRAM_plugin.vhd
4 FillFifo.vhd
7 lppFIFOx5.vhd
5 lpp_FIFO.vhd
6 lppFIFOxN.vhd
8 lppFIFOxN.vhd
7 lppFIFOxN.vhd.bak
8 lpp_memory.vhd
9 lpp_memory.vhd.bak
10 SSRAM_plugin.vhd
11 SSRAM_plugin_vsim.vhd
Show file before | Show file after | Hide comments
This diff has been collapsed as it changes many lines, (596 lines changed) Show them Hide them
@@ -8,8 +8,10 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
13
15
14 LIBRARY techmap;
16 LIBRARY techmap;
15 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
@@ -23,11 +25,11 USE GRLIB.DMA2AHB_Package.ALL;
23 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
24 GENERIC (
26 GENERIC (
25 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
26 nb_burst_available_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
27 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
28 delta_snapshot_size : INTEGER := 16;
31 delta_vector_size : INTEGER := 20;
29 delta_f2_f0_size : INTEGER := 10;
32 delta_vector_size_f0_2 : INTEGER := 7;
30 delta_f2_f1_size : INTEGER := 10;
31
33
32 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
33 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
@@ -35,30 +37,39 ENTITY lpp_lfr IS
35 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
36 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
37
39
38 hindex_wfp : INTEGER := 2;
40 hindex : INTEGER := 2;
39 hindex_ms : INTEGER := 3
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
40
43
41 );
44 );
42 PORT (
45 PORT (
43 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
44 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
45 --
48 -- SAMPLE
46 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
47 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
48 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
49 --
52 -- APB
50 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
51 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
52 --
55 -- AHB
53 ahbi_wfp : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
54 ahbo_wfp : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
55 --
58 -- TIME
56 ahbi_ms : IN AHB_Mst_In_Type;
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
57 ahbo_ms : OUT AHB_Mst_Out_Type;
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
58 --
61 --
59 coarse_time_0 : IN STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
60 --
63
61 data_shaping_BW : OUT STD_LOGIC
64 --debug
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 debug_f0_data_valid : OUT STD_LOGIC;
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 debug_f1_data_valid : OUT STD_LOGIC;
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 debug_f2_data_valid : OUT STD_LOGIC;
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC
62 );
73 );
63 END lpp_lfr;
74 END lpp_lfr;
64
75
@@ -115,10 +126,14 ARCHITECTURE beh OF lpp_lfr IS
115 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
118 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
129 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 SIGNAL delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
130 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 SIGNAL delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
131 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
121 SIGNAL nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
132 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
133 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
134
135 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
136 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
122 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
137 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
123 SIGNAL enable_f0 : STD_LOGIC;
138 SIGNAL enable_f0 : STD_LOGIC;
124 SIGNAL enable_f1 : STD_LOGIC;
139 SIGNAL enable_f1 : STD_LOGIC;
@@ -132,17 +147,82 ARCHITECTURE beh OF lpp_lfr IS
132 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
133 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
134
149
135 --
150 SIGNAL run : STD_LOGIC;
136 SIGNAL time_info : STD_LOGIC_VECTOR( (4*16)-1 DOWNTO 0);
151 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
137 SIGNAL data_f0_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
152
138 SIGNAL data_f1_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
139 SIGNAL data_f2_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL data_f3_wfp : STD_LOGIC_VECTOR(159 DOWNTO 0) ;
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
157 SIGNAL data_f0_data_out_ren : STD_LOGIC;
158 --f1
159 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f1_data_out_valid : STD_LOGIC;
162 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f1_data_out_ren : STD_LOGIC;
164 --f2
165 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 SIGNAL data_f2_data_out_valid : STD_LOGIC;
168 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
169 SIGNAL data_f2_data_out_ren : STD_LOGIC;
170 --f3
171 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL data_f3_data_out_valid : STD_LOGIC;
174 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
175 SIGNAL data_f3_data_out_ren : STD_LOGIC;
141
176
142 SIGNAL val_f0_wfp : STD_LOGIC;
177 -----------------------------------------------------------------------------
143 SIGNAL val_f1_wfp : STD_LOGIC;
178 --
144 SIGNAL val_f2_wfp : STD_LOGIC;
179 -----------------------------------------------------------------------------
145 SIGNAL val_f3_wfp : STD_LOGIC;
180 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
182 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
183 --f1
184 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
186 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
187 --f2
188 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
190 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
191 --f3
192 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
194 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
195
196 -----------------------------------------------------------------------------
197 -- DMA RR
198 -----------------------------------------------------------------------------
199 SIGNAL dma_sel_valid : STD_LOGIC;
200 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
203
204 -----------------------------------------------------------------------------
205 -- DMA_REG
206 -----------------------------------------------------------------------------
207 SIGNAL ongoing_reg : STD_LOGIC;
208 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 SIGNAL dma_send_reg : STD_LOGIC;
210 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
211 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
213
214
215 -----------------------------------------------------------------------------
216 -- DMA
217 -----------------------------------------------------------------------------
218 SIGNAL dma_send : STD_LOGIC;
219 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
220 SIGNAL dma_done : STD_LOGIC;
221 SIGNAL dma_ren : STD_LOGIC;
222 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
146 BEGIN
226 BEGIN
147
227
148 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
228 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
@@ -175,24 +255,24 BEGIN
175 sample_f3_wdata => sample_f3_data);
255 sample_f3_wdata => sample_f3_data);
176
256
177 -----------------------------------------------------------------------------
257 -----------------------------------------------------------------------------
178 lpp_top_apbreg_1 : lpp_lfr_apbreg
258 lpp_lfr_apbreg_1: lpp_lfr_apbreg
179 GENERIC MAP (
259 GENERIC MAP (
180 nb_burst_available_size => nb_burst_available_size,
260 nb_data_by_buffer_size => nb_data_by_buffer_size,
181 nb_snapshot_param_size => nb_snapshot_param_size,
261 nb_word_by_buffer_size => nb_word_by_buffer_size,
182 delta_snapshot_size => delta_snapshot_size,
262 nb_snapshot_param_size => nb_snapshot_param_size,
183 delta_f2_f0_size => delta_f2_f0_size,
263 delta_vector_size => delta_vector_size,
184 delta_f2_f1_size => delta_f2_f1_size,
264 delta_vector_size_f0_2 => delta_vector_size_f0_2,
185 pindex => pindex,
265 pindex => pindex,
186 paddr => paddr,
266 paddr => paddr,
187 pmask => pmask,
267 pmask => pmask,
188 pirq_ms => pirq_ms,
268 pirq_ms => pirq_ms,
189 pirq_wfp => pirq_wfp)
269 pirq_wfp => pirq_wfp,
270 top_lfr_version => top_lfr_version)
190 PORT MAP (
271 PORT MAP (
191 HCLK => clk,
272 HCLK => clk,
192 HRESETn => rstn,
273 HRESETn => rstn,
193 apbi => apbi,
274 apbi => apbi,
194 apbo => apbo,
275 apbo => apbo,
195
196 ready_matrix_f0_0 => ready_matrix_f0_0,
276 ready_matrix_f0_0 => ready_matrix_f0_0,
197 ready_matrix_f0_1 => ready_matrix_f0_1,
277 ready_matrix_f0_1 => ready_matrix_f0_1,
198 ready_matrix_f1 => ready_matrix_f1,
278 ready_matrix_f1 => ready_matrix_f1,
@@ -212,54 +292,60 BEGIN
212 addr_matrix_f0_1 => addr_matrix_f0_1,
292 addr_matrix_f0_1 => addr_matrix_f0_1,
213 addr_matrix_f1 => addr_matrix_f1,
293 addr_matrix_f1 => addr_matrix_f1,
214 addr_matrix_f2 => addr_matrix_f2,
294 addr_matrix_f2 => addr_matrix_f2,
215
295 status_full => status_full,
216 status_full => status_full,
296 status_full_ack => status_full_ack,
217 status_full_ack => status_full_ack,
297 status_full_err => status_full_err,
218 status_full_err => status_full_err,
298 status_new_err => status_new_err,
219 status_new_err => status_new_err,
299 data_shaping_BW => data_shaping_BW,
220 data_shaping_BW => data_shaping_BW,
300 data_shaping_SP0 => data_shaping_SP0,
221 data_shaping_SP0 => data_shaping_SP0,
301 data_shaping_SP1 => data_shaping_SP1,
222 data_shaping_SP1 => data_shaping_SP1,
302 data_shaping_R0 => data_shaping_R0,
223 data_shaping_R0 => data_shaping_R0,
303 data_shaping_R1 => data_shaping_R1,
224 data_shaping_R1 => data_shaping_R1,
304 delta_snapshot => delta_snapshot,
225 delta_snapshot => delta_snapshot,
305 delta_f0 => delta_f0,
226 delta_f2_f1 => delta_f2_f1,
306 delta_f0_2 => delta_f0_2,
227 delta_f2_f0 => delta_f2_f0,
307 delta_f1 => delta_f1,
228 nb_burst_available => nb_burst_available,
308 delta_f2 => delta_f2,
229 nb_snapshot_param => nb_snapshot_param,
309 nb_data_by_buffer => nb_data_by_buffer,
230 enable_f0 => enable_f0,
310 nb_word_by_buffer => nb_word_by_buffer,
231 enable_f1 => enable_f1,
311 nb_snapshot_param => nb_snapshot_param,
232 enable_f2 => enable_f2,
312 enable_f0 => enable_f0,
233 enable_f3 => enable_f3,
313 enable_f1 => enable_f1,
234 burst_f0 => burst_f0,
314 enable_f2 => enable_f2,
235 burst_f1 => burst_f1,
315 enable_f3 => enable_f3,
236 burst_f2 => burst_f2,
316 burst_f0 => burst_f0,
237 addr_data_f0 => addr_data_f0,
317 burst_f1 => burst_f1,
238 addr_data_f1 => addr_data_f1,
318 burst_f2 => burst_f2,
239 addr_data_f2 => addr_data_f2,
319 run => run,
240 addr_data_f3 => addr_data_f3);
320 addr_data_f0 => addr_data_f0,
321 addr_data_f1 => addr_data_f1,
322 addr_data_f2 => addr_data_f2,
323 addr_data_f3 => addr_data_f3,
324 start_date => start_date);
241
325
242 -----------------------------------------------------------------------------
326 -----------------------------------------------------------------------------
243 lpp_waveform_1: lpp_waveform
327 lpp_waveform_1: lpp_waveform
244 GENERIC MAP (
328 GENERIC MAP (
245 hindex => hindex_wfp,
246 tech => inferred,
329 tech => inferred,
247 data_size => 160,
330 data_size => 6*16,
248 nb_burst_available_size => nb_burst_available_size,
331 nb_data_by_buffer_size => nb_data_by_buffer_size,
332 nb_word_by_buffer_size => nb_word_by_buffer_size,
249 nb_snapshot_param_size => nb_snapshot_param_size,
333 nb_snapshot_param_size => nb_snapshot_param_size,
250 delta_snapshot_size => delta_snapshot_size,
334 delta_vector_size => delta_vector_size,
251 delta_f2_f0_size => delta_f2_f0_size,
335 delta_vector_size_f0_2 => delta_vector_size_f0_2
252 delta_f2_f1_size => delta_f2_f1_size)
336 )
253 PORT MAP (
337 PORT MAP (
254 clk => clk,
338 clk => clk,
255 rstn => rstn,
339 rstn => rstn,
256 AHB_Master_In => ahbi_wfp,
340
257 AHB_Master_Out => ahbo_wfp,
341 reg_run => run,
258 coarse_time_0 => coarse_time_0,
342 reg_start_date => start_date,
343 reg_delta_snapshot => delta_snapshot,
344 reg_delta_f0 => delta_f0,
345 reg_delta_f0_2 => delta_f0_2,
346 reg_delta_f1 => delta_f1,
347 reg_delta_f2 => delta_f2,
259
348
260 delta_snapshot => delta_snapshot,
261 delta_f2_f1 => delta_f2_f1,
262 delta_f2_f0 => delta_f2_f0,
263 enable_f0 => enable_f0,
349 enable_f0 => enable_f0,
264 enable_f1 => enable_f1,
350 enable_f1 => enable_f1,
265 enable_f2 => enable_f2,
351 enable_f2 => enable_f2,
@@ -267,76 +353,306 BEGIN
267 burst_f0 => burst_f0,
353 burst_f0 => burst_f0,
268 burst_f1 => burst_f1,
354 burst_f1 => burst_f1,
269 burst_f2 => burst_f2,
355 burst_f2 => burst_f2,
270 nb_burst_available => nb_burst_available,
356
357 nb_data_by_buffer => nb_data_by_buffer,
358 nb_word_by_buffer => nb_word_by_buffer,
271 nb_snapshot_param => nb_snapshot_param,
359 nb_snapshot_param => nb_snapshot_param,
272 status_full => status_full,
360 status_full => status_full,
273 status_full_ack => status_full_ack,
361 status_full_ack => status_full_ack,
274 status_full_err => status_full_err,
362 status_full_err => status_full_err,
275 status_new_err => status_new_err,
363 status_new_err => status_new_err,
364
365 coarse_time => coarse_time,
366 fine_time => fine_time,
367
368 --f0
276 addr_data_f0 => addr_data_f0,
369 addr_data_f0 => addr_data_f0,
370 data_f0_in_valid => sample_f0_val,
371 data_f0_in => sample_f0_data,
372 --f1
277 addr_data_f1 => addr_data_f1,
373 addr_data_f1 => addr_data_f1,
374 data_f1_in_valid => sample_f1_val,
375 data_f1_in => sample_f1_data,
376 --f2
278 addr_data_f2 => addr_data_f2,
377 addr_data_f2 => addr_data_f2,
378 data_f2_in_valid => sample_f2_val,
379 data_f2_in => sample_f2_data,
380 --f3
279 addr_data_f3 => addr_data_f3,
381 addr_data_f3 => addr_data_f3,
382 data_f3_in_valid => sample_f3_val,
383 data_f3_in => sample_f3_data,
384 -- OUTPUT -- DMA interface
385 --f0
386 data_f0_addr_out => data_f0_addr_out_s,
387 data_f0_data_out => data_f0_data_out,
388 data_f0_data_out_valid => data_f0_data_out_valid_s,
389 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
390 data_f0_data_out_ren => data_f0_data_out_ren,
391 --f1
392 data_f1_addr_out => data_f1_addr_out_s,
393 data_f1_data_out => data_f1_data_out,
394 data_f1_data_out_valid => data_f1_data_out_valid_s,
395 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
396 data_f1_data_out_ren => data_f1_data_out_ren,
397 --f2
398 data_f2_addr_out => data_f2_addr_out_s,
399 data_f2_data_out => data_f2_data_out,
400 data_f2_data_out_valid => data_f2_data_out_valid_s,
401 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
402 data_f2_data_out_ren => data_f2_data_out_ren,
403 --f3
404 data_f3_addr_out => data_f3_addr_out_s,
405 data_f3_data_out => data_f3_data_out,
406 data_f3_data_out_valid => data_f3_data_out_valid_s,
407 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
408 data_f3_data_out_ren => data_f3_data_out_ren,
409
410 --debug
411 debug_f0_data => debug_f0_data,
412 debug_f0_data_valid => debug_f0_data_valid ,
413 debug_f1_data => debug_f1_data ,
414 debug_f1_data_valid => debug_f1_data_valid,
415 debug_f2_data => debug_f2_data ,
416 debug_f2_data_valid => debug_f2_data_valid ,
417 debug_f3_data => debug_f3_data ,
418 debug_f3_data_valid => debug_f3_data_valid
280
419
281 data_f0_in => data_f0_wfp,
420 );
282 data_f1_in => data_f1_wfp,
421
283 data_f2_in => data_f2_wfp,
422
284 data_f3_in => data_f3_wfp,
423 -----------------------------------------------------------------------------
285 data_f0_in_valid => sample_f0_val,
424 -- TEMP
286 data_f1_in_valid => sample_f1_val,
425 -----------------------------------------------------------------------------
287 data_f2_in_valid => sample_f2_val,
426
288 data_f3_in_valid => sample_f3_val);
427 PROCESS (clk, rstn)
428 BEGIN -- PROCESS
429 IF rstn = '0' THEN -- asynchronous reset (active low)
430 data_f0_data_out_valid <= '0';
431 data_f0_data_out_valid_burst <= '0';
432 data_f1_data_out_valid <= '0';
433 data_f1_data_out_valid_burst <= '0';
434 data_f2_data_out_valid <= '0';
435 data_f2_data_out_valid_burst <= '0';
436 data_f3_data_out_valid <= '0';
437 data_f3_data_out_valid_burst <= '0';
438 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
439 data_f0_data_out_valid <= data_f0_data_out_valid_s;
440 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
441 data_f1_data_out_valid <= data_f1_data_out_valid_s;
442 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
443 data_f2_data_out_valid <= data_f2_data_out_valid_s;
444 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
445 data_f3_data_out_valid <= data_f3_data_out_valid_s;
446 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
447 END IF;
448 END PROCESS;
289
449
290 data_f0_wfp <= sample_f0_data & time_info;
450 data_f0_addr_out <= data_f0_addr_out_s;
291 data_f1_wfp <= sample_f1_data & time_info;
451 data_f1_addr_out <= data_f1_addr_out_s;
292 data_f2_wfp <= sample_f2_data & time_info;
452 data_f2_addr_out <= data_f2_addr_out_s;
293 data_f3_wfp <= sample_f3_data & time_info;
453 data_f3_addr_out <= data_f3_addr_out_s;
454
455 -----------------------------------------------------------------------------
456 -- RoundRobin Selection For DMA
457 -----------------------------------------------------------------------------
458
459 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
460 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
461 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
462 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
463
464 RR_Arbiter_4_1: RR_Arbiter_4
465 PORT MAP (
466 clk => clk,
467 rstn => rstn,
468 in_valid => dma_rr_valid,
469 out_grant => dma_rr_grant);
470
294
471
295 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
296 sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
473 -- in : dma_rr_grant
297 NOT(sample_f0_val) & NOT(sample_f0_val) ;
474 -- send
298 sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
475 -- out : dma_sel
299 NOT(sample_f1_val) & NOT(sample_f1_val) ;
476 -- dma_valid_burst
300 sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
477 -- dma_sel_valid
301 NOT(sample_f3_val) & NOT(sample_f3_val) ;
478 -----------------------------------------------------------------------------
479 PROCESS (clk, rstn)
480 BEGIN -- PROCESS
481 IF rstn = '0' THEN -- asynchronous reset (active low)
482 dma_sel <= (OTHERS => '0');
483 dma_send <= '0';
484 dma_valid_burst <= '0';
485 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
486 -- IF dma_sel = "0000" OR dma_send = '1' THEN
487 IF dma_sel = "0000" OR dma_done = '1' THEN
488 dma_sel <= dma_rr_grant;
489 IF dma_rr_grant(0) = '1' THEN
490 dma_send <= '1';
491 dma_valid_burst <= data_f0_data_out_valid_burst;
492 dma_sel_valid <= data_f0_data_out_valid;
493 ELSIF dma_rr_grant(1) = '1' THEN
494 dma_send <= '1';
495 dma_valid_burst <= data_f1_data_out_valid_burst;
496 dma_sel_valid <= data_f1_data_out_valid;
497 ELSIF dma_rr_grant(2) = '1' THEN
498 dma_send <= '1';
499 dma_valid_burst <= data_f2_data_out_valid_burst;
500 dma_sel_valid <= data_f2_data_out_valid;
501 ELSIF dma_rr_grant(3) = '1' THEN
502 dma_send <= '1';
503 dma_valid_burst <= data_f3_data_out_valid_burst;
504 dma_sel_valid <= data_f3_data_out_valid;
505 END IF;
506 ELSE
507 dma_sel <= dma_sel;
508 dma_send <= '0';
509 END IF;
510 END IF;
511 END PROCESS;
512
513
514 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
515 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
516 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
517 data_f3_addr_out ;
518
519 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
520 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
521 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
522 data_f3_data_out ;
302
523
303 sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
524 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
304 sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
525 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
305 sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
526 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
527 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
528 -- '0';
529
530 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
531 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
532 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
533 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
534 -- '0';
535
536 -- TODO
537 --dma_send <= dma_sel_valid OR dma_valid_burst;
538
539 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
540 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
541 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
542 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
543
544 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
545 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
546 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
547 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
548
549
550 --PROCESS (clk, rstn)
551 --BEGIN -- PROCESS
552 -- IF rstn = '0' THEN -- asynchronous reset (active low)
553 -- ongoing_reg <= '0';
554 -- dma_sel_reg <= (OTHERS => '0');
555 -- dma_send_reg <= '0';
556 -- dma_valid_burst_reg <= '0';
557 -- dma_address_reg <= (OTHERS => '0');
558 -- dma_data_reg <= (OTHERS => '0');
559 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
560 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
561 -- ongoing_reg <= '1';
562 -- dma_valid_burst_reg <= dma_valid_burst;
563 -- dma_sel_reg <= dma_sel;
564 -- ELSE
565 -- IF dma_done = '1' THEN
566 -- ongoing_reg <= '0';
567 -- END IF;
568 -- END IF;
569 -- dma_send_reg <= dma_send;
570 -- dma_address_reg <= dma_address;
571 -- dma_data_reg <= dma_data;
572 -- END IF;
573 --END PROCESS;
574
575 dma_data_2 <= dma_data;
576 --PROCESS (clk, rstn)
577 --BEGIN -- PROCESS
578 -- IF rstn = '0' THEN -- asynchronous reset (active low)
579 -- dma_data_2 <= (OTHERS => '0');
580 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
581 -- dma_data_2 <= dma_data;
582
583 -- END IF;
584 --END PROCESS;
585
586
306 -----------------------------------------------------------------------------
587 -----------------------------------------------------------------------------
307 lpp_lfr_ms_1: lpp_lfr_ms
588 -- DMA
589 -----------------------------------------------------------------------------
590 lpp_dma_singleOrBurst_1: lpp_dma_singleOrBurst
308 GENERIC MAP (
591 GENERIC MAP (
309 hindex => hindex_ms)
592 tech => inferred,
593 hindex => hindex)
310 PORT MAP (
594 PORT MAP (
311 clk => clk,
595 HCLK => clk,
312 rstn => rstn,
596 HRESETn => rstn,
313 sample_f0_wen => sample_f0_wen,
597 run => run,
314 sample_f0_wdata => sample_f0_wdata,
598 AHB_Master_In => ahbi,
315 sample_f1_wen => sample_f1_wen,
599 AHB_Master_Out => ahbo,
316 sample_f1_wdata => sample_f1_wdata,
317 sample_f3_wen => sample_f3_wen,
318 sample_f3_wdata => sample_f3_wdata,
319 AHB_Master_In => ahbi_ms,
320 AHB_Master_Out => ahbo_ms,
321
600
322 ready_matrix_f0_0 => ready_matrix_f0_0,
601 send => dma_send,--_reg,
323 ready_matrix_f0_1 => ready_matrix_f0_1,
602 valid_burst => dma_valid_burst,--_reg,
324 ready_matrix_f1 => ready_matrix_f1,
603 done => dma_done,
325 ready_matrix_f2 => ready_matrix_f2,
604 ren => dma_ren,
326 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
605 address => dma_address,--_reg,
327 error_bad_component_error => error_bad_component_error,
606 data => dma_data_2);--_reg);
328 debug_reg => debug_reg,
607
329 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
608 -----------------------------------------------------------------------------
330 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
609 -- Matrix Spectral - TODO
331 status_ready_matrix_f1 => status_ready_matrix_f1,
610 -----------------------------------------------------------------------------
332 status_ready_matrix_f2 => status_ready_matrix_f2,
611 -----------------------------------------------------------------------------
333 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
612 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
334 status_error_bad_component_error => status_error_bad_component_error,
613 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
335 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
614 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
336 config_active_interruption_onError => config_active_interruption_onError,
615 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
337 addr_matrix_f0_0 => addr_matrix_f0_0,
616 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
338 addr_matrix_f0_1 => addr_matrix_f0_1,
617 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
339 addr_matrix_f1 => addr_matrix_f1,
340 addr_matrix_f2 => addr_matrix_f2);
341
618
342 END beh; No newline at end of file
619 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
620 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
621 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
622 -------------------------------------------------------------------------------
623 --lpp_lfr_ms_1: lpp_lfr_ms
624 -- GENERIC MAP (
625 -- hindex => hindex_ms)
626 -- PORT MAP (
627 -- clk => clk,
628 -- rstn => rstn,
629 -- sample_f0_wen => sample_f0_wen,
630 -- sample_f0_wdata => sample_f0_wdata,
631 -- sample_f1_wen => sample_f1_wen,
632 -- sample_f1_wdata => sample_f1_wdata,
633 -- sample_f3_wen => sample_f3_wen,
634 -- sample_f3_wdata => sample_f3_wdata,
635 -- AHB_Master_In => ahbi_ms,
636 -- AHB_Master_Out => ahbo_ms,
637
638 -- ready_matrix_f0_0 => ready_matrix_f0_0,
639 -- ready_matrix_f0_1 => ready_matrix_f0_1,
640 -- ready_matrix_f1 => ready_matrix_f1,
641 -- ready_matrix_f2 => ready_matrix_f2,
642 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
643 -- error_bad_component_error => error_bad_component_error,
644 -- debug_reg => debug_reg,
645 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
646 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
647 -- status_ready_matrix_f1 => status_ready_matrix_f1,
648 -- status_ready_matrix_f2 => status_ready_matrix_f2,
649 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
650 -- status_error_bad_component_error => status_error_bad_component_error,
651 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
652 -- config_active_interruption_onError => config_active_interruption_onError,
653 -- addr_matrix_f0_0 => addr_matrix_f0_0,
654 -- addr_matrix_f0_1 => addr_matrix_f0_1,
655 -- addr_matrix_f1 => addr_matrix_f1,
656 -- addr_matrix_f2 => addr_matrix_f2);
657
658 END beh;
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1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_burst_available_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_snapshot_param_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 delta_snapshot_size : INTEGER := 16;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_f2_f0_size : INTEGER := 10;
42 delta_vector_size : INTEGER := 20;
43 delta_f2_f1_size : INTEGER := 10;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1);
49 pirq_wfp : INTEGER := 1;
50 PORT (
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
51 -- AMBA AHB system signals
51 PORT (
52 HCLK : IN STD_ULOGIC;
52 -- AMBA AHB system signals
53 HRESETn : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54
54 HRESETn : IN STD_ULOGIC;
55 -- AMBA APB Slave Interface
55
56 apbi : IN apb_slv_in_type;
56 -- AMBA APB Slave Interface
57 apbo : OUT apb_slv_out_type;
57 apbi : IN apb_slv_in_type;
58
58 apbo : OUT apb_slv_out_type;
59 ---------------------------------------------------------------------------
59
60 -- Spectral Matrix Reg
60 ---------------------------------------------------------------------------
61 -- IN
61 -- Spectral Matrix Reg
62 ready_matrix_f0_0 : IN STD_LOGIC;
62 -- IN
63 ready_matrix_f0_1 : IN STD_LOGIC;
63 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f1 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f2 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
66 error_anticipating_empty_fifo : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
67 error_bad_component_error : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
68 error_bad_component_error : IN STD_LOGIC;
69
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70 -- OUT
70
71 status_ready_matrix_f0_0 : OUT STD_LOGIC;
71 -- OUT
72 status_ready_matrix_f0_1 : OUT STD_LOGIC;
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f2 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_bad_component_error : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77
77 status_error_bad_component_error : OUT STD_LOGIC;
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
78
79 config_active_interruption_onError : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 config_active_interruption_onError : OUT STD_LOGIC;
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 ---------------------------------------------------------------------------
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 -- WaveForm picker Reg
86 ---------------------------------------------------------------------------
87 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 -- WaveForm picker Reg
88 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92 -- OUT
92
93 data_shaping_BW : OUT STD_LOGIC;
93 -- OUT
94 data_shaping_SP0 : OUT STD_LOGIC;
94 data_shaping_BW : OUT STD_LOGIC;
95 data_shaping_SP1 : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
96 data_shaping_R0 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
97 data_shaping_R1 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
98
98 data_shaping_R1 : OUT STD_LOGIC;
99 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
99
100 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 enable_f0 : OUT STD_LOGIC;
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 enable_f1 : OUT STD_LOGIC;
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 enable_f2 : OUT STD_LOGIC;
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108 enable_f3 : OUT STD_LOGIC;
108
109
109 enable_f0 : OUT STD_LOGIC;
110 burst_f0 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
111 burst_f1 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
112 burst_f2 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
113
113
114 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 burst_f0 : OUT STD_LOGIC;
115 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 burst_f1 : OUT STD_LOGIC;
116 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 burst_f2 : OUT STD_LOGIC;
117 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
117
118
118 run : OUT STD_LOGIC;
119 ---------------------------------------------------------------------------
119
120 );
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 END lpp_lfr_apbreg;
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 ARCHITECTURE beh OF lpp_lfr_apbreg IS
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0)
125
125
126 CONSTANT REVISION : INTEGER := 1;
126 ---------------------------------------------------------------------------
127
127 );
128 CONSTANT pconfig : apb_config_type := (
128
129 0 => ahb_device_reg (VENDOR_LPP, LPP_DMA_TYPE, 2, REVISION, pirq_wfp),
129 END lpp_lfr_apbreg;
130 1 => apb_iobar(paddr, pmask));
130
131
131 ARCHITECTURE beh OF lpp_lfr_apbreg IS
132 TYPE lpp_SpectralMatrix_regs IS RECORD
132
133 config_active_interruption_onNewMatrix : STD_LOGIC;
133 CONSTANT REVISION : INTEGER := 1;
134 config_active_interruption_onError : STD_LOGIC;
134
135 status_ready_matrix_f0_0 : STD_LOGIC;
135 CONSTANT pconfig : apb_config_type := (
136 status_ready_matrix_f0_1 : STD_LOGIC;
136 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
137 status_ready_matrix_f1 : STD_LOGIC;
137 1 => apb_iobar(paddr, pmask));
138 status_ready_matrix_f2 : STD_LOGIC;
138
139 status_error_anticipating_empty_fifo : STD_LOGIC;
139 TYPE lpp_SpectralMatrix_regs IS RECORD
140 status_error_bad_component_error : STD_LOGIC;
140 config_active_interruption_onNewMatrix : STD_LOGIC;
141 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
141 config_active_interruption_onError : STD_LOGIC;
142 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
142 status_ready_matrix_f0_0 : STD_LOGIC;
143 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
143 status_ready_matrix_f0_1 : STD_LOGIC;
144 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
144 status_ready_matrix_f1 : STD_LOGIC;
145 END RECORD;
145 status_ready_matrix_f2 : STD_LOGIC;
146 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
146 status_error_anticipating_empty_fifo : STD_LOGIC;
147
147 status_error_bad_component_error : STD_LOGIC;
148 TYPE lpp_WaveformPicker_regs IS RECORD
148 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
149 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
150 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
151 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 data_shaping_BW : STD_LOGIC;
152 END RECORD;
153 data_shaping_SP0 : STD_LOGIC;
153 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
154 data_shaping_SP1 : STD_LOGIC;
154
155 data_shaping_R0 : STD_LOGIC;
155 TYPE lpp_WaveformPicker_regs IS RECORD
156 data_shaping_R1 : STD_LOGIC;
156 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 delta_snapshot : STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
157 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 delta_f2_f1 : STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
158 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
159 delta_f2_f0 : STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
159 data_shaping_BW : STD_LOGIC;
160 nb_burst_available : STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
160 data_shaping_SP0 : STD_LOGIC;
161 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
161 data_shaping_SP1 : STD_LOGIC;
162 enable_f0 : STD_LOGIC;
162 data_shaping_R0 : STD_LOGIC;
163 enable_f1 : STD_LOGIC;
163 data_shaping_R1 : STD_LOGIC;
164 enable_f2 : STD_LOGIC;
164 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 enable_f3 : STD_LOGIC;
165 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 burst_f0 : STD_LOGIC;
166 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
167 burst_f1 : STD_LOGIC;
167 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
168 burst_f2 : STD_LOGIC;
168 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
169 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
169 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
170 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
171 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
171 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
172 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 enable_f0 : STD_LOGIC;
173 END RECORD;
173 enable_f1 : STD_LOGIC;
174 SIGNAL reg_wp : lpp_WaveformPicker_regs;
174 enable_f2 : STD_LOGIC;
175
175 enable_f3 : STD_LOGIC;
176 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 burst_f0 : STD_LOGIC;
177
177 burst_f1 : STD_LOGIC;
178 BEGIN -- beh
178 burst_f2 : STD_LOGIC;
179
179 run : STD_LOGIC;
180 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
180 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
181 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
182 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
182 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
183 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
184 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
185 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
185 END RECORD;
186
186 SIGNAL reg_wp : lpp_WaveformPicker_regs;
187 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
187
188 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
188 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
189
190 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
190 -----------------------------------------------------------------------------
191 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
191 -- IRQ
192 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
192 -----------------------------------------------------------------------------
193
193 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
194
194 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
195 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
195 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
196 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
196 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
197 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
197 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
198 data_shaping_R0 <= reg_wp.data_shaping_R0;
198 SIGNAL ored_irq_wfp : STD_LOGIC;
199 data_shaping_R1 <= reg_wp.data_shaping_R1;
199
200
200 BEGIN -- beh
201 delta_snapshot <= reg_wp.delta_snapshot;
201
202 delta_f2_f1 <= reg_wp.delta_f2_f1;
202 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
203 delta_f2_f0 <= reg_wp.delta_f2_f0;
203 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
204 nb_burst_available <= reg_wp.nb_burst_available;
204 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
205 nb_snapshot_param <= reg_wp.nb_snapshot_param;
205 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
206
206 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
207 enable_f0 <= reg_wp.enable_f0;
207 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
208 enable_f1 <= reg_wp.enable_f1;
208
209 enable_f2 <= reg_wp.enable_f2;
209 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
210 enable_f3 <= reg_wp.enable_f3;
210 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
211
211 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
212 burst_f0 <= reg_wp.burst_f0;
212 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
213 burst_f1 <= reg_wp.burst_f1;
213 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
214 burst_f2 <= reg_wp.burst_f2;
214 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
215
215
216 addr_data_f0 <= reg_wp.addr_data_f0;
216
217 addr_data_f1 <= reg_wp.addr_data_f1;
217 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
218 addr_data_f2 <= reg_wp.addr_data_f2;
218 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
219 addr_data_f3 <= reg_wp.addr_data_f3;
219 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
220
220 data_shaping_R0 <= reg_wp.data_shaping_R0;
221 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
221 data_shaping_R1 <= reg_wp.data_shaping_R1;
222 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
222
223 BEGIN -- PROCESS lpp_dma_top
223 delta_snapshot <= reg_wp.delta_snapshot;
224 IF HRESETn = '0' THEN -- asynchronous reset (active low)
224 delta_f0 <= reg_wp.delta_f0;
225 reg_sp.config_active_interruption_onNewMatrix <= '0';
225 delta_f0_2 <= reg_wp.delta_f0_2;
226 reg_sp.config_active_interruption_onError <= '0';
226 delta_f1 <= reg_wp.delta_f1;
227 reg_sp.status_ready_matrix_f0_0 <= '0';
227 delta_f2 <= reg_wp.delta_f2;
228 reg_sp.status_ready_matrix_f0_1 <= '0';
228 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
229 reg_sp.status_ready_matrix_f1 <= '0';
229 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
230 reg_sp.status_ready_matrix_f2 <= '0';
230 nb_snapshot_param <= reg_wp.nb_snapshot_param;
231 reg_sp.status_error_anticipating_empty_fifo <= '0';
231
232 reg_sp.status_error_bad_component_error <= '0';
232 enable_f0 <= reg_wp.enable_f0;
233 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
233 enable_f1 <= reg_wp.enable_f1;
234 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
234 enable_f2 <= reg_wp.enable_f2;
235 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
235 enable_f3 <= reg_wp.enable_f3;
236 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
236
237 prdata <= (OTHERS => '0');
237 burst_f0 <= reg_wp.burst_f0;
238
238 burst_f1 <= reg_wp.burst_f1;
239 apbo.pirq <= (OTHERS => '0');
239 burst_f2 <= reg_wp.burst_f2;
240
240
241 status_full_ack <= (OTHERS => '0');
241 run <= reg_wp.run;
242
242
243 reg_wp.data_shaping_BW <= '0';
243 addr_data_f0 <= reg_wp.addr_data_f0;
244 reg_wp.data_shaping_SP0 <= '0';
244 addr_data_f1 <= reg_wp.addr_data_f1;
245 reg_wp.data_shaping_SP1 <= '0';
245 addr_data_f2 <= reg_wp.addr_data_f2;
246 reg_wp.data_shaping_R0 <= '0';
246 addr_data_f3 <= reg_wp.addr_data_f3;
247 reg_wp.data_shaping_R1 <= '0';
247
248 reg_wp.enable_f0 <= '0';
248 start_date <= reg_wp.start_date;
249 reg_wp.enable_f1 <= '0';
249
250 reg_wp.enable_f2 <= '0';
250 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
251 reg_wp.enable_f3 <= '0';
251 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
252 reg_wp.burst_f0 <= '0';
252 BEGIN -- PROCESS lpp_dma_top
253 reg_wp.burst_f1 <= '0';
253 IF HRESETn = '0' THEN -- asynchronous reset (active low)
254 reg_wp.burst_f2 <= '0';
254 reg_sp.config_active_interruption_onNewMatrix <= '0';
255 reg_wp.addr_data_f0 <= (OTHERS => '0');
255 reg_sp.config_active_interruption_onError <= '0';
256 reg_wp.addr_data_f1 <= (OTHERS => '0');
256 reg_sp.status_ready_matrix_f0_0 <= '0';
257 reg_wp.addr_data_f2 <= (OTHERS => '0');
257 reg_sp.status_ready_matrix_f0_1 <= '0';
258 reg_wp.addr_data_f3 <= (OTHERS => '0');
258 reg_sp.status_ready_matrix_f1 <= '0';
259 reg_wp.status_full <= (OTHERS => '0');
259 reg_sp.status_ready_matrix_f2 <= '0';
260 reg_wp.status_full_err <= (OTHERS => '0');
260 reg_sp.status_error_anticipating_empty_fifo <= '0';
261 reg_wp.status_new_err <= (OTHERS => '0');
261 reg_sp.status_error_bad_component_error <= '0';
262 reg_wp.delta_snapshot <= (OTHERS => '0');
262 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
263 reg_wp.delta_f2_f1 <= (OTHERS => '0');
263 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
264 reg_wp.delta_f2_f0 <= (OTHERS => '0');
264 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
265 reg_wp.nb_burst_available <= (OTHERS => '0');
265 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
266 reg_wp.nb_snapshot_param <= (OTHERS => '0');
266 prdata <= (OTHERS => '0');
267
267
268 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
268 apbo.pirq <= (OTHERS => '0');
269 status_full_ack <= (OTHERS => '0');
269
270
270 status_full_ack <= (OTHERS => '0');
271 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
271
272 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
272 reg_wp.data_shaping_BW <= '0';
273 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
273 reg_wp.data_shaping_SP0 <= '0';
274 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
274 reg_wp.data_shaping_SP1 <= '0';
275
275 reg_wp.data_shaping_R0 <= '0';
276 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
276 reg_wp.data_shaping_R1 <= '0';
277 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
277 reg_wp.enable_f0 <= '0';
278
278 reg_wp.enable_f1 <= '0';
279 reg_wp.status_full <= reg_wp.status_full OR status_full;
279 reg_wp.enable_f2 <= '0';
280 reg_wp.status_full_err <= reg_wp.status_full_err OR status_full_err;
280 reg_wp.enable_f3 <= '0';
281 reg_wp.status_new_err <= reg_wp.status_new_err OR status_new_err;
281 reg_wp.burst_f0 <= '0';
282
282 reg_wp.burst_f1 <= '0';
283 paddr := "000000";
283 reg_wp.burst_f2 <= '0';
284 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
284 reg_wp.run <= '0';
285 prdata <= (OTHERS => '0');
285 reg_wp.addr_data_f0 <= (OTHERS => '0');
286 IF apbi.psel(pindex) = '1' THEN
286 reg_wp.addr_data_f1 <= (OTHERS => '0');
287 -- APB DMA READ --
287 reg_wp.addr_data_f2 <= (OTHERS => '0');
288 CASE paddr(7 DOWNTO 2) IS
288 reg_wp.addr_data_f3 <= (OTHERS => '0');
289 --
289 reg_wp.status_full <= (OTHERS => '0');
290 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
290 reg_wp.status_full_err <= (OTHERS => '0');
291 prdata(1) <= reg_sp.config_active_interruption_onError;
291 reg_wp.status_new_err <= (OTHERS => '0');
292 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
292 reg_wp.delta_snapshot <= (OTHERS => '0');
293 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
293 reg_wp.delta_f0 <= (OTHERS => '0');
294 prdata(2) <= reg_sp.status_ready_matrix_f1;
294 reg_wp.delta_f0_2 <= (OTHERS => '0');
295 prdata(3) <= reg_sp.status_ready_matrix_f2;
295 reg_wp.delta_f1 <= (OTHERS => '0');
296 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
296 reg_wp.delta_f2 <= (OTHERS => '0');
297 prdata(5) <= reg_sp.status_error_bad_component_error;
297 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
298 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
298 reg_wp.nb_snapshot_param <= (OTHERS => '0');
299 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
299 reg_wp.start_date <= (OTHERS => '0');
300 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
300
301 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
301 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
302 WHEN "000110" => prdata <= debug_reg;
302 status_full_ack <= (OTHERS => '0');
303 --
303
304 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
304 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
305 prdata(1) <= reg_wp.data_shaping_SP0;
305 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
306 prdata(2) <= reg_wp.data_shaping_SP1;
306 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
307 prdata(3) <= reg_wp.data_shaping_R0;
307 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
308 prdata(4) <= reg_wp.data_shaping_R1;
308
309 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
309 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
310 prdata(1) <= reg_wp.enable_f1;
310 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
311 prdata(2) <= reg_wp.enable_f2;
311 all_status: FOR I IN 3 DOWNTO 0 LOOP
312 prdata(3) <= reg_wp.enable_f3;
312 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
313 prdata(4) <= reg_wp.burst_f0;
313 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
314 prdata(5) <= reg_wp.burst_f1;
314 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
315 prdata(6) <= reg_wp.burst_f2;
315 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
316 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
316 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
317 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
317 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
318 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
318 END LOOP all_status;
319 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
319
320 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
320 paddr := "000000";
321 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
321 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
322 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
322 prdata <= (OTHERS => '0');
323 WHEN "001111" => prdata(delta_snapshot_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
323 IF apbi.psel(pindex) = '1' THEN
324 WHEN "010000" => prdata(delta_f2_f1_size-1 DOWNTO 0) <= reg_wp.delta_f2_f1;
324 -- APB DMA READ --
325 WHEN "010001" => prdata(delta_f2_f0_size-1 DOWNTO 0) <= reg_wp.delta_f2_f0;
325 CASE paddr(7 DOWNTO 2) IS
326 WHEN "010010" => prdata(nb_burst_available_size-1 DOWNTO 0) <= reg_wp.nb_burst_available;
326 --
327 WHEN "010011" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
327 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
328 --
328 prdata(1) <= reg_sp.config_active_interruption_onError;
329 WHEN OTHERS => NULL;
329 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
330 END CASE;
330 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
331 IF (apbi.pwrite AND apbi.penable) = '1' THEN
331 prdata(2) <= reg_sp.status_ready_matrix_f1;
332 -- APB DMA WRITE --
332 prdata(3) <= reg_sp.status_ready_matrix_f2;
333 CASE paddr(7 DOWNTO 2) IS
333 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
334 --
334 prdata(5) <= reg_sp.status_error_bad_component_error;
335 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
335 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
336 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
336 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
337 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
337 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
338 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
338 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
339 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
339 WHEN "000110" => prdata <= debug_reg;
340 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
340 --
341 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
341 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
342 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
342 prdata(1) <= reg_wp.data_shaping_SP0;
343 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
343 prdata(2) <= reg_wp.data_shaping_SP1;
344 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
344 prdata(3) <= reg_wp.data_shaping_R0;
345 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
345 prdata(4) <= reg_wp.data_shaping_R1;
346 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
346 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
347 --
347 prdata(1) <= reg_wp.enable_f1;
348 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
348 prdata(2) <= reg_wp.enable_f2;
349 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
349 prdata(3) <= reg_wp.enable_f3;
350 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
350 prdata(4) <= reg_wp.burst_f0;
351 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
351 prdata(5) <= reg_wp.burst_f1;
352 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
352 prdata(6) <= reg_wp.burst_f2;
353 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
353 prdata(7) <= reg_wp.run;
354 reg_wp.enable_f1 <= apbi.pwdata(1);
354 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
355 reg_wp.enable_f2 <= apbi.pwdata(2);
355 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
356 reg_wp.enable_f3 <= apbi.pwdata(3);
356 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
357 reg_wp.burst_f0 <= apbi.pwdata(4);
357 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
358 reg_wp.burst_f1 <= apbi.pwdata(5);
358 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
359 reg_wp.burst_f2 <= apbi.pwdata(6);
359 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
360 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
360 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
361 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
361 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
362 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
362 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
363 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
363 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
364 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
364 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
365 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
365 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
366 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
366 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
367 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
367 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
368 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
368 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
369 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
369 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
370 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
370 ----------------------------------------------------
371 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_snapshot_size-1 DOWNTO 0);
371 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
372 WHEN "010000" => reg_wp.delta_f2_f1 <= apbi.pwdata(delta_f2_f1_size-1 DOWNTO 0);
372 WHEN OTHERS => NULL;
373 WHEN "010001" => reg_wp.delta_f2_f0 <= apbi.pwdata(delta_f2_f0_size-1 DOWNTO 0);
373 END CASE;
374 WHEN "010010" => reg_wp.nb_burst_available <= apbi.pwdata(nb_burst_available_size-1 DOWNTO 0);
374 IF (apbi.pwrite AND apbi.penable) = '1' THEN
375 WHEN "010011" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
375 -- APB DMA WRITE --
376 --
376 CASE paddr(7 DOWNTO 2) IS
377 WHEN OTHERS => NULL;
377 --
378 END CASE;
378 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
379 END IF;
379 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
380 END IF;
380 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
381
381 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
382 apbo.pirq(pirq_ms) <= (reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
382 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
383 ready_matrix_f0_1 OR
383 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
384 ready_matrix_f1 OR
384 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
385 ready_matrix_f2)
385 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
386 )
386 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
387 OR
387 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
388 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
388 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
389 error_bad_component_error)
389 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
390 );
390 --
391
391 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
392 apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
392 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
393 status_full(1) OR status_full_err(1) OR status_new_err(1) OR
393 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
394 status_full(2) OR status_full_err(2) OR status_new_err(2) OR
394 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
395 status_full(3) OR status_full_err(3) OR status_new_err(3)
395 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
396 );
396 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
397
397 reg_wp.enable_f1 <= apbi.pwdata(1);
398
398 reg_wp.enable_f2 <= apbi.pwdata(2);
399 END IF;
399 reg_wp.enable_f3 <= apbi.pwdata(3);
400 END PROCESS lpp_lfr_apbreg;
400 reg_wp.burst_f0 <= apbi.pwdata(4);
401
401 reg_wp.burst_f1 <= apbi.pwdata(5);
402 apbo.pindex <= pindex;
402 reg_wp.burst_f2 <= apbi.pwdata(6);
403 apbo.pconfig <= pconfig;
403 reg_wp.run <= apbi.pwdata(7);
404 apbo.prdata <= prdata;
404 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
405
405 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
406
406 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
407 END beh;
407 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
408 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
409 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
410 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
411 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
412 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
413 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
414 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
415 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
416 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
417 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
418 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
419 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
420 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
421 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
422 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
423 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
424 --
425 WHEN OTHERS => NULL;
426 END CASE;
427 END IF;
428 END IF;
429
430 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
431 ready_matrix_f0_1 OR
432 ready_matrix_f1 OR
433 ready_matrix_f2)
434 )
435 OR
436 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
437 error_bad_component_error)
438 ));
439
440 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
441 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
442 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
443 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
444 -- );
445 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
446
447 END IF;
448 END PROCESS lpp_lfr_apbreg;
449
450 apbo.pindex <= pindex;
451 apbo.pconfig <= pconfig;
452 apbo.prdata <= prdata;
453
454 -----------------------------------------------------------------------------
455 -- IRQ
456 -----------------------------------------------------------------------------
457 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
458
459 PROCESS (HCLK, HRESETn)
460 BEGIN -- PROCESS
461 IF HRESETn = '0' THEN -- asynchronous reset (active low)
462 irq_wfp_reg <= (OTHERS => '0');
463 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
464 irq_wfp_reg <= irq_wfp_reg_s;
465 END IF;
466 END PROCESS;
467
468 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
469 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
470 END GENERATE all_irq_wfp;
471
472 irq_wfp_ZERO <= (OTHERS => '0');
473 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
474
475 END beh;
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@@ -73,10 +73,10 ARCHITECTURE tb OF lpp_lfr_filter IS
73 CONSTANT CoefPerCel : INTEGER := 5;
73 CONSTANT CoefPerCel : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
74 CONSTANT Cels_count : INTEGER := 5;
75
75
76 SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
76 --SIGNAL coefs : STD_LOGIC_VECTOR((Coef_SZ*CoefCntPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
77 SIGNAL coefs_v2 : STD_LOGIC_VECTOR((Coef_SZ*CoefPerCel*Cels_count)-1 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
78 SIGNAL sample_filter_in : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
79 --SIGNAL sample_filter_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
80 --
80 --
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
81 SIGNAL sample_filter_v2_out_val : STD_LOGIC;
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
82 SIGNAL sample_filter_v2_out : samplT(ChanelCount-1 DOWNTO 0, 17 DOWNTO 0);
@@ -107,10 +107,10 ARCHITECTURE tb OF lpp_lfr_filter IS
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
107 SIGNAL sample_f3 : samplT(5 DOWNTO 0, 15 DOWNTO 0);
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
110 --SIGNAL data_f0_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
111 --SIGNAL data_f1_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
112 --SIGNAL data_f2_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
113 --SIGNAL data_f3_in_valid : STD_LOGIC_VECTOR(159 DOWNTO 0) := (OTHERS => '0');
114 -----------------------------------------------------------------------------
114 -----------------------------------------------------------------------------
115
115
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
116 SIGNAL sample_f0_wdata_s : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
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This diff has been collapsed as it changes many lines, (690 lines changed) Show them Hide them
@@ -1,346 +1,346
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY lpp;
4 LIBRARY lpp;
5 USE lpp.lpp_amba.ALL;
5 USE lpp.lpp_amba.ALL;
6 USE lpp.lpp_memory.ALL;
6 USE lpp.lpp_memory.ALL;
7 USE lpp.lpp_uart.ALL;
7 --USE lpp.lpp_uart.ALL;
8 USE lpp.lpp_matrix.ALL;
8 USE lpp.lpp_matrix.ALL;
9 USE lpp.lpp_delay.ALL;
9 --USE lpp.lpp_delay.ALL;
10 USE lpp.lpp_fft.ALL;
10 USE lpp.lpp_fft.ALL;
11 USE lpp.fft_components.ALL;
11 USE lpp.fft_components.ALL;
12 USE lpp.lpp_ad_conv.ALL;
12 USE lpp.lpp_ad_conv.ALL;
13 USE lpp.iir_filter.ALL;
13 USE lpp.iir_filter.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15 USE lpp.Filtercfg.ALL;
15 USE lpp.Filtercfg.ALL;
16 USE lpp.lpp_demux.ALL;
16 USE lpp.lpp_demux.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
17 USE lpp.lpp_top_lfr_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
18 USE lpp.lpp_dma_pkg.ALL;
19 USE lpp.lpp_Header.ALL;
19 USE lpp.lpp_Header.ALL;
20
20
21 LIBRARY grlib;
21 LIBRARY grlib;
22 USE grlib.amba.ALL;
22 USE grlib.amba.ALL;
23 USE grlib.stdlib.ALL;
23 USE grlib.stdlib.ALL;
24 USE grlib.devices.ALL;
24 USE grlib.devices.ALL;
25 USE GRLIB.DMA2AHB_Package.ALL;
25 USE GRLIB.DMA2AHB_Package.ALL;
26
26
27
27
28 ENTITY lpp_lfr_ms IS
28 ENTITY lpp_lfr_ms IS
29 GENERIC (
29 GENERIC (
30 hindex : INTEGER := 2
30 hindex : INTEGER := 2
31 );
31 );
32 PORT (
32 PORT (
33 clk : IN STD_LOGIC;
33 clk : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
34 rstn : IN STD_LOGIC;
35
35
36 ---------------------------------------------------------------------------
36 ---------------------------------------------------------------------------
37 -- DATA INPUT
37 -- DATA INPUT
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 --
39 --
40 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
40 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
41 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
41 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
42 --
42 --
43 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
43 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
44 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
44 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
45 --
45 --
46 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
46 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
47 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
47 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
48
48
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 -- DMA
50 -- DMA
51 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
52
52
53 -- AMBA AHB Master Interface
53 -- AMBA AHB Master Interface
54 AHB_Master_In : IN AHB_Mst_In_Type;
54 AHB_Master_In : IN AHB_Mst_In_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
55 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56
56
57 -- Reg out
57 -- Reg out
58 ready_matrix_f0_0 : OUT STD_LOGIC;
58 ready_matrix_f0_0 : OUT STD_LOGIC;
59 ready_matrix_f0_1 : OUT STD_LOGIC;
59 ready_matrix_f0_1 : OUT STD_LOGIC;
60 ready_matrix_f1 : OUT STD_LOGIC;
60 ready_matrix_f1 : OUT STD_LOGIC;
61 ready_matrix_f2 : OUT STD_LOGIC;
61 ready_matrix_f2 : OUT STD_LOGIC;
62 error_anticipating_empty_fifo : OUT STD_LOGIC;
62 error_anticipating_empty_fifo : OUT STD_LOGIC;
63 error_bad_component_error : OUT STD_LOGIC;
63 error_bad_component_error : OUT STD_LOGIC;
64 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
64 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
65
65
66 -- Reg In
66 -- Reg In
67 status_ready_matrix_f0_0 :IN STD_LOGIC;
67 status_ready_matrix_f0_0 :IN STD_LOGIC;
68 status_ready_matrix_f0_1 :IN STD_LOGIC;
68 status_ready_matrix_f0_1 :IN STD_LOGIC;
69 status_ready_matrix_f1 :IN STD_LOGIC;
69 status_ready_matrix_f1 :IN STD_LOGIC;
70 status_ready_matrix_f2 :IN STD_LOGIC;
70 status_ready_matrix_f2 :IN STD_LOGIC;
71 status_error_anticipating_empty_fifo :IN STD_LOGIC;
71 status_error_anticipating_empty_fifo :IN STD_LOGIC;
72 status_error_bad_component_error :IN STD_LOGIC;
72 status_error_bad_component_error :IN STD_LOGIC;
73
73
74 config_active_interruption_onNewMatrix : IN STD_LOGIC;
74 config_active_interruption_onNewMatrix : IN STD_LOGIC;
75 config_active_interruption_onError : IN STD_LOGIC;
75 config_active_interruption_onError : IN STD_LOGIC;
76 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
76 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
77 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
79 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
79 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
80 );
80 );
81 END;
81 END;
82
82
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
83 ARCHITECTURE Behavioral OF lpp_lfr_ms IS
84 -----------------------------------------------------------------------------
84 -----------------------------------------------------------------------------
85 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
85 SIGNAL FifoF0_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL FifoF1_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL FifoF3_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
88 SIGNAL FifoF0_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
89 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
89 SIGNAL FifoF1_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
90 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
90 SIGNAL FifoF3_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
91
91
92 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
93 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
93 SIGNAL DMUX_Read : STD_LOGIC_VECTOR(14 DOWNTO 0);
94 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
94 SIGNAL DMUX_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
95 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
95 SIGNAL DMUX_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
96 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
96 SIGNAL DMUX_WorkFreq : STD_LOGIC_VECTOR(1 DOWNTO 0);
97
97
98 -----------------------------------------------------------------------------
98 -----------------------------------------------------------------------------
99 SIGNAL FFT_Load : STD_LOGIC;
99 SIGNAL FFT_Load : STD_LOGIC;
100 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
100 SIGNAL FFT_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
101 SIGNAL FFT_Write : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
102 SIGNAL FFT_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
103 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
103 SIGNAL FFT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
104
104
105 -----------------------------------------------------------------------------
105 -----------------------------------------------------------------------------
106 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
106 SIGNAL FifoINT_Full : STD_LOGIC_VECTOR(4 DOWNTO 0);
107 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
107 SIGNAL FifoINT_Data : STD_LOGIC_VECTOR(79 DOWNTO 0);
108
108
109 -----------------------------------------------------------------------------
109 -----------------------------------------------------------------------------
110 SIGNAL SM_FlagError : STD_LOGIC;
110 SIGNAL SM_FlagError : STD_LOGIC;
111 SIGNAL SM_Pong : STD_LOGIC;
111 SIGNAL SM_Pong : STD_LOGIC;
112 SIGNAL SM_Wen : STD_LOGIC;
112 SIGNAL SM_Wen : STD_LOGIC;
113 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
113 SIGNAL SM_Read : STD_LOGIC_VECTOR(4 DOWNTO 0);
114 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
114 SIGNAL SM_Write : STD_LOGIC_VECTOR(1 DOWNTO 0);
115 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
116 SIGNAL SM_Param : STD_LOGIC_VECTOR(3 DOWNTO 0);
117 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
117 SIGNAL SM_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
118
118
119 -----------------------------------------------------------------------------
119 -----------------------------------------------------------------------------
120 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
120 SIGNAL FifoOUT_Full : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
121 SIGNAL FifoOUT_Empty : STD_LOGIC_VECTOR(1 DOWNTO 0);
122 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
122 SIGNAL FifoOUT_Data : STD_LOGIC_VECTOR(63 DOWNTO 0);
123
123
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
125 SIGNAL Head_Read : STD_LOGIC_VECTOR(1 DOWNTO 0);
126 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
126 SIGNAL Head_Data : STD_LOGIC_VECTOR(31 DOWNTO 0);
127 SIGNAL Head_Empty : STD_LOGIC;
127 SIGNAL Head_Empty : STD_LOGIC;
128 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
128 SIGNAL Head_Header : STD_LOGIC_VECTOR(31 DOWNTO 0);
129 SIGNAL Head_Valid : STD_LOGIC;
129 SIGNAL Head_Valid : STD_LOGIC;
130 SIGNAL Head_Val : STD_LOGIC;
130 SIGNAL Head_Val : STD_LOGIC;
131
131
132 -----------------------------------------------------------------------------
132 -----------------------------------------------------------------------------
133 SIGNAL DMA_Read : STD_LOGIC;
133 SIGNAL DMA_Read : STD_LOGIC;
134 SIGNAL DMA_ack : STD_LOGIC;
134 SIGNAL DMA_ack : STD_LOGIC;
135
135
136 BEGIN
136 BEGIN
137
137
138 -----------------------------------------------------------------------------
138 -----------------------------------------------------------------------------
139 Memf0: lppFIFOxN
139 Memf0: lppFIFOxN
140 GENERIC MAP (
140 GENERIC MAP (
141 tech => 0, Mem_use => use_RAM, Data_sz => 16,
141 tech => 0, Mem_use => use_RAM, Data_sz => 16,
142 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
142 Addr_sz => 9, FifoCnt => 5, Enable_ReUse => '0')
143 PORT MAP (
143 PORT MAP (
144 rst => rstn, wclk => clk, rclk => clk,
144 rst => rstn, wclk => clk, rclk => clk,
145 ReUse => (OTHERS => '0'),
145 ReUse => (OTHERS => '0'),
146 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
146 wen => sample_f0_wen, ren => DMUX_Read(4 DOWNTO 0),
147 wdata => sample_f0_wdata, rdata => FifoF0_Data,
147 wdata => sample_f0_wdata, rdata => FifoF0_Data,
148 full => OPEN, empty => FifoF0_Empty);
148 full => OPEN, empty => FifoF0_Empty);
149
149
150 Memf1: lppFIFOxN
150 Memf1: lppFIFOxN
151 GENERIC MAP (
151 GENERIC MAP (
152 tech => 0, Mem_use => use_RAM, Data_sz => 16,
152 tech => 0, Mem_use => use_RAM, Data_sz => 16,
153 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
153 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
154 PORT MAP (
154 PORT MAP (
155 rst => rstn, wclk => clk, rclk => clk,
155 rst => rstn, wclk => clk, rclk => clk,
156 ReUse => (OTHERS => '0'),
156 ReUse => (OTHERS => '0'),
157 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
157 wen => sample_f1_wen, ren => DMUX_Read(9 DOWNTO 5),
158 wdata => sample_f1_wdata, rdata => FifoF1_Data,
158 wdata => sample_f1_wdata, rdata => FifoF1_Data,
159 full => OPEN, empty => FifoF1_Empty);
159 full => OPEN, empty => FifoF1_Empty);
160
160
161
161
162 Memf2: lppFIFOxN
162 Memf2: lppFIFOxN
163 GENERIC MAP (
163 GENERIC MAP (
164 tech => 0, Mem_use => use_RAM, Data_sz => 16,
164 tech => 0, Mem_use => use_RAM, Data_sz => 16,
165 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
165 Addr_sz => 8, FifoCnt => 5, Enable_ReUse => '0')
166 PORT MAP (
166 PORT MAP (
167 rst => rstn, wclk => clk, rclk => clk,
167 rst => rstn, wclk => clk, rclk => clk,
168 ReUse => (OTHERS => '0'),
168 ReUse => (OTHERS => '0'),
169 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
169 wen => sample_f3_wen, ren => DMUX_Read(14 DOWNTO 10),
170 wdata => sample_f3_wdata, rdata => FifoF3_Data,
170 wdata => sample_f3_wdata, rdata => FifoF3_Data,
171 full => OPEN, empty => FifoF3_Empty);
171 full => OPEN, empty => FifoF3_Empty);
172 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
173
173
174
174
175 -----------------------------------------------------------------------------
175 -----------------------------------------------------------------------------
176 DMUX0 : DEMUX
176 DMUX0 : DEMUX
177 GENERIC MAP (
177 GENERIC MAP (
178 Data_sz => 16)
178 Data_sz => 16)
179 PORT MAP (
179 PORT MAP (
180 clk => clk,
180 clk => clk,
181 rstn => rstn,
181 rstn => rstn,
182 Read => FFT_Read,
182 Read => FFT_Read,
183 Load => FFT_Load,
183 Load => FFT_Load,
184 EmptyF0 => FifoF0_Empty,
184 EmptyF0 => FifoF0_Empty,
185 EmptyF1 => FifoF1_Empty,
185 EmptyF1 => FifoF1_Empty,
186 EmptyF2 => FifoF3_Empty,
186 EmptyF2 => FifoF3_Empty,
187 DataF0 => FifoF0_Data,
187 DataF0 => FifoF0_Data,
188 DataF1 => FifoF1_Data,
188 DataF1 => FifoF1_Data,
189 DataF2 => FifoF3_Data,
189 DataF2 => FifoF3_Data,
190 WorkFreq => DMUX_WorkFreq,
190 WorkFreq => DMUX_WorkFreq,
191 Read_DEMUX => DMUX_Read,
191 Read_DEMUX => DMUX_Read,
192 Empty => DMUX_Empty,
192 Empty => DMUX_Empty,
193 Data => DMUX_Data);
193 Data => DMUX_Data);
194 -----------------------------------------------------------------------------
194 -----------------------------------------------------------------------------
195
195
196
196
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198 FFT0: FFT
198 FFT0: FFT
199 GENERIC MAP (
199 GENERIC MAP (
200 Data_sz => 16,
200 Data_sz => 16,
201 NbData => 256)
201 NbData => 256)
202 PORT MAP (
202 PORT MAP (
203 clkm => clk,
203 clkm => clk,
204 rstn => rstn,
204 rstn => rstn,
205 FifoIN_Empty => DMUX_Empty,
205 FifoIN_Empty => DMUX_Empty,
206 FifoIN_Data => DMUX_Data,
206 FifoIN_Data => DMUX_Data,
207 FifoOUT_Full => FifoINT_Full,
207 FifoOUT_Full => FifoINT_Full,
208 Load => FFT_Load,
208 Load => FFT_Load,
209 Read => FFT_Read,
209 Read => FFT_Read,
210 Write => FFT_Write,
210 Write => FFT_Write,
211 ReUse => FFT_ReUse,
211 ReUse => FFT_ReUse,
212 Data => FFT_Data);
212 Data => FFT_Data);
213 -----------------------------------------------------------------------------
213 -----------------------------------------------------------------------------
214
214
215
215
216 -----------------------------------------------------------------------------
216 -----------------------------------------------------------------------------
217 MemInt : lppFIFOxN
217 MemInt : lppFIFOxN
218 GENERIC MAP (
218 GENERIC MAP (
219 tech => 0,
219 tech => 0,
220 Mem_use => use_RAM,
220 Mem_use => use_RAM,
221 Data_sz => 16,
221 Data_sz => 16,
222 Addr_sz => 8,
222 Addr_sz => 8,
223 FifoCnt => 5,
223 FifoCnt => 5,
224 Enable_ReUse => '1')
224 Enable_ReUse => '1')
225 PORT MAP (
225 PORT MAP (
226 rst => rstn,
226 rst => rstn,
227 wclk => clk,
227 wclk => clk,
228 rclk => clk,
228 rclk => clk,
229 ReUse => SM_ReUse,
229 ReUse => SM_ReUse,
230 wen => FFT_Write,
230 wen => FFT_Write,
231 ren => SM_Read,
231 ren => SM_Read,
232 wdata => FFT_Data,
232 wdata => FFT_Data,
233 rdata => FifoINT_Data,
233 rdata => FifoINT_Data,
234 full => FifoINT_Full,
234 full => FifoINT_Full,
235 empty => OPEN);
235 empty => OPEN);
236 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
237
237
238 -----------------------------------------------------------------------------
238 -----------------------------------------------------------------------------
239 SM0 : MatriceSpectrale
239 SM0 : MatriceSpectrale
240 GENERIC MAP (
240 GENERIC MAP (
241 Input_SZ => 16,
241 Input_SZ => 16,
242 Result_SZ => 32)
242 Result_SZ => 32)
243 PORT MAP (
243 PORT MAP (
244 clkm => clk,
244 clkm => clk,
245 rstn => rstn,
245 rstn => rstn,
246 FifoIN_Full => FifoINT_Full,
246 FifoIN_Full => FifoINT_Full,
247 SetReUse => FFT_ReUse,
247 SetReUse => FFT_ReUse,
248 Valid => Head_Valid,
248 Valid => Head_Valid,
249 Data_IN => FifoINT_Data,
249 Data_IN => FifoINT_Data,
250 ACQ => DMA_ack,
250 ACQ => DMA_ack,
251 SM_Write => SM_Wen,
251 SM_Write => SM_Wen,
252 FlagError => SM_FlagError,
252 FlagError => SM_FlagError,
253 Pong => SM_Pong,
253 Pong => SM_Pong,
254 Statu => SM_Param,
254 Statu => SM_Param,
255 Write => SM_Write,
255 Write => SM_Write,
256 Read => SM_Read,
256 Read => SM_Read,
257 ReUse => SM_ReUse,
257 ReUse => SM_ReUse,
258 Data_OUT => SM_Data);
258 Data_OUT => SM_Data);
259 -----------------------------------------------------------------------------
259 -----------------------------------------------------------------------------
260
260
261 -----------------------------------------------------------------------------
261 -----------------------------------------------------------------------------
262 MemOut : lppFIFOxN
262 MemOut : lppFIFOxN
263 GENERIC MAP (
263 GENERIC MAP (
264 tech => 0,
264 tech => 0,
265 Mem_use => use_RAM,
265 Mem_use => use_RAM,
266 Data_sz => 32,
266 Data_sz => 32,
267 Addr_sz => 8,
267 Addr_sz => 8,
268 FifoCnt => 2,
268 FifoCnt => 2,
269 Enable_ReUse => '0')
269 Enable_ReUse => '0')
270 PORT MAP (
270 PORT MAP (
271 rst => rstn,
271 rst => rstn,
272 wclk => clk,
272 wclk => clk,
273 rclk => clk,
273 rclk => clk,
274 ReUse => (OTHERS => '0'),
274 ReUse => (OTHERS => '0'),
275 wen => SM_Write,
275 wen => SM_Write,
276 ren => Head_Read,
276 ren => Head_Read,
277 wdata => SM_Data,
277 wdata => SM_Data,
278 rdata => FifoOUT_Data,
278 rdata => FifoOUT_Data,
279 full => FifoOUT_Full,
279 full => FifoOUT_Full,
280 empty => FifoOUT_Empty);
280 empty => FifoOUT_Empty);
281 -----------------------------------------------------------------------------
281 -----------------------------------------------------------------------------
282
282
283 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
284 Head0 : HeaderBuilder
284 Head0 : HeaderBuilder
285 GENERIC MAP (
285 GENERIC MAP (
286 Data_sz => 32)
286 Data_sz => 32)
287 PORT MAP (
287 PORT MAP (
288 clkm => clk,
288 clkm => clk,
289 rstn => rstn,
289 rstn => rstn,
290 pong => SM_Pong,
290 pong => SM_Pong,
291 Statu => SM_Param,
291 Statu => SM_Param,
292 Matrix_Type => DMUX_WorkFreq,
292 Matrix_Type => DMUX_WorkFreq,
293 Matrix_Write => SM_Wen,
293 Matrix_Write => SM_Wen,
294 Valid => Head_Valid,
294 Valid => Head_Valid,
295 dataIN => FifoOUT_Data,
295 dataIN => FifoOUT_Data,
296 emptyIN => FifoOUT_Empty,
296 emptyIN => FifoOUT_Empty,
297 RenOUT => Head_Read,
297 RenOUT => Head_Read,
298 dataOUT => Head_Data,
298 dataOUT => Head_Data,
299 emptyOUT => Head_Empty,
299 emptyOUT => Head_Empty,
300 RenIN => DMA_Read,
300 RenIN => DMA_Read,
301 header => Head_Header,
301 header => Head_Header,
302 header_val => Head_Val,
302 header_val => Head_Val,
303 header_ack => DMA_ack );
303 header_ack => DMA_ack );
304 -----------------------------------------------------------------------------
304 -----------------------------------------------------------------------------
305
305
306 -----------------------------------------------------------------------------
306 -----------------------------------------------------------------------------
307 lpp_dma_ip_1: lpp_dma_ip
307 lpp_dma_ip_1: lpp_dma_ip
308 GENERIC MAP (
308 GENERIC MAP (
309 tech => 0,
309 tech => 0,
310 hindex => hindex)
310 hindex => hindex)
311 PORT MAP (
311 PORT MAP (
312 HCLK => clk,
312 HCLK => clk,
313 HRESETn => rstn,
313 HRESETn => rstn,
314 AHB_Master_In => AHB_Master_In,
314 AHB_Master_In => AHB_Master_In,
315 AHB_Master_Out => AHB_Master_Out,
315 AHB_Master_Out => AHB_Master_Out,
316
316
317 fifo_data => Head_Data,
317 fifo_data => Head_Data,
318 fifo_empty => Head_Empty,
318 fifo_empty => Head_Empty,
319 fifo_ren => DMA_Read,
319 fifo_ren => DMA_Read,
320
320
321 header => Head_Header,
321 header => Head_Header,
322 header_val => Head_Val,
322 header_val => Head_Val,
323 header_ack => DMA_ack,
323 header_ack => DMA_ack,
324
324
325 ready_matrix_f0_0 => ready_matrix_f0_0,
325 ready_matrix_f0_0 => ready_matrix_f0_0,
326 ready_matrix_f0_1 => ready_matrix_f0_1,
326 ready_matrix_f0_1 => ready_matrix_f0_1,
327 ready_matrix_f1 => ready_matrix_f1,
327 ready_matrix_f1 => ready_matrix_f1,
328 ready_matrix_f2 => ready_matrix_f2,
328 ready_matrix_f2 => ready_matrix_f2,
329 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
329 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
330 error_bad_component_error => error_bad_component_error,
330 error_bad_component_error => error_bad_component_error,
331 debug_reg => debug_reg,
331 debug_reg => debug_reg,
332 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
332 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
333 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
333 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
334 status_ready_matrix_f1 => status_ready_matrix_f1,
334 status_ready_matrix_f1 => status_ready_matrix_f1,
335 status_ready_matrix_f2 => status_ready_matrix_f2,
335 status_ready_matrix_f2 => status_ready_matrix_f2,
336 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
336 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
337 status_error_bad_component_error => status_error_bad_component_error,
337 status_error_bad_component_error => status_error_bad_component_error,
338 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
338 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
339 config_active_interruption_onError => config_active_interruption_onError,
339 config_active_interruption_onError => config_active_interruption_onError,
340 addr_matrix_f0_0 => addr_matrix_f0_0,
340 addr_matrix_f0_0 => addr_matrix_f0_0,
341 addr_matrix_f0_1 => addr_matrix_f0_1,
341 addr_matrix_f0_1 => addr_matrix_f0_1,
342 addr_matrix_f1 => addr_matrix_f1,
342 addr_matrix_f1 => addr_matrix_f1,
343 addr_matrix_f2 => addr_matrix_f2);
343 addr_matrix_f2 => addr_matrix_f2);
344 -----------------------------------------------------------------------------
344 -----------------------------------------------------------------------------
345
345
346 END Behavioral; No newline at end of file
346 END Behavioral;
Show file before | Show file after | Hide comments
@@ -32,7 +32,7 PACKAGE lpp_lfr_pkg IS
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
@@ -73,47 +73,58 PACKAGE lpp_lfr_pkg IS
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_burst_available_size : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
78 nb_snapshot_param_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
79 delta_snapshot_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
80 delta_f2_f0_size : INTEGER;
80 delta_vector_size : INTEGER;
81 delta_f2_f1_size : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
82 pindex : INTEGER;
82 pindex : INTEGER;
83 paddr : INTEGER;
83 paddr : INTEGER;
84 pmask : INTEGER;
84 pmask : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
86 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
87 hindex_wfp : INTEGER;
87 hindex : INTEGER;
88 hindex_ms : INTEGER);
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
89 );
89 PORT (
90 PORT (
90 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
91 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_val : IN STD_LOGIC;
95 sample_val : IN STD_LOGIC;
95 apbi : IN apb_slv_in_type;
96 apbi : IN apb_slv_in_type;
96 apbo : OUT apb_slv_out_type;
97 apbo : OUT apb_slv_out_type;
97 ahbi_wfp : IN AHB_Mst_In_Type;
98 ahbi : IN AHB_Mst_In_Type;
98 ahbo_wfp : OUT AHB_Mst_Out_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
99 ahbi_ms : IN AHB_Mst_In_Type;
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 ahbo_ms : OUT AHB_Mst_Out_Type;
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 coarse_time_0 : IN STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC);
103
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC );
103 END COMPONENT;
113 END COMPONENT;
104
114
105 COMPONENT lpp_lfr_apbreg
115 COMPONENT lpp_lfr_apbreg
106 GENERIC (
116 GENERIC (
107 nb_burst_available_size : INTEGER;
117 nb_data_by_buffer_size : INTEGER;
108 nb_snapshot_param_size : INTEGER;
118 nb_word_by_buffer_size : INTEGER;
109 delta_snapshot_size : INTEGER;
119 nb_snapshot_param_size : INTEGER;
110 delta_f2_f0_size : INTEGER;
120 delta_vector_size : INTEGER;
111 delta_f2_f1_size : INTEGER;
121 delta_vector_size_f0_2 : INTEGER;
112 pindex : INTEGER;
122 pindex : INTEGER;
113 paddr : INTEGER;
123 paddr : INTEGER;
114 pmask : INTEGER;
124 pmask : INTEGER;
115 pirq_ms : INTEGER;
125 pirq_ms : INTEGER;
116 pirq_wfp : INTEGER);
126 pirq_wfp : INTEGER;
127 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
117 PORT (
128 PORT (
118 HCLK : IN STD_ULOGIC;
129 HCLK : IN STD_ULOGIC;
119 HRESETn : IN STD_ULOGIC;
130 HRESETn : IN STD_ULOGIC;
@@ -147,10 +158,13 PACKAGE lpp_lfr_pkg IS
147 data_shaping_SP1 : OUT STD_LOGIC;
158 data_shaping_SP1 : OUT STD_LOGIC;
148 data_shaping_R0 : OUT STD_LOGIC;
159 data_shaping_R0 : OUT STD_LOGIC;
149 data_shaping_R1 : OUT STD_LOGIC;
160 data_shaping_R1 : OUT STD_LOGIC;
150 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
161 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
151 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
162 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
152 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
163 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
153 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
164 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
154 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
168 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
155 enable_f0 : OUT STD_LOGIC;
169 enable_f0 : OUT STD_LOGIC;
156 enable_f1 : OUT STD_LOGIC;
170 enable_f1 : OUT STD_LOGIC;
@@ -159,10 +173,40 PACKAGE lpp_lfr_pkg IS
159 burst_f0 : OUT STD_LOGIC;
173 burst_f0 : OUT STD_LOGIC;
160 burst_f1 : OUT STD_LOGIC;
174 burst_f1 : OUT STD_LOGIC;
161 burst_f2 : OUT STD_LOGIC;
175 burst_f2 : OUT STD_LOGIC;
176 run : OUT STD_LOGIC;
162 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
177 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
163 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
164 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0));
182 END COMPONENT;
183
184 COMPONENT lpp_top_ms
185 GENERIC (
186 Mem_use : INTEGER;
187 nb_burst_available_size : INTEGER;
188 nb_snapshot_param_size : INTEGER;
189 delta_snapshot_size : INTEGER;
190 delta_f2_f0_size : INTEGER;
191 delta_f2_f1_size : INTEGER;
192 pindex : INTEGER;
193 paddr : INTEGER;
194 pmask : INTEGER;
195 pirq_ms : INTEGER;
196 pirq_wfp : INTEGER;
197 hindex_wfp : INTEGER;
198 hindex_ms : INTEGER);
199 PORT (
200 clk : IN STD_LOGIC;
201 rstn : IN STD_LOGIC;
202 sample_B : IN Samples14v(2 DOWNTO 0);
203 sample_E : IN Samples14v(4 DOWNTO 0);
204 sample_val : IN STD_LOGIC;
205 apbi : IN apb_slv_in_type;
206 apbo : OUT apb_slv_out_type;
207 ahbi_ms : IN AHB_Mst_In_Type;
208 ahbo_ms : OUT AHB_Mst_Out_Type;
209 data_shaping_BW : OUT STD_LOGIC);
166 END COMPONENT;
210 END COMPONENT;
167
211
168 END lpp_lfr_pkg;
212 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -45,69 +45,7 PACKAGE lpp_top_lfr_pkg IS
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
45 sample_f3_wdata : OUT STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0)
46 );
46 );
47 END COMPONENT;
47 END COMPONENT;
48
48
49 COMPONENT lpp_top_apbreg
50 GENERIC (
51 nb_burst_available_size : INTEGER;
52 nb_snapshot_param_size : INTEGER;
53 delta_snapshot_size : INTEGER;
54 delta_f2_f0_size : INTEGER;
55 delta_f2_f1_size : INTEGER;
56 pindex : INTEGER;
57 paddr : INTEGER;
58 pmask : INTEGER;
59 pirq : INTEGER);
60 PORT (
61 HCLK : IN STD_ULOGIC;
62 HRESETn : IN STD_ULOGIC;
63 apbi : IN apb_slv_in_type;
64 apbo : OUT apb_slv_out_type;
65 ready_matrix_f0_0 : IN STD_LOGIC;
66 ready_matrix_f0_1 : IN STD_LOGIC;
67 ready_matrix_f1 : IN STD_LOGIC;
68 ready_matrix_f2 : IN STD_LOGIC;
69 error_anticipating_empty_fifo : IN STD_LOGIC;
70 error_bad_component_error : IN STD_LOGIC;
71 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onError : OUT STD_LOGIC;
80 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
85 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
86 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
87 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 data_shaping_BW : OUT STD_LOGIC;
89 data_shaping_SP0 : OUT STD_LOGIC;
90 data_shaping_SP1 : OUT STD_LOGIC;
91 data_shaping_R0 : OUT STD_LOGIC;
92 data_shaping_R1 : OUT STD_LOGIC;
93 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
94 delta_f2_f1 : OUT STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
95 delta_f2_f0 : OUT STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
96 nb_burst_available : OUT STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
97 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
98 enable_f0 : OUT STD_LOGIC;
99 enable_f1 : OUT STD_LOGIC;
100 enable_f2 : OUT STD_LOGIC;
101 enable_f3 : OUT STD_LOGIC;
102 burst_f0 : OUT STD_LOGIC;
103 burst_f1 : OUT STD_LOGIC;
104 burst_f2 : OUT STD_LOGIC;
105 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
106 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
107 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
109 END COMPONENT;
110
111 COMPONENT lpp_top_lfr_wf_picker
49 COMPONENT lpp_top_lfr_wf_picker
112 GENERIC (
50 GENERIC (
113 hindex : INTEGER;
51 hindex : INTEGER;
Show file before | Show file after | Hide comments
@@ -1,15 +1,6
1 lpp_lfr_apbreg.vhd
1 lpp_top_lfr_pkg.vhd
2 lpp_lfr_pkg.vhd
2 lpp_lfr_filter.vhd
3 lpp_lfr_filter.vhd
4 lpp_lfr_apbreg.vhd
3 lpp_lfr_ms.vhd
5 lpp_lfr_ms.vhd
4 lpp_lfr_pkg.vhd
5 lpp_lfr.vhd
6 lpp_lfr.vhd
6 lpp_top_acq.vhd
7 lpp_top_acq.vhd.bak
8 lpp_top_apbreg.vhd
9 lpp_top_lfr_pkg.vhd
10 lpp_top_lfr_pkg.vhd.bak
11 lpp_top_lfr.vhd
12 lpp_top_lfr_wf_picker_ip.vhd
13 lpp_top_lfr_wf_picker_ip_whitout_filter.vhd
14 lpp_top_lfr_wf_picker.vhd
15 top_wf_picker.vhd
Show file before | Show file after | Hide comments
@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
1 LIBRARY IEEE;
23 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
@@ -17,30 +39,31 USE techmap.gencomp.ALL;
17 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
18
40
19 GENERIC (
41 GENERIC (
20 hindex : INTEGER := 2;
42 tech : INTEGER := inferred;
21 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
22 data_size : INTEGER := 160;
44 nb_data_by_buffer_size : INTEGER := 11;
23 nb_burst_available_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
24 nb_snapshot_param_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
25 delta_snapshot_size : INTEGER := 16;
47 delta_vector_size : INTEGER := 20;
26 delta_f2_f0_size : INTEGER := 10;
48 delta_vector_size_f0_2 : INTEGER := 3);
27 delta_f2_f1_size : INTEGER := 10);
28
49
29 PORT (
50 PORT (
30 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
31 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
32
53
33 -- AMBA AHB Master Interface
54 ---- AMBA AHB Master Interface
34 AHB_Master_In : IN AHB_Mst_In_Type;
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
35 AHB_Master_Out : OUT AHB_Mst_Out_Type;
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
36
57
37 coarse_time_0 : IN STD_LOGIC;
38
39 --config
58 --config
40 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
59 reg_run : IN STD_LOGIC;
41 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
42 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
43
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
44 enable_f0 : IN STD_LOGIC;
67 enable_f0 : IN STD_LOGIC;
45 enable_f1 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
46 enable_f2 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
@@ -50,26 +73,71 ENTITY lpp_waveform IS
50 burst_f1 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
51 burst_f2 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
52
75
53 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
54 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
55 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
57 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
58 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
59 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
60 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
83 ---------------------------------------------------------------------------
61 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
84 -- INPUT
62 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
88 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
63
104
64 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
105 ---------------------------------------------------------------------------
65 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
106 -- OUTPUT
66 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 --f0
67 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
68
131
69 data_f0_in_valid : IN STD_LOGIC;
132 --debug
70 data_f1_in_valid : IN STD_LOGIC;
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_f2_in_valid : IN STD_LOGIC;
134 debug_f0_data_valid : OUT STD_LOGIC;
72 data_f3_in_valid : IN STD_LOGIC
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 debug_f1_data_valid : OUT STD_LOGIC;
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 debug_f2_data_valid : OUT STD_LOGIC;
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 debug_f3_data_valid : OUT STD_LOGIC
73 );
141 );
74
142
75 END lpp_waveform;
143 END lpp_waveform;
@@ -84,46 +152,65 ARCHITECTURE beh OF lpp_waveform IS
84 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
85 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
86
154
87 SIGNAL data_f0_out_valid : STD_LOGIC;
155 SIGNAL data_f0_out_valid : STD_LOGIC;
88 SIGNAL data_f1_out_valid : STD_LOGIC;
156 SIGNAL data_f1_out_valid : STD_LOGIC;
89 SIGNAL data_f2_out_valid : STD_LOGIC;
157 SIGNAL data_f2_out_valid : STD_LOGIC;
90 SIGNAL data_f3_out_valid : STD_LOGIC;
158 SIGNAL data_f3_out_valid : STD_LOGIC;
91 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
159 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
92
93 --
160 --
94 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
161 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
95 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
97 SIGNAL ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
98 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
99 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
100 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
101 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
168 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
102 --
174 --
103 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
104 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
105 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 --
180 SIGNAL run : STD_LOGIC;
181 --
182 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
186 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
187 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
106
188
107 BEGIN -- beh
189 BEGIN -- beh
108
190
109 lpp_waveform_snapshot_controler_1: lpp_waveform_snapshot_controler
191 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
110 GENERIC MAP (
192 GENERIC MAP (
111 delta_snapshot_size => delta_snapshot_size,
193 delta_vector_size => delta_vector_size,
112 delta_f2_f0_size => delta_f2_f0_size,
194 delta_vector_size_f0_2 => delta_vector_size_f0_2
113 delta_f2_f1_size => delta_f2_f1_size)
195 )
114 PORT MAP (
196 PORT MAP (
115 clk => clk,
197 clk => clk,
116 rstn => rstn,
198 rstn => rstn,
117 delta_snapshot => delta_snapshot,
199 reg_run => reg_run,
118 delta_f2_f1 => delta_f2_f1,
200 reg_start_date => reg_start_date,
119 delta_f2_f0 => delta_f2_f0,
201 reg_delta_snapshot => reg_delta_snapshot,
120 coarse_time_0 => coarse_time_0,
202 reg_delta_f0 => reg_delta_f0,
121 data_f0_in_valid => data_f0_in_valid,
203 reg_delta_f0_2 => reg_delta_f0_2,
122 data_f2_in_valid => data_f2_in_valid,
204 reg_delta_f1 => reg_delta_f1,
123 start_snapshot_f0 => start_snapshot_f0,
205 reg_delta_f2 => reg_delta_f2,
124 start_snapshot_f1 => start_snapshot_f1,
206 coarse_time => coarse_time(30 DOWNTO 0),
125 start_snapshot_f2 => start_snapshot_f2);
207 data_f0_valid => data_f0_in_valid,
126
208 data_f2_valid => data_f2_in_valid,
209 start_snapshot_f0 => start_snapshot_f0,
210 start_snapshot_f1 => start_snapshot_f1,
211 start_snapshot_f2 => start_snapshot_f2,
212 wfp_on => run);
213
127 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
214 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
128 GENERIC MAP (
215 GENERIC MAP (
129 data_size => data_size,
216 data_size => data_size,
@@ -131,6 +218,7 BEGIN -- beh
131 PORT MAP (
218 PORT MAP (
132 clk => clk,
219 clk => clk,
133 rstn => rstn,
220 rstn => rstn,
221 run => run,
134 enable => enable_f0,
222 enable => enable_f0,
135 burst_enable => burst_f0,
223 burst_enable => burst_f0,
136 nb_snapshot_param => nb_snapshot_param,
224 nb_snapshot_param => nb_snapshot_param,
@@ -139,9 +227,9 BEGIN -- beh
139 data_in_valid => data_f0_in_valid,
227 data_in_valid => data_f0_in_valid,
140 data_out => data_f0_out,
228 data_out => data_f0_out,
141 data_out_valid => data_f0_out_valid);
229 data_out_valid => data_f0_out_valid);
142
230
143 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
231 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
144
232
145 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
233 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
146 GENERIC MAP (
234 GENERIC MAP (
147 data_size => data_size,
235 data_size => data_size,
@@ -149,6 +237,7 BEGIN -- beh
149 PORT MAP (
237 PORT MAP (
150 clk => clk,
238 clk => clk,
151 rstn => rstn,
239 rstn => rstn,
240 run => run,
152 enable => enable_f1,
241 enable => enable_f1,
153 burst_enable => burst_f1,
242 burst_enable => burst_f1,
154 nb_snapshot_param => nb_snapshot_param_more_one,
243 nb_snapshot_param => nb_snapshot_param_more_one,
@@ -165,6 +254,7 BEGIN -- beh
165 PORT MAP (
254 PORT MAP (
166 clk => clk,
255 clk => clk,
167 rstn => rstn,
256 rstn => rstn,
257 run => run,
168 enable => enable_f2,
258 enable => enable_f2,
169 burst_enable => burst_f2,
259 burst_enable => burst_f2,
170 nb_snapshot_param => nb_snapshot_param_more_one,
260 nb_snapshot_param => nb_snapshot_param_more_one,
@@ -174,92 +264,194 BEGIN -- beh
174 data_out => data_f2_out,
264 data_out => data_f2_out,
175 data_out_valid => data_f2_out_valid);
265 data_out_valid => data_f2_out_valid);
176
266
177 lpp_waveform_burst_f3: lpp_waveform_burst
267 lpp_waveform_burst_f3 : lpp_waveform_burst
178 GENERIC MAP (
268 GENERIC MAP (
179 data_size => data_size)
269 data_size => data_size)
180 PORT MAP (
270 PORT MAP (
181 clk => clk,
271 clk => clk,
182 rstn => rstn,
272 rstn => rstn,
273 run => run,
183 enable => enable_f3,
274 enable => enable_f3,
184 data_in => data_f3_in,
275 data_in => data_f3_in,
185 data_in_valid => data_f3_in_valid,
276 data_in_valid => data_f3_in_valid,
186 data_out => data_f3_out,
277 data_out => data_f3_out,
187 data_out_valid => data_f3_out_valid);
278 data_out_valid => data_f3_out_valid);
188
279
280 -----------------------------------------------------------------------------
281 -- DEBUG
282 debug_f0_data_valid <= data_f0_out_valid;
283 debug_f0_data <= data_f0_out;
284 debug_f1_data_valid <= data_f1_out_valid;
285 debug_f1_data <= data_f1_out;
286 debug_f2_data_valid <= data_f2_out_valid;
287 debug_f2_data <= data_f2_out;
288 debug_f3_data_valid <= data_f3_out_valid;
289 debug_f3_data <= data_f3_out;
290 -----------------------------------------------------------------------------
189
291
190 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
292 PROCESS (clk, rstn)
293 BEGIN -- PROCESS
294 IF rstn = '0' THEN -- asynchronous reset (active low)
295 time_reg1 <= (OTHERS => '0');
296 time_reg2 <= (OTHERS => '0');
297 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
298 time_reg1 <= fine_time & coarse_time;
299 time_reg2 <= time_reg1;
300 END IF;
301 END PROCESS;
191
302
192 all_input_valid: FOR i IN 3 DOWNTO 0 GENERATE
303 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
193 lpp_waveform_dma_gen_valid_I: lpp_waveform_dma_gen_valid
304 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
305 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
194 PORT MAP (
306 PORT MAP (
195 HCLK => clk,
307 HCLK => clk,
196 HRESETn => rstn,
308 HRESETn => rstn,
309 run => run,
197 valid_in => valid_in(I),
310 valid_in => valid_in(I),
198 ack_in => valid_ack(I),
311 ack_in => valid_ack(I),
312 time_in => time_reg2, -- Todo
199 valid_out => valid_out(I),
313 valid_out => valid_out(I),
314 time_out => time_out(I), -- Todo
200 error => status_new_err(I));
315 error => status_new_err(I));
201 END GENERATE all_input_valid;
316 END GENERATE all_input_valid;
202
317
203 lpp_waveform_fifo_arbiter_1: lpp_waveform_fifo_arbiter
318 all_bit_of_data_out: FOR I IN 95 DOWNTO 0 GENERATE
204 GENERIC MAP (tech => tech)
319 data_out(0,I) <= data_f0_out(I);
320 data_out(1,I) <= data_f1_out(I);
321 data_out(2,I) <= data_f2_out(I);
322 data_out(3,I) <= data_f3_out(I);
323 END GENERATE all_bit_of_data_out;
324
325 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
326 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
327 time_out_2(J,I) <= time_out(J)(I);
328 END GENERATE all_sample_of_time_out;
329 END GENERATE all_bit_of_time_out;
330
331 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
332 GENERIC MAP (tech => tech,
333 nb_data_by_buffer_size =>nb_data_by_buffer_size)
205 PORT MAP (
334 PORT MAP (
206 clk => clk,
335 clk => clk,
207 rstn => rstn,
336 rstn => rstn,
208 data_f0_valid => valid_out(0),
337 run => run,
209 data_f1_valid => valid_out(1),
338 nb_data_by_buffer => nb_data_by_buffer,
210 data_f2_valid => valid_out(2),
339 data_in_valid => valid_out,
211 data_f3_valid => valid_out(3),
340 data_in_ack => valid_ack,
212
341 data_in => data_out,
213 data_valid_ack => valid_ack,
342 time_in => time_out_2,
214
215 data_f0 => data_f0_out,
216 data_f1 => data_f1_out,
217 data_f2 => data_f2_out,
218 data_f3 => data_f3_out,
219
220 ready => ready_arb,
221 time_wen => time_wen,
222 data_wen => data_wen,
223 data => wdata);
224
343
225 ready_arb <= NOT ready;
344 data_out => wdata,
226
345 data_out_wen => data_wen,
227 lpp_waveform_fifo_1: lpp_waveform_fifo
346 full_almost => full_almost,
347 full => full);
348
349 lpp_waveform_fifo_1 : lpp_waveform_fifo
228 GENERIC MAP (tech => tech)
350 GENERIC MAP (tech => tech)
229 PORT MAP (
351 PORT MAP (
230 clk => clk,
352 clk => clk,
231 rstn => rstn,
353 rstn => rstn,
232 ready => ready,
354 run => run,
233 time_ren => time_ren, -- todo
355
234 data_ren => data_ren, -- todo
356 empty => empty,
235 rdata => rdata, -- todo
357 empty_almost => empty_almost,
358
359 data_ren => data_ren,
360 rdata => rdata,
361
362
363 full_almost => full_almost,
364 full => full,
365 data_wen => data_wen,
366 wdata => wdata);
367
368 data_f0_data_out <= rdata;
369 data_f1_data_out <= rdata;
370 data_f2_data_out <= rdata;
371 data_f3_data_out <= rdata;
372
373 --lpp_waveform_fifo_withoutLatency_1: lpp_waveform_fifo_withoutLatency
374 -- GENERIC MAP (
375 -- tech => tech)
376 -- PORT MAP (
377 -- clk => clk,
378 -- rstn => rstn,
379 -- run => run,
380
381 -- empty_almost => empty_almost,
382 -- empty => empty,
383 -- data_ren => data_ren,
384
385 -- rdata_0 => data_f0_data_out,
386 -- rdata_1 => data_f1_data_out,
387 -- rdata_2 => data_f2_data_out,
388 -- rdata_3 => data_f3_data_out,
236
389
237 time_wen => time_wen,
390 -- full_almost => full_almost,
238 data_wen => data_wen,
391 -- full => full,
239 wdata => wdata);
392 -- data_wen => data_wen,
240
393 -- wdata => wdata);
241 pp_waveform_dma_1: lpp_waveform_dma
394
242 GENERIC MAP (
395
243 data_size => data_size,
396
244 tech => tech,
397
245 hindex => hindex,
398 data_ren <= data_f3_data_out_ren &
246 nb_burst_available_size => nb_burst_available_size)
399 data_f2_data_out_ren &
247 PORT MAP (
400 data_f1_data_out_ren &
248 HCLK => clk,
401 data_f0_data_out_ren;
249 HRESETn => rstn,
402
250 AHB_Master_In => AHB_Master_In,
403 -----------------------------------------------------------------------------
251 AHB_Master_Out => AHB_Master_Out,
404 -- TODO : set the alterance : time, data, data, .....
252 data_ready => ready,
405 -----------------------------------------------------------------------------
253 data => rdata,
406 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
254 data_data_ren => data_ren,
407 GENERIC MAP (
255 data_time_ren => time_ren,
408 nb_data_by_buffer_size => nb_word_by_buffer_size)
256 nb_burst_available => nb_burst_available,
409 PORT MAP (
257 status_full => status_full,
410 clk => clk,
258 status_full_ack => status_full_ack,
411 rstn => rstn,
259 status_full_err => status_full_err,
412 run => run,
260 addr_data_f0 => addr_data_f0,
413
261 addr_data_f1 => addr_data_f1,
414 -------------------------------------------------------------------------
262 addr_data_f2 => addr_data_f2,
415 -- CONFIG
263 addr_data_f3 => addr_data_f3);
416 -------------------------------------------------------------------------
417 nb_data_by_buffer => nb_word_by_buffer,
418
419 addr_data_f0 => addr_data_f0,
420 addr_data_f1 => addr_data_f1,
421 addr_data_f2 => addr_data_f2,
422 addr_data_f3 => addr_data_f3,
423 -------------------------------------------------------------------------
424 -- CTRL
425 -------------------------------------------------------------------------
426 -- IN
427 empty => empty,
428 empty_almost => empty_almost,
429 data_ren => data_ren,
430
431 -------------------------------------------------------------------------
432 -- STATUS
433 -------------------------------------------------------------------------
434 status_full => status_full,
435 status_full_ack => status_full_ack,
436 status_full_err => status_full_err,
437
438 -------------------------------------------------------------------------
439 -- ADDR DATA OUT
440 -------------------------------------------------------------------------
441 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
442 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
443 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
444 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
445
446 data_f0_data_out_valid => data_f0_data_out_valid,
447 data_f1_data_out_valid => data_f1_data_out_valid,
448 data_f2_data_out_valid => data_f2_data_out_valid,
449 data_f3_data_out_valid => data_f3_data_out_valid,
450
451 data_f0_addr_out => data_f0_addr_out,
452 data_f1_addr_out => data_f1_addr_out,
453 data_f2_addr_out => data_f2_addr_out,
454 data_f3_addr_out => data_f3_addr_out
455 );
264
456
265 END beh;
457 END beh;
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@@ -9,6 +9,7 ENTITY lpp_waveform_burst IS
9 PORT (
9 PORT (
10 clk : IN STD_LOGIC;
10 clk : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
11 rstn : IN STD_LOGIC;
12 run : IN STD_LOGIC;
12
13
13 enable : IN STD_LOGIC;
14 enable : IN STD_LOGIC;
14
15
@@ -31,7 +32,7 BEGIN -- beh
31 data_out_valid <= '0';
32 data_out_valid <= '0';
32 ELSIF clk'EVENT AND clk = '1' THEN
33 ELSIF clk'EVENT AND clk = '1' THEN
33 data_out <= data_in;
34 data_out <= data_in;
34 IF enable = '0' THEN
35 IF enable = '0' OR run = '0' THEN
35 data_out_valid <= '0';
36 data_out_valid <= '0';
36 ELSE
37 ELSE
37 data_out_valid <= data_in_valid;
38 data_out_valid <= data_in_valid;
Show file before | Show file after | Hide comments
@@ -53,14 +53,18 ENTITY lpp_waveform_dma IS
53 -- AMBA AHB system signals
53 -- AMBA AHB system signals
54 HCLK : IN STD_ULOGIC;
54 HCLK : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
55 HRESETn : IN STD_ULOGIC;
56 --
57 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
58 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
59 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
60 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
61 --
60 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 enable : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
61 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
63 time_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
62 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
64 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
63 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- todo
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
67 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
64 -- Reg
68 -- Reg
65 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
69 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
66 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
70 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
@@ -79,7 +83,7 ARCHITECTURE Behavioral OF lpp_waveform_
79 SIGNAL DMAIn : DMA_In_Type;
83 SIGNAL DMAIn : DMA_In_Type;
80 SIGNAL DMAOut : DMA_OUt_Type;
84 SIGNAL DMAOut : DMA_OUt_Type;
81 -----------------------------------------------------------------------------
85 -----------------------------------------------------------------------------
82 TYPE state_DMAWriteBurst IS (IDLE,
86 TYPE state_DMAWriteBurst IS (IDLE,TRASH_FIFO_TIME,TRASH_FIFO_DATA,
83 SEND_TIME_0, WAIT_TIME_0,
87 SEND_TIME_0, WAIT_TIME_0,
84 SEND_TIME_1, WAIT_TIME_1,
88 SEND_TIME_1, WAIT_TIME_1,
85 SEND_5_TIME,
89 SEND_5_TIME,
@@ -88,9 +92,12 ARCHITECTURE Behavioral OF lpp_waveform_
88 -----------------------------------------------------------------------------
92 -----------------------------------------------------------------------------
89 -- CONTROL
93 -- CONTROL
90 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
94 SIGNAL sel_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
95 SIGNAL sel_data_ss : STD_LOGIC;
96 SIGNAL sel_time_s : STD_LOGIC;
91 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
97 SIGNAL sel_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
92 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 SIGNAL update : STD_LOGIC_VECTOR(1 DOWNTO 0);
93 SIGNAL time_select : STD_LOGIC;
99 SIGNAL time_select : STD_LOGIC;
100 SIGNAL enable_sel : STD_LOGIC;
94 SIGNAL time_write : STD_LOGIC;
101 SIGNAL time_write : STD_LOGIC;
95 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
102 SIGNAL time_already_send : STD_LOGIC_VECTOR(3 DOWNTO 0);
96 SIGNAL time_already_send_s : STD_LOGIC;
103 SIGNAL time_already_send_s : STD_LOGIC;
@@ -109,6 +116,7 ARCHITECTURE Behavioral OF lpp_waveform_
109 SIGNAL data_send_ok : STD_LOGIC;
116 SIGNAL data_send_ok : STD_LOGIC;
110 SIGNAL data_send_ko : STD_LOGIC;
117 SIGNAL data_send_ko : STD_LOGIC;
111 SIGNAL data_fifo_ren : STD_LOGIC;
118 SIGNAL data_fifo_ren : STD_LOGIC;
119 SIGNAL trash_fifo_ren : STD_LOGIC;
112 SIGNAL data_ren : STD_LOGIC;
120 SIGNAL data_ren : STD_LOGIC;
113 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
114 -- SELECT ADDRESS
122 -- SELECT ADDRESS
@@ -170,6 +178,21 BEGIN
170 "01" WHEN data_ready(1) = '1' ELSE
178 "01" WHEN data_ready(1) = '1' ELSE
171 "10" WHEN data_ready(2) = '1' ELSE
179 "10" WHEN data_ready(2) = '1' ELSE
172 "11";
180 "11";
181
182 sel_data_ss <= data_ready(0) WHEN sel_data = "00" ELSE
183 data_ready(1) WHEN sel_data = "01" ELSE
184 data_ready(2) WHEN sel_data = "10" ELSE
185 data_ready(3);
186
187 sel_time_s <= time_ready(0) WHEN sel_data = "00" ELSE
188 time_ready(1) WHEN sel_data = "01" ELSE
189 time_ready(2) WHEN sel_data = "10" ELSE
190 time_ready(3);
191
192 enable_sel <= enable(0) WHEN sel_data = "00" ELSE
193 enable(1) WHEN sel_data = "01" ELSE
194 enable(2) WHEN sel_data = "10" ELSE
195 enable(3);
173
196
174 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
197 time_already_send_s <= time_already_send(0) WHEN data_ready(0) = '1' ELSE
175 time_already_send(1) WHEN data_ready(1) = '1' ELSE
198 time_already_send(1) WHEN data_ready(1) = '1' ELSE
@@ -186,6 +209,7 BEGIN
186 update <= "00";
209 update <= "00";
187 time_select <= '0';
210 time_select <= '0';
188 time_fifo_ren <= '1';
211 time_fifo_ren <= '1';
212 trash_fifo_ren <= '1';
189 data_send <= '0';
213 data_send <= '0';
190 time_send <= '0';
214 time_send <= '0';
191 time_write <= '0';
215 time_write <= '0';
@@ -203,14 +227,37 BEGIN
203 data_send <= '0';
227 data_send <= '0';
204 time_send <= '0';
228 time_send <= '0';
205 time_write <= '0';
229 time_write <= '0';
206
230 trash_fifo_ren <= '1';
207 IF data_ready = "0000" THEN
231 IF data_ready = "0000" THEN
208 state <= IDLE;
232 state <= IDLE;
209 ELSE
233 ELSE
210 sel_data <= sel_data_s;
234 sel_data <= sel_data_s;
211 state <= SEND_5_TIME;
235 IF enable_sel = '1' THEN
236 state <= SEND_5_TIME;
237 ELSE
238 state <= TRASH_FIFO_TIME;
239 END IF;
240
212 END IF;
241 END IF;
213
242
243 WHEN TRASH_FIFO_TIME =>
244 time_select <= '1';
245 time_fifo_ren <= '0';
246 IF sel_time_s = '1' THEN
247 time_fifo_ren <= '1';
248 state <= TRASH_FIFO_DATA;
249 END IF;
250
251
252 WHEN TRASH_FIFO_DATA =>
253 time_select <= '1';
254 trash_fifo_ren <= '0';
255 IF sel_data_ss = '1' THEN
256 trash_fifo_ren <= '1';
257 state <= IDLE;
258 END IF;
259
260
214 WHEN SEND_5_TIME =>
261 WHEN SEND_5_TIME =>
215 update <= "00";
262 update <= "00";
216 time_select <= '1';
263 time_select <= '1';
@@ -283,9 +330,9 BEGIN
283 send_ok => data_send_ok,
330 send_ok => data_send_ok,
284 send_ko => data_send_ko);
331 send_ko => data_send_ko);
285
332
286 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
333 DMAIn <= time_dmai WHEN time_select = '1' ELSE data_dmai;
287 data_ren <= '1' WHEN time_select = '1' ELSE data_fifo_ren;
334 data_ren <= trash_fifo_ren WHEN time_select = '1' ELSE data_fifo_ren;
288 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
335 time_ren <= time_fifo_ren WHEN time_select = '1' ELSE '1';
289
336
290 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
337 all_data_ren : FOR I IN 3 DOWNTO 0 GENERATE
291 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
338 data_data_ren(I) <= data_ren WHEN UNSIGNED(sel_data) = I ELSE '1';
@@ -306,6 +353,10 BEGIN
306 PORT MAP (
353 PORT MAP (
307 HCLK => HCLK,
354 HCLK => HCLK,
308 HRESETn => HRESETn,
355 HRESETn => HRESETn,
356
357 run => run,
358
359 enable => enable(I),
309 update => update_and_sel((2*I)+1 DOWNTO 2*I),
360 update => update_and_sel((2*I)+1 DOWNTO 2*I),
310 nb_burst_available => nb_burst_available,
361 nb_burst_available => nb_burst_available,
311 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
362 addr_data_reg => addr_data_reg_vector(32*I+31 DOWNTO 32*I),
Show file before | Show file after | Hide comments
@@ -1,4 +1,3
1
2 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
@@ -29,20 +28,23 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
28 USE ieee.numeric_std.ALL;
30
29
31
30
32 ENTITY lpp_waveform_dma_gen_valid IS
31 ENTITY lpp_waveform_dma_genvalid IS
33 PORT (
32 PORT (
34 HCLK : IN STD_LOGIC;
33 HCLK : IN STD_LOGIC;
35 HRESETn : IN STD_LOGIC;
34 HRESETn : IN STD_LOGIC;
36
35 run : IN STD_LOGIC;
37 valid_in : IN STD_LOGIC;
36
38 ack_in : IN STD_LOGIC;
37 valid_in : IN STD_LOGIC;
39
38 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
40 valid_out : OUT STD_LOGIC;
39
41 error : OUT STD_LOGIC
40 ack_in : IN STD_LOGIC;
41 valid_out : OUT STD_LOGIC;
42 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
43 error : OUT STD_LOGIC
42 );
44 );
43 END;
45 END;
44
46
45 ARCHITECTURE Behavioral OF lpp_waveform_dma_gen_valid IS
47 ARCHITECTURE Behavioral OF lpp_waveform_dma_genvalid IS
46 TYPE state_fsm IS (IDLE, VALID);
48 TYPE state_fsm IS (IDLE, VALID);
47 SIGNAL state : state_fsm;
49 SIGNAL state : state_fsm;
48 BEGIN
50 BEGIN
@@ -50,34 +52,42 BEGIN
50 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
52 FSM_SELECT_ADDRESS : PROCESS (HCLK, HRESETn)
51 BEGIN
53 BEGIN
52 IF HRESETn = '0' THEN
54 IF HRESETn = '0' THEN
53 state <= IDLE;
55 state <= IDLE;
54 valid_out <= '0';
56 valid_out <= '0';
55 error <= '0';
57 error <= '0';
58 time_out <= (OTHERS => '0');
56 ELSIF HCLK'EVENT AND HCLK = '1' THEN
59 ELSIF HCLK'EVENT AND HCLK = '1' THEN
57 CASE state IS
60 CASE state IS
58 WHEN IDLE =>
61 WHEN IDLE =>
59 valid_out <= '0';
62
60 error <= '0';
63 valid_out <= '0';
61 IF valid_in = '1' THEN
64 error <= '0';
62 state <= VALID;
65 IF run = '1' AND valid_in = '1' THEN
63 valid_out <= '1';
66 state <= VALID;
67 valid_out <= '1';
68 time_out <= time_in;
64 END IF;
69 END IF;
65
70
66 WHEN VALID =>
71 WHEN VALID =>
67 valid_out <= '1';
72 IF run = '0' THEN
68 error <= '0';
73 state <= IDLE;
69 IF valid_in = '1' THEN
74 valid_out <= '0';
70 IF ack_in = '1' THEN
75 error <= '0';
71 state <= VALID;
76 ELSE
72 valid_out <= '1';
77 IF valid_in = '1' THEN
73 ELSE
78 IF ack_in = '1' THEN
74 state <= IDLE;
79 state <= VALID;
75 error <= '1';
80 valid_out <= '1';
76 valid_out <= '0';
81 time_out <= time_in;
82 ELSE
83 state <= IDLE;
84 error <= '1';
85 valid_out <= '0';
86 END IF;
87 ELSIF ack_in = '1' THEN
88 state <= IDLE;
89 valid_out <= '0';
77 END IF;
90 END IF;
78 ELSIF ack_in = '1' THEN
79 state <= IDLE;
80 valid_out <= '0';
81 END IF;
91 END IF;
82
92
83 WHEN OTHERS => NULL;
93 WHEN OTHERS => NULL;
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@@ -37,6 +37,9 ENTITY lpp_waveform_dma_selectaddress IS
37 HCLK : IN STD_ULOGIC;
37 HCLK : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
38 HRESETn : IN STD_ULOGIC;
39
39
40 run : IN STD_ULOGIC;
41
42 enable : IN STD_LOGIC;
40 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
43 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
41
44
42 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
45 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
@@ -77,52 +80,81 BEGIN
77 status_full_err <= '0';
80 status_full_err <= '0';
78 update_r <= "00";
81 update_r <= "00";
79 ELSIF HCLK'EVENT AND HCLK = '1' THEN
82 ELSIF HCLK'EVENT AND HCLK = '1' THEN
80 update_r <= update;
83 update_r <= update;
81 CASE state IS
84 CASE state IS
82 WHEN IDLE =>
85 WHEN IDLE =>
83 IF update_s = '1' THEN
86 IF run = '0' THEN
84 state <= ADD;
87 state <= IDLE;
88 address <= (OTHERS => '0');
89 nb_send <= (OTHERS => '0');
90 status_full <= '0';
91 status_full_err <= '0';
92 update_r <= "00";
93 ELSE
94 IF enable = '0' THEN
95 state <= UPDATED;
96 ELSIF update_s = '1' THEN
97 state <= ADD;
98 END IF;
85 END IF;
99 END IF;
86
100
87 WHEN ADD =>
101 WHEN ADD =>
88 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
102 IF run = '0' THEN
89 state <= IDLE;
103 state <= IDLE;
90 IF update_r = "10" THEN
104 ELSE
91 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
105 IF UNSIGNED(nb_send_next) < UNSIGNED(nb_burst_available) THEN
92 nb_send <= nb_send_next;
106 state <= IDLE;
93 ELSIF update_r = "01" THEN
107 IF update_r = "10" THEN
94 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
108 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 64);
109 nb_send <= nb_send_next;
110 ELSIF update_r = "01" THEN
111 address <= STD_LOGIC_VECTOR(UNSIGNED(address) + 4);
112 END IF;
113 ELSE
114 state <= FULL;
115 nb_send <= (OTHERS => '0');
116 status_full <= '1';
95 END IF;
117 END IF;
96 ELSE
97 state <= FULL;
98 nb_send <= (OTHERS => '0');
99 status_full <= '1';
100 END IF;
118 END IF;
101
119
102 WHEN FULL =>
120 WHEN FULL =>
103 status_full <= '0';
121 IF run = '0' THEN
104 IF status_full_ack = '1' THEN
122 state <= IDLE;
105 IF update_s = '1' THEN
106 status_full_err <= '1';
107 END IF;
108 state <= UPDATED;
109 ELSE
123 ELSE
110 IF update_s = '1' THEN
124 status_full <= '0';
111 status_full_err <= '1';
125 IF status_full_ack = '1' THEN
112 state <= ERR;
126 IF update_s = '1' THEN
127 status_full_err <= '1';
128 END IF;
129 state <= UPDATED;
130 ELSE
131 IF update_s = '1' THEN
132 status_full_err <= '1';
133 state <= ERR;
134 END IF;
113 END IF;
135 END IF;
114 END IF;
136 END IF;
115
137
116 WHEN ERR =>
138 WHEN ERR =>
117 status_full_err <= '0';
139 IF run = '0' THEN
118 IF status_full_ack = '1' THEN
140 state <= IDLE;
119 state <= UPDATED;
141 ELSE
142 status_full_err <= '0';
143 IF status_full_ack = '1' THEN
144 state <= UPDATED;
145 END IF;
120 END IF;
146 END IF;
121
147
122 WHEN UPDATED =>
148 WHEN UPDATED =>
123 status_full_err <= '0';
149 IF run = '0' THEN
124 state <= IDLE;
150 state <= IDLE;
125 address <= addr_data_reg;
151 ELSE
152 status_full_err <= '0';
153 address <= addr_data_reg;
154 IF enable = '1' THEN
155 state <= IDLE;
156 END IF;
157 END IF;
126
158
127 WHEN OTHERS => NULL;
159 WHEN OTHERS => NULL;
128 END CASE;
160 END CASE;
Show file before | Show file after | Hide comments
@@ -37,113 +37,83 ENTITY lpp_waveform_fifo IS
37 PORT(
37 PORT(
38 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
40
41 ---------------------------------------------------------------------------
40 ---------------------------------------------------------------------------
42 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- FIFO_DATA occupancy is greater than 16 * 32b
41 run : IN STD_LOGIC;
43
42
44 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
45 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 empty_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is lesser than 16 * 32b
46 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 empty : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
47
46 data_ren : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
48 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
47 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
49
48
50 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
51 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
50 full_almost : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0); --occupancy is greater than MAX - 5 * 32b
52 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
51 full : OUT STD_LOGIC_VECTOR( 3 DOWNTO 0);
53
52 data_wen : IN STD_LOGIC_VECTOR( 3 DOWNTO 0);
54 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
55 );
54 );
56 END ENTITY;
55 END ENTITY;
57
56
58
57
59 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
58 ARCHITECTURE ar_lpp_waveform_fifo OF lpp_waveform_fifo IS
60
59
61
62 SIGNAL time_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
63 SIGNAL time_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
64 SIGNAL time_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 SIGNAL time_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
66
67 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
60 SIGNAL data_mem_addr_r : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
68 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
61 SIGNAL data_mem_addr_w : LPP_TYPE_ADDR_FIFO_WAVEFORM(3 DOWNTO 0);
69 SIGNAL data_mem_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
62 SIGNAL data_mem_re : STD_LOGIC_VECTOR(3 DOWNTO 0);
70 SIGNAL data_mem_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
63 SIGNAL data_mem_we : STD_LOGIC_VECTOR(3 DOWNTO 0);
71
64
72 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
65 SIGNAL data_addr_r : STD_LOGIC_VECTOR(6 DOWNTO 0);
73 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
66 SIGNAL data_addr_w : STD_LOGIC_VECTOR(6 DOWNTO 0);
74 SIGNAL ren : STD_LOGIC;
67 SIGNAL re : STD_LOGIC;
75 SIGNAL wen : STD_LOGIC;
68 SIGNAL we : STD_LOGIC;
76
69
77 BEGIN
70 BEGIN
78
71
79 SRAM : syncram_2p
72 SRAM : syncram_2p
80 GENERIC MAP(tech, 7, 32)
73 GENERIC MAP(tech, 7, 32)
81 PORT MAP(clk, ren, data_addr_r, rdata,
74 PORT MAP(clk, re, data_addr_r, rdata,
82 clk, wen, data_addr_w, wdata);
75 clk, we, data_addr_w, wdata);
83
84
76
85 ren <= time_mem_ren(3) OR data_mem_ren(3) OR
77 re <= data_mem_re(3) OR
86 time_mem_ren(2) OR data_mem_ren(2) OR
78 data_mem_re(2) OR
87 time_mem_ren(1) OR data_mem_ren(1) OR
79 data_mem_re(1) OR
88 time_mem_ren(0) OR data_mem_ren(0);
80 data_mem_re(0);
89
81
90 wen <= time_mem_wen(3) OR data_mem_wen(3) OR
82 we <= data_mem_we(3) OR
91 time_mem_wen(2) OR data_mem_wen(2) OR
83 data_mem_we(2) OR
92 time_mem_wen(1) OR data_mem_wen(1) OR
84 data_mem_we(1) OR
93 time_mem_wen(0) OR data_mem_wen(0);
85 data_mem_we(0);
94
86
95 data_addr_r <= time_mem_addr_r(0) WHEN time_mem_ren(0) = '1' ELSE
87 data_addr_r <= data_mem_addr_r(0) WHEN data_mem_re(0) = '1' ELSE
96 time_mem_addr_r(1) WHEN time_mem_ren(1) = '1' ELSE
88 data_mem_addr_r(1) WHEN data_mem_re(1) = '1' ELSE
97 time_mem_addr_r(2) WHEN time_mem_ren(2) = '1' ELSE
89 data_mem_addr_r(2) WHEN data_mem_re(2) = '1' ELSE
98 time_mem_addr_r(3) WHEN time_mem_ren(3) = '1' ELSE
99 data_mem_addr_r(0) WHEN data_mem_ren(0) = '1' ELSE
100 data_mem_addr_r(1) WHEN data_mem_ren(1) = '1' ELSE
101 data_mem_addr_r(2) WHEN data_mem_ren(2) = '1' ELSE
102 data_mem_addr_r(3);
90 data_mem_addr_r(3);
103
91
104 data_addr_w <= time_mem_addr_w(0) WHEN time_mem_wen(0) = '1' ELSE
92 data_addr_w <= data_mem_addr_w(0) WHEN data_mem_we(0) = '1' ELSE
105 time_mem_addr_w(1) WHEN time_mem_wen(1) = '1' ELSE
93 data_mem_addr_w(1) WHEN data_mem_we(1) = '1' ELSE
106 time_mem_addr_w(2) WHEN time_mem_wen(2) = '1' ELSE
94 data_mem_addr_w(2) WHEN data_mem_we(2) = '1' ELSE
107 time_mem_addr_w(3) WHEN time_mem_wen(3) = '1' ELSE
95 data_mem_addr_w(3);
108 data_mem_addr_w(0) WHEN data_mem_wen(0) = '1' ELSE
109 data_mem_addr_w(1) WHEN data_mem_wen(1) = '1' ELSE
110 data_mem_addr_w(2) WHEN data_mem_wen(2) = '1' ELSE
111 data_mem_addr_w(3);
112
113 gen_fifo_ctrl_time: FOR I IN 3 DOWNTO 0 GENERATE
114 lpp_waveform_fifo_ctrl_time: lpp_waveform_fifo_ctrl
115 GENERIC MAP (
116 offset => 32*I + 20,
117 length => 10,
118 enable_ready => '0')
119 PORT MAP (
120 clk => clk,
121 rstn => rstn,
122 ren => time_ren(I),
123 wen => time_wen(I),
124 mem_re => time_mem_ren(I),
125 mem_we => time_mem_wen(I),
126 mem_addr_ren => time_mem_addr_r(I),
127 mem_addr_wen => time_mem_addr_w(I),
128 ready => OPEN);
129 END GENERATE gen_fifo_ctrl_time;
130
96
131 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
97 gen_fifo_ctrl_data: FOR I IN 3 DOWNTO 0 GENERATE
132 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
98 lpp_waveform_fifo_ctrl_data: lpp_waveform_fifo_ctrl
133 GENERIC MAP (
99 GENERIC MAP (
134 offset => 32*I,
100 offset => 32*I,
135 length => 20,
101 length => 32)
136 enable_ready => '1')
137 PORT MAP (
102 PORT MAP (
138 clk => clk,
103 clk => clk,
139 rstn => rstn,
104 rstn => rstn,
105 run => run,
140 ren => data_ren(I),
106 ren => data_ren(I),
141 wen => data_wen(I),
107 wen => data_wen(I),
142 mem_re => data_mem_ren(I),
108 mem_re => data_mem_re(I),
143 mem_we => data_mem_wen(I),
109 mem_we => data_mem_we(I),
144 mem_addr_ren => data_mem_addr_r(I),
110 mem_addr_ren => data_mem_addr_r(I),
145 mem_addr_wen => data_mem_addr_w(I),
111 mem_addr_wen => data_mem_addr_w(I),
146 ready => ready(I));
112 empty_almost => empty_almost(I),
113 empty => empty(I),
114 full_almost => full_almost(I),
115 full => full(I)
116 );
147 END GENERATE gen_fifo_ctrl_data;
117 END GENERATE gen_fifo_ctrl_data;
148
118
149
119
Show file before | Show file after | Hide comments
@@ -25,129 +25,346 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28
29
29 ENTITY lpp_waveform_fifo_arbiter IS
30 ENTITY lpp_waveform_fifo_arbiter IS
30 GENERIC(
31 GENERIC(
31 tech : INTEGER := 0
32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
32 );
34 );
33 PORT(
35 PORT(
34 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
35 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 ---------------------------------------------------------------------------
42 -- SNAPSHOT INTERFACE (INPUT)
43 ---------------------------------------------------------------------------
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
36
48
37 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
38 data_f0_valid : IN STD_LOGIC;
50 -- FIFO INTERFACE (OUTPUT)
39 data_f1_valid : IN STD_LOGIC;
40 data_f2_valid : IN STD_LOGIC;
41 data_f3_valid : IN STD_LOGIC;
42
43 data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
44
45 data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
46 data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
47 data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
48 data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
49
50 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
51 ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
53 ---------------------------------------------------------------------------
54 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
54 time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
55 data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
56 data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
57
56
58 );
57 );
59 END ENTITY;
58 END ENTITY;
60
59
61
60
62 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
61 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
63 TYPE state_fsm IS (IDLE, T1, T2, D1, D2);
62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
64 SIGNAL state : state_fsm;
63 SIGNAL state : state_type_fifo_arbiter;
65
64
66 SIGNAL data_valid_and_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
65 -----------------------------------------------------------------------------
67 SIGNAL data_selected : STD_LOGIC_VECTOR(159 DOWNTO 0);
66 -- DATA MUX
68 SIGNAL data_valid_selected : STD_LOGIC_VECTOR(3 DOWNTO 0);
67 -----------------------------------------------------------------------------
69 SIGNAL data_ready_to_go : STD_LOGIC;
68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70
69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_temp : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 SIGNAL time_en_temp : STD_LOGIC_VECTOR(3 DOWNTO 0);
71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
78
79 -----------------------------------------------------------------------------
80 -- RR and SELECTION
81 -----------------------------------------------------------------------------
82 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 SIGNAL sel_reg : STD_LOGIC;
86 SIGNAL sel_ack : STD_LOGIC;
87 SIGNAL no_sel : STD_LOGIC;
88
89 -----------------------------------------------------------------------------
90 -- REG
91 -----------------------------------------------------------------------------
92 SIGNAL count_enable : STD_LOGIC;
93 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
95
96 --SIGNAL shift_data_enable : STD_LOGIC;
97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
99
100 --SIGNAL shift_time_enable : STD_LOGIC;
101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
103
73 BEGIN
104 BEGIN
74
75 data_valid_and_ready(0) <= ready(0) AND data_f0_valid;
76 data_valid_and_ready(1) <= ready(1) AND data_f1_valid;
77 data_valid_and_ready(2) <= ready(2) AND data_f2_valid;
78 data_valid_and_ready(3) <= ready(3) AND data_f3_valid;
79
80 data_selected <= data_f0 WHEN data_valid_and_ready(0) = '1' ELSE
81 data_f1 WHEN data_valid_and_ready(1) = '1' ELSE
82 data_f2 WHEN data_valid_and_ready(2) = '1' ELSE
83 data_f3;
84
105
85 data_valid_selected <= "0001" WHEN data_valid_and_ready(0) = '1' ELSE
106 -----------------------------------------------------------------------------
86 "0010" WHEN data_valid_and_ready(1) = '1' ELSE
107 -- CONTROL
87 "0100" WHEN data_valid_and_ready(2) = '1' ELSE
108 -----------------------------------------------------------------------------
88 "1000" WHEN data_valid_and_ready(3) = '1' ELSE
89 "0000";
90
91 data_ready_to_go <= data_valid_and_ready(0) OR
92 data_valid_and_ready(1) OR
93 data_valid_and_ready(2) OR
94 data_valid_and_ready(3);
95
96 PROCESS (clk, rstn)
109 PROCESS (clk, rstn)
97 BEGIN
110 BEGIN -- PROCESS
98 IF rstn = '0' THEN
111 IF rstn = '0' THEN -- asynchronous reset (active low)
99 state <= IDLE;
112 count_enable <= '0';
100 data_valid_ack <= (OTHERS => '0');
113 data_in_ack <= (OTHERS => '0');
101 data_wen <= (OTHERS => '1');
114 data_out_wen <= (OTHERS => '1');
102 time_wen <= (OTHERS => '1');
115 sel_ack <= '0';
103 data <= (OTHERS => '0');
116 state <= IDLE;
104 data_temp <= (OTHERS => '0');
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
105 time_en_temp <= (OTHERS => '0');
118 count_enable <= '0';
106 ELSIF clk'EVENT AND clk = '1' THEN
119 data_in_ack <= (OTHERS => '0');
107 CASE state IS
120 data_out_wen <= (OTHERS => '1');
108 WHEN IDLE =>
121 sel_ack <= '0';
109 data_valid_ack <= (OTHERS => '0');
122 IF run = '0' THEN
110 time_wen <= (OTHERS => '1');
123 state <= IDLE;
111 data_wen <= (OTHERS => '1');
124 ELSE
112 data <= (OTHERS => '0');
125 CASE state IS
113 data_temp <= (OTHERS => '0');
126 WHEN IDLE =>
114 IF data_ready_to_go = '1' THEN
127 IF no_sel = '0' THEN
115 state <= T1;
128 state <= TIME1;
116 data_valid_ack <= data_valid_selected;
129 END IF;
117 time_wen <= NOT data_valid_selected;
130 WHEN TIME1 =>
118 time_en_temp <= NOT data_valid_selected;
131 count_enable <= '1';
119 data <= data_selected(31 DOWNTO 0);
132 IF UNSIGNED(count) = 0 THEN
120 data_temp <= data_selected(159 DOWNTO 32);
133 state <= TIME2;
121 END IF;
134 data_out_wen <= NOT sel;
122 WHEN T1 =>
135 data_out <= data_sel(0);
123 state <= T2;
136 ELSE
124 data_valid_ack <= (OTHERS => '0');
137 state <= DATA1;
125 data <= data_temp(31 DOWNTO 0);
138 END IF;
126 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
139 WHEN TIME2 =>
127
140 data_out_wen <= NOT sel;
128 WHEN T2 =>
141 data_out <= data_sel(1) ;
129 state <= D1;
142 state <= DATA1;
130 time_wen <= (OTHERS => '1');
143 WHEN DATA1 =>
131 data_wen <= time_en_temp;
144 data_out_wen <= NOT sel;
132 data <= data_temp(31 DOWNTO 0);
145 data_out <= data_sel(2);
133 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
146 state <= DATA2;
134
147 WHEN DATA2 =>
135 WHEN D1 =>
148 data_out_wen <= NOT sel;
136 state <= D2;
149 data_out <= data_sel(3);
137 data <= data_temp(31 DOWNTO 0);
150 state <= DATA3;
138 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
151 WHEN DATA3 =>
139
152 data_out_wen <= NOT sel;
140 WHEN D2 =>
153 data_out <= data_sel(4);
141 state <= IDLE;
154 state <= LAST;
142 data <= data_temp(31 DOWNTO 0);
155 data_in_ack <= sel;
143 data_temp(32*3-1 DOWNTO 0) <= data_temp(32*4-1 DOWNTO 32);
156 WHEN LAST =>
144
157 state <= IDLE;
145 WHEN OTHERS => NULL;
158 sel_ack <= '1';
146 END CASE;
159
147
160 WHEN OTHERS => NULL;
161 END CASE;
162 END IF;
148 END IF;
163 END IF;
149 END PROCESS;
164 END PROCESS;
150
165 -----------------------------------------------------------------------------
166
167
168 --PROCESS (clk, rstn)
169 --BEGIN -- PROCESS
170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
171 -- count_enable <= '0';
172 -- shift_time_enable <= '0';
173 -- shift_data_enable <= '0';
174 -- data_in_ack <= (OTHERS => '0');
175 -- data_out_wen <= (OTHERS => '1');
176 -- sel_ack <= '0';
177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
178 -- IF run = '0' OR no_sel = '1' THEN
179 -- count_enable <= '0';
180 -- shift_time_enable <= '0';
181 -- shift_data_enable <= '0';
182 -- data_in_ack <= (OTHERS => '0');
183 -- data_out_wen <= (OTHERS => '1');
184 -- sel_ack <= '0';
185 -- ELSE
186 -- --COUNT
187 -- IF shift_data_s = "10" THEN
188 -- count_enable <= '1';
189 -- ELSE
190 -- count_enable <= '0';
191 -- END IF;
192 -- --DATA
193 -- IF shift_time_s = "10" THEN
194 -- shift_data_enable <= '1';
195 -- ELSE
196 -- shift_data_enable <= '0';
197 -- END IF;
198
199 -- --TIME
200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
201 -- shift_time_s = "00" OR
202 -- shift_time_s = "01"
203 -- THEN
204 -- shift_time_enable <= '1';
205 -- ELSE
206 -- shift_time_enable <= '0';
207 -- END IF;
208
209 -- --ACK
210 -- IF shift_data_s = "10" THEN
211 -- data_in_ack <= sel;
212 -- sel_ack <= '1';
213 -- ELSE
214 -- data_in_ack <= (OTHERS => '0');
215 -- sel_ack <= '0';
216 -- END IF;
217
218 -- --VALID OUT
219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
220 -- IF sel(I) = '1' AND count_enable = '0' THEN
221 -- data_out_wen(I) <= '0';
222 -- ELSE
223 -- data_out_wen(I) <= '1';
224 -- END IF;
225 -- END LOOP all_wen;
226
227 -- END IF;
228 -- END IF;
229 --END PROCESS;
230
231 -----------------------------------------------------------------------------
232 -- DATA MUX
233 -----------------------------------------------------------------------------
234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
235 I_time_in: IF I < 48 GENERATE
236 data_0_v(I) <= time_in(0,I);
237 data_1_v(I) <= time_in(1,I);
238 data_2_v(I) <= time_in(2,I);
239 data_3_v(I) <= time_in(3,I);
240 END GENERATE I_time_in;
241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
242 data_0_v(I) <= '0';
243 data_1_v(I) <= '0';
244 data_2_v(I) <= '0';
245 data_3_v(I) <= '0';
246 END GENERATE I_null;
247 I_data_in: IF I > 32*2-1 GENERATE
248 data_0_v(I) <= data_in(0,I-32*2);
249 data_1_v(I) <= data_in(1,I-32*2);
250 data_2_v(I) <= data_in(2,I-32*2);
251 data_3_v(I) <= data_in(3,I-32*2);
252 END GENERATE I_data_in;
253 END GENERATE all_bit_data_in;
254
255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
256 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
257 data_0(J)(I) <= data_0_v(J*32+I);
258 data_1(J)(I) <= data_1_v(J*32+I);
259 data_2(J)(I) <= data_2_v(J*32+I);
260 data_3(J)(I) <= data_3_v(J*32+I);
261 END GENERATE all_data_bit;
262 END GENERATE all_word;
263
264 data_sel <= data_0 WHEN sel(0) = '1' ELSE
265 data_1 WHEN sel(1) = '1' ELSE
266 data_2 WHEN sel(2) = '1' ELSE
267 data_3;
268
269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
270 -- data_sel(1) WHEN shift_time = "01" ELSE
271 -- data_sel(2) WHEN shift_data = "00" ELSE
272 -- data_sel(3) WHEN shift_data = "01" ELSE
273 -- data_sel(4);
274
275
276 -----------------------------------------------------------------------------
277 -- RR and SELECTION
278 -----------------------------------------------------------------------------
279 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
281 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
282 END GENERATE all_input_rr;
283
284 RR_Arbiter_4_1 : RR_Arbiter_4
285 PORT MAP (
286 clk => clk,
287 rstn => rstn,
288 in_valid => valid_in_rr,
289 out_grant => sel_s); --sel_s);
290
291 -- sel <= sel_s;
292
293 PROCESS (clk, rstn)
294 BEGIN -- PROCESS
295 IF rstn = '0' THEN -- asynchronous reset (active low)
296 sel <= "0000";
297 sel_reg <= '0';
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 -- sel_reg
300 -- sel_ack
301 -- sel_s
302 -- sel = "0000 "
303 --sel <= sel_s;
304 IF sel_reg = '0' OR sel_ack = '1'
305 --OR shift_data_s = "10"
306 THEN
307 sel <= sel_s;
308 IF sel_s = "0000" THEN
309 sel_reg <= '0';
310 ELSE
311 sel_reg <= '1';
312 END IF;
313 END IF;
314 END IF;
315 END PROCESS;
316
317 no_sel <= '1' WHEN sel = "0000" ELSE '0';
318
319 -----------------------------------------------------------------------------
320 -- REG
321 -----------------------------------------------------------------------------
322 reg_count_i: lpp_waveform_fifo_arbiter_reg
323 GENERIC MAP (
324 data_size => nb_data_by_buffer_size,
325 data_nb => 4)
326 PORT MAP (
327 clk => clk,
328 rstn => rstn,
329 run => run,
330 max_count => nb_data_by_buffer,
331 enable => count_enable,
332 sel => sel,
333 data => count,
334 data_s => count_s);
335
336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
337 -- GENERIC MAP (
338 -- data_size => 2,
339 -- data_nb => 4)
340 -- PORT MAP (
341 -- clk => clk,
342 -- rstn => rstn,
343 -- run => run,
344 -- max_count => "10", -- 2
345 -- enable => shift_data_enable,
346 -- sel => sel,
347 -- data => shift_data,
348 -- data_s => shift_data_s);
349
350
351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
352 -- GENERIC MAP (
353 -- data_size => 2,
354 -- data_nb => 4)
355 -- PORT MAP (
356 -- clk => clk,
357 -- rstn => rstn,
358 -- run => run,
359 -- max_count => "10", -- 2
360 -- enable => shift_time_enable,
361 -- sel => sel,
362 -- data => shift_time,
363 -- data_s => shift_time_s);
364
365
366
367
151 END ARCHITECTURE;
368 END ARCHITECTURE;
152
369
153
370
Show file before | Show file after | Hide comments
@@ -33,12 +33,13 USE techmap.gencomp.ALL;
33 ENTITY lpp_waveform_fifo_ctrl IS
33 ENTITY lpp_waveform_fifo_ctrl IS
34 generic(
34 generic(
35 offset : INTEGER := 0;
35 offset : INTEGER := 0;
36 length : INTEGER := 20;
36 length : INTEGER := 20
37 enable_ready : STD_LOGIC := '1'
38 );
37 );
39 PORT(
38 PORT(
40 clk : IN STD_LOGIC;
39 clk : IN STD_LOGIC;
41 rstn : IN STD_LOGIC;
40 rstn : IN STD_LOGIC;
41
42 run : IN STD_LOGIC;
42
43
43 ren : IN STD_LOGIC;
44 ren : IN STD_LOGIC;
44 wen : IN STD_LOGIC;
45 wen : IN STD_LOGIC;
@@ -48,8 +49,12 ENTITY lpp_waveform_fifo_ctrl IS
48
49
49 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
50 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
50 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
51 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
51
52 ---------------------------------------------------------------------------
52 ready : OUT STD_LOGIC
53 empty_almost : OUT STD_LOGIC; --occupancy is lesser than 16 * 32b
54 empty : OUT STD_LOGIC;
55 full_almost : OUT STD_LOGIC; --occupancy is greater than MAX - 5 * 32b
56 full : OUT STD_LOGIC
57
53 );
58 );
54 END ENTITY;
59 END ENTITY;
55
60
@@ -71,6 +76,9 ARCHITECTURE ar_lpp_waveform_fifo_ctrl O
71 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
76 SIGNAL Waddr_vect_s : INTEGER RANGE 0 TO length := 0;
72 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
77 SIGNAL Raddr_vect_s : INTEGER RANGE 0 TO length := 0;
73
78
79 SIGNAL space_busy : INTEGER RANGE 0 TO length := 0;
80 SIGNAL space_free : INTEGER RANGE 0 TO length := 0;
81
74 BEGIN
82 BEGIN
75 mem_re <= sRE;
83 mem_re <= sRE;
76 mem_we <= sWE;
84 mem_we <= sWE;
@@ -92,12 +100,15 BEGIN
92 Raddr_vect <= 0;
100 Raddr_vect <= 0;
93 sempty <= '1';
101 sempty <= '1';
94 ELSIF(clk'EVENT AND clk = '1')then
102 ELSIF(clk'EVENT AND clk = '1')then
95 sEmpty <= sempty_s;
103 IF run = '0' THEN
96
104 Raddr_vect <= 0;
97 IF(sREN = '0' and sempty = '0')then
105 sempty <= '1';
98 Raddr_vect <= Raddr_vect_s;
106 ELSE
107 sEmpty <= sempty_s;
108 IF(sREN = '0' and sempty = '0')then
109 Raddr_vect <= Raddr_vect_s;
110 END IF;
99 END IF;
111 END IF;
100
101 END IF;
112 END IF;
102 END PROCESS;
113 END PROCESS;
103
114
@@ -118,13 +129,16 BEGIN
118 IF(rstn = '0')then
129 IF(rstn = '0')then
119 Waddr_vect <= 0;
130 Waddr_vect <= 0;
120 sfull <= '0';
131 sfull <= '0';
121 ELSIF(clk'EVENT AND clk = '1')then
132 ELSIF(clk'EVENT AND clk = '1')THEN
122 sfull <= sfull_s;
133 IF run = '0' THEN
123
134 Waddr_vect <= 0;
124 IF(sWEN = '0' and sfull = '0')THEN
135 sfull <= '0';
125 Waddr_vect <= Waddr_vect_s;
136 ELSE
137 sfull <= sfull_s;
138 IF(sWEN = '0' and sfull = '0')THEN
139 Waddr_vect <= Waddr_vect_s;
140 END IF;
126 END IF;
141 END IF;
127
128 END IF;
142 END IF;
129 END PROCESS;
143 END PROCESS;
130
144
@@ -132,15 +146,32 BEGIN
132 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
146 mem_addr_wen <= std_logic_vector(to_unsigned((Waddr_vect + offset), mem_addr_wen'length));
133 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
147 mem_addr_ren <= std_logic_vector(to_unsigned((Raddr_vect + offset), mem_addr_ren'length));
134
148
135 ready_gen: IF enable_ready = '1' GENERATE
149
136 ready <= '1' WHEN Waddr_vect > Raddr_vect AND (Waddr_vect - Raddr_vect) > 15 ELSE
150 -----------------------------------------------------------------------------
137 '1' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
151 --
138 '0';
152 -----------------------------------------------------------------------------
139 END GENERATE ready_gen;
153 --empty_almost <= '0' WHEN Waddr_vect > Raddr_vect AND ( Waddr_vect - Raddr_vect) > 15 ELSE
154 -- '0' WHEN Waddr_vect < Raddr_vect AND (length + Waddr_vect - Raddr_vect) > 15 ELSE
155 -- '1';
156 empty_almost <= '0' WHEN space_busy > 15 ELSE '1';
157 empty <= sEmpty;
140
158
141 ready_not_gen: IF enable_ready = '0' GENERATE
159 --full_almost <= '0' WHEN Waddr_vect > Raddr_vect AND (length + Raddr_vect - Waddr_vect) > 5 ELSE
142 ready <= '0';
160 -- '0' WHEN Waddr_vect < Raddr_vect AND ( Raddr_vect - Waddr_vect) > 5 ELSE
143 END GENERATE ready_not_gen;
161 -- sfull WHEN Waddr_vect = Raddr_vect ELSE
162 -- '1';
163 full_almost <= '0' WHEN space_free > 4 ELSE '1';
164 full <= sfull;
165
166 -----------------------------------------------------------------------------
167 --
168 -----------------------------------------------------------------------------
169 space_busy <= length WHEN sfull = '1' ELSE
170 length + Waddr_vect - Raddr_vect WHEN Waddr_vect < Raddr_vect ELSE
171 Waddr_vect - Raddr_vect;
172
173 space_free <= length - space_busy;
174
144
175
145 END ARCHITECTURE;
176 END ARCHITECTURE;
146
177
@@ -168,4 +199,3 END ARCHITECTURE;
168
199
169
200
170
201
171
Show file before | Show file after | Hide comments
@@ -1,3 +1,25
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
1 LIBRARY IEEE;
23 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
3
25
@@ -13,7 +35,13 USE techmap.gencomp.ALL;
13 PACKAGE lpp_waveform_pkg IS
35 PACKAGE lpp_waveform_pkg IS
14
36
15 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
16
38
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40
41 -----------------------------------------------------------------------------
42 -- SNAPSHOT
43 -----------------------------------------------------------------------------
44
17 COMPONENT lpp_waveform_snapshot
45 COMPONENT lpp_waveform_snapshot
18 GENERIC (
46 GENERIC (
19 data_size : INTEGER;
47 data_size : INTEGER;
@@ -21,6 +49,7 PACKAGE lpp_waveform_pkg IS
21 PORT (
49 PORT (
22 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
23 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
52 run : IN STD_LOGIC;
24 enable : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
25 burst_enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
26 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
@@ -37,6 +66,7 PACKAGE lpp_waveform_pkg IS
37 PORT (
66 PORT (
38 clk : IN STD_LOGIC;
67 clk : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 run : IN STD_LOGIC;
40 enable : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
41 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
42 data_in_valid : IN STD_LOGIC;
72 data_in_valid : IN STD_LOGIC;
@@ -46,198 +76,269 PACKAGE lpp_waveform_pkg IS
46
76
47 COMPONENT lpp_waveform_snapshot_controler
77 COMPONENT lpp_waveform_snapshot_controler
48 GENERIC (
78 GENERIC (
49 delta_snapshot_size : INTEGER;
79 delta_vector_size : INTEGER;
50 delta_f2_f0_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER);
51 delta_f2_f1_size : INTEGER);
52 PORT (
81 PORT (
53 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
54 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
55 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
84 reg_run : IN STD_LOGIC;
56 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
57 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
58 coarse_time_0 : IN STD_LOGIC;
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
59 data_f0_in_valid : IN STD_LOGIC;
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
60 data_f2_in_valid : IN STD_LOGIC;
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 start_snapshot_f0 : OUT STD_LOGIC;
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 start_snapshot_f1 : OUT STD_LOGIC;
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
63 start_snapshot_f2 : OUT STD_LOGIC);
92 data_f0_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
97 wfp_on : OUT STD_LOGIC);
64 END COMPONENT;
98 END COMPONENT;
65
99
66
100 -----------------------------------------------------------------------------
67
101 --
102 -----------------------------------------------------------------------------
68 COMPONENT lpp_waveform
103 COMPONENT lpp_waveform
69 GENERIC (
104 GENERIC (
70 hindex : INTEGER;
71 tech : INTEGER;
105 tech : INTEGER;
72 data_size : INTEGER;
106 data_size : INTEGER;
73 nb_burst_available_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
74 nb_snapshot_param_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
75 delta_snapshot_size : INTEGER;
110 delta_vector_size : INTEGER;
76 delta_f2_f0_size : INTEGER;
111 delta_vector_size_f0_2 : INTEGER);
77 delta_f2_f1_size : INTEGER);
78 PORT (
112 PORT (
79 clk : IN STD_LOGIC;
113 clk : IN STD_LOGIC;
80 rstn : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
81 AHB_Master_In : IN AHB_Mst_In_Type;
115 reg_run : IN STD_LOGIC;
82 AHB_Master_Out : OUT AHB_Mst_Out_Type;
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
83 coarse_time_0 : IN STD_LOGIC;
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
84 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
85 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
86 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 enable_f0 : IN STD_LOGIC;
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 enable_f1 : IN STD_LOGIC;
122 enable_f0 : IN STD_LOGIC;
89 enable_f2 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
90 enable_f3 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
91 burst_f0 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
92 burst_f1 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
93 burst_f2 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
94 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
128 burst_f2 : IN STD_LOGIC;
95 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
96 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
97 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
98 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
99 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
100 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
101 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
102 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
103 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
104 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
105 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 data_f0_in_valid : IN STD_LOGIC;
106 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
107 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
108 data_f0_in_valid : IN STD_LOGIC;
142 data_f1_in_valid : IN STD_LOGIC;
109 data_f1_in_valid : IN STD_LOGIC;
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
110 data_f2_in_valid : IN STD_LOGIC;
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
111 data_f3_in_valid : IN STD_LOGIC);
145 data_f2_in_valid : IN STD_LOGIC;
112 END COMPONENT;
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
113
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
114 COMPONENT lpp_waveform_dma_send_Nword
148 data_f3_in_valid : IN STD_LOGIC;
115 PORT (
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
116 HCLK : IN STD_ULOGIC;
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
117 HRESETn : IN STD_ULOGIC;
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 DMAIn : OUT DMA_In_Type;
152 data_f0_data_out_valid : OUT STD_LOGIC;
119 DMAOut : IN DMA_OUt_Type;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
120 Nb_word_less1 : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
154 data_f0_data_out_ren : IN STD_LOGIC;
121 send : IN STD_LOGIC;
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f1_data_out_valid : OUT STD_LOGIC;
124 ren : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
125 send_ok : OUT STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
126 send_ko : OUT STD_LOGIC);
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 data_f2_data_out_valid : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_f3_data_out_valid : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
170
171 --debug
172 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 debug_f0_data_valid : OUT STD_LOGIC;
174 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 debug_f1_data_valid : OUT STD_LOGIC;
176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177 debug_f2_data_valid : OUT STD_LOGIC;
178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 debug_f3_data_valid : OUT STD_LOGIC);
127 END COMPONENT;
180 END COMPONENT;
128
181
129 COMPONENT lpp_waveform_dma_selectaddress
182 COMPONENT lpp_waveform_dma_genvalid
130 GENERIC (
131 nb_burst_available_size : INTEGER);
132 PORT (
133 HCLK : IN STD_ULOGIC;
134 HRESETn : IN STD_ULOGIC;
135 update : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
136 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
137 addr_data_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
139 status_full : OUT STD_LOGIC;
140 status_full_ack : IN STD_LOGIC;
141 status_full_err : OUT STD_LOGIC);
142 END COMPONENT;
143
144 COMPONENT lpp_waveform_dma_gen_valid
145 PORT (
183 PORT (
146 HCLK : IN STD_LOGIC;
184 HCLK : IN STD_LOGIC;
147 HRESETn : IN STD_LOGIC;
185 HRESETn : IN STD_LOGIC;
186 run : IN STD_LOGIC;
148 valid_in : IN STD_LOGIC;
187 valid_in : IN STD_LOGIC;
149 ack_in : IN STD_LOGIC;
188 ack_in : IN STD_LOGIC;
189 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
150 valid_out : OUT STD_LOGIC;
190 valid_out : OUT STD_LOGIC;
191 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
151 error : OUT STD_LOGIC);
192 error : OUT STD_LOGIC);
152 END COMPONENT;
193 END COMPONENT;
153
194
154 COMPONENT lpp_waveform_dma
195 -----------------------------------------------------------------------------
155 GENERIC (
196 -- FIFO
156 data_size : INTEGER;
197 -----------------------------------------------------------------------------
157 tech : INTEGER;
158 hindex : INTEGER;
159 nb_burst_available_size : INTEGER);
160 PORT (
161 HCLK : IN STD_ULOGIC;
162 HRESETn : IN STD_ULOGIC;
163 AHB_Master_In : IN AHB_Mst_In_Type;
164 AHB_Master_Out : OUT AHB_Mst_Out_Type;
165 data_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
166 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
168 data_time_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
169 --data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
170 --data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
171 --data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 --data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 --data_f0_in_valid : IN STD_LOGIC;
174 --data_f1_in_valid : IN STD_LOGIC;
175 --data_f2_in_valid : IN STD_LOGIC;
176 --data_f3_in_valid : IN STD_LOGIC;
177 nb_burst_available : IN STD_LOGIC_VECTOR(nb_burst_available_size-1 DOWNTO 0);
178 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
179 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
180 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
181 -- status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
182 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
183 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
184 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
186 END COMPONENT;
187
188 COMPONENT lpp_waveform_fifo_ctrl
198 COMPONENT lpp_waveform_fifo_ctrl
189 GENERIC (
199 GENERIC (
190 offset : INTEGER;
200 offset : INTEGER;
191 length : INTEGER;
201 length : INTEGER);
192 enable_ready : STD_LOGIC);
193 PORT (
202 PORT (
194 clk : IN STD_LOGIC;
203 clk : IN STD_LOGIC;
195 rstn : IN STD_LOGIC;
204 rstn : IN STD_LOGIC;
205 run : IN STD_LOGIC;
196 ren : IN STD_LOGIC;
206 ren : IN STD_LOGIC;
197 wen : IN STD_LOGIC;
207 wen : IN STD_LOGIC;
198 mem_re : OUT STD_LOGIC;
208 mem_re : OUT STD_LOGIC;
199 mem_we : OUT STD_LOGIC;
209 mem_we : OUT STD_LOGIC;
200 mem_addr_ren : out STD_LOGIC_VECTOR(6 DOWNTO 0);
210 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
201 mem_addr_wen : out STD_LOGIC_VECTOR(6 DOWNTO 0);
211 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
202 ready : OUT STD_LOGIC);
212 empty_almost : OUT STD_LOGIC;
213 empty : OUT STD_LOGIC;
214 full_almost : OUT STD_LOGIC;
215 full : OUT STD_LOGIC);
203 END COMPONENT;
216 END COMPONENT;
204
217
205 COMPONENT lpp_waveform_fifo_arbiter
218 COMPONENT lpp_waveform_fifo_arbiter
206 GENERIC (
219 GENERIC (
207 tech : INTEGER);
220 tech : INTEGER;
221 nb_data_by_buffer_size : INTEGER);
208 PORT (
222 PORT (
209 clk : IN STD_LOGIC;
223 clk : IN STD_LOGIC;
210 rstn : IN STD_LOGIC;
224 rstn : IN STD_LOGIC;
211 data_f0_valid : IN STD_LOGIC;
225 run : IN STD_LOGIC;
212 data_f1_valid : IN STD_LOGIC;
226 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
213 data_f2_valid : IN STD_LOGIC;
227 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
214 data_f3_valid : IN STD_LOGIC;
228 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
215 data_valid_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
229 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
216 data_f0 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
230 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
217 data_f1 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
231 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
218 data_f2 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
232 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
219 data_f3 : IN STD_LOGIC_VECTOR(159 DOWNTO 0);
233 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
220 ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
221 time_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
222 data_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
223 data : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
224 END COMPONENT;
235 END COMPONENT;
225
236
226 COMPONENT lpp_waveform_fifo
237 COMPONENT lpp_waveform_fifo
227 GENERIC (
238 GENERIC (
228 tech : INTEGER);
239 tech : INTEGER);
229 PORT (
240 PORT (
230 clk : IN STD_LOGIC;
241 clk : IN STD_LOGIC;
231 rstn : IN STD_LOGIC;
242 rstn : IN STD_LOGIC;
232 ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
243 run : IN STD_LOGIC;
233 time_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
244 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
234 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
245 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
235 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
246 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
236 time_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
247 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
237 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
248 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
238 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
249 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
252 END COMPONENT;
253
254 COMPONENT lpp_waveform_fifo_latencyCorrection
255 GENERIC (
256 tech : INTEGER);
257 PORT (
258 clk : IN STD_LOGIC;
259 rstn : IN STD_LOGIC;
260 run : IN STD_LOGIC;
261 empty_almost : OUT STD_LOGIC;
262 empty : OUT STD_LOGIC;
263 data_ren : IN STD_LOGIC;
264 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
265 empty_almost_fifo : IN STD_LOGIC;
266 empty_fifo : IN STD_LOGIC;
267 data_ren_fifo : OUT STD_LOGIC;
268 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
269 END COMPONENT;
270
271 COMPONENT lpp_waveform_fifo_withoutLatency
272 GENERIC (
273 tech : INTEGER);
274 PORT (
275 clk : IN STD_LOGIC;
276 rstn : IN STD_LOGIC;
277 run : IN STD_LOGIC;
278 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
279 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
280 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
281 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
282 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
283 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
284 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
286 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
287 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
288 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
239 END COMPONENT;
289 END COMPONENT;
240
290
291 -----------------------------------------------------------------------------
292 -- GEN ADDRESS
293 -----------------------------------------------------------------------------
294 COMPONENT lpp_waveform_genaddress
295 GENERIC (
296 nb_data_by_buffer_size : INTEGER);
297 PORT (
298 clk : IN STD_LOGIC;
299 rstn : IN STD_LOGIC;
300 run : IN STD_LOGIC;
301 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
302 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
303 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
304 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
305 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
306 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
307 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
308 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
309 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
310 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
311 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
312 data_f0_data_out_valid_burst : OUT STD_LOGIC;
313 data_f1_data_out_valid_burst : OUT STD_LOGIC;
314 data_f2_data_out_valid_burst : OUT STD_LOGIC;
315 data_f3_data_out_valid_burst : OUT STD_LOGIC;
316 data_f0_data_out_valid : OUT STD_LOGIC;
317 data_f1_data_out_valid : OUT STD_LOGIC;
318 data_f2_data_out_valid : OUT STD_LOGIC;
319 data_f3_data_out_valid : OUT STD_LOGIC;
320 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
321 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
322 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
323 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
324 END COMPONENT;
241
325
326 -----------------------------------------------------------------------------
327 -- lpp_waveform_fifo_arbiter_reg
328 -----------------------------------------------------------------------------
329 COMPONENT lpp_waveform_fifo_arbiter_reg
330 GENERIC (
331 data_size : INTEGER;
332 data_nb : INTEGER);
333 PORT (
334 clk : IN STD_LOGIC;
335 rstn : IN STD_LOGIC;
336 run : IN STD_LOGIC;
337 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
338 enable : IN STD_LOGIC;
339 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
340 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
341 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
342 END COMPONENT;
242
343
243 END lpp_waveform_pkg;
344 END lpp_waveform_pkg;
Show file before | Show file after | Hide comments
@@ -11,6 +11,7 ENTITY lpp_waveform_snapshot IS
11 PORT (
11 PORT (
12 clk : IN STD_LOGIC;
12 clk : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
13 rstn : IN STD_LOGIC;
14 run : IN STD_LOGIC;
14
15
15 enable : IN STD_LOGIC;
16 enable : IN STD_LOGIC;
16 burst_enable : IN STD_LOGIC;
17 burst_enable : IN STD_LOGIC;
@@ -39,7 +40,7 BEGIN -- beh
39 counter_points_snapshot <= 0;
40 counter_points_snapshot <= 0;
40 ELSIF clk'EVENT AND clk = '1' THEN
41 ELSIF clk'EVENT AND clk = '1' THEN
41 data_out <= data_in;
42 data_out <= data_in;
42 IF enable = '0' THEN
43 IF enable = '0' OR run = '0' THEN
43 data_out_valid <= '0';
44 data_out_valid <= '0';
44 counter_points_snapshot <= 0;
45 counter_points_snapshot <= 0;
45 ELSE
46 ELSE
Show file before | Show file after | Hide comments
@@ -1,114 +1,226
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
1 LIBRARY IEEE;
23 LIBRARY IEEE;
2 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
3 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
4
26
27 LIBRARY lpp;
28 USE lpp.general_purpose.ALL;
29
5 ENTITY lpp_waveform_snapshot_controler IS
30 ENTITY lpp_waveform_snapshot_controler IS
6
31
7 GENERIC (
32 GENERIC (
8 delta_snapshot_size : INTEGER := 16;
33 delta_vector_size : INTEGER := 20;
9 delta_f2_f0_size : INTEGER := 10;
34 delta_vector_size_f0_2 : INTEGER := 3
10 delta_f2_f1_size : INTEGER := 10);
35 );
11
36
12 PORT (
37 PORT (
13 clk : IN STD_LOGIC;
38 clk : IN STD_LOGIC;
14 rstn : IN STD_LOGIC;
39 rstn : IN STD_LOGIC;
15 --config
40 ---------------------------------------------------------------------------
16 delta_snapshot : IN STD_LOGIC_VECTOR(delta_snapshot_size-1 DOWNTO 0);
41 --REGISTER CONTROL
17 delta_f2_f1 : IN STD_LOGIC_VECTOR(delta_f2_f1_size-1 DOWNTO 0);
42 reg_run : IN STD_LOGIC;
18 delta_f2_f0 : IN STD_LOGIC_VECTOR(delta_f2_f0_size-1 DOWNTO 0);
43 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
19
44 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
20 --input
45 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
21 coarse_time_0 : IN STD_LOGIC;
46 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
22 data_f0_in_valid : IN STD_LOGIC;
47 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
23 data_f2_in_valid : IN STD_LOGIC;
48 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
24 --output
49 ---------------------------------------------------------------------------
25 start_snapshot_f0 : OUT STD_LOGIC;
50 -- INPUT
26 start_snapshot_f1 : OUT STD_LOGIC;
51 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
27 start_snapshot_f2 : OUT STD_LOGIC
52 data_f0_valid : IN STD_LOGIC;
53 data_f2_valid : IN STD_LOGIC;
54 ---------------------------------------------------------------------------
55 -- OUTPUT
56 start_snapshot_f0 : OUT STD_LOGIC;
57 start_snapshot_f1 : OUT STD_LOGIC;
58 start_snapshot_f2 : OUT STD_LOGIC;
59 wfp_on : OUT STD_LOGIC
28 );
60 );
29
61
30 END lpp_waveform_snapshot_controler;
62 END lpp_waveform_snapshot_controler;
31
63
32 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
64 ARCHITECTURE beh OF lpp_waveform_snapshot_controler IS
65 -----------------------------------------------------------------------------
66 -- WAVEFORM ON/OFF FSM
67 SIGNAL state_on : STD_LOGIC;
68 SIGNAL wfp_on_s : STD_LOGIC;
69 -----------------------------------------------------------------------------
70 -- StartSnapshot Generator for f2, f1 and f0_pre
71 SIGNAL start_snapshot_f0_pre : STD_LOGIC;
72 -- SIGNAL first_decount_s : STD_LOGIC;
73 SIGNAL first_decount : STD_LOGIC;
74 SIGNAL first_init : STD_LOGIC;
33 SIGNAL counter_delta_snapshot : INTEGER;
75 SIGNAL counter_delta_snapshot : INTEGER;
76 -----------------------------------------------------------------------------
77 -- StartSnapshot Generator for f0
34 SIGNAL counter_delta_f0 : INTEGER;
78 SIGNAL counter_delta_f0 : INTEGER;
79 SIGNAL send_start_snapshot_f0 : STD_LOGIC;
80 BEGIN -- beh
81 wfp_on <= wfp_on_s;
35
82
36 SIGNAL coarse_time_0_r : STD_LOGIC;
83 -----------------------------------------------------------------------------
37 SIGNAL start_snapshot_f2_temp : STD_LOGIC;
84 -- WAVEFORM ON/OFF FSM
38 SIGNAL start_snapshot_fothers_temp : STD_LOGIC;
85 -----------------------------------------------------------------------------
39 BEGIN -- beh
86 -- INPUT reg_run
40
87 -- coarse_time
41 PROCESS (clk, rstn)
88 -- reg_start_date
89 -- OUTPUT wfp_on_s
90 -----------------------------------------------------------------------------
91 waveform_on_off_fsm : PROCESS (clk, rstn)
42 BEGIN
92 BEGIN
43 IF rstn = '0' THEN
93 IF rstn = '0' THEN
44 start_snapshot_f0 <= '0';
94 state_on <= '0';
45 start_snapshot_f1 <= '0';
46 start_snapshot_f2 <= '0';
47 counter_delta_snapshot <= 0;
48 counter_delta_f0 <= 0;
49 coarse_time_0_r <= '0';
50 start_snapshot_f2_temp <= '0';
51 start_snapshot_fothers_temp <= '0';
52 ELSIF clk'EVENT AND clk = '1' THEN
95 ELSIF clk'EVENT AND clk = '1' THEN
53 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
96 IF state_on = '1' THEN -- Waveform Picker ON
54 start_snapshot_f2_temp <= '1';
97 state_on <= reg_run;
55 ELSE
98 ELSE -- Waveform Picker OFF
56 start_snapshot_f2_temp <= '0';
99 IF coarse_time = reg_start_date THEN
57 END IF;
100 state_on <= reg_run;
58 -------------------------------------------------------------------------
59 IF counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN
60 start_snapshot_f2 <= '1';
61 ELSE
62 start_snapshot_f2 <= '0';
63 END IF;
64 -------------------------------------------------------------------------
65 coarse_time_0_r <= coarse_time_0;
66 IF coarse_time_0 = NOT coarse_time_0_r THEN --AND coarse_time_0 = '1' THEN
67 IF counter_delta_snapshot = 0 THEN
68 counter_delta_snapshot <= to_integer(UNSIGNED(delta_snapshot));
69 ELSE
70 counter_delta_snapshot <= counter_delta_snapshot - 1;
71 END IF;
101 END IF;
72 END IF;
102 END IF;
103 END IF;
104 END PROCESS waveform_on_off_fsm;
105 wfp_on_s <= state_on;
106 -----------------------------------------------------------------------------
73
107
108 -----------------------------------------------------------------------------
109 -- StartSnapshot Generator for f2, f1 and f0_pre
110 -----------------------------------------------------------------------------
111 -- INPUT wfp_on_s
112 -- reg_delta_snapshot
113 -- reg_delta_f0
114 -- reg_delta_f1
115 -- reg_delta_f2
116 -- data_f2_valid
117 -- OUTPUT start_snapshot_f0_pre
118 -- start_snapshot_f1
119 -- start_snapshot_f2
120 -----------------------------------------------------------------------------
121 --lpp_front_positive_detection_1 : lpp_front_positive_detection
122 -- PORT MAP (
123 -- clk => clk,
124 -- rstn => rstn,
125 -- sin => wfp_on_s,
126 -- sout => first_decount_s);
74
127
75 -------------------------------------------------------------------------
128 Decounter_Cyclic_DeltaSnapshot : PROCESS (clk, rstn)
129 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
130 IF rstn = '0' THEN -- asynchronous reset (active low)
131 counter_delta_snapshot <= 0;
132 first_decount <= '1';
133 first_init <= '1';
134 start_snapshot_f0_pre <= '0';
135 start_snapshot_f1 <= '0';
136 start_snapshot_f2 <= '0';
137 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
138 IF wfp_on_s = '0' THEN
139 counter_delta_snapshot <= 0;
140 first_decount <= '1';
141 first_init <= '1';
142 start_snapshot_f0_pre <= '0';
143 start_snapshot_f1 <= '0';
144 start_snapshot_f2 <= '0';
145 ELSE
146 start_snapshot_f0_pre <= '0';
147 start_snapshot_f1 <= '0';
148 start_snapshot_f2 <= '0';
149
150 IF data_f2_valid = '1' THEN
151 IF first_init = '1' THEN
152 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_f2));
153 first_init <= '0';
154 ELSE
155 IF counter_delta_snapshot > 0 THEN
156 counter_delta_snapshot <= counter_delta_snapshot - 1;
157 ELSE
158 counter_delta_snapshot <= to_integer(UNSIGNED(reg_delta_snapshot));
159 first_decount <= '0';
160 END IF;
161
162 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f0)) THEN
163 IF first_decount = '0' THEN
164 start_snapshot_f0_pre <= '1';
165 END IF;
166 END IF;
167
168 IF counter_delta_snapshot = to_integer(UNSIGNED(reg_delta_f1)) THEN
169 IF first_decount = '0' THEN
170 start_snapshot_f1 <= '1';
171 END IF;
172 END IF;
173
174 IF counter_delta_snapshot = 0 THEN
175 start_snapshot_f2 <= '1';
176 END IF;
177 END IF;
178 END IF;
179 END IF;
180 END IF;
181 END PROCESS Decounter_Cyclic_DeltaSnapshot;
182 -----------------------------------------------------------------------------
76
183
77
184
78
185 -----------------------------------------------------------------------------
79 IF counter_delta_f0 = UNSIGNED(delta_f2_f1) THEN
186 -- StartSnapshot Generator for f0
80 start_snapshot_f1 <= '1';
187 -----------------------------------------------------------------------------
81 ELSE
188 -- INPUT wfp_on_s
82 start_snapshot_f1 <= '0';
189 -- start_snapshot_f0_pre
83 END IF;
190 -- reg_delta_snapshot
84
191 -- reg_delta_f0_2
85 IF counter_delta_f0 = 1 THEN --UNSIGNED(delta_f2_f0) THEN
192 -- data_f0_valid
86 start_snapshot_f0 <= '1';
193 -- OUTPUT start_snapshot_f0
194 -----------------------------------------------------------------------------
195 Decounter_DeltaSnapshot_f0 : PROCESS (clk, rstn)
196 BEGIN -- PROCESS Decounter_Cyclic_DeltaSnapshot
197 IF rstn = '0' THEN -- asynchronous reset (active low)
198 counter_delta_f0 <= 0;
199 start_snapshot_f0 <= '0';
200 send_start_snapshot_f0 <= '0';
201 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
202 start_snapshot_f0 <= '0';
203 IF wfp_on_s = '0' THEN
204 counter_delta_f0 <= 0;
205 send_start_snapshot_f0 <= '1';
87 ELSE
206 ELSE
88 start_snapshot_f0 <= '0';
207 IF start_snapshot_f0_pre = '1' THEN
89 END IF;
208 send_start_snapshot_f0 <= '0';
90
209 counter_delta_f0 <= to_integer(UNSIGNED(reg_delta_f0_2));
91 IF counter_delta_snapshot = UNSIGNED(delta_snapshot)
210 ELSIF data_f0_valid = '1' THEN
92 AND start_snapshot_f2_temp = '0'
211 IF counter_delta_f0 > 0 THEN
93 THEN --
212 send_start_snapshot_f0 <= '0';
94 start_snapshot_fothers_temp <= '1';
213 counter_delta_f0 <= counter_delta_f0 - 1;
95 ELSIF counter_delta_f0 > 0 THEN
214 ELSE
96 start_snapshot_fothers_temp <= '0';
215 IF send_start_snapshot_f0 = '0' THEN
97 END IF;
216 send_start_snapshot_f0 <= '1';
98
217 start_snapshot_f0 <= '1';
99
218 END IF;
100 -------------------------------------------------------------------------
219 END IF;
101 IF (start_snapshot_fothers_temp = '1' OR (counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0')) AND data_f2_in_valid = '1' THEN
102 --counter_delta_snapshot = UNSIGNED(delta_snapshot) AND start_snapshot_f2_temp = '0' THEN --
103 --counter_delta_snapshot = UNSIGNED(delta_snapshot) THEN
104 counter_delta_f0 <= to_integer(UNSIGNED(delta_f2_f0)); --0;
105 ELSE
106 IF (( counter_delta_f0 > 0 ) AND ( data_f0_in_valid = '1' )) THEN --<= UNSIGNED(delta_f2_f0) THEN
107 counter_delta_f0 <= counter_delta_f0 - 1;--counter_delta_f0 + 1;
108 END IF;
220 END IF;
109 END IF;
221 END IF;
110 -------------------------------------------------------------------------
111 END IF;
222 END IF;
112 END PROCESS;
223 END PROCESS Decounter_DeltaSnapshot_f0;
224 -----------------------------------------------------------------------------
113
225
114 END beh; No newline at end of file
226 END beh;
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@@ -1,13 +1,13
1 lpp_waveform_pkg.vhd
2 lpp_waveform.vhd
1 lpp_waveform_burst.vhd
3 lpp_waveform_burst.vhd
2 lpp_waveform_dma_genvalid.vhd
4 lpp_waveform_fifo_withoutLatency.vhd
3 lpp_waveform_dma_selectaddress.vhd
5 lpp_waveform_fifo_latencyCorrection.vhd
4 lpp_waveform_dma_send_Nword.vhd
6 lpp_waveform_fifo.vhd
5 lpp_waveform_dma.vhd
6 lpp_waveform_fifo_arbiter.vhd
7 lpp_waveform_fifo_arbiter.vhd
7 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo_ctrl.vhd
8 lpp_waveform_fifo.vhd
9 lpp_waveform_snapshot.vhd
9 lpp_waveform_pkg.vhd
10 lpp_waveform_snapshot_controler.vhd
10 lpp_waveform_snapshot_controler.vhd
11 lpp_waveform_snapshot.vhd
11 lpp_waveform_genaddress.vhd
12 lpp_waveform_valid_ack.vhd
12 lpp_waveform_dma_genvalid.vhd
13 lpp_waveform.vhd
13 lpp_waveform_fifo_arbiter_reg.vhd
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