##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)
pellion -
r286:8b7f4967459c JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -1,299 +1,479
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -------------------------------------------------------------------------------
21 -------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.numeric_std.ALL;
23 USE IEEE.numeric_std.ALL;
24 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27 USE grlib.stdlib.ALL;
27 USE grlib.stdlib.ALL;
28 LIBRARY techmap;
28 LIBRARY techmap;
29 USE techmap.gencomp.ALL;
29 USE techmap.gencomp.ALL;
30 LIBRARY gaisler;
30 LIBRARY gaisler;
31 USE gaisler.memctrl.ALL;
31 USE gaisler.memctrl.ALL;
32 USE gaisler.leon3.ALL;
32 USE gaisler.leon3.ALL;
33 USE gaisler.uart.ALL;
33 USE gaisler.uart.ALL;
34 USE gaisler.misc.ALL;
34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
35 USE gaisler.spacewire.ALL;
36 LIBRARY esa;
36 LIBRARY esa;
37 USE esa.memoryctrl.ALL;
37 USE esa.memoryctrl.ALL;
38 LIBRARY lpp;
38 LIBRARY lpp;
39 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_memory.ALL;
40 USE lpp.lpp_ad_conv.ALL;
40 USE lpp.lpp_ad_conv.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
41 USE lpp.lpp_lfr_pkg.ALL;
42 USE lpp.iir_filter.ALL;
42 USE lpp.iir_filter.ALL;
43 USE lpp.general_purpose.ALL;
43 USE lpp.general_purpose.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
44 USE lpp.lpp_lfr_time_management.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
45 USE lpp.lpp_leon3_soc_pkg.ALL;
46 USE lpp.lpp_debug_lfr_pkg.ALL;
46 USE lpp.lpp_debug_lfr_pkg.ALL;
47
47
48 ENTITY MINI_LFR_top IS
48 ENTITY MINI_LFR_top IS
49
49
50 PORT (
50 PORT (
51 clk_50 : IN STD_LOGIC;
51 clk_50 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
52 clk_49 : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
53 reset : IN STD_LOGIC;
54 --BPs
54 --BPs
55 BP0 : IN STD_LOGIC;
55 BP0 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
56 BP1 : IN STD_LOGIC;
57 --LEDs
57 --LEDs
58 LED0 : OUT STD_LOGIC;
58 LED0 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
59 LED1 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
60 LED2 : OUT STD_LOGIC;
61 --UARTs
61 --UARTs
62 TXD1 : IN STD_LOGIC;
62 TXD1 : IN STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66
66
67 TXD2 : IN STD_LOGIC;
67 TXD2 : IN STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73
73
74 --EXT CONNECTOR
74 --EXT CONNECTOR
75 IO0 : INOUT STD_LOGIC;
75 IO0 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
76 IO1 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
77 IO2 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
78 IO3 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
79 IO4 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
80 IO5 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
81 IO6 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
82 IO7 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
83 IO8 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
84 IO9 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
85 IO10 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
86 IO11 : INOUT STD_LOGIC;
87
87
88 --SPACE WIRE
88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 SPW_NOM_SIN : IN STD_LOGIC;
91 SPW_NOM_SIN : IN STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 SPW_RED_SIN : IN STD_LOGIC;
95 SPW_RED_SIN : IN STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
96 SPW_RED_DOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
97 SPW_RED_SOUT : OUT STD_LOGIC;
98 -- MINI LFR ADC INPUTS
98 -- MINI LFR ADC INPUTS
99 ADC_nCS : OUT STD_LOGIC;
99 ADC_nCS : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102
102
103 -- SRAM
103 -- SRAM
104 SRAM_nWE : OUT STD_LOGIC;
104 SRAM_nWE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
105 SRAM_CE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
106 SRAM_nOE : OUT STD_LOGIC;
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 );
110 );
111
111
112 END MINI_LFR_top;
112 END MINI_LFR_top;
113
113
114
114
115 ARCHITECTURE beh OF MINI_LFR_top IS
115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 -----------------------------------------------------------------------------
118 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 --
121 --
122 SIGNAL errorn : STD_LOGIC;
122 SIGNAL errorn : STD_LOGIC;
123 -- UART AHB ---------------------------------------------------------------
123 -- UART AHB ---------------------------------------------------------------
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126
126
127 -- UART APB ---------------------------------------------------------------
127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
130 --
131 SIGNAL I00_s : STD_LOGIC;
131 SIGNAL I00_s : STD_LOGIC;
132 --
132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 1;
133 CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
136
136
137 SIGNAL apbi_ext : apb_slv_in_type;
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
143 --
143
144 SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0);
144 -- Spacewire signals
145
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153 -- SIGNAL clkmn : STD_ULOGIC;
154 -- SIGNAL txclk : STD_ULOGIC;
155
156 -- AD Converter RHF1401
157 SIGNAL sample : Samples14v(7 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
159 -- ADC --------------------------------------------------------------------
160 SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
161 SIGNAL ADC_smpclk_sig : STD_LOGIC;
162 SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
163
164 SIGNAL bias_fail_sw_sig : STD_LOGIC;
165 -----------------------------------------------------------------------------
166 SIGNAL sample_val_s : STD_LOGIC;
167 SIGNAL sample_val_s2 : STD_LOGIC;
146 BEGIN -- beh
168 BEGIN -- beh
147
169
148 -----------------------------------------------------------------------------
170 -----------------------------------------------------------------------------
149 -- CLK
171 -- CLK
150 -----------------------------------------------------------------------------
172 -----------------------------------------------------------------------------
151
173
152 PROCESS(clk_50)
174 PROCESS(clk_50)
153 BEGIN
175 BEGIN
154 IF clk_50'EVENT AND clk_50 = '1' THEN
176 IF clk_50'EVENT AND clk_50 = '1' THEN
155 clk_50_s <= NOT clk_50_s;
177 clk_50_s <= NOT clk_50_s;
156 END IF;
178 END IF;
157 END PROCESS;
179 END PROCESS;
158
180
159 PROCESS(clk_50_s)
181 PROCESS(clk_50_s)
160 BEGIN
182 BEGIN
161 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
183 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
162 clk_25 <= NOT clk_25;
184 clk_25 <= NOT clk_25;
163 END IF;
185 END IF;
164 END PROCESS;
186 END PROCESS;
165
187
166 -----------------------------------------------------------------------------
188 -----------------------------------------------------------------------------
167
189
168 PROCESS (clk_25, reset)
190 PROCESS (clk_25, reset)
169 BEGIN -- PROCESS
191 BEGIN -- PROCESS
170 IF reset = '0' THEN -- asynchronous reset (active low)
192 IF reset = '0' THEN -- asynchronous reset (active low)
171 LED0 <= '0';
193 LED0 <= '0';
172 LED1 <= '0';
194 LED1 <= '0';
173 LED2 <= '0';
195 LED2 <= '0';
174 IO1 <= '0';
196 IO0 <= '0';
175 IO2 <= '1';
197 --IO1 <= '0';
198 IO2 <= '1';
176 IO3 <= '0';
199 IO3 <= '0';
177 IO4 <= '0';
200 IO4 <= '0';
178 IO5 <= '0';
201 IO5 <= '0';
179 IO6 <= '0';
202 IO6 <= '0';
180 IO7 <= '0';
203 IO7 <= '0';
181 IO8 <= '0';
204 IO8 <= '0';
182 IO9 <= '0';
205 IO9 <= '0';
183 IO10 <= '0';
206 IO10 <= '0';
184 IO11 <= '0';
207 IO11 <= '0';
185 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
208 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
186 LED0 <= '0';
209 LED0 <= '0';
187 LED1 <= '1';
210 LED1 <= '1';
188 LED2 <= BP0;
211 LED2 <= BP0;
189 IO1 <= '1';
212 IO0 <= '1';
190 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
213 --IO1 <= '1';
191 IO3 <= ADC_SDO(0) OR ADC_SDO(1);
214 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
192 IO4 <= ADC_SDO(2) OR ADC_SDO(1);
215 IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
193 IO5 <= ADC_SDO(3) OR ADC_SDO(4);
216 IO4 <= sample_val;
194 IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
217 IO5 <= ahbi_m_ext.HREADY;
195 IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
218 IO6 <= ahbi_m_ext.HRESP(0);
196 IO8 <= IO_s(8);
219 IO7 <= ahbi_m_ext.HRESP(1);
197 IO9 <= IO_s(9);
220 IO8 <= ahbi_m_ext.HGRANT(2);
198 IO10 <= IO_s(10);
221 IO9 <= ahbo_m_ext(2).HLOCK;
199 IO11 <= IO_s(11);
222 IO10 <= ahbo_m_ext(2).HBUSREQ;
223 IO11 <= sample_val_s2;
200 END IF;
224 END IF;
201 END PROCESS;
225 END PROCESS;
202
226
203 PROCESS (clk_49, reset)
227 --PROCESS (clk_49, reset)
204 BEGIN -- PROCESS
228 --BEGIN -- PROCESS
205 IF reset = '0' THEN -- asynchronous reset (active low)
229 -- IF reset = '0' THEN -- asynchronous reset (active low)
206 I00_s <= '0';
230 -- I00_s <= '0';
207 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
231 -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
208 I00_s <= NOT I00_s;
232 -- I00_s <= NOT I00_s;
209 END IF;
233 -- END IF;
210 END PROCESS;
234 --END PROCESS;
211 IO0 <= I00_s;
235 --IO0 <= I00_s;
212
236
213 --UARTs
237 --UARTs
214 nCTS1 <= '1';
238 nCTS1 <= '1';
215 nCTS2 <= '1';
239 nCTS2 <= '1';
216 nDCD2 <= '1';
240 nDCD2 <= '1';
241
242 --EXT CONNECTOR
217
243
218 --SPACE WIRE
244 --SPACE WIRE
219 SPW_EN <= '0'; -- 0 => off
220
221 SPW_NOM_DOUT <= '0';
222 SPW_NOM_SOUT <= '0';
223 SPW_RED_DOUT <= '0';
224 SPW_RED_SOUT <= '0';
225
226 ADC_nCS <= '0';
227 ADC_CLK <= '0';
228
245
229
246 ADC_nCS <= '0';
230 -----------------------------------------------------------------------------
247 ADC_CLK <= '0';
231 lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst
232 GENERIC MAP (
233 tech => apa3e,
234 hindex => 1,
235 pindex => 5,
236 paddr => 5,
237 pmask => 16#fff#)
238 PORT MAP (
239 HCLK => clk_25,
240 HRESETn => reset ,
241 ahbmi => ahbi_m_ext ,
242 ahbmo => ahbo_m_ext(1),
243 apbi => apbi_ext,
244 apbo => apbo_ext(5),
245 out_ren => IO_s(11),
246 out_send => IO_s(10),
247 out_done => IO_s(9),
248 out_dmaout_okay => IO_s(8)
249 );
250
251 -----------------------------------------------------------------------------
252
248
253 leon3_soc_1: leon3_soc
249
250 leon3_soc_1 : leon3_soc
254 GENERIC MAP (
251 GENERIC MAP (
255 fabtech => apa3e,
252 fabtech => apa3e,
256 memtech => apa3e,
253 memtech => apa3e,
257 padtech => inferred,
254 padtech => inferred,
258 clktech => inferred,
255 clktech => inferred,
259 disas => 0,
256 disas => 0,
260 dbguart => 0,
257 dbguart => 0,
261 pclow => 2,
258 pclow => 2,
262 clk_freq => 25000,
259 clk_freq => 25000,
263 NB_CPU => 1,
260 NB_CPU => 1,
264 ENABLE_FPU => 0,
261 ENABLE_FPU => 0,
265 FPU_NETLIST => 0,
262 FPU_NETLIST => 0,
266 ENABLE_DSU => 1,
263 ENABLE_DSU => 1,
267 ENABLE_AHB_UART => 1,
264 ENABLE_AHB_UART => 1,
268 ENABLE_APB_UART => 1,
265 ENABLE_APB_UART => 1,
269 ENABLE_IRQMP => 1,
266 ENABLE_IRQMP => 1,
270 ENABLE_GPT => 1,
267 ENABLE_GPT => 1,
271 NB_AHB_MASTER => NB_AHB_MASTER,
268 NB_AHB_MASTER => NB_AHB_MASTER,
272 NB_AHB_SLAVE => NB_AHB_SLAVE,
269 NB_AHB_SLAVE => NB_AHB_SLAVE,
273 NB_APB_SLAVE => NB_APB_SLAVE)
270 NB_APB_SLAVE => NB_APB_SLAVE)
274 PORT MAP (
271 PORT MAP (
275 clk => clk_25,
272 clk => clk_25,
276 reset => reset,
273 reset => reset,
277 errorn => errorn,
274 errorn => errorn,
278 ahbrxd => TXD1,
275 ahbrxd => TXD1,
279 ahbtxd => RXD1,
276 ahbtxd => RXD1,
280 urxd1 => TXD2,
277 urxd1 => TXD2,
281 utxd1 => RXD2,
278 utxd1 => RXD2,
282 address => SRAM_A,
279 address => SRAM_A,
283 data => SRAM_DQ,
280 data => SRAM_DQ,
284 nSRAM_BE0 => SRAM_nBE(0),
281 nSRAM_BE0 => SRAM_nBE(0),
285 nSRAM_BE1 => SRAM_nBE(1),
282 nSRAM_BE1 => SRAM_nBE(1),
286 nSRAM_BE2 => SRAM_nBE(2),
283 nSRAM_BE2 => SRAM_nBE(2),
287 nSRAM_BE3 => SRAM_nBE(3),
284 nSRAM_BE3 => SRAM_nBE(3),
288 nSRAM_WE => SRAM_nWE,
285 nSRAM_WE => SRAM_nWE,
289 nSRAM_CE => SRAM_CE,
286 nSRAM_CE => SRAM_CE,
290 nSRAM_OE => SRAM_nOE,
287 nSRAM_OE => SRAM_nOE,
291
288
292 apbi_ext => apbi_ext,
289 apbi_ext => apbi_ext,
293 apbo_ext => apbo_ext,
290 apbo_ext => apbo_ext,
294 ahbi_s_ext => ahbi_s_ext,
291 ahbi_s_ext => ahbi_s_ext,
295 ahbo_s_ext => ahbo_s_ext,
292 ahbo_s_ext => ahbo_s_ext,
296 ahbi_m_ext => ahbi_m_ext,
293 ahbi_m_ext => ahbi_m_ext,
297 ahbo_m_ext => ahbo_m_ext);
294 ahbo_m_ext => ahbo_m_ext);
295
296 -------------------------------------------------------------------------------
297 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
298 -------------------------------------------------------------------------------
299 apb_lfr_time_management_1 : apb_lfr_time_management
300 GENERIC MAP (
301 pindex => 7,
302 paddr => 7,
303 pmask => 16#fff#,
304 pirq => 12)
305 PORT MAP (
306 clk25MHz => clk_25,
307 clk49_152MHz => clk_49,
308 resetn => reset,
309 grspw_tick => swno.tickout,
310 apbi => apbi_ext,
311 apbo => apbo_ext(7),
312 coarse_time => coarse_time,
313 fine_time => fine_time);
314
315 -----------------------------------------------------------------------
316 --- SpaceWire --------------------------------------------------------
317 -----------------------------------------------------------------------
318
319 SPW_EN <= '1';
320
321 spw_clk <= clk_50_s;
322 spw_rxtxclk <= spw_clk;
323 spw_rxclkn <= NOT spw_rxtxclk;
324
325 -- PADS for SPW1
326 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
327 PORT MAP (SPW_NOM_DIN, dtmp(0));
328 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
329 PORT MAP (SPW_NOM_SIN, stmp(0));
330 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
331 PORT MAP (SPW_NOM_DOUT, swno.d(0));
332 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
333 PORT MAP (SPW_NOM_SOUT, swno.s(0));
334 -- PADS FOR SPW2
335 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 PORT MAP (SPW_RED_SIN, dtmp(1));
337 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
338 PORT MAP (SPW_RED_DIN, stmp(1));
339 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_RED_DOUT, swno.d(1));
341 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_RED_SOUT, swno.s(1));
343
344 -- GRSPW PHY
345 --spw1_input: if CFG_SPW_GRSPW = 1 generate
346 spw_inputloop : FOR j IN 0 TO 1 GENERATE
347 spw_phy0 : grspw_phy
348 GENERIC MAP(
349 tech => apa3e,
350 rxclkbuftype => 1,
351 scantest => 0)
352 PORT MAP(
353 rxrst => swno.rxrst,
354 di => dtmp(j),
355 si => stmp(j),
356 rxclko => spw_rxclk(j),
357 do => swni.d(j),
358 ndo => swni.nd(j*5+4 DOWNTO j*5),
359 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
360 END GENERATE spw_inputloop;
361
362 -- SPW core
363 sw0 : grspwm GENERIC MAP(
364 tech => apa3e,
365 hindex => 1,
366 pindex => 5,
367 paddr => 5,
368 pirq => 11,
369 sysfreq => 25000, -- CPU_FREQ
370 rmap => 1,
371 rmapcrc => 1,
372 fifosize1 => 16,
373 fifosize2 => 16,
374 rxclkbuftype => 1,
375 rxunaligned => 0,
376 rmapbufs => 4,
377 ft => 0,
378 netlist => 0,
379 ports => 2,
380 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
381 memtech => apa3e,
382 destkey => 2,
383 spwcore => 1
384 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
385 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
386 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
387 )
388 PORT MAP(reset, clk_25, spw_rxclk(0),
389 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
390 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
391 swni, swno);
392
393 swni.tickin <= '0';
394 swni.rmapen <= '1';
395 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
396 swni.tickinraw <= '0';
397 swni.timein <= (OTHERS => '0');
398 swni.dcrstval <= (OTHERS => '0');
399 swni.timerrstval <= (OTHERS => '0');
400
401 -------------------------------------------------------------------------------
402 -- LFR ------------------------------------------------------------------------
403 -------------------------------------------------------------------------------
404 lpp_lfr_1 : lpp_lfr
405 GENERIC MAP (
406 Mem_use => use_RAM,
407 nb_data_by_buffer_size => 32,
408 nb_word_by_buffer_size => 30,
409 nb_snapshot_param_size => 32,
410 delta_vector_size => 32,
411 delta_vector_size_f0_2 => 7, -- log2(96)
412 pindex => 6,
413 paddr => 6,
414 pmask => 16#fff#,
415 pirq_ms => 6,
416 pirq_wfp => 14,
417 hindex => 2,
418 top_lfr_version => X"00000009")
419 PORT MAP (
420 clk => clk_25,
421 rstn => reset,
422 sample_B => sample(2 DOWNTO 0),
423 sample_E => sample(7 DOWNTO 3),
424 sample_val => sample_val,
425 apbi => apbi_ext,
426 apbo => apbo_ext(6),
427 ahbi => ahbi_m_ext,
428 ahbo => ahbo_m_ext(2),
429 coarse_time => coarse_time,
430 fine_time => fine_time,
431 data_shaping_BW => bias_fail_sw_sig);
432
433 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
434 GENERIC MAP (
435 ChanelCount => 8,
436 ncycle_cnv_high => 79,
437 ncycle_cnv => 500)
438 PORT MAP (
439 cnv_clk => clk_49,
440 cnv_rstn => reset,
441 cnv => ADC_smpclk_sig,
442 clk => clk_25,
443 rstn => reset,
444 ADC_data => ADC_data_sig,
445 ADC_nOE => ADC_OEB_bar_CH_sig,
446 sample => OPEN,
447 sample_val => sample_val);--OPEN );--
448
449 ADC_data_sig <= (OTHERS => '1');
450
451 lpp_debug_lfr_1 : lpp_debug_lfr
452 GENERIC MAP (
453 pindex => 8,
454 paddr => 8,
455 pmask => 16#fff#)
456 PORT MAP (
457 HCLK => clk_25,
458 HRESETn => reset,
459 apbi => apbi_ext,
460 apbo => apbo_ext(8),
461 sample_B => sample(2 DOWNTO 0),
462 sample_E => sample(7 DOWNTO 3));
463
464 PROCESS (clk_25, reset)
465 BEGIN -- PROCESS
466 IF reset = '0' THEN -- asynchronous reset (active low)
467 sample_val_s2 <= '0';
468 sample_val_s <= '0';
469 --sample_val <= '0';
470 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
471 sample_val_s <= IO1;
472 sample_val_s2 <= sample_val_s;
473 --sample_val <= (NOT sample_val_s2) AND sample_val_s;
474 END IF;
475 END PROCESS;
476
477
298
478
299 END beh;
479 END beh;
Show file before | Show file after | Hide comments
@@ -1,50 +1,51
1 VHDLIB=../..
1 VHDLIB=../..
2 SCRIPTSDIR=$(VHDLIB)/scripts/
2 SCRIPTSDIR=$(VHDLIB)/scripts/
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
3 GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
4 TOP=MINI_LFR_top
4 TOP=MINI_LFR_top
5 BOARD=MINI-LFR
5 BOARD=MINI-LFR
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
6 include $(VHDLIB)/boards/$(BOARD)/Makefile.inc
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
7 DEVICE=$(PART)-$(PACKAGE)$(SPEED)
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
8 UCF=$(VHDLIB)/boards/$(BOARD)/$(TOP).ucf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
9 QSF=$(VHDLIB)/boards/$(BOARD)/$(TOP).qsf
10 EFFORT=high
10 EFFORT=high
11 XSTOPT=
11 XSTOPT=
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
12 SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
13 VHDLSYNFILES= MINI_LFR_top.vhd
13 VHDLSYNFILES= MINI_LFR_top.vhd
14
14
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
15 PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
16 BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut
17 CLEAN=soft-clean
17 CLEAN=soft-clean
18
18
19 TECHLIBS = proasic3e
19 TECHLIBS = proasic3e
20
20
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
22 tmtc openchip hynix ihp gleichmann micron usbhc
23
23
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
26 ./amba_lcd_16x2_ctrlr \
26 ./amba_lcd_16x2_ctrlr \
27 ./general_purpose/lpp_AMR \
27 ./general_purpose/lpp_AMR \
28 ./general_purpose/lpp_balise \
28 ./general_purpose/lpp_balise \
29 ./general_purpose/lpp_delay \
29 ./general_purpose/lpp_delay \
30 ./dsp/lpp_fft \
30 ./dsp/lpp_fft \
31 ./lpp_bootloader \
31 ./lpp_bootloader \
32 ./lpp_cna \
32 ./lpp_cna \
33 ./lpp_demux \
33 ./lpp_demux \
34 ./lpp_matrix \
34 ./lpp_matrix \
35 ./lpp_uart \
35 ./lpp_uart \
36 ./lpp_usb \
36 ./lpp_usb \
37 ./lpp_Header \
37 ./lpp_Header \
38 ./lpp_sim/CY7C1061DV33 \
38
39
39 FILESKIP =lpp_lfr_ms.vhd \
40 FILESKIP =lpp_lfr_ms.vhd \
40 i2cmst.vhd \
41 i2cmst.vhd \
41 APB_MULTI_DIODE.vhd \
42 APB_MULTI_DIODE.vhd \
42 APB_SIMPLE_DIODE.vhd \
43 APB_SIMPLE_DIODE.vhd \
43 Top_MatrixSpec.vhd \
44 Top_MatrixSpec.vhd \
44 APB_FFT.vhd
45 APB_FFT.vhd
45
46
46 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/bin/Makefile
47 include $(GRLIB)/software/leon3/Makefile
48 include $(GRLIB)/software/leon3/Makefile
48
49
49 ################## project specific targets ##########################
50 ################## project specific targets ##########################
50
51
Show file before | Show file after | Hide comments
@@ -1,25 +1,26
1 ./amba_lcd_16x2_ctrlr
1 ./amba_lcd_16x2_ctrlr
2 ./general_purpose
2 ./general_purpose
3 ./general_purpose/lpp_AMR
3 ./general_purpose/lpp_AMR
4 ./general_purpose/lpp_balise
4 ./general_purpose/lpp_balise
5 ./general_purpose/lpp_delay
5 ./general_purpose/lpp_delay
6 ./lpp_amba
6 ./lpp_amba
7 ./dsp/iir_filter
7 ./dsp/iir_filter
8 ./dsp/lpp_downsampling
8 ./dsp/lpp_downsampling
9 ./dsp/lpp_fft
9 ./dsp/lpp_fft
10 ./lfr_time_management
10 ./lfr_time_management
11 ./lpp_ad_Conv
11 ./lpp_ad_Conv
12 ./lpp_bootloader
12 ./lpp_bootloader
13 ./lpp_cna
13 ./lpp_cna
14 ./lpp_demux
14 ./lpp_demux
15 ./lpp_Header
15 ./lpp_Header
16 ./lpp_matrix
16 ./lpp_matrix
17 ./lpp_memory
17 ./lpp_memory
18 ./lpp_dma
18 ./lpp_dma
19 ./lpp_uart
19 ./lpp_uart
20 ./lpp_usb
20 ./lpp_usb
21 ./lpp_waveform
21 ./lpp_waveform
22 ./lpp_top_lfr
22 ./lpp_top_lfr
23 ./lpp_Header
23 ./lpp_Header
24 ./lpp_leon3_soc
24 ./lpp_leon3_soc
25 ./lpp_debug_lfr
25 ./lpp_debug_lfr
26 ./lpp_sim/CY7C1061DV33
Show file before | Show file after | Hide comments
@@ -1,84 +1,81
1 ----------------------------------------------------------------------------------
1 ----------------------------------------------------------------------------------
2 -- Company:
2 -- Company:
3 -- Engineer:
3 -- Engineer:
4 --
4 --
5 -- Create Date: 13:04:01 07/02/2012
5 -- Create Date: 13:04:01 07/02/2012
6 -- Design Name:
6 -- Design Name:
7 -- Module Name: lpp_lfr_time_management - Behavioral
7 -- Module Name: lpp_lfr_time_management - Behavioral
8 -- Project Name:
8 -- Project Name:
9 -- Target Devices:
9 -- Target Devices:
10 -- Tool versions:
10 -- Tool versions:
11 -- Description:
11 -- Description:
12 --
12 --
13 -- Dependencies:
13 -- Dependencies:
14 --
14 --
15 -- Revision:
15 -- Revision:
16 -- Revision 0.01 - File Created
16 -- Revision 0.01 - File Created
17 -- Additional Comments:
17 -- Additional Comments:
18 --
18 --
19 ----------------------------------------------------------------------------------
19 ----------------------------------------------------------------------------------
20 LIBRARY IEEE;
20 LIBRARY IEEE;
21 USE IEEE.STD_LOGIC_1164.ALL;
21 USE IEEE.STD_LOGIC_1164.ALL;
22 LIBRARY grlib;
22 LIBRARY grlib;
23 USE grlib.amba.ALL;
23 USE grlib.amba.ALL;
24 USE grlib.stdlib.ALL;
24 USE grlib.stdlib.ALL;
25 USE grlib.devices.ALL;
25 USE grlib.devices.ALL;
26
26
27 PACKAGE lpp_lfr_time_management IS
27 PACKAGE lpp_lfr_time_management IS
28
28
29 --***************************
29 --***************************
30 -- APB_LFR_TIME_MANAGEMENT
30 -- APB_LFR_TIME_MANAGEMENT
31
31
32 COMPONENT apb_lfr_time_management IS
32 COMPONENT apb_lfr_time_management IS
33
34 GENERIC(
33 GENERIC(
35 pindex : INTEGER := 0; --! APB slave index
34 pindex : INTEGER := 0; --! APB slave index
36 paddr : INTEGER := 0; --! ADDR field of the APB BAR
35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 pirq : INTEGER := 0
37 pirq : INTEGER := 0
39 );
38 );
40
41 PORT (
39 PORT (
42 clk25MHz : IN STD_LOGIC; --! Clock
40 clk25MHz : IN STD_LOGIC; --! Clock
43 clk49_152MHz : IN STD_LOGIC; --! secondary clock
41 clk49_152MHz : IN STD_LOGIC; --! secondary clock
44 resetn : IN STD_LOGIC; --! Reset
42 resetn : IN STD_LOGIC; --! Reset
45 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
43 grspw_tick : IN STD_LOGIC; --! grspw signal asserted when a valid time-code is received
46 apbi : IN apb_slv_in_type; --! APB slave input signals
44 apbi : IN apb_slv_in_type; --! APB slave input signals
47 apbo : OUT apb_slv_out_type; --! APB slave output signals
45 apbo : OUT apb_slv_out_type; --! APB slave output signals
48 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
49 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
50 );
48 );
51
52 END COMPONENT;
49 END COMPONENT;
53
50
54 COMPONENT lfr_time_management
51 COMPONENT lfr_time_management
55 GENERIC (
52 GENERIC (
56 nb_time_code_missing_limit : INTEGER);
53 nb_time_code_missing_limit : INTEGER);
57 PORT (
54 PORT (
58 clk : IN STD_LOGIC;
55 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
56 rstn : IN STD_LOGIC;
60 new_timecode : IN STD_LOGIC;
57 new_timecode : IN STD_LOGIC;
61 new_coarsetime : IN STD_LOGIC;
58 new_coarsetime : IN STD_LOGIC;
62 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
59 coarsetime_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
63 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
60 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
64 fine_time_new : OUT STD_LOGIC;
61 fine_time_new : OUT STD_LOGIC;
65 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
62 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
66 coarse_time_new : OUT STD_LOGIC
63 coarse_time_new : OUT STD_LOGIC
67 );
64 );
68 END COMPONENT;
65 END COMPONENT;
69
66
70 COMPONENT lpp_counter
67 COMPONENT lpp_counter
71 GENERIC (
68 GENERIC (
72 nb_wait_period : INTEGER;
69 nb_wait_period : INTEGER;
73 nb_bit_of_data : INTEGER);
70 nb_bit_of_data : INTEGER);
74 PORT (
71 PORT (
75 clk : IN STD_LOGIC;
72 clk : IN STD_LOGIC;
76 rstn : IN STD_LOGIC;
73 rstn : IN STD_LOGIC;
77 clear : IN STD_LOGIC;
74 clear : IN STD_LOGIC;
78 full : OUT STD_LOGIC;
75 full : OUT STD_LOGIC;
79 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
76 data : OUT STD_LOGIC_VECTOR(nb_bit_of_data-1 DOWNTO 0);
80 new_data : OUT STD_LOGIC );
77 new_data : OUT STD_LOGIC );
81 END COMPONENT;
78 END COMPONENT;
82
79
83 END lpp_lfr_time_management;
80 END lpp_lfr_time_management;
84
81
Show file before | Show file after | Hide comments
@@ -1,43 +1,44
1
1
2 --=================================================================================
2 --=================================================================================
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
3 --THIS FILE IS GENERATED BY A SCRIPT, DON'T TRY TO EDIT
4 --
4 --
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
5 --TAKE A LOOK AT VHD_LIB/APB_DEVICES FOLDER TO ADD A DEVICE ID OR VENDOR ID
6 --=================================================================================
6 --=================================================================================
7
7
8
8
9 LIBRARY ieee;
9 LIBRARY ieee;
10 USE ieee.std_logic_1164.ALL;
10 USE ieee.std_logic_1164.ALL;
11 LIBRARY grlib;
11 LIBRARY grlib;
12 USE grlib.amba.ALL;
12 USE grlib.amba.ALL;
13 USE std.textio.ALL;
13 USE std.textio.ALL;
14
14
15
15
16 PACKAGE apb_devices_list IS
16 PACKAGE apb_devices_list IS
17
17
18
18
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
19 CONSTANT VENDOR_LPP : amba_vendor_type := 16#19#;
20
20
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
21 CONSTANT ROCKET_TM : amba_device_type := 16#1#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
22 CONSTANT otherCore : amba_device_type := 16#2#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
23 CONSTANT LPP_SIMPLE_DIODE : amba_device_type := 16#3#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
24 CONSTANT LPP_MULTI_DIODE : amba_device_type := 16#4#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
25 CONSTANT LPP_LCD_CTRLR : amba_device_type := 16#5#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
26 CONSTANT LPP_UART : amba_device_type := 16#6#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
27 CONSTANT LPP_CNA : amba_device_type := 16#7#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
28 CONSTANT LPP_APB_ADC : amba_device_type := 16#8#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
29 CONSTANT LPP_CHENILLARD : amba_device_type := 16#9#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
30 CONSTANT LPP_IIR_CEL_FILTER : amba_device_type := 16#10#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
31 CONSTANT LPP_FIFO_PID : amba_device_type := 16#11#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
32 CONSTANT LPP_FFT : amba_device_type := 16#12#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
33 CONSTANT LPP_MATRIX : amba_device_type := 16#13#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
34 CONSTANT LPP_DELAY : amba_device_type := 16#14#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
35 CONSTANT LPP_USB : amba_device_type := 16#15#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
36 CONSTANT LPP_BALISE : amba_device_type := 16#16#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
37 CONSTANT LPP_DMA_TYPE : amba_device_type := 16#17#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
38 CONSTANT LPP_BOOTLOADER_TYPE : amba_device_type := 16#18#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40
40
41 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
41 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
42 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
42
43
43 END;
44 END;
Show file before | Show file after | Hide comments
@@ -1,51 +1,71
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
26 USE grlib.amba.ALL;
27
27 LIBRARY lpp;
28 PACKAGE lpp_debug_lfr_pkg IS
28 USE lpp.lpp_lfr_pkg.ALL;
29
29 USE lpp.lpp_ad_conv.ALL;
30 COMPONENT lpp_debug_dma_singleOrBurst
30
31 GENERIC (
31 PACKAGE lpp_debug_lfr_pkg IS
32 tech : INTEGER;
32
33 hindex : INTEGER;
33 COMPONENT lpp_debug_dma_singleOrBurst
34 pindex : INTEGER;
34 GENERIC (
35 paddr : INTEGER;
35 tech : INTEGER;
36 pmask : INTEGER);
36 hindex : INTEGER;
37 PORT (
37 pindex : INTEGER;
38 HCLK : IN STD_ULOGIC;
38 paddr : INTEGER;
39 HRESETn : IN STD_ULOGIC;
39 pmask : INTEGER);
40 ahbmi : IN AHB_Mst_In_Type;
40 PORT (
41 ahbmo : OUT AHB_Mst_Out_Type;
41 HCLK : IN STD_ULOGIC;
42 apbi : IN apb_slv_in_type;
42 HRESETn : IN STD_ULOGIC;
43 apbo : OUT apb_slv_out_type;
43 ahbmi : IN AHB_Mst_In_Type;
44 out_ren : OUT STD_LOGIC;
44 ahbmo : OUT AHB_Mst_Out_Type;
45 out_send : OUT STD_LOGIC;
45 apbi : IN apb_slv_in_type;
46 out_done : OUT STD_LOGIC;
46 apbo : OUT apb_slv_out_type;
47 out_dmaout_okay : OUT STD_LOGIC
47 out_ren : OUT STD_LOGIC;
48 );
48 out_send : OUT STD_LOGIC;
49 END COMPONENT;
49 out_done : OUT STD_LOGIC;
50
50 out_dmaout_okay : OUT STD_LOGIC
51 END;
51 );
52 END COMPONENT;
53
54 COMPONENT lpp_debug_lfr
55 GENERIC (
56 tech : INTEGER;
57 hindex : INTEGER;
58 pindex : INTEGER;
59 paddr : INTEGER;
60 pmask : INTEGER);
61 PORT (
62 HCLK : IN STD_ULOGIC;
63 HRESETn : IN STD_ULOGIC;
64 apbi : IN apb_slv_in_type;
65 apbo : OUT apb_slv_out_type;
66 sample_B : OUT Samples14v(2 DOWNTO 0);
67 sample_E : OUT Samples14v(4 DOWNTO 0));
68 END COMPONENT;
69
70
71 END; No newline at end of file
Show file before | Show file after | Hide comments
@@ -1,2 +1,3
1 lpp_debug_lfr_pkg.vhd
1 lpp_debug_lfr_pkg.vhd
2 lpp_debug_dma_singleOrBurst.vhd
2 lpp_debug_dma_singleOrBurst.vhd
3 lpp_debug_lfr.vhd
Show file before | Show file after | Hide comments
@@ -1,190 +1,195
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23
23
24 LIBRARY ieee;
24 LIBRARY ieee;
25 USE ieee.std_logic_1164.ALL;
25 USE ieee.std_logic_1164.ALL;
26 USE ieee.numeric_std.ALL;
26 USE ieee.numeric_std.ALL;
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32 LIBRARY lpp;
32 LIBRARY lpp;
33 USE lpp.lpp_amba.ALL;
33 USE lpp.lpp_amba.ALL;
34 USE lpp.apb_devices_list.ALL;
34 USE lpp.apb_devices_list.ALL;
35 USE lpp.lpp_memory.ALL;
35 USE lpp.lpp_memory.ALL;
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_dma_send_16word IS
39 ENTITY lpp_dma_send_16word IS
40 PORT (
40 PORT (
41 -- AMBA AHB system signals
41 -- AMBA AHB system signals
42 HCLK : IN STD_ULOGIC;
42 HCLK : IN STD_ULOGIC;
43 HRESETn : IN STD_ULOGIC;
43 HRESETn : IN STD_ULOGIC;
44
44
45 -- DMA
45 -- DMA
46 DMAIn : OUT DMA_In_Type;
46 DMAIn : OUT DMA_In_Type;
47 DMAOut : IN DMA_OUt_Type;
47 DMAOut : IN DMA_OUt_Type;
48
48
49 --
49 --
50 send : IN STD_LOGIC;
50 send : IN STD_LOGIC;
51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
53 ren : OUT STD_LOGIC;
53 ren : OUT STD_LOGIC;
54 --
54 --
55 send_ok : OUT STD_LOGIC;
55 send_ok : OUT STD_LOGIC;
56 send_ko : OUT STD_LOGIC
56 send_ko : OUT STD_LOGIC
57
57
58 );
58 );
59 END lpp_dma_send_16word;
59 END lpp_dma_send_16word;
60
60
61 ARCHITECTURE beh OF lpp_dma_send_16word IS
61 ARCHITECTURE beh OF lpp_dma_send_16word IS
62
62
63 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
63 TYPE state_fsm_send_16word IS (IDLE, REQUEST_BUS, SEND_DATA, ERROR0, ERROR1, WAIT_LAST_READY);
64 SIGNAL state : state_fsm_send_16word;
64 SIGNAL state : state_fsm_send_16word;
65
65
66 SIGNAL data_counter : INTEGER;
66 SIGNAL data_counter : INTEGER;
67 SIGNAL grant_counter : INTEGER;
67 SIGNAL grant_counter : INTEGER;
68
68
69 BEGIN -- beh
69 BEGIN -- beh
70
70
71 DMAIn.Beat <= HINCR16;
71 DMAIn.Beat <= HINCR16;
72 DMAIn.Size <= HSIZE32;
72 DMAIn.Size <= HSIZE32;
73
73
74 PROCESS (HCLK, HRESETn)
74 PROCESS (HCLK, HRESETn)
75 BEGIN -- PROCESS
75 BEGIN -- PROCESS
76 IF HRESETn = '0' THEN -- asynchronous reset (active low)
76 IF HRESETn = '0' THEN -- asynchronous reset (active low)
77 state <= IDLE;
77 state <= IDLE;
78 send_ok <= '0';
78 send_ok <= '0';
79 send_ko <= '0';
79 send_ko <= '0';
80
80
81 DMAIn.Reset <= '1';
81 DMAIn.Reset <= '1';
82 DMAIn.Address <= (OTHERS => '0');
82 DMAIn.Address <= (OTHERS => '0');
83 DMAIn.Request <= '0';
83 DMAIn.Request <= '0';
84 DMAIn.Store <= '0';
84 DMAIn.Store <= '0';
85 DMAIn.Burst <= '1';
85 DMAIn.Burst <= '1';
86 DMAIn.Lock <= '0';
86 DMAIn.Lock <= '0';
87 data_counter <= 0;
87 data_counter <= 0;
88 grant_counter <= 0;
88 grant_counter <= 0;
89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
89 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
90
90
91 DMAIn.Reset <= '0';
91 DMAIn.Reset <= '0';
92
92
93 CASE state IS
93 CASE state IS
94 WHEN IDLE =>
94 WHEN IDLE =>
95 DMAIn.Store <= '1';
95 DMAIn.Store <= '1';
96 DMAIn.Request <= '0';
96 DMAIn.Request <= '0';
97 send_ok <= '0';
97 send_ok <= '0';
98 send_ko <= '0';
98 send_ko <= '0';
99 DMAIn.Address <= address;
99 DMAIn.Address <= address;
100 data_counter <= 0;
100 data_counter <= 0;
101 DMAIn.Lock <= '0'; -- FIX test
101 DMAIn.Lock <= '0'; -- FIX test
102 IF send = '1' THEN
102 IF send = '1' THEN
103 state <= REQUEST_BUS;
103 state <= REQUEST_BUS;
104 DMAIn.Request <= '1';
104 DMAIn.Request <= '1';
105 DMAIn.Lock <= '1'; -- FIX test
105 DMAIn.Lock <= '1'; -- FIX test
106 DMAIn.Store <= '1';
106 DMAIn.Store <= '1';
107 END IF;
107 END IF;
108 WHEN REQUEST_BUS =>
108 WHEN REQUEST_BUS =>
109 IF DMAOut.Grant = '1' THEN
109 IF DMAOut.Grant = '1' THEN
110 data_counter <= 1;
110 data_counter <= 1;
111 grant_counter <= 1;
111 grant_counter <= 1;
112 state <= SEND_DATA;
112 state <= SEND_DATA;
113 END IF;
113 END IF;
114 WHEN SEND_DATA =>
114 WHEN SEND_DATA =>
115
115
116 IF DMAOut.Fault = '1' THEN
116 IF DMAOut.Fault = '1' THEN
117 DMAIn.Reset <= '0';
117 DMAIn.Reset <= '0';
118 DMAIn.Address <= (OTHERS => '0');
118 DMAIn.Address <= (OTHERS => '0');
119 DMAIn.Request <= '0';
119 DMAIn.Request <= '0';
120 DMAIn.Store <= '0';
120 DMAIn.Store <= '0';
121 DMAIn.Burst <= '0';
121 DMAIn.Burst <= '0';
122 state <= ERROR0;
122 state <= ERROR0;
123 ELSE
123 ELSE
124
124
125 IF DMAOut.Grant = '1' THEN
125 IF DMAOut.Grant = '1' THEN
126 IF grant_counter = 15 THEN
126 IF grant_counter = 15 THEN
127 DMAIn.Reset <= '0';
127 DMAIn.Reset <= '0';
128 DMAIn.Request <= '0';
128 DMAIn.Request <= '0';
129 DMAIn.Store <= '0';
129 DMAIn.Store <= '0';
130 DMAIn.Burst <= '0';
130 DMAIn.Burst <= '0';
131 ELSE
131 ELSE
132 grant_counter <= grant_counter+1;
132 grant_counter <= grant_counter+1;
133 END IF;
133 END IF;
134 END IF;
134 END IF;
135
135
136 IF DMAOut.OKAY = '1' THEN
136 IF DMAOut.OKAY = '1' THEN
137 IF data_counter = 15 THEN
137 IF data_counter = 15 THEN
138 DMAIn.Address <= (OTHERS => '0');
138 DMAIn.Address <= (OTHERS => '0');
139 state <= WAIT_LAST_READY;
139 state <= WAIT_LAST_READY;
140 ELSE
140 ELSE
141 data_counter <= data_counter + 1;
141 data_counter <= data_counter + 1;
142 END IF;
142 END IF;
143 END IF;
143 END IF;
144 END IF;
144 END IF;
145
145
146
146
147 WHEN WAIT_LAST_READY =>
147 WHEN WAIT_LAST_READY =>
148 IF DMAOut.Ready = '1' THEN
148 IF DMAOut.Ready = '1' THEN
149 IF grant_counter = 15 THEN
149 IF grant_counter = 15 THEN
150 state <= IDLE;
150 state <= IDLE;
151 send_ok <= '1';
151 send_ok <= '1';
152 send_ko <= '0';
152 send_ko <= '0';
153 ELSE
153 ELSE
154 state <= ERROR0;
154 state <= ERROR0;
155 END IF;
155 END IF;
156 END IF;
156 END IF;
157
157
158 WHEN ERROR0 =>
158 WHEN ERROR0 =>
159 state <= ERROR1;
159 state <= ERROR1;
160 WHEN ERROR1 =>
160 WHEN ERROR1 =>
161 send_ok <= '0';
161 send_ok <= '0';
162 send_ko <= '1';
162 send_ko <= '1';
163 state <= IDLE;
163 state <= IDLE;
164 WHEN OTHERS => NULL;
164 WHEN OTHERS => NULL;
165 END CASE;
165 END CASE;
166 END IF;
166 END IF;
167 END PROCESS;
167 END PROCESS;
168
168
169 DMAIn.Data <= data;
169 DMAIn.Data <= data;
170
171 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 '1';
170
173
171 ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
174 -- \/ JC - 20/01/2014 \/
172 '1';
175 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 -- '1';
177 -- /\ JC - 20/01/2014 /\
173
178
174 -- \/ JC - 11/12/2013 \/
179 -- \/ JC - 11/12/2013 \/
175 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
180 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
176 -- '1';
181 -- '1';
177 -- /\ JC - 11/12/2013 /\
182 -- /\ JC - 11/12/2013 /\
178
183
179 -- \/ JC - 10/12/2013 \/
184 -- \/ JC - 10/12/2013 \/
180 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
185 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
181 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
186 -- '0' WHEN state = REQUEST_BUS AND DMAOut.Grant = '1' ELSE
182 -- '1';
187 -- '1';
183 -- /\ JC - 10/12/2013 /\
188 -- /\ JC - 10/12/2013 /\
184
189
185 -- \/ JC - 09/12/2013 \/
190 -- \/ JC - 09/12/2013 \/
186 --ren <= '0' WHEN state = SEND_DATA ELSE
191 --ren <= '0' WHEN state = SEND_DATA ELSE
187 -- '1';
192 -- '1';
188 -- /\ JC - 09/12/2013 /\
193 -- /\ JC - 09/12/2013 /\
189
194
190 END beh;
195 END beh;
Show file before | Show file after | Hide comments
@@ -1,185 +1,191
1
1
2 ------------------------------------------------------------------------------
2 ------------------------------------------------------------------------------
3 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- This file is a part of the LPP VHDL IP LIBRARY
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
5 --
5 --
6 -- This program is free software; you can redistribute it and/or modify
6 -- This program is free software; you can redistribute it and/or modify
7 -- it under the terms of the GNU General Public License as published by
7 -- it under the terms of the GNU General Public License as published by
8 -- the Free Software Foundation; either version 3 of the License, or
8 -- the Free Software Foundation; either version 3 of the License, or
9 -- (at your option) any later version.
9 -- (at your option) any later version.
10 --
10 --
11 -- This program is distributed in the hope that it will be useful,
11 -- This program is distributed in the hope that it will be useful,
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 -- GNU General Public License for more details.
14 -- GNU General Public License for more details.
15 --
15 --
16 -- You should have received a copy of the GNU General Public License
16 -- You should have received a copy of the GNU General Public License
17 -- along with this program; if not, write to the Free Software
17 -- along with this program; if not, write to the Free Software
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
19 -------------------------------------------------------------------------------
19 -------------------------------------------------------------------------------
20 -- Author : Jean-christophe Pellion
20 -- Author : Jean-christophe Pellion
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
22 -- jean-christophe.pellion@easii-ic.com
22 -- jean-christophe.pellion@easii-ic.com
23 -------------------------------------------------------------------------------
23 -------------------------------------------------------------------------------
24 -- 1.0 - initial version
24 -- 1.0 - initial version
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
25 -- 1.1 - (01/11/2013) FIX boundary error (1kB address should not be crossed by BURSTS)
26 -------------------------------------------------------------------------------
26 -------------------------------------------------------------------------------
27 LIBRARY ieee;
27 LIBRARY ieee;
28 USE ieee.std_logic_1164.ALL;
28 USE ieee.std_logic_1164.ALL;
29 USE ieee.numeric_std.ALL;
29 USE ieee.numeric_std.ALL;
30 LIBRARY grlib;
30 LIBRARY grlib;
31 USE grlib.amba.ALL;
31 USE grlib.amba.ALL;
32 USE grlib.stdlib.ALL;
32 USE grlib.stdlib.ALL;
33 USE grlib.devices.ALL;
33 USE grlib.devices.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
34 USE GRLIB.DMA2AHB_Package.ALL;
35 LIBRARY lpp;
35 LIBRARY lpp;
36 USE lpp.lpp_amba.ALL;
36 USE lpp.lpp_amba.ALL;
37 USE lpp.apb_devices_list.ALL;
37 USE lpp.apb_devices_list.ALL;
38 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_memory.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
39 USE lpp.lpp_dma_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
40 USE lpp.lpp_waveform_pkg.ALL;
41 LIBRARY techmap;
41 LIBRARY techmap;
42 USE techmap.gencomp.ALL;
42 USE techmap.gencomp.ALL;
43
43
44
44
45 ENTITY lpp_dma_singleOrBurst IS
45 ENTITY lpp_dma_singleOrBurst IS
46 GENERIC (
46 GENERIC (
47 tech : INTEGER := inferred;
47 tech : INTEGER := inferred;
48 hindex : INTEGER := 2
48 hindex : INTEGER := 2
49 );
49 );
50 PORT (
50 PORT (
51 -- AMBA AHB system signals
51 -- AMBA AHB system signals
52 HCLK : IN STD_ULOGIC;
52 HCLK : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
53 HRESETn : IN STD_ULOGIC;
54 --
54 --
55 run : IN STD_LOGIC;
55 run : IN STD_LOGIC;
56 -- AMBA AHB Master Interface
56 -- AMBA AHB Master Interface
57 AHB_Master_In : IN AHB_Mst_In_Type;
57 AHB_Master_In : IN AHB_Mst_In_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
58 AHB_Master_Out : OUT AHB_Mst_Out_Type;
59 --
59 --
60 send : IN STD_LOGIC;
60 send : IN STD_LOGIC;
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
61 valid_burst : IN STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
62 done : OUT STD_LOGIC;
62 done : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
63 ren : OUT STD_LOGIC;
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
64 address : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
65 data : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
66 --
66 --
67 debug_dmaout_okay : OUT STD_LOGIC
67 debug_dmaout_okay : OUT STD_LOGIC
68
68
69 );
69 );
70 END;
70 END;
71
71
72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
72 ARCHITECTURE Behavioral OF lpp_dma_singleOrBurst IS
73 -----------------------------------------------------------------------------
73 -----------------------------------------------------------------------------
74 SIGNAL DMAIn : DMA_In_Type;
74 SIGNAL DMAIn : DMA_In_Type;
75 SIGNAL DMAOut : DMA_OUt_Type;
75 SIGNAL DMAOut : DMA_OUt_Type;
76 -----------------------------------------------------------------------------
76 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
77 -----------------------------------------------------------------------------
78 -- CONTROL
78 -- CONTROL
79 SIGNAL single_send : STD_LOGIC;
79 SIGNAL single_send : STD_LOGIC;
80 SIGNAL burst_send : STD_LOGIC;
80 SIGNAL burst_send : STD_LOGIC;
81
81
82 -----------------------------------------------------------------------------
82 -----------------------------------------------------------------------------
83 -- SEND SINGLE MODULE
83 -- SEND SINGLE MODULE
84 SIGNAL single_dmai : DMA_In_Type;
84 SIGNAL single_dmai : DMA_In_Type;
85
85
86 SIGNAL single_send_ok : STD_LOGIC;
86 SIGNAL single_send_ok : STD_LOGIC;
87 SIGNAL single_send_ko : STD_LOGIC;
87 SIGNAL single_send_ko : STD_LOGIC;
88 SIGNAL single_ren : STD_LOGIC;
88 SIGNAL single_ren : STD_LOGIC;
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 -- SEND SINGLE MODULE
90 -- SEND SINGLE MODULE
91 SIGNAL burst_dmai : DMA_In_Type;
91 SIGNAL burst_dmai : DMA_In_Type;
92
92
93 SIGNAL burst_send_ok : STD_LOGIC;
93 SIGNAL burst_send_ok : STD_LOGIC;
94 SIGNAL burst_send_ko : STD_LOGIC;
94 SIGNAL burst_send_ko : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 BEGIN
98 BEGIN
99
99
100 debug_dmaout_okay <= DMAOut.OKAY;
100 debug_dmaout_okay <= DMAOut.OKAY;
101
101
102
102
103 -----------------------------------------------------------------------------
103 -----------------------------------------------------------------------------
104 -- DMA to AHB interface
104 -- DMA to AHB interface
105 DMA2AHB_1 : DMA2AHB
105 DMA2AHB_1 : DMA2AHB
106 GENERIC MAP (
106 GENERIC MAP (
107 hindex => hindex,
107 hindex => hindex,
108 vendorid => VENDOR_LPP,
108 vendorid => VENDOR_LPP,
109 deviceid => 10,
109 deviceid => 10,
110 version => 0,
110 version => 0,
111 syncrst => 1,
111 syncrst => 1,
112 boundary => 1) -- FIX 11/01/2013
112 boundary => 1) -- FIX 11/01/2013
113 PORT MAP (
113 PORT MAP (
114 HCLK => HCLK,
114 HCLK => HCLK,
115 HRESETn => HRESETn,
115 HRESETn => HRESETn,
116 DMAIn => DMAIn,
116 DMAIn => DMAIn,
117 DMAOut => DMAOut,
117 DMAOut => DMAOut,
118
118
119 AHBIn => AHB_Master_In,
119 AHBIn => AHB_Master_In,
120 AHBOut => AHB_Master_Out);
120 AHBOut => AHB_Master_Out);
121 -----------------------------------------------------------------------------
121 -----------------------------------------------------------------------------
122
122
123 -----------------------------------------------------------------------------
123 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
125 -- LE PROBLEME EST LA !!!!!
125 -- LE PROBLEME EST LA !!!!!
126 -----------------------------------------------------------------------------
126 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
127 -----------------------------------------------------------------------------
128 -- C'est le signal valid_burst qui n'est pas assez long.
128 -- C'est le signal valid_burst qui n'est pas assez long.
129 -----------------------------------------------------------------------------
129 -----------------------------------------------------------------------------
130 single_send <= send WHEN valid_burst = '0' ELSE '0';
130 single_send <= send WHEN valid_burst = '0' ELSE '0';
131 burst_send <= send WHEN valid_burst = '1' ELSE '0';
131 burst_send <= send WHEN valid_burst = '1' ELSE '0';
132 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
132 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
133
133
134 -- TODO : verifier
134 -- TODO : verifier
135 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
135 done <= single_send_ok OR single_send_ko OR burst_send_ok OR burst_send_ko;
136 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
136 --done <= single_send_ok OR single_send_ko WHEN valid_burst = '0' ELSE
137 -- burst_send_ok OR burst_send_ko;
137 -- burst_send_ok OR burst_send_ko;
138
138
139 --ren <= burst_ren WHEN valid_burst = '1' ELSE
139 --ren <= burst_ren WHEN valid_burst = '1' ELSE
140 -- NOT single_send_ok;
140 -- NOT single_send_ok;
141 --ren <= burst_ren AND single_ren;
141 --ren <= burst_ren AND single_ren;
142
142
143 ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
143 -- \/ JC - 20/01/2014 \/
144 '1';
144 ren <= burst_ren WHEN valid_burst = '1' ELSE
145 single_ren;
146
147
148 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
149 -- '1';
150 -- /\ JC - 20/01/2014 /\
145
151
146 -----------------------------------------------------------------------------
152 -----------------------------------------------------------------------------
147 -- SEND 1 word by DMA
153 -- SEND 1 word by DMA
148 -----------------------------------------------------------------------------
154 -----------------------------------------------------------------------------
149 lpp_dma_send_1word_1 : lpp_dma_send_1word
155 lpp_dma_send_1word_1 : lpp_dma_send_1word
150 PORT MAP (
156 PORT MAP (
151 HCLK => HCLK,
157 HCLK => HCLK,
152 HRESETn => HRESETn,
158 HRESETn => HRESETn,
153 DMAIn => single_dmai,
159 DMAIn => single_dmai,
154 DMAOut => DMAOut,
160 DMAOut => DMAOut,
155
161
156 send => single_send,
162 send => single_send,
157 address => address,
163 address => address,
158 data => data_2_halfword,
164 data => data_2_halfword,
159 ren => single_ren,
165 ren => single_ren,
160
166
161 send_ok => single_send_ok, -- TODO
167 send_ok => single_send_ok, -- TODO
162 send_ko => single_send_ko -- TODO
168 send_ko => single_send_ko -- TODO
163 );
169 );
164
170
165 -----------------------------------------------------------------------------
171 -----------------------------------------------------------------------------
166 -- SEND 16 word by DMA (in burst mode)
172 -- SEND 16 word by DMA (in burst mode)
167 -----------------------------------------------------------------------------
173 -----------------------------------------------------------------------------
168 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
174 data_2_halfword(31 DOWNTO 0) <= data(15 DOWNTO 0) & data (31 DOWNTO 16);
169
175
170 lpp_dma_send_16word_1 : lpp_dma_send_16word
176 lpp_dma_send_16word_1 : lpp_dma_send_16word
171 PORT MAP (
177 PORT MAP (
172 HCLK => HCLK,
178 HCLK => HCLK,
173 HRESETn => HRESETn,
179 HRESETn => HRESETn,
174 DMAIn => burst_dmai,
180 DMAIn => burst_dmai,
175 DMAOut => DMAOut,
181 DMAOut => DMAOut,
176
182
177 send => burst_send,
183 send => burst_send,
178 address => address,
184 address => address,
179 data => data_2_halfword,
185 data => data_2_halfword,
180 ren => burst_ren,
186 ren => burst_ren,
181
187
182 send_ok => burst_send_ok,
188 send_ok => burst_send_ok,
183 send_ko => burst_send_ko);
189 send_ko => burst_send_ko);
184
190
185 END Behavioral;
191 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,424 +1,424
1 -----------------------------------------------------------------------------
1 -----------------------------------------------------------------------------
2 -- LEON3 Demonstration design
2 -- LEON3 Demonstration design
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
3 -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 2 of the License, or
7 -- the Free Software Foundation; either version 2 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19
19
20
20
21 LIBRARY ieee;
21 LIBRARY ieee;
22 USE ieee.std_logic_1164.ALL;
22 USE ieee.std_logic_1164.ALL;
23 LIBRARY grlib;
23 LIBRARY grlib;
24 USE grlib.amba.ALL;
24 USE grlib.amba.ALL;
25 USE grlib.stdlib.ALL;
25 USE grlib.stdlib.ALL;
26 LIBRARY techmap;
26 LIBRARY techmap;
27 USE techmap.gencomp.ALL;
27 USE techmap.gencomp.ALL;
28 LIBRARY gaisler;
28 LIBRARY gaisler;
29 USE gaisler.memctrl.ALL;
29 USE gaisler.memctrl.ALL;
30 USE gaisler.leon3.ALL;
30 USE gaisler.leon3.ALL;
31 USE gaisler.uart.ALL;
31 USE gaisler.uart.ALL;
32 USE gaisler.misc.ALL;
32 USE gaisler.misc.ALL;
33 USE gaisler.spacewire.ALL; -- PLE
33 USE gaisler.spacewire.ALL; -- PLE
34 LIBRARY esa;
34 LIBRARY esa;
35 USE esa.memoryctrl.ALL;
35 USE esa.memoryctrl.ALL;
36 LIBRARY lpp;
36 LIBRARY lpp;
37 USE lpp.lpp_memory.ALL;
37 USE lpp.lpp_memory.ALL;
38 USE lpp.lpp_ad_conv.ALL;
38 USE lpp.lpp_ad_conv.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
39 USE lpp.lpp_lfr_pkg.ALL;
40 USE lpp.iir_filter.ALL;
40 USE lpp.iir_filter.ALL;
41 USE lpp.general_purpose.ALL;
41 USE lpp.general_purpose.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
42 USE lpp.lpp_lfr_time_management.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
43 USE lpp.lpp_leon3_soc_pkg.ALL;
44
44
45 ENTITY leon3_soc IS
45 ENTITY leon3_soc IS
46 GENERIC (
46 GENERIC (
47 fabtech : INTEGER := apa3e;
47 fabtech : INTEGER := apa3e;
48 memtech : INTEGER := apa3e;
48 memtech : INTEGER := apa3e;
49 padtech : INTEGER := inferred;
49 padtech : INTEGER := inferred;
50 clktech : INTEGER := inferred;
50 clktech : INTEGER := inferred;
51 disas : INTEGER := 0; -- Enable disassembly to console
51 disas : INTEGER := 0; -- Enable disassembly to console
52 dbguart : INTEGER := 0; -- Print UART on console
52 dbguart : INTEGER := 0; -- Print UART on console
53 pclow : INTEGER := 2;
53 pclow : INTEGER := 2;
54 --
54 --
55 clk_freq : INTEGER := 25000; --kHz
55 clk_freq : INTEGER := 25000; --kHz
56 --
56 --
57 NB_CPU : INTEGER := 1;
57 NB_CPU : INTEGER := 1;
58 ENABLE_FPU : INTEGER := 1;
58 ENABLE_FPU : INTEGER := 1;
59 FPU_NETLIST : INTEGER := 1;
59 FPU_NETLIST : INTEGER := 1;
60 ENABLE_DSU : INTEGER := 1;
60 ENABLE_DSU : INTEGER := 1;
61 ENABLE_AHB_UART : INTEGER := 1;
61 ENABLE_AHB_UART : INTEGER := 1;
62 ENABLE_APB_UART : INTEGER := 1;
62 ENABLE_APB_UART : INTEGER := 1;
63 ENABLE_IRQMP : INTEGER := 1;
63 ENABLE_IRQMP : INTEGER := 1;
64 ENABLE_GPT : INTEGER := 1;
64 ENABLE_GPT : INTEGER := 1;
65 --
65 --
66 NB_AHB_MASTER : INTEGER := 0;
66 NB_AHB_MASTER : INTEGER := 0;
67 NB_AHB_SLAVE : INTEGER := 0;
67 NB_AHB_SLAVE : INTEGER := 0;
68 NB_APB_SLAVE : INTEGER := 0
68 NB_APB_SLAVE : INTEGER := 0
69 );
69 );
70 PORT (
70 PORT (
71 clk : IN STD_ULOGIC;
71 clk : IN STD_ULOGIC;
72 reset : IN STD_ULOGIC;
72 reset : IN STD_ULOGIC;
73
73
74 errorn : OUT STD_ULOGIC;
74 errorn : OUT STD_ULOGIC;
75
75
76 -- UART AHB ---------------------------------------------------------------
76 -- UART AHB ---------------------------------------------------------------
77 ahbrxd : IN STD_ULOGIC; -- DSU rx data
77 ahbrxd : IN STD_ULOGIC; -- DSU rx data
78 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
78 ahbtxd : OUT STD_ULOGIC; -- DSU tx data
79
79
80 -- UART APB ---------------------------------------------------------------
80 -- UART APB ---------------------------------------------------------------
81 urxd1 : IN STD_ULOGIC; -- UART1 rx data
81 urxd1 : IN STD_ULOGIC; -- UART1 rx data
82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
82 utxd1 : OUT STD_ULOGIC; -- UART1 tx data
83
83
84 -- RAM --------------------------------------------------------------------
84 -- RAM --------------------------------------------------------------------
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
85 address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
87 nSRAM_BE0 : OUT STD_LOGIC;
87 nSRAM_BE0 : OUT STD_LOGIC;
88 nSRAM_BE1 : OUT STD_LOGIC;
88 nSRAM_BE1 : OUT STD_LOGIC;
89 nSRAM_BE2 : OUT STD_LOGIC;
89 nSRAM_BE2 : OUT STD_LOGIC;
90 nSRAM_BE3 : OUT STD_LOGIC;
90 nSRAM_BE3 : OUT STD_LOGIC;
91 nSRAM_WE : OUT STD_LOGIC;
91 nSRAM_WE : OUT STD_LOGIC;
92 nSRAM_CE : OUT STD_LOGIC;
92 nSRAM_CE : OUT STD_LOGIC;
93 nSRAM_OE : OUT STD_LOGIC;
93 nSRAM_OE : OUT STD_LOGIC;
94
94
95 -- APB --------------------------------------------------------------------
95 -- APB --------------------------------------------------------------------
96 apbi_ext : OUT apb_slv_in_type;
96 apbi_ext : OUT apb_slv_in_type;
97 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
97 apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);
98 -- AHB_Slave --------------------------------------------------------------
98 -- AHB_Slave --------------------------------------------------------------
99 ahbi_s_ext : OUT ahb_slv_in_type;
99 ahbi_s_ext : OUT ahb_slv_in_type;
100 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
100 ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);
101 -- AHB_Master -------------------------------------------------------------
101 -- AHB_Master -------------------------------------------------------------
102 ahbi_m_ext : OUT AHB_Mst_In_Type;
102 ahbi_m_ext : OUT AHB_Mst_In_Type;
103 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
103 ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU)
104
104
105 );
105 );
106 END;
106 END;
107
107
108 ARCHITECTURE Behavioral OF leon3_soc IS
108 ARCHITECTURE Behavioral OF leon3_soc IS
109
109
110 -----------------------------------------------------------------------------
110 -----------------------------------------------------------------------------
111 -- CONFIG -------------------------------------------------------------------
111 -- CONFIG -------------------------------------------------------------------
112 -----------------------------------------------------------------------------
112 -----------------------------------------------------------------------------
113
113
114 -- Clock generator
114 -- Clock generator
115 constant CFG_CLKMUL : integer := (1);
115 constant CFG_CLKMUL : integer := (1);
116 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
116 constant CFG_CLKDIV : integer := (1); -- divide 50MHz by 2 to get 25MHz
117 constant CFG_OCLKDIV : integer := (1);
117 constant CFG_OCLKDIV : integer := (1);
118 constant CFG_CLK_NOFB : integer := 0;
118 constant CFG_CLK_NOFB : integer := 0;
119 -- LEON3 processor core
119 -- LEON3 processor core
120 constant CFG_LEON3 : integer := 1;
120 constant CFG_LEON3 : integer := 1;
121 constant CFG_NCPU : integer := NB_CPU;
121 constant CFG_NCPU : integer := NB_CPU;
122 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
122 constant CFG_NWIN : integer := (8); -- to be compatible with BCC and RCC
123 constant CFG_V8 : integer := 0;
123 constant CFG_V8 : integer := 0;
124 constant CFG_MAC : integer := 0;
124 constant CFG_MAC : integer := 0;
125 constant CFG_SVT : integer := 0;
125 constant CFG_SVT : integer := 0;
126 constant CFG_RSTADDR : integer := 16#00000#;
126 constant CFG_RSTADDR : integer := 16#00000#;
127 constant CFG_LDDEL : integer := (1);
127 constant CFG_LDDEL : integer := (1);
128 constant CFG_NWP : integer := (0);
128 constant CFG_NWP : integer := (0);
129 constant CFG_PWD : integer := 1*2;
129 constant CFG_PWD : integer := 1*2;
130 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
130 constant CFG_FPU : integer := ENABLE_FPU *(8 + 16 * FPU_NETLIST);
131 -- 1*(8 + 16 * 0) => grfpu-light
131 -- 1*(8 + 16 * 0) => grfpu-light
132 -- 1*(8 + 16 * 1) => netlist
132 -- 1*(8 + 16 * 1) => netlist
133 -- 0*(8 + 16 * 0) => No FPU
133 -- 0*(8 + 16 * 0) => No FPU
134 -- 0*(8 + 16 * 1) => No FPU;
134 -- 0*(8 + 16 * 1) => No FPU;
135 constant CFG_ICEN : integer := 1;
135 constant CFG_ICEN : integer := 1;
136 constant CFG_ISETS : integer := 1;
136 constant CFG_ISETS : integer := 1;
137 constant CFG_ISETSZ : integer := 4;
137 constant CFG_ISETSZ : integer := 4;
138 constant CFG_ILINE : integer := 4;
138 constant CFG_ILINE : integer := 4;
139 constant CFG_IREPL : integer := 0;
139 constant CFG_IREPL : integer := 0;
140 constant CFG_ILOCK : integer := 0;
140 constant CFG_ILOCK : integer := 0;
141 constant CFG_ILRAMEN : integer := 0;
141 constant CFG_ILRAMEN : integer := 0;
142 constant CFG_ILRAMADDR: integer := 16#8E#;
142 constant CFG_ILRAMADDR: integer := 16#8E#;
143 constant CFG_ILRAMSZ : integer := 1;
143 constant CFG_ILRAMSZ : integer := 1;
144 constant CFG_DCEN : integer := 1;
144 constant CFG_DCEN : integer := 1;
145 constant CFG_DSETS : integer := 1;
145 constant CFG_DSETS : integer := 1;
146 constant CFG_DSETSZ : integer := 4;
146 constant CFG_DSETSZ : integer := 4;
147 constant CFG_DLINE : integer := 4;
147 constant CFG_DLINE : integer := 4;
148 constant CFG_DREPL : integer := 0;
148 constant CFG_DREPL : integer := 0;
149 constant CFG_DLOCK : integer := 0;
149 constant CFG_DLOCK : integer := 0;
150 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
150 constant CFG_DSNOOP : integer := 0 + 0 + 4*0;
151 constant CFG_DLRAMEN : integer := 0;
151 constant CFG_DLRAMEN : integer := 0;
152 constant CFG_DLRAMADDR: integer := 16#8F#;
152 constant CFG_DLRAMADDR: integer := 16#8F#;
153 constant CFG_DLRAMSZ : integer := 1;
153 constant CFG_DLRAMSZ : integer := 1;
154 constant CFG_MMUEN : integer := 0;
154 constant CFG_MMUEN : integer := 0;
155 constant CFG_ITLBNUM : integer := 2;
155 constant CFG_ITLBNUM : integer := 2;
156 constant CFG_DTLBNUM : integer := 2;
156 constant CFG_DTLBNUM : integer := 2;
157 constant CFG_TLB_TYPE : integer := 1 + 0*2;
157 constant CFG_TLB_TYPE : integer := 1 + 0*2;
158 constant CFG_TLB_REP : integer := 1;
158 constant CFG_TLB_REP : integer := 1;
159
159
160 constant CFG_DSU : integer := ENABLE_DSU;
160 constant CFG_DSU : integer := ENABLE_DSU;
161 constant CFG_ITBSZ : integer := 0;
161 constant CFG_ITBSZ : integer := 0;
162 constant CFG_ATBSZ : integer := 0;
162 constant CFG_ATBSZ : integer := 0;
163
163
164 -- AMBA settings
164 -- AMBA settings
165 constant CFG_DEFMST : integer := (0);
165 constant CFG_DEFMST : integer := (0);
166 constant CFG_RROBIN : integer := 1;
166 constant CFG_RROBIN : integer := 1;
167 constant CFG_SPLIT : integer := 0;
167 constant CFG_SPLIT : integer := 0;
168 constant CFG_AHBIO : integer := 16#FFF#;
168 constant CFG_AHBIO : integer := 16#FFF#;
169 constant CFG_APBADDR : integer := 16#800#;
169 constant CFG_APBADDR : integer := 16#800#;
170
170
171 -- DSU UART
171 -- DSU UART
172 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
172 constant CFG_AHB_UART : integer := ENABLE_AHB_UART;
173
173
174 -- LEON2 memory controller
174 -- LEON2 memory controller
175 constant CFG_MCTRL_SDEN : integer := 0;
175 constant CFG_MCTRL_SDEN : integer := 0;
176
176
177 -- UART 1
177 -- UART 1
178 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
178 constant CFG_UART1_ENABLE : integer := ENABLE_APB_UART;
179 constant CFG_UART1_FIFO : integer := 1;
179 constant CFG_UART1_FIFO : integer := 1;
180
180
181 -- LEON3 interrupt controller
181 -- LEON3 interrupt controller
182 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
182 constant CFG_IRQ3_ENABLE : integer := ENABLE_IRQMP;
183
183
184 -- Modular timer
184 -- Modular timer
185 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
185 constant CFG_GPT_ENABLE : integer := ENABLE_GPT;
186 constant CFG_GPT_NTIM : integer := (2);
186 constant CFG_GPT_NTIM : integer := (2);
187 constant CFG_GPT_SW : integer := (8);
187 constant CFG_GPT_SW : integer := (8);
188 constant CFG_GPT_TW : integer := (32);
188 constant CFG_GPT_TW : integer := (32);
189 constant CFG_GPT_IRQ : integer := (8);
189 constant CFG_GPT_IRQ : integer := (8);
190 constant CFG_GPT_SEPIRQ : integer := 1;
190 constant CFG_GPT_SEPIRQ : integer := 1;
191 constant CFG_GPT_WDOGEN : integer := 0;
191 constant CFG_GPT_WDOGEN : integer := 0;
192 constant CFG_GPT_WDOG : integer := 16#0#;
192 constant CFG_GPT_WDOG : integer := 16#0#;
193 -----------------------------------------------------------------------------
193 -----------------------------------------------------------------------------
194
194
195 -----------------------------------------------------------------------------
195 -----------------------------------------------------------------------------
196 -- SIGNALs
196 -- SIGNALs
197 -----------------------------------------------------------------------------
197 -----------------------------------------------------------------------------
198 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
198 CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER;
199 -- CLK & RST --
199 -- CLK & RST --
200 SIGNAL clk2x : STD_ULOGIC;
200 SIGNAL clk2x : STD_ULOGIC;
201 SIGNAL clkmn : STD_ULOGIC;
201 SIGNAL clkmn : STD_ULOGIC;
202 SIGNAL clkm : STD_ULOGIC;
202 SIGNAL clkm : STD_ULOGIC;
203 SIGNAL rstn : STD_ULOGIC;
203 SIGNAL rstn : STD_ULOGIC;
204 SIGNAL rstraw : STD_ULOGIC;
204 SIGNAL rstraw : STD_ULOGIC;
205 SIGNAL pciclk : STD_ULOGIC;
205 SIGNAL pciclk : STD_ULOGIC;
206 SIGNAL sdclkl : STD_ULOGIC;
206 SIGNAL sdclkl : STD_ULOGIC;
207 SIGNAL cgi : clkgen_in_type;
207 SIGNAL cgi : clkgen_in_type;
208 SIGNAL cgo : clkgen_out_type;
208 SIGNAL cgo : clkgen_out_type;
209 --- AHB / APB
209 --- AHB / APB
210 SIGNAL apbi : apb_slv_in_type;
210 SIGNAL apbi : apb_slv_in_type;
211 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
211 SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none);
212 SIGNAL ahbsi : ahb_slv_in_type;
212 SIGNAL ahbsi : ahb_slv_in_type;
213 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
213 SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none);
214 SIGNAL ahbmi : ahb_mst_in_type;
214 SIGNAL ahbmi : ahb_mst_in_type;
215 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
215 SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none);
216 --UART
216 --UART
217 SIGNAL ahbuarti : uart_in_type;
217 SIGNAL ahbuarti : uart_in_type;
218 SIGNAL ahbuarto : uart_out_type;
218 SIGNAL ahbuarto : uart_out_type;
219 SIGNAL apbuarti : uart_in_type;
219 SIGNAL apbuarti : uart_in_type;
220 SIGNAL apbuarto : uart_out_type;
220 SIGNAL apbuarto : uart_out_type;
221 --MEM CTRLR
221 --MEM CTRLR
222 SIGNAL memi : memory_in_type;
222 SIGNAL memi : memory_in_type;
223 SIGNAL memo : memory_out_type;
223 SIGNAL memo : memory_out_type;
224 SIGNAL wpo : wprot_out_type;
224 SIGNAL wpo : wprot_out_type;
225 SIGNAL sdo : sdram_out_type;
225 SIGNAL sdo : sdram_out_type;
226 --IRQ
226 --IRQ
227 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
227 SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1);
228 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
228 SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1);
229 --Timer
229 --Timer
230 SIGNAL gpti : gptimer_in_type;
230 SIGNAL gpti : gptimer_in_type;
231 SIGNAL gpto : gptimer_out_type;
231 SIGNAL gpto : gptimer_out_type;
232 --DSU
232 --DSU
233 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
233 SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1);
234 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
234 SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1);
235 SIGNAL dsui : dsu_in_type;
235 SIGNAL dsui : dsu_in_type;
236 SIGNAL dsuo : dsu_out_type;
236 SIGNAL dsuo : dsu_out_type;
237 -----------------------------------------------------------------------------
237 -----------------------------------------------------------------------------
238 BEGIN
238 BEGIN
239
239
240
240
241 ----------------------------------------------------------------------
241 ----------------------------------------------------------------------
242 --- Reset and Clock generation -------------------------------------
242 --- Reset and Clock generation -------------------------------------
243 ----------------------------------------------------------------------
243 ----------------------------------------------------------------------
244
244
245 cgi.pllctrl <= "00";
245 cgi.pllctrl <= "00";
246 cgi.pllrst <= rstraw;
246 cgi.pllrst <= rstraw;
247
247
248 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
248 rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw);
249
249
250 clkgen0 : clkgen -- clock generator
250 clkgen0 : clkgen -- clock generator
251 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
251 GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN,
252 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
252 CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV)
253 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
253 PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo);
254
254
255 ----------------------------------------------------------------------
255 ----------------------------------------------------------------------
256 --- LEON3 processor / DSU / IRQ ------------------------------------
256 --- LEON3 processor / DSU / IRQ ------------------------------------
257 ----------------------------------------------------------------------
257 ----------------------------------------------------------------------
258
258
259 l3 : IF CFG_LEON3 = 1 GENERATE
259 l3 : IF CFG_LEON3 = 1 GENERATE
260 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
260 cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE
261 u0 : leon3s -- LEON3 processor
261 u0 : leon3s -- LEON3 processor
262 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
262 GENERIC MAP (i, fabtech, memtech, CFG_NWIN, CFG_DSU, CFG_FPU, CFG_V8,
263 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
263 0, CFG_MAC, pclow, 0, CFG_NWP, CFG_ICEN, CFG_IREPL, CFG_ISETS, CFG_ILINE,
264 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
264 CFG_ISETSZ, CFG_ILOCK, CFG_DCEN, CFG_DREPL, CFG_DSETS, CFG_DLINE, CFG_DSETSZ,
265 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
265 CFG_DLOCK, CFG_DSNOOP, CFG_ILRAMEN, CFG_ILRAMSZ, CFG_ILRAMADDR, CFG_DLRAMEN,
266 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
266 CFG_DLRAMSZ, CFG_DLRAMADDR, CFG_MMUEN, CFG_ITLBNUM, CFG_DTLBNUM, CFG_TLB_TYPE, CFG_TLB_REP,
267 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
267 CFG_LDDEL, disas, CFG_ITBSZ, CFG_PWD, CFG_SVT, CFG_RSTADDR, CFG_NCPU-1)
268 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
268 PORT MAP (clkm, rstn, ahbmi, ahbmo(i), ahbsi, ahbso,
269 irqi(i), irqo(i), dbgi(i), dbgo(i));
269 irqi(i), irqo(i), dbgi(i), dbgo(i));
270 END GENERATE;
270 END GENERATE;
271 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
271 errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error);
272
272
273 dsugen : IF CFG_DSU = 1 GENERATE
273 dsugen : IF CFG_DSU = 1 GENERATE
274 dsu0 : dsu3 -- LEON3 Debug Support Unit
274 dsu0 : dsu3 -- LEON3 Debug Support Unit
275 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
275 GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#,
276 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
276 ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ)
277 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
277 PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo);
278 dsui.enable <= '1';
278 dsui.enable <= '1';
279 dsui.break <= '0';
279 dsui.break <= '0';
280 END GENERATE;
280 END GENERATE;
281 END GENERATE;
281 END GENERATE;
282
282
283 nodsu : IF CFG_DSU = 0 GENERATE
283 nodsu : IF CFG_DSU = 0 GENERATE
284 ahbso(2) <= ahbs_none;
284 ahbso(2) <= ahbs_none;
285 dsuo.tstop <= '0';
285 dsuo.tstop <= '0';
286 dsuo.active <= '0';
286 dsuo.active <= '0';
287 END GENERATE;
287 END GENERATE;
288
288
289 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
289 irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE
290 irqctrl0 : irqmp -- interrupt controller
290 irqctrl0 : irqmp -- interrupt controller
291 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
291 GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU)
292 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
292 PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi);
293 END GENERATE;
293 END GENERATE;
294 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
294 irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE
295 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
295 x : FOR i IN 0 TO CFG_NCPU-1 GENERATE
296 irqi(i).irl <= "0000";
296 irqi(i).irl <= "0000";
297 END GENERATE;
297 END GENERATE;
298 apbo(2) <= apb_none;
298 apbo(2) <= apb_none;
299 END GENERATE;
299 END GENERATE;
300
300
301 ----------------------------------------------------------------------
301 ----------------------------------------------------------------------
302 --- Memory controllers ---------------------------------------------
302 --- Memory controllers ---------------------------------------------
303 ----------------------------------------------------------------------
303 ----------------------------------------------------------------------
304 memctrlr : mctrl GENERIC MAP (
304 memctrlr : mctrl GENERIC MAP (
305 hindex => 0,
305 hindex => 0,
306 pindex => 0,
306 pindex => 0,
307 paddr => 0,
307 paddr => 0,
308 srbanks => 1
308 srbanks => 1
309 )
309 )
310 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
310 PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo);
311
311
312 memi.brdyn <= '1';
312 memi.brdyn <= '1';
313 memi.bexcn <= '1';
313 memi.bexcn <= '1';
314 memi.writen <= '1';
314 memi.writen <= '1';
315 memi.wrn <= "1111";
315 memi.wrn <= "1111";
316 memi.bwidth <= "10";
316 memi.bwidth <= "10";
317
317
318 bdr : FOR i IN 0 TO 3 GENERATE
318 bdr : FOR i IN 0 TO 3 GENERATE
319 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
319 data_pad : iopadv GENERIC MAP (tech => padtech, width => 8)
320 PORT MAP (
320 PORT MAP (
321 data(31-i*8 DOWNTO 24-i*8),
321 data(31-i*8 DOWNTO 24-i*8),
322 memo.data(31-i*8 DOWNTO 24-i*8),
322 memo.data(31-i*8 DOWNTO 24-i*8),
323 memo.bdrive(i),
323 memo.bdrive(i),
324 memi.data(31-i*8 DOWNTO 24-i*8));
324 memi.data(31-i*8 DOWNTO 24-i*8));
325 END GENERATE;
325 END GENERATE;
326
326
327 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
327 addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech)
328 PORT MAP (address, memo.address(21 DOWNTO 2));
328 PORT MAP (address, memo.address(21 DOWNTO 2));
329
329
330 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
330 rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, NOT(memo.ramsn(0)));
331 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
331 oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0));
332 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
332 nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen);
333 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
333 nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3));
334 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
334 nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2));
335 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
335 nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1));
336 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
336 nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0));
337
337
338 ----------------------------------------------------------------------
338 ----------------------------------------------------------------------
339 --- AHB CONTROLLER -------------------------------------------------
339 --- AHB CONTROLLER -------------------------------------------------
340 ----------------------------------------------------------------------
340 ----------------------------------------------------------------------
341 ahb0 : ahbctrl -- AHB arbiter/multiplexer
341 ahb0 : ahbctrl -- AHB arbiter/multiplexer
342 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
342 GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT,
343 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
343 rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO,
344 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
344 ioen => 0, nahbm => maxahbmsp, nahbs => 8)
345 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
345 PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso);
346
346
347 ----------------------------------------------------------------------
347 ----------------------------------------------------------------------
348 --- AHB UART -------------------------------------------------------
348 --- AHB UART -------------------------------------------------------
349 ----------------------------------------------------------------------
349 ----------------------------------------------------------------------
350 dcomgen : IF CFG_AHB_UART = 1 GENERATE
350 dcomgen : IF CFG_AHB_UART = 1 GENERATE
351 dcom0 : ahbuart
351 dcom0 : ahbuart
352 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
352 GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4)
353 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
353 PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1));
354 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
354 dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd);
355 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
355 dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd);
356 END GENERATE;
356 END GENERATE;
357 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
357 nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE;
358
358
359 ----------------------------------------------------------------------
359 ----------------------------------------------------------------------
360 --- APB Bridge -----------------------------------------------------
360 --- APB Bridge -----------------------------------------------------
361 ----------------------------------------------------------------------
361 ----------------------------------------------------------------------
362 apb0 : apbctrl -- AHB/APB bridge
362 apb0 : apbctrl -- AHB/APB bridge
363 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
363 GENERIC MAP (hindex => 1, haddr => CFG_APBADDR)
364 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
364 PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo);
365
365
366 ----------------------------------------------------------------------
366 ----------------------------------------------------------------------
367 --- GPT Timer ------------------------------------------------------
367 --- GPT Timer ------------------------------------------------------
368 ----------------------------------------------------------------------
368 ----------------------------------------------------------------------
369 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
369 gpt : IF CFG_GPT_ENABLE /= 0 GENERATE
370 timer0 : gptimer -- timer unit
370 timer0 : gptimer -- timer unit
371 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
371 GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ,
372 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
372 sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM,
373 nbits => CFG_GPT_TW)
373 nbits => CFG_GPT_TW)
374 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
374 PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto);
375 gpti.dhalt <= dsuo.tstop;
375 gpti.dhalt <= dsuo.tstop;
376 gpti.extclk <= '0';
376 gpti.extclk <= '0';
377 END GENERATE;
377 END GENERATE;
378 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
378 notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE;
379
379
380
380
381 ----------------------------------------------------------------------
381 ----------------------------------------------------------------------
382 --- APB UART -------------------------------------------------------
382 --- APB UART -------------------------------------------------------
383 ----------------------------------------------------------------------
383 ----------------------------------------------------------------------
384 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
384 ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE
385 uart1 : apbuart -- UART 1
385 uart1 : apbuart -- UART 1
386 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
386 GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart,
387 fifosize => CFG_UART1_FIFO)
387 fifosize => CFG_UART1_FIFO)
388 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
388 PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto);
389 apbuarti.rxd <= urxd1;
389 apbuarti.rxd <= urxd1;
390 apbuarti.extclk <= '0';
390 apbuarti.extclk <= '0';
391 utxd1 <= apbuarto.txd;
391 utxd1 <= apbuarto.txd;
392 apbuarti.ctsn <= '0';
392 apbuarti.ctsn <= '0';
393 END GENERATE;
393 END GENERATE;
394 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
394 noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE;
395
395
396 -------------------------------------------------------------------------------
396 -------------------------------------------------------------------------------
397 -- AMBA BUS -------------------------------------------------------------------
397 -- AMBA BUS -------------------------------------------------------------------
398 -------------------------------------------------------------------------------
398 -------------------------------------------------------------------------------
399
399
400 -- APB --------------------------------------------------------------------
400 -- APB --------------------------------------------------------------------
401 apbi_ext <= apbi;
401 apbi_ext <= apbi;
402 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
402 all_apb: FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE
403 max_16_apb: IF I + 5 < 16 GENERATE
403 max_16_apb: IF I + 5 < 16 GENERATE
404 apbo(I+5)<= apbo_ext(I+5);
404 apbo(I+5)<= apbo_ext(I+5);
405 END GENERATE max_16_apb;
405 END GENERATE max_16_apb;
406 END GENERATE all_apb;
406 END GENERATE all_apb;
407 -- AHB_Slave --------------------------------------------------------------
407 -- AHB_Slave --------------------------------------------------------------
408 ahbi_s_ext <= ahbsi;
408 ahbi_s_ext <= ahbsi;
409 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
409 all_ahbs: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
410 max_16_ahbs: IF I + 3 < 16 GENERATE
410 max_16_ahbs: IF I + 3 < 16 GENERATE
411 ahbso(I+3) <= ahbo_s_ext(I+3);
411 ahbso(I+3) <= ahbo_s_ext(I+3);
412 END GENERATE max_16_ahbs;
412 END GENERATE max_16_ahbs;
413 END GENERATE all_ahbs;
413 END GENERATE all_ahbs;
414 -- AHB_Master -------------------------------------------------------------
414 -- AHB_Master -------------------------------------------------------------
415 ahbi_m_ext <= ahbmi;
415 ahbi_m_ext <= ahbmi;
416 all_ahbm: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
416 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
417 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
417 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
418 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
418 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
419 END GENERATE max_16_ahbm;
419 END GENERATE max_16_ahbm;
420 END GENERATE all_ahbm;
420 END GENERATE all_ahbm;
421
421
422
422
423
423
424 END Behavioral;
424 END Behavioral;
Show file before | Show file after | Hide comments
@@ -1,695 +1,708
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3 USE ieee.numeric_std.ALL;
3 USE ieee.numeric_std.ALL;
4
4
5 LIBRARY lpp;
5 LIBRARY lpp;
6 USE lpp.lpp_ad_conv.ALL;
6 USE lpp.lpp_ad_conv.ALL;
7 USE lpp.iir_filter.ALL;
7 USE lpp.iir_filter.ALL;
8 USE lpp.FILTERcfg.ALL;
8 USE lpp.FILTERcfg.ALL;
9 USE lpp.lpp_memory.ALL;
9 USE lpp.lpp_memory.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
10 USE lpp.lpp_waveform_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
11 USE lpp.lpp_dma_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
12 USE lpp.lpp_top_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
13 USE lpp.lpp_lfr_pkg.ALL;
14 USE lpp.general_purpose.ALL;
14 USE lpp.general_purpose.ALL;
15
15
16 LIBRARY techmap;
16 LIBRARY techmap;
17 USE techmap.gencomp.ALL;
17 USE techmap.gencomp.ALL;
18
18
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.devices.ALL;
22 USE grlib.devices.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
23 USE GRLIB.DMA2AHB_Package.ALL;
24
24
25 ENTITY lpp_lfr IS
25 ENTITY lpp_lfr IS
26 GENERIC (
26 GENERIC (
27 Mem_use : INTEGER := use_RAM;
27 Mem_use : INTEGER := use_RAM;
28 nb_data_by_buffer_size : INTEGER := 11;
28 nb_data_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
29 nb_word_by_buffer_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
30 nb_snapshot_param_size : INTEGER := 11;
31 delta_vector_size : INTEGER := 20;
31 delta_vector_size : INTEGER := 20;
32 delta_vector_size_f0_2 : INTEGER := 7;
32 delta_vector_size_f0_2 : INTEGER := 7;
33
33
34 pindex : INTEGER := 4;
34 pindex : INTEGER := 4;
35 paddr : INTEGER := 4;
35 paddr : INTEGER := 4;
36 pmask : INTEGER := 16#fff#;
36 pmask : INTEGER := 16#fff#;
37 pirq_ms : INTEGER := 0;
37 pirq_ms : INTEGER := 0;
38 pirq_wfp : INTEGER := 1;
38 pirq_wfp : INTEGER := 1;
39
39
40 hindex : INTEGER := 2;
40 hindex : INTEGER := 2;
41
41
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0')
42 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0) := (OTHERS => '0')
43
43
44 );
44 );
45 PORT (
45 PORT (
46 clk : IN STD_LOGIC;
46 clk : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
47 rstn : IN STD_LOGIC;
48 -- SAMPLE
48 -- SAMPLE
49 sample_B : IN Samples14v(2 DOWNTO 0);
49 sample_B : IN Samples14v(2 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
50 sample_E : IN Samples14v(4 DOWNTO 0);
51 sample_val : IN STD_LOGIC;
51 sample_val : IN STD_LOGIC;
52 -- APB
52 -- APB
53 apbi : IN apb_slv_in_type;
53 apbi : IN apb_slv_in_type;
54 apbo : OUT apb_slv_out_type;
54 apbo : OUT apb_slv_out_type;
55 -- AHB
55 -- AHB
56 ahbi : IN AHB_Mst_In_Type;
56 ahbi : IN AHB_Mst_In_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
57 ahbo : OUT AHB_Mst_Out_Type;
58 -- TIME
58 -- TIME
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
59 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
60 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0); -- todo
61 --
61 --
62 data_shaping_BW : OUT STD_LOGIC;
62 data_shaping_BW : OUT STD_LOGIC;
63
63
64 --debug
64 --debug
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
65 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
66 debug_f0_data_valid : OUT STD_LOGIC;
66 debug_f0_data_valid : OUT STD_LOGIC;
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
67 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
68 debug_f1_data_valid : OUT STD_LOGIC;
68 debug_f1_data_valid : OUT STD_LOGIC;
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 debug_f2_data_valid : OUT STD_LOGIC;
70 debug_f2_data_valid : OUT STD_LOGIC;
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC
72 debug_f3_data_valid : OUT STD_LOGIC;
73
74 -- debug FIFO_IN
75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
83
84 --debug FIFO OUT
85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
93
94 --debug DMA IN
95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
73 );
103 );
74 END lpp_lfr;
104 END lpp_lfr;
75
105
76 ARCHITECTURE beh OF lpp_lfr IS
106 ARCHITECTURE beh OF lpp_lfr IS
77 SIGNAL sample : Samples14v(7 DOWNTO 0);
107 SIGNAL sample : Samples14v(7 DOWNTO 0);
78 SIGNAL sample_s : Samples(7 DOWNTO 0);
108 SIGNAL sample_s : Samples(7 DOWNTO 0);
79 --
109 --
80 SIGNAL data_shaping_SP0 : STD_LOGIC;
110 SIGNAL data_shaping_SP0 : STD_LOGIC;
81 SIGNAL data_shaping_SP1 : STD_LOGIC;
111 SIGNAL data_shaping_SP1 : STD_LOGIC;
82 SIGNAL data_shaping_R0 : STD_LOGIC;
112 SIGNAL data_shaping_R0 : STD_LOGIC;
83 SIGNAL data_shaping_R1 : STD_LOGIC;
113 SIGNAL data_shaping_R1 : STD_LOGIC;
84 --
114 --
85 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
115 SIGNAL sample_f0_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
86 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
116 SIGNAL sample_f1_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
87 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
117 SIGNAL sample_f3_wen : STD_LOGIC_VECTOR(4 DOWNTO 0);
88 --
118 --
89 SIGNAL sample_f0_val : STD_LOGIC;
119 SIGNAL sample_f0_val : STD_LOGIC;
90 SIGNAL sample_f1_val : STD_LOGIC;
120 SIGNAL sample_f1_val : STD_LOGIC;
91 SIGNAL sample_f2_val : STD_LOGIC;
121 SIGNAL sample_f2_val : STD_LOGIC;
92 SIGNAL sample_f3_val : STD_LOGIC;
122 SIGNAL sample_f3_val : STD_LOGIC;
93 --
123 --
94 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
124 SIGNAL sample_f0_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
95 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
125 SIGNAL sample_f1_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
96 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
126 SIGNAL sample_f2_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
97 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
127 SIGNAL sample_f3_data : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
98 --
128 --
99 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
129 SIGNAL sample_f0_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
100 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
130 SIGNAL sample_f1_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
101 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
131 SIGNAL sample_f3_wdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
102
132
103 -- SM
133 -- SM
104 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
134 SIGNAL ready_matrix_f0_0 : STD_LOGIC;
105 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
135 SIGNAL ready_matrix_f0_1 : STD_LOGIC;
106 SIGNAL ready_matrix_f1 : STD_LOGIC;
136 SIGNAL ready_matrix_f1 : STD_LOGIC;
107 SIGNAL ready_matrix_f2 : STD_LOGIC;
137 SIGNAL ready_matrix_f2 : STD_LOGIC;
108 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
138 SIGNAL error_anticipating_empty_fifo : STD_LOGIC;
109 SIGNAL error_bad_component_error : STD_LOGIC;
139 SIGNAL error_bad_component_error : STD_LOGIC;
110 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
140 SIGNAL debug_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
111 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
141 SIGNAL status_ready_matrix_f0_0 : STD_LOGIC;
112 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
142 SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
113 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
143 SIGNAL status_ready_matrix_f1 : STD_LOGIC;
114 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
144 SIGNAL status_ready_matrix_f2 : STD_LOGIC;
115 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
145 SIGNAL status_error_anticipating_empty_fifo : STD_LOGIC;
116 SIGNAL status_error_bad_component_error : STD_LOGIC;
146 SIGNAL status_error_bad_component_error : STD_LOGIC;
117 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
147 SIGNAL config_active_interruption_onNewMatrix : STD_LOGIC;
118 SIGNAL config_active_interruption_onError : STD_LOGIC;
148 SIGNAL config_active_interruption_onError : STD_LOGIC;
119 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149 SIGNAL addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
150 SIGNAL addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
121 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
151 SIGNAL addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
122 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 SIGNAL addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
123
153
124 -- WFP
154 -- WFP
125 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
155 SIGNAL status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
126 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
156 SIGNAL status_full_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
127 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
157 SIGNAL status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
128 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
158 SIGNAL status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
129 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
159 SIGNAL delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
130 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
160 SIGNAL delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
131 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
161 SIGNAL delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
132 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 SIGNAL delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
133 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 SIGNAL delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
134
164
135 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
165 SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
136 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
166 SIGNAL nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
137 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
167 SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
138 SIGNAL enable_f0 : STD_LOGIC;
168 SIGNAL enable_f0 : STD_LOGIC;
139 SIGNAL enable_f1 : STD_LOGIC;
169 SIGNAL enable_f1 : STD_LOGIC;
140 SIGNAL enable_f2 : STD_LOGIC;
170 SIGNAL enable_f2 : STD_LOGIC;
141 SIGNAL enable_f3 : STD_LOGIC;
171 SIGNAL enable_f3 : STD_LOGIC;
142 SIGNAL burst_f0 : STD_LOGIC;
172 SIGNAL burst_f0 : STD_LOGIC;
143 SIGNAL burst_f1 : STD_LOGIC;
173 SIGNAL burst_f1 : STD_LOGIC;
144 SIGNAL burst_f2 : STD_LOGIC;
174 SIGNAL burst_f2 : STD_LOGIC;
145 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
175 SIGNAL addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
146 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
176 SIGNAL addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
147 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
177 SIGNAL addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
148 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
149
179
150 SIGNAL run : STD_LOGIC;
180 SIGNAL run : STD_LOGIC;
151 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
181 SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
152
182
153 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
183 SIGNAL data_f0_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
154 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
184 SIGNAL data_f0_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
155 SIGNAL data_f0_data_out_valid : STD_LOGIC;
185 SIGNAL data_f0_data_out_valid : STD_LOGIC;
156 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
186 SIGNAL data_f0_data_out_valid_burst : STD_LOGIC;
157 SIGNAL data_f0_data_out_ren : STD_LOGIC;
187 SIGNAL data_f0_data_out_ren : STD_LOGIC;
158 --f1
188 --f1
159 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f1_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 SIGNAL data_f1_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 SIGNAL data_f1_data_out_valid : STD_LOGIC;
191 SIGNAL data_f1_data_out_valid : STD_LOGIC;
162 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
192 SIGNAL data_f1_data_out_valid_burst : STD_LOGIC;
163 SIGNAL data_f1_data_out_ren : STD_LOGIC;
193 SIGNAL data_f1_data_out_ren : STD_LOGIC;
164 --f2
194 --f2
165 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
195 SIGNAL data_f2_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
166 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
196 SIGNAL data_f2_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
167 SIGNAL data_f2_data_out_valid : STD_LOGIC;
197 SIGNAL data_f2_data_out_valid : STD_LOGIC;
168 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
198 SIGNAL data_f2_data_out_valid_burst : STD_LOGIC;
169 SIGNAL data_f2_data_out_ren : STD_LOGIC;
199 SIGNAL data_f2_data_out_ren : STD_LOGIC;
170 --f3
200 --f3
171 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
201 SIGNAL data_f3_addr_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
172 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
202 SIGNAL data_f3_data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
173 SIGNAL data_f3_data_out_valid : STD_LOGIC;
203 SIGNAL data_f3_data_out_valid : STD_LOGIC;
174 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
204 SIGNAL data_f3_data_out_valid_burst : STD_LOGIC;
175 SIGNAL data_f3_data_out_ren : STD_LOGIC;
205 SIGNAL data_f3_data_out_ren : STD_LOGIC;
176
206
177 -----------------------------------------------------------------------------
207 -----------------------------------------------------------------------------
178 --
208 --
179 -----------------------------------------------------------------------------
209 -----------------------------------------------------------------------------
180 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
210 SIGNAL data_f0_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
181 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
211 SIGNAL data_f0_data_out_valid_s : STD_LOGIC;
182 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
212 SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
183 --f1
213 --f1
184 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
214 SIGNAL data_f1_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
215 SIGNAL data_f1_data_out_valid_s : STD_LOGIC;
186 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
216 SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
187 --f2
217 --f2
188 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
218 SIGNAL data_f2_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
219 SIGNAL data_f2_data_out_valid_s : STD_LOGIC;
190 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
220 SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
191 --f3
221 --f3
192 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
222 SIGNAL data_f3_addr_out_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
223 SIGNAL data_f3_data_out_valid_s : STD_LOGIC;
194 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
224 SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
195
225
196 -----------------------------------------------------------------------------
226 -----------------------------------------------------------------------------
197 -- DMA RR
227 -- DMA RR
198 -----------------------------------------------------------------------------
228 -----------------------------------------------------------------------------
199 SIGNAL dma_sel_valid : STD_LOGIC;
229 SIGNAL dma_sel_valid : STD_LOGIC;
200 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
230 SIGNAL dma_sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
201 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
231 SIGNAL dma_rr_valid : STD_LOGIC_VECTOR(3 DOWNTO 0);
202 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
232 SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(3 DOWNTO 0);
203
233
204 -----------------------------------------------------------------------------
234 -----------------------------------------------------------------------------
205 -- DMA_REG
235 -- DMA_REG
206 -----------------------------------------------------------------------------
236 -----------------------------------------------------------------------------
207 SIGNAL ongoing_reg : STD_LOGIC;
237 SIGNAL ongoing_reg : STD_LOGIC;
208 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
238 SIGNAL dma_sel_reg : STD_LOGIC_VECTOR(3 DOWNTO 0);
209 SIGNAL dma_send_reg : STD_LOGIC;
239 SIGNAL dma_send_reg : STD_LOGIC;
210 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
240 SIGNAL dma_valid_burst_reg : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
211 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL dma_address_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
212 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL dma_data_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
213
243
214
244
215 -----------------------------------------------------------------------------
245 -----------------------------------------------------------------------------
216 -- DMA
246 -- DMA
217 -----------------------------------------------------------------------------
247 -----------------------------------------------------------------------------
218 SIGNAL dma_send : STD_LOGIC;
248 SIGNAL dma_send : STD_LOGIC;
219 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
249 SIGNAL dma_valid_burst : STD_LOGIC; -- (1 => BURST , 0 => SINGLE)
220 SIGNAL dma_done : STD_LOGIC;
250 SIGNAL dma_done : STD_LOGIC;
221 SIGNAL dma_ren : STD_LOGIC;
251 SIGNAL dma_ren : STD_LOGIC;
222 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
252 SIGNAL dma_address : STD_LOGIC_VECTOR(31 DOWNTO 0);
223 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
253 SIGNAL dma_data : STD_LOGIC_VECTOR(31 DOWNTO 0);
224 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
254 SIGNAL dma_data_2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
225
255
226 -----------------------------------------------------------------------------
256 -----------------------------------------------------------------------------
227 -- DEBUG
257 -- DEBUG
228 -----------------------------------------------------------------------------
258 -----------------------------------------------------------------------------
229 --
259 --
230 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
260 SIGNAL sample_f0_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
231 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
261 SIGNAL sample_f1_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
232 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
262 SIGNAL sample_f2_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
233 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
263 SIGNAL sample_f3_data_debug : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
234
264
235 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
265 SIGNAL debug_reg0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
236 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
266 SIGNAL debug_reg1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
237 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
267 SIGNAL debug_reg2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
238 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
268 SIGNAL debug_reg3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
239 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
269 SIGNAL debug_reg4 : STD_LOGIC_VECTOR(31 DOWNTO 0);
240 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
270 SIGNAL debug_reg5 : STD_LOGIC_VECTOR(31 DOWNTO 0);
241 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
271 SIGNAL debug_reg6 : STD_LOGIC_VECTOR(31 DOWNTO 0);
242 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
272 SIGNAL debug_reg7 : STD_LOGIC_VECTOR(31 DOWNTO 0);
243
273
244 BEGIN
274 BEGIN
245
275
246 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
276 sample(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
247 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
277 sample(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
248
278
249 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
279 all_channel : FOR i IN 7 DOWNTO 0 GENERATE
250 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
280 sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
251 END GENERATE all_channel;
281 END GENERATE all_channel;
252
282
253 -----------------------------------------------------------------------------
283 -----------------------------------------------------------------------------
254 lpp_lfr_filter_1 : lpp_lfr_filter
284 lpp_lfr_filter_1 : lpp_lfr_filter
255 GENERIC MAP (
285 GENERIC MAP (
256 Mem_use => Mem_use)
286 Mem_use => Mem_use)
257 PORT MAP (
287 PORT MAP (
258 sample => sample_s,
288 sample => sample_s,
259 sample_val => sample_val,
289 sample_val => sample_val,
260 clk => clk,
290 clk => clk,
261 rstn => rstn,
291 rstn => rstn,
262 data_shaping_SP0 => data_shaping_SP0,
292 data_shaping_SP0 => data_shaping_SP0,
263 data_shaping_SP1 => data_shaping_SP1,
293 data_shaping_SP1 => data_shaping_SP1,
264 data_shaping_R0 => data_shaping_R0,
294 data_shaping_R0 => data_shaping_R0,
265 data_shaping_R1 => data_shaping_R1,
295 data_shaping_R1 => data_shaping_R1,
266 sample_f0_val => sample_f0_val,
296 sample_f0_val => sample_f0_val,
267 sample_f1_val => sample_f1_val,
297 sample_f1_val => sample_f1_val,
268 sample_f2_val => sample_f2_val,
298 sample_f2_val => sample_f2_val,
269 sample_f3_val => sample_f3_val,
299 sample_f3_val => sample_f3_val,
270 sample_f0_wdata => sample_f0_data,
300 sample_f0_wdata => sample_f0_data,
271 sample_f1_wdata => sample_f1_data,
301 sample_f1_wdata => sample_f1_data,
272 sample_f2_wdata => sample_f2_data,
302 sample_f2_wdata => sample_f2_data,
273 sample_f3_wdata => sample_f3_data);
303 sample_f3_wdata => sample_f3_data);
274
304
275 -----------------------------------------------------------------------------
305 -----------------------------------------------------------------------------
276 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
306 lpp_lfr_apbreg_1 : lpp_lfr_apbreg
277 GENERIC MAP (
307 GENERIC MAP (
278 nb_data_by_buffer_size => nb_data_by_buffer_size,
308 nb_data_by_buffer_size => nb_data_by_buffer_size,
279 nb_word_by_buffer_size => nb_word_by_buffer_size,
309 nb_word_by_buffer_size => nb_word_by_buffer_size,
280 nb_snapshot_param_size => nb_snapshot_param_size,
310 nb_snapshot_param_size => nb_snapshot_param_size,
281 delta_vector_size => delta_vector_size,
311 delta_vector_size => delta_vector_size,
282 delta_vector_size_f0_2 => delta_vector_size_f0_2,
312 delta_vector_size_f0_2 => delta_vector_size_f0_2,
283 pindex => pindex,
313 pindex => pindex,
284 paddr => paddr,
314 paddr => paddr,
285 pmask => pmask,
315 pmask => pmask,
286 pirq_ms => pirq_ms,
316 pirq_ms => pirq_ms,
287 pirq_wfp => pirq_wfp,
317 pirq_wfp => pirq_wfp,
288 top_lfr_version => top_lfr_version)
318 top_lfr_version => top_lfr_version)
289 PORT MAP (
319 PORT MAP (
290 HCLK => clk,
320 HCLK => clk,
291 HRESETn => rstn,
321 HRESETn => rstn,
292 apbi => apbi,
322 apbi => apbi,
293 apbo => apbo,
323 apbo => apbo,
294 ready_matrix_f0_0 => ready_matrix_f0_0,
324 ready_matrix_f0_0 => ready_matrix_f0_0,
295 ready_matrix_f0_1 => ready_matrix_f0_1,
325 ready_matrix_f0_1 => ready_matrix_f0_1,
296 ready_matrix_f1 => ready_matrix_f1,
326 ready_matrix_f1 => ready_matrix_f1,
297 ready_matrix_f2 => ready_matrix_f2,
327 ready_matrix_f2 => ready_matrix_f2,
298 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
328 error_anticipating_empty_fifo => error_anticipating_empty_fifo,
299 error_bad_component_error => error_bad_component_error,
329 error_bad_component_error => error_bad_component_error,
300 debug_reg => debug_reg,
330 debug_reg => debug_reg,
301 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
331 status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
302 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
332 status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
303 status_ready_matrix_f1 => status_ready_matrix_f1,
333 status_ready_matrix_f1 => status_ready_matrix_f1,
304 status_ready_matrix_f2 => status_ready_matrix_f2,
334 status_ready_matrix_f2 => status_ready_matrix_f2,
305 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
335 status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
306 status_error_bad_component_error => status_error_bad_component_error,
336 status_error_bad_component_error => status_error_bad_component_error,
307 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
337 config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
308 config_active_interruption_onError => config_active_interruption_onError,
338 config_active_interruption_onError => config_active_interruption_onError,
309 addr_matrix_f0_0 => addr_matrix_f0_0,
339 addr_matrix_f0_0 => addr_matrix_f0_0,
310 addr_matrix_f0_1 => addr_matrix_f0_1,
340 addr_matrix_f0_1 => addr_matrix_f0_1,
311 addr_matrix_f1 => addr_matrix_f1,
341 addr_matrix_f1 => addr_matrix_f1,
312 addr_matrix_f2 => addr_matrix_f2,
342 addr_matrix_f2 => addr_matrix_f2,
313 status_full => status_full,
343 status_full => status_full,
314 status_full_ack => status_full_ack,
344 status_full_ack => status_full_ack,
315 status_full_err => status_full_err,
345 status_full_err => status_full_err,
316 status_new_err => status_new_err,
346 status_new_err => status_new_err,
317 data_shaping_BW => data_shaping_BW,
347 data_shaping_BW => data_shaping_BW,
318 data_shaping_SP0 => data_shaping_SP0,
348 data_shaping_SP0 => data_shaping_SP0,
319 data_shaping_SP1 => data_shaping_SP1,
349 data_shaping_SP1 => data_shaping_SP1,
320 data_shaping_R0 => data_shaping_R0,
350 data_shaping_R0 => data_shaping_R0,
321 data_shaping_R1 => data_shaping_R1,
351 data_shaping_R1 => data_shaping_R1,
322 delta_snapshot => delta_snapshot,
352 delta_snapshot => delta_snapshot,
323 delta_f0 => delta_f0,
353 delta_f0 => delta_f0,
324 delta_f0_2 => delta_f0_2,
354 delta_f0_2 => delta_f0_2,
325 delta_f1 => delta_f1,
355 delta_f1 => delta_f1,
326 delta_f2 => delta_f2,
356 delta_f2 => delta_f2,
327 nb_data_by_buffer => nb_data_by_buffer,
357 nb_data_by_buffer => nb_data_by_buffer,
328 nb_word_by_buffer => nb_word_by_buffer,
358 nb_word_by_buffer => nb_word_by_buffer,
329 nb_snapshot_param => nb_snapshot_param,
359 nb_snapshot_param => nb_snapshot_param,
330 enable_f0 => enable_f0,
360 enable_f0 => enable_f0,
331 enable_f1 => enable_f1,
361 enable_f1 => enable_f1,
332 enable_f2 => enable_f2,
362 enable_f2 => enable_f2,
333 enable_f3 => enable_f3,
363 enable_f3 => enable_f3,
334 burst_f0 => burst_f0,
364 burst_f0 => burst_f0,
335 burst_f1 => burst_f1,
365 burst_f1 => burst_f1,
336 burst_f2 => burst_f2,
366 burst_f2 => burst_f2,
337 run => run,
367 run => run,
338 addr_data_f0 => addr_data_f0,
368 addr_data_f0 => addr_data_f0,
339 addr_data_f1 => addr_data_f1,
369 addr_data_f1 => addr_data_f1,
340 addr_data_f2 => addr_data_f2,
370 addr_data_f2 => addr_data_f2,
341 addr_data_f3 => addr_data_f3,
371 addr_data_f3 => addr_data_f3,
342 start_date => start_date,
372 start_date => start_date,
343 ---------------------------------------------------------------------------
373 ---------------------------------------------------------------------------
344 debug_reg0 => debug_reg0,
374 debug_reg0 => debug_reg0,
345 debug_reg1 => debug_reg1,
375 debug_reg1 => debug_reg1,
346 debug_reg2 => debug_reg2,
376 debug_reg2 => debug_reg2,
347 debug_reg3 => debug_reg3,
377 debug_reg3 => debug_reg3,
348 debug_reg4 => debug_reg4,
378 debug_reg4 => debug_reg4,
349 debug_reg5 => debug_reg5,
379 debug_reg5 => debug_reg5,
350 debug_reg6 => debug_reg6,
380 debug_reg6 => debug_reg6,
351 debug_reg7 => debug_reg7);
381 debug_reg7 => debug_reg7);
352
382
353 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
383 debug_reg5 <= sample_f0_data(32*1-1 DOWNTO 32*0);
354 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
384 debug_reg6 <= sample_f0_data(32*2-1 DOWNTO 32*1);
355 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
385 debug_reg7 <= sample_f0_data(32*3-1 DOWNTO 32*2);
356 -----------------------------------------------------------------------------
386 -----------------------------------------------------------------------------
357 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
387 --sample_f0_data_debug <= x"01234567" & x"89ABCDEF" & x"02481357"; -- TODO : debug
358 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
388 --sample_f1_data_debug <= x"00112233" & x"44556677" & x"8899AABB"; -- TODO : debug
359 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
389 --sample_f2_data_debug <= x"CDEF1234" & x"ABBAEFFE" & x"01103773"; -- TODO : debug
360 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
390 --sample_f3_data_debug <= x"FEDCBA98" & x"76543210" & x"78945612"; -- TODO : debug
361
391
362
392
363 -----------------------------------------------------------------------------
393 -----------------------------------------------------------------------------
364 lpp_waveform_1 : lpp_waveform
394 lpp_waveform_1 : lpp_waveform
365 GENERIC MAP (
395 GENERIC MAP (
366 tech => inferred,
396 tech => inferred,
367 data_size => 6*16,
397 data_size => 6*16,
368 nb_data_by_buffer_size => nb_data_by_buffer_size,
398 nb_data_by_buffer_size => nb_data_by_buffer_size,
369 nb_word_by_buffer_size => nb_word_by_buffer_size,
399 nb_word_by_buffer_size => nb_word_by_buffer_size,
370 nb_snapshot_param_size => nb_snapshot_param_size,
400 nb_snapshot_param_size => nb_snapshot_param_size,
371 delta_vector_size => delta_vector_size,
401 delta_vector_size => delta_vector_size,
372 delta_vector_size_f0_2 => delta_vector_size_f0_2
402 delta_vector_size_f0_2 => delta_vector_size_f0_2
373 )
403 )
374 PORT MAP (
404 PORT MAP (
375 clk => clk,
405 clk => clk,
376 rstn => rstn,
406 rstn => rstn,
377
407
378 reg_run => run,
408 reg_run => run,
379 reg_start_date => start_date,
409 reg_start_date => start_date,
380 reg_delta_snapshot => delta_snapshot,
410 reg_delta_snapshot => delta_snapshot,
381 reg_delta_f0 => delta_f0,
411 reg_delta_f0 => delta_f0,
382 reg_delta_f0_2 => delta_f0_2,
412 reg_delta_f0_2 => delta_f0_2,
383 reg_delta_f1 => delta_f1,
413 reg_delta_f1 => delta_f1,
384 reg_delta_f2 => delta_f2,
414 reg_delta_f2 => delta_f2,
385
415
386 enable_f0 => enable_f0,
416 enable_f0 => enable_f0,
387 enable_f1 => enable_f1,
417 enable_f1 => enable_f1,
388 enable_f2 => enable_f2,
418 enable_f2 => enable_f2,
389 enable_f3 => enable_f3,
419 enable_f3 => enable_f3,
390 burst_f0 => burst_f0,
420 burst_f0 => burst_f0,
391 burst_f1 => burst_f1,
421 burst_f1 => burst_f1,
392 burst_f2 => burst_f2,
422 burst_f2 => burst_f2,
393
423
394 nb_data_by_buffer => nb_data_by_buffer,
424 nb_data_by_buffer => nb_data_by_buffer,
395 nb_word_by_buffer => nb_word_by_buffer,
425 nb_word_by_buffer => nb_word_by_buffer,
396 nb_snapshot_param => nb_snapshot_param,
426 nb_snapshot_param => nb_snapshot_param,
397 status_full => status_full,
427 status_full => status_full,
398 status_full_ack => status_full_ack,
428 status_full_ack => status_full_ack,
399 status_full_err => status_full_err,
429 status_full_err => status_full_err,
400 status_new_err => status_new_err,
430 status_new_err => status_new_err,
401
431
402 coarse_time => coarse_time,
432 coarse_time => coarse_time,
403 fine_time => fine_time,
433 fine_time => fine_time,
404
434
405 --f0
435 --f0
406 addr_data_f0 => addr_data_f0,
436 addr_data_f0 => addr_data_f0,
407 data_f0_in_valid => sample_f0_val,
437 data_f0_in_valid => sample_f0_val,
408 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
438 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
409 --f1
439 --f1
410 addr_data_f1 => addr_data_f1,
440 addr_data_f1 => addr_data_f1,
411 data_f1_in_valid => sample_f1_val,
441 data_f1_in_valid => sample_f1_val,
412 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
442 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
413 --f2
443 --f2
414 addr_data_f2 => addr_data_f2,
444 addr_data_f2 => addr_data_f2,
415 data_f2_in_valid => sample_f2_val,
445 data_f2_in_valid => sample_f2_val,
416 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
446 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
417 --f3
447 --f3
418 addr_data_f3 => addr_data_f3,
448 addr_data_f3 => addr_data_f3,
419 data_f3_in_valid => sample_f3_val,
449 data_f3_in_valid => sample_f3_val,
420 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
450 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
421 -- OUTPUT -- DMA interface
451 -- OUTPUT -- DMA interface
422 --f0
452 --f0
423 data_f0_addr_out => data_f0_addr_out_s,
453 data_f0_addr_out => data_f0_addr_out_s,
424 data_f0_data_out => data_f0_data_out,
454 data_f0_data_out => data_f0_data_out,
425 data_f0_data_out_valid => data_f0_data_out_valid_s,
455 data_f0_data_out_valid => data_f0_data_out_valid_s,
426 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
456 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst_s,
427 data_f0_data_out_ren => data_f0_data_out_ren,
457 data_f0_data_out_ren => data_f0_data_out_ren,
428 --f1
458 --f1
429 data_f1_addr_out => data_f1_addr_out_s,
459 data_f1_addr_out => data_f1_addr_out_s,
430 data_f1_data_out => data_f1_data_out,
460 data_f1_data_out => data_f1_data_out,
431 data_f1_data_out_valid => data_f1_data_out_valid_s,
461 data_f1_data_out_valid => data_f1_data_out_valid_s,
432 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
462 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst_s,
433 data_f1_data_out_ren => data_f1_data_out_ren,
463 data_f1_data_out_ren => data_f1_data_out_ren,
434 --f2
464 --f2
435 data_f2_addr_out => data_f2_addr_out_s,
465 data_f2_addr_out => data_f2_addr_out_s,
436 data_f2_data_out => data_f2_data_out,
466 data_f2_data_out => data_f2_data_out,
437 data_f2_data_out_valid => data_f2_data_out_valid_s,
467 data_f2_data_out_valid => data_f2_data_out_valid_s,
438 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
468 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst_s,
439 data_f2_data_out_ren => data_f2_data_out_ren,
469 data_f2_data_out_ren => data_f2_data_out_ren,
440 --f3
470 --f3
441 data_f3_addr_out => data_f3_addr_out_s,
471 data_f3_addr_out => data_f3_addr_out_s,
442 data_f3_data_out => data_f3_data_out,
472 data_f3_data_out => data_f3_data_out,
443 data_f3_data_out_valid => data_f3_data_out_valid_s,
473 data_f3_data_out_valid => data_f3_data_out_valid_s,
444 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
445 data_f3_data_out_ren => data_f3_data_out_ren,
475 data_f3_data_out_ren => data_f3_data_out_ren,
446
476
447 --debug
477 -- debug SNAPSHOT_OUT
448 debug_f0_data => debug_f0_data,
478 debug_f0_data => debug_f0_data,
449 debug_f0_data_valid => debug_f0_data_valid ,
479 debug_f0_data_valid => debug_f0_data_valid ,
450 debug_f1_data => debug_f1_data ,
480 debug_f1_data => debug_f1_data ,
451 debug_f1_data_valid => debug_f1_data_valid,
481 debug_f1_data_valid => debug_f1_data_valid,
452 debug_f2_data => debug_f2_data ,
482 debug_f2_data => debug_f2_data ,
453 debug_f2_data_valid => debug_f2_data_valid ,
483 debug_f2_data_valid => debug_f2_data_valid ,
454 debug_f3_data => debug_f3_data ,
484 debug_f3_data => debug_f3_data ,
455 debug_f3_data_valid => debug_f3_data_valid
485 debug_f3_data_valid => debug_f3_data_valid,
486
487 -- debug FIFO_IN
488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
456
496
457 );
497 );
458
498
459
499
460 -----------------------------------------------------------------------------
500 -----------------------------------------------------------------------------
501 -- DEBUG -- WFP OUT
502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
503 debug_f0_data_fifo_out <= data_f0_data_out;
504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
505 debug_f1_data_fifo_out <= data_f1_data_out;
506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
507 debug_f2_data_fifo_out <= data_f2_data_out;
508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
509 debug_f3_data_fifo_out <= data_f3_data_out;
510 -----------------------------------------------------------------------------
511
512
513 -----------------------------------------------------------------------------
461 -- TEMP
514 -- TEMP
462 -----------------------------------------------------------------------------
515 -----------------------------------------------------------------------------
463
516
464 PROCESS (clk, rstn)
517 PROCESS (clk, rstn)
465 BEGIN -- PROCESS
518 BEGIN -- PROCESS
466 IF rstn = '0' THEN -- asynchronous reset (active low)
519 IF rstn = '0' THEN -- asynchronous reset (active low)
467 data_f0_data_out_valid <= '0';
520 data_f0_data_out_valid <= '0';
468 data_f0_data_out_valid_burst <= '0';
521 data_f0_data_out_valid_burst <= '0';
469 data_f1_data_out_valid <= '0';
522 data_f1_data_out_valid <= '0';
470 data_f1_data_out_valid_burst <= '0';
523 data_f1_data_out_valid_burst <= '0';
471 data_f2_data_out_valid <= '0';
524 data_f2_data_out_valid <= '0';
472 data_f2_data_out_valid_burst <= '0';
525 data_f2_data_out_valid_burst <= '0';
473 data_f3_data_out_valid <= '0';
526 data_f3_data_out_valid <= '0';
474 data_f3_data_out_valid_burst <= '0';
527 data_f3_data_out_valid_burst <= '0';
475 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
528 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
476 data_f0_data_out_valid <= data_f0_data_out_valid_s;
529 data_f0_data_out_valid <= data_f0_data_out_valid_s;
477 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
530 data_f0_data_out_valid_burst <= data_f0_data_out_valid_burst_s;
478 data_f1_data_out_valid <= data_f1_data_out_valid_s;
531 data_f1_data_out_valid <= data_f1_data_out_valid_s;
479 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
532 data_f1_data_out_valid_burst <= data_f1_data_out_valid_burst_s;
480 data_f2_data_out_valid <= data_f2_data_out_valid_s;
533 data_f2_data_out_valid <= data_f2_data_out_valid_s;
481 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
534 data_f2_data_out_valid_burst <= data_f2_data_out_valid_burst_s;
482 data_f3_data_out_valid <= data_f3_data_out_valid_s;
535 data_f3_data_out_valid <= data_f3_data_out_valid_s;
483 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
536 data_f3_data_out_valid_burst <= data_f3_data_out_valid_burst_s;
484 END IF;
537 END IF;
485 END PROCESS;
538 END PROCESS;
486
539
487 data_f0_addr_out <= data_f0_addr_out_s;
540 data_f0_addr_out <= data_f0_addr_out_s;
488 data_f1_addr_out <= data_f1_addr_out_s;
541 data_f1_addr_out <= data_f1_addr_out_s;
489 data_f2_addr_out <= data_f2_addr_out_s;
542 data_f2_addr_out <= data_f2_addr_out_s;
490 data_f3_addr_out <= data_f3_addr_out_s;
543 data_f3_addr_out <= data_f3_addr_out_s;
491
544
492 -----------------------------------------------------------------------------
545 -----------------------------------------------------------------------------
493 -- RoundRobin Selection For DMA
546 -- RoundRobin Selection For DMA
494 -----------------------------------------------------------------------------
547 -----------------------------------------------------------------------------
495
548
496 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
549 dma_rr_valid(0) <= data_f0_data_out_valid OR data_f0_data_out_valid_burst;
497 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
550 dma_rr_valid(1) <= data_f1_data_out_valid OR data_f1_data_out_valid_burst;
498 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
551 dma_rr_valid(2) <= data_f2_data_out_valid OR data_f2_data_out_valid_burst;
499 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
552 dma_rr_valid(3) <= data_f3_data_out_valid OR data_f3_data_out_valid_burst;
500
553
501 RR_Arbiter_4_1 : RR_Arbiter_4
554 RR_Arbiter_4_1 : RR_Arbiter_4
502 PORT MAP (
555 PORT MAP (
503 clk => clk,
556 clk => clk,
504 rstn => rstn,
557 rstn => rstn,
505 in_valid => dma_rr_valid,
558 in_valid => dma_rr_valid,
506 out_grant => dma_rr_grant);
559 out_grant => dma_rr_grant);
507
560
508
561
509 -----------------------------------------------------------------------------
562 -----------------------------------------------------------------------------
510 -- in : dma_rr_grant
563 -- in : dma_rr_grant
511 -- send
564 -- send
512 -- out : dma_sel
565 -- out : dma_sel
513 -- dma_valid_burst
566 -- dma_valid_burst
514 -- dma_sel_valid
567 -- dma_sel_valid
515 -----------------------------------------------------------------------------
568 -----------------------------------------------------------------------------
516 PROCESS (clk, rstn)
569 PROCESS (clk, rstn)
517 BEGIN -- PROCESS
570 BEGIN -- PROCESS
518 IF rstn = '0' THEN -- asynchronous reset (active low)
571 IF rstn = '0' THEN -- asynchronous reset (active low)
519 dma_sel <= (OTHERS => '0');
572 dma_sel <= (OTHERS => '0');
520 dma_send <= '0';
573 dma_send <= '0';
521 dma_valid_burst <= '0';
574 dma_valid_burst <= '0';
522 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
575 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
523 -- IF dma_sel = "0000" OR dma_send = '1' THEN
576 -- IF dma_sel = "0000" OR dma_send = '1' THEN
524 IF dma_sel = "0000" OR dma_done = '1' THEN
577 IF dma_sel = "0000" OR dma_done = '1' THEN
525 dma_sel <= dma_rr_grant;
578 dma_sel <= dma_rr_grant;
526 IF dma_rr_grant(0) = '1' THEN
579 IF dma_rr_grant(0) = '1' THEN
527 dma_send <= '1';
580 dma_send <= '1';
528 dma_valid_burst <= data_f0_data_out_valid_burst;
581 dma_valid_burst <= data_f0_data_out_valid_burst;
529 dma_sel_valid <= data_f0_data_out_valid;
582 dma_sel_valid <= data_f0_data_out_valid;
530 ELSIF dma_rr_grant(1) = '1' THEN
583 ELSIF dma_rr_grant(1) = '1' THEN
531 dma_send <= '1';
584 dma_send <= '1';
532 dma_valid_burst <= data_f1_data_out_valid_burst;
585 dma_valid_burst <= data_f1_data_out_valid_burst;
533 dma_sel_valid <= data_f1_data_out_valid;
586 dma_sel_valid <= data_f1_data_out_valid;
534 ELSIF dma_rr_grant(2) = '1' THEN
587 ELSIF dma_rr_grant(2) = '1' THEN
535 dma_send <= '1';
588 dma_send <= '1';
536 dma_valid_burst <= data_f2_data_out_valid_burst;
589 dma_valid_burst <= data_f2_data_out_valid_burst;
537 dma_sel_valid <= data_f2_data_out_valid;
590 dma_sel_valid <= data_f2_data_out_valid;
538 ELSIF dma_rr_grant(3) = '1' THEN
591 ELSIF dma_rr_grant(3) = '1' THEN
539 dma_send <= '1';
592 dma_send <= '1';
540 dma_valid_burst <= data_f3_data_out_valid_burst;
593 dma_valid_burst <= data_f3_data_out_valid_burst;
541 dma_sel_valid <= data_f3_data_out_valid;
594 dma_sel_valid <= data_f3_data_out_valid;
542 END IF;
595 END IF;
543 ELSE
596 ELSE
544 dma_sel <= dma_sel;
597 dma_sel <= dma_sel;
545 dma_send <= '0';
598 dma_send <= '0';
546 END IF;
599 END IF;
547 END IF;
600 END IF;
548 END PROCESS;
601 END PROCESS;
549
602
550
603
551 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
604 dma_address <= data_f0_addr_out WHEN dma_sel(0) = '1' ELSE
552 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
605 data_f1_addr_out WHEN dma_sel(1) = '1' ELSE
553 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
606 data_f2_addr_out WHEN dma_sel(2) = '1' ELSE
554 data_f3_addr_out;
607 data_f3_addr_out;
555
608
556 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
609 dma_data <= data_f0_data_out WHEN dma_sel(0) = '1' ELSE
557 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
610 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
558 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
611 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
559 data_f3_data_out;
612 data_f3_data_out;
560
561 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
562 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
563 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
564 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
565 -- '0';
566
567 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
568 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
569 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
570 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
571 -- '0';
572
573 -- TODO
574 --dma_send <= dma_sel_valid OR dma_valid_burst;
575
576 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
577 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
578 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
579 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
580
613
581 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
614 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
582 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
615 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
583 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
616 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
584 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
617 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
585
618
619 dma_data_2 <= dma_data;
586
620
587 --PROCESS (clk, rstn)
588 --BEGIN -- PROCESS
589 -- IF rstn = '0' THEN -- asynchronous reset (active low)
590 -- ongoing_reg <= '0';
591 -- dma_sel_reg <= (OTHERS => '0');
592 -- dma_send_reg <= '0';
593 -- dma_valid_burst_reg <= '0';
594 -- dma_address_reg <= (OTHERS => '0');
595 -- dma_data_reg <= (OTHERS => '0');
596 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
597 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
598 -- ongoing_reg <= '1';
599 -- dma_valid_burst_reg <= dma_valid_burst;
600 -- dma_sel_reg <= dma_sel;
601 -- ELSE
602 -- IF dma_done = '1' THEN
603 -- ongoing_reg <= '0';
604 -- END IF;
605 -- END IF;
606 -- dma_send_reg <= dma_send;
607 -- dma_address_reg <= dma_address;
608 -- dma_data_reg <= dma_data;
609 -- END IF;
610 --END PROCESS;
611
621
612 dma_data_2 <= dma_data;
622
613 --PROCESS (clk, rstn)
614 --BEGIN -- PROCESS
615 -- IF rstn = '0' THEN -- asynchronous reset (active low)
616 -- dma_data_2 <= (OTHERS => '0');
617 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
618 -- dma_data_2 <= dma_data;
619
620 -- END IF;
621 --END PROCESS;
622
623
623
624
624 -----------------------------------------------------------------------------
625 -----------------------------------------------------------------------------
626 -- DEBUG -- DMA IN
627 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
628 debug_f0_data_dma_in <= dma_data;
629 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
630 debug_f1_data_dma_in <= dma_data;
631 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
632 debug_f2_data_dma_in <= dma_data;
633 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
634 debug_f3_data_dma_in <= dma_data;
635 -----------------------------------------------------------------------------
636
637 -----------------------------------------------------------------------------
625 -- DMA
638 -- DMA
626 -----------------------------------------------------------------------------
639 -----------------------------------------------------------------------------
627 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
640 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
628 GENERIC MAP (
641 GENERIC MAP (
629 tech => inferred,
642 tech => inferred,
630 hindex => hindex)
643 hindex => hindex)
631 PORT MAP (
644 PORT MAP (
632 HCLK => clk,
645 HCLK => clk,
633 HRESETn => rstn,
646 HRESETn => rstn,
634 run => run,
647 run => run,
635 AHB_Master_In => ahbi,
648 AHB_Master_In => ahbi,
636 AHB_Master_Out => ahbo,
649 AHB_Master_Out => ahbo,
637
650
638 send => dma_send, --_reg,
651 send => dma_send,
639 valid_burst => dma_valid_burst, --_reg,
652 valid_burst => dma_valid_burst,
640 done => dma_done,
653 done => dma_done,
641 ren => dma_ren,
654 ren => dma_ren,
642 address => dma_address, --_reg,
655 address => dma_address,
643 data => dma_data_2); --_reg);
656 data => dma_data_2);
644
657
645 -----------------------------------------------------------------------------
658 -----------------------------------------------------------------------------
646 -- Matrix Spectral - TODO
659 -- Matrix Spectral - TODO
647 -----------------------------------------------------------------------------
660 -----------------------------------------------------------------------------
648 -----------------------------------------------------------------------------
661 -----------------------------------------------------------------------------
649 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
662 --sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
650 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
663 -- NOT(sample_f0_val) & NOT(sample_f0_val) ;
651 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
664 --sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
652 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
665 -- NOT(sample_f1_val) & NOT(sample_f1_val) ;
653 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
666 --sample_f3_wen <= NOT(sample_f3_val) & NOT(sample_f3_val) & NOT(sample_f3_val) &
654 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
667 -- NOT(sample_f3_val) & NOT(sample_f3_val) ;
655
668
656 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
669 --sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16)); -- (MSB) E2 E1 B2 B1 B0 (LSB)
657 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
670 --sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
658 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
671 --sample_f3_wdata <= sample_f3_data((3*16)-1 DOWNTO (1*16)) & sample_f3_data((6*16)-1 DOWNTO (3*16));
659 -------------------------------------------------------------------------------
672 -------------------------------------------------------------------------------
660 --lpp_lfr_ms_1: lpp_lfr_ms
673 --lpp_lfr_ms_1: lpp_lfr_ms
661 -- GENERIC MAP (
674 -- GENERIC MAP (
662 -- hindex => hindex_ms)
675 -- hindex => hindex_ms)
663 -- PORT MAP (
676 -- PORT MAP (
664 -- clk => clk,
677 -- clk => clk,
665 -- rstn => rstn,
678 -- rstn => rstn,
666 -- sample_f0_wen => sample_f0_wen,
679 -- sample_f0_wen => sample_f0_wen,
667 -- sample_f0_wdata => sample_f0_wdata,
680 -- sample_f0_wdata => sample_f0_wdata,
668 -- sample_f1_wen => sample_f1_wen,
681 -- sample_f1_wen => sample_f1_wen,
669 -- sample_f1_wdata => sample_f1_wdata,
682 -- sample_f1_wdata => sample_f1_wdata,
670 -- sample_f3_wen => sample_f3_wen,
683 -- sample_f3_wen => sample_f3_wen,
671 -- sample_f3_wdata => sample_f3_wdata,
684 -- sample_f3_wdata => sample_f3_wdata,
672 -- AHB_Master_In => ahbi_ms,
685 -- AHB_Master_In => ahbi_ms,
673 -- AHB_Master_Out => ahbo_ms,
686 -- AHB_Master_Out => ahbo_ms,
674
687
675 -- ready_matrix_f0_0 => ready_matrix_f0_0,
688 -- ready_matrix_f0_0 => ready_matrix_f0_0,
676 -- ready_matrix_f0_1 => ready_matrix_f0_1,
689 -- ready_matrix_f0_1 => ready_matrix_f0_1,
677 -- ready_matrix_f1 => ready_matrix_f1,
690 -- ready_matrix_f1 => ready_matrix_f1,
678 -- ready_matrix_f2 => ready_matrix_f2,
691 -- ready_matrix_f2 => ready_matrix_f2,
679 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
692 -- error_anticipating_empty_fifo => error_anticipating_empty_fifo,
680 -- error_bad_component_error => error_bad_component_error,
693 -- error_bad_component_error => error_bad_component_error,
681 -- debug_reg => debug_reg,
694 -- debug_reg => debug_reg,
682 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
695 -- status_ready_matrix_f0_0 => status_ready_matrix_f0_0,
683 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
696 -- status_ready_matrix_f0_1 => status_ready_matrix_f0_1,
684 -- status_ready_matrix_f1 => status_ready_matrix_f1,
697 -- status_ready_matrix_f1 => status_ready_matrix_f1,
685 -- status_ready_matrix_f2 => status_ready_matrix_f2,
698 -- status_ready_matrix_f2 => status_ready_matrix_f2,
686 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
699 -- status_error_anticipating_empty_fifo => status_error_anticipating_empty_fifo,
687 -- status_error_bad_component_error => status_error_bad_component_error,
700 -- status_error_bad_component_error => status_error_bad_component_error,
688 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
701 -- config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
689 -- config_active_interruption_onError => config_active_interruption_onError,
702 -- config_active_interruption_onError => config_active_interruption_onError,
690 -- addr_matrix_f0_0 => addr_matrix_f0_0,
703 -- addr_matrix_f0_0 => addr_matrix_f0_0,
691 -- addr_matrix_f0_1 => addr_matrix_f0_1,
704 -- addr_matrix_f0_1 => addr_matrix_f0_1,
692 -- addr_matrix_f1 => addr_matrix_f1,
705 -- addr_matrix_f1 => addr_matrix_f1,
693 -- addr_matrix_f2 => addr_matrix_f2);
706 -- addr_matrix_f2 => addr_matrix_f2);
694
707
695 END beh;
708 END beh;
Show file before | Show file after | Hide comments
@@ -1,493 +1,493
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
24 USE ieee.std_logic_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 LIBRARY lpp;
30 LIBRARY lpp;
31 USE lpp.lpp_amba.ALL;
31 USE lpp.lpp_amba.ALL;
32 USE lpp.apb_devices_list.ALL;
32 USE lpp.apb_devices_list.ALL;
33 USE lpp.lpp_memory.ALL;
33 USE lpp.lpp_memory.ALL;
34 LIBRARY techmap;
34 LIBRARY techmap;
35 USE techmap.gencomp.ALL;
35 USE techmap.gencomp.ALL;
36
36
37 ENTITY lpp_lfr_apbreg IS
37 ENTITY lpp_lfr_apbreg IS
38 GENERIC (
38 GENERIC (
39 nb_data_by_buffer_size : INTEGER := 11;
39 nb_data_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
40 nb_word_by_buffer_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
41 nb_snapshot_param_size : INTEGER := 11;
42 delta_vector_size : INTEGER := 20;
42 delta_vector_size : INTEGER := 20;
43 delta_vector_size_f0_2 : INTEGER := 3;
43 delta_vector_size_f0_2 : INTEGER := 3;
44
44
45 pindex : INTEGER := 4;
45 pindex : INTEGER := 4;
46 paddr : INTEGER := 4;
46 paddr : INTEGER := 4;
47 pmask : INTEGER := 16#fff#;
47 pmask : INTEGER := 16#fff#;
48 pirq_ms : INTEGER := 0;
48 pirq_ms : INTEGER := 0;
49 pirq_wfp : INTEGER := 1;
49 pirq_wfp : INTEGER := 1;
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
50 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
51 PORT (
51 PORT (
52 -- AMBA AHB system signals
52 -- AMBA AHB system signals
53 HCLK : IN STD_ULOGIC;
53 HCLK : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
54 HRESETn : IN STD_ULOGIC;
55
55
56 -- AMBA APB Slave Interface
56 -- AMBA APB Slave Interface
57 apbi : IN apb_slv_in_type;
57 apbi : IN apb_slv_in_type;
58 apbo : OUT apb_slv_out_type;
58 apbo : OUT apb_slv_out_type;
59
59
60 ---------------------------------------------------------------------------
60 ---------------------------------------------------------------------------
61 -- Spectral Matrix Reg
61 -- Spectral Matrix Reg
62 -- IN
62 -- IN
63 ready_matrix_f0_0 : IN STD_LOGIC;
63 ready_matrix_f0_0 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
64 ready_matrix_f0_1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
65 ready_matrix_f1 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
66 ready_matrix_f2 : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
67 error_anticipating_empty_fifo : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
68 error_bad_component_error : IN STD_LOGIC;
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
69 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
70
70
71 -- OUT
71 -- OUT
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
72 status_ready_matrix_f0_0 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
73 status_ready_matrix_f0_1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
74 status_ready_matrix_f1 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
75 status_ready_matrix_f2 : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
76 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
77 status_error_bad_component_error : OUT STD_LOGIC;
78
78
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
79 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
80 config_active_interruption_onError : OUT STD_LOGIC;
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
81 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
83 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
84 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
85 ---------------------------------------------------------------------------
85 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
86 ---------------------------------------------------------------------------
87 -- WaveForm picker Reg
87 -- WaveForm picker Reg
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
88 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
89 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
90 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
91 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
92
92
93 -- OUT
93 -- OUT
94 data_shaping_BW : OUT STD_LOGIC;
94 data_shaping_BW : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
95 data_shaping_SP0 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
96 data_shaping_SP1 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
97 data_shaping_R0 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
98 data_shaping_R1 : OUT STD_LOGIC;
99
99
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
100 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
101 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
102 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
103 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
104 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
105 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
106 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
107 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
108
108
109 enable_f0 : OUT STD_LOGIC;
109 enable_f0 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
110 enable_f1 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
111 enable_f2 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
112 enable_f3 : OUT STD_LOGIC;
113
113
114 burst_f0 : OUT STD_LOGIC;
114 burst_f0 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
115 burst_f1 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
116 burst_f2 : OUT STD_LOGIC;
117
117
118 run : OUT STD_LOGIC;
118 run : OUT STD_LOGIC;
119
119
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
123 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
124 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
125 ---------------------------------------------------------------------------
125 ---------------------------------------------------------------------------
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
127 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
129 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
131 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
133 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
134
134
135 ---------------------------------------------------------------------------
135 ---------------------------------------------------------------------------
136 );
136 );
137
137
138 END lpp_lfr_apbreg;
138 END lpp_lfr_apbreg;
139
139
140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
140 ARCHITECTURE beh OF lpp_lfr_apbreg IS
141
141
142 CONSTANT REVISION : INTEGER := 1;
142 CONSTANT REVISION : INTEGER := 1;
143
143
144 CONSTANT pconfig : apb_config_type := (
144 CONSTANT pconfig : apb_config_type := (
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
146 1 => apb_iobar(paddr, pmask));
146 1 => apb_iobar(paddr, pmask));
147
147
148 TYPE lpp_SpectralMatrix_regs IS RECORD
148 TYPE lpp_SpectralMatrix_regs IS RECORD
149 config_active_interruption_onNewMatrix : STD_LOGIC;
149 config_active_interruption_onNewMatrix : STD_LOGIC;
150 config_active_interruption_onError : STD_LOGIC;
150 config_active_interruption_onError : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
151 status_ready_matrix_f0_0 : STD_LOGIC;
152 status_ready_matrix_f0_1 : STD_LOGIC;
152 status_ready_matrix_f0_1 : STD_LOGIC;
153 status_ready_matrix_f1 : STD_LOGIC;
153 status_ready_matrix_f1 : STD_LOGIC;
154 status_ready_matrix_f2 : STD_LOGIC;
154 status_ready_matrix_f2 : STD_LOGIC;
155 status_error_anticipating_empty_fifo : STD_LOGIC;
155 status_error_anticipating_empty_fifo : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
156 status_error_bad_component_error : STD_LOGIC;
157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
157 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
158 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
159 addr_matrix_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
160 addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
161 END RECORD;
161 END RECORD;
162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
162 SIGNAL reg_sp : lpp_SpectralMatrix_regs;
163
163
164 TYPE lpp_WaveformPicker_regs IS RECORD
164 TYPE lpp_WaveformPicker_regs IS RECORD
165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 status_full : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 data_shaping_BW : STD_LOGIC;
168 data_shaping_BW : STD_LOGIC;
169 data_shaping_SP0 : STD_LOGIC;
169 data_shaping_SP0 : STD_LOGIC;
170 data_shaping_SP1 : STD_LOGIC;
170 data_shaping_SP1 : STD_LOGIC;
171 data_shaping_R0 : STD_LOGIC;
171 data_shaping_R0 : STD_LOGIC;
172 data_shaping_R1 : STD_LOGIC;
172 data_shaping_R1 : STD_LOGIC;
173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
173 delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
174 delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
175 delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
176 delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
177 delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
178 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
179 nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
180 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
181 enable_f0 : STD_LOGIC;
181 enable_f0 : STD_LOGIC;
182 enable_f1 : STD_LOGIC;
182 enable_f1 : STD_LOGIC;
183 enable_f2 : STD_LOGIC;
183 enable_f2 : STD_LOGIC;
184 enable_f3 : STD_LOGIC;
184 enable_f3 : STD_LOGIC;
185 burst_f0 : STD_LOGIC;
185 burst_f0 : STD_LOGIC;
186 burst_f1 : STD_LOGIC;
186 burst_f1 : STD_LOGIC;
187 burst_f2 : STD_LOGIC;
187 burst_f2 : STD_LOGIC;
188 run : STD_LOGIC;
188 run : STD_LOGIC;
189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
189 addr_data_f0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
190 addr_data_f1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
191 addr_data_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
192 addr_data_f3 : STD_LOGIC_VECTOR(31 DOWNTO 0);
193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
193 start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
194 END RECORD;
194 END RECORD;
195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
195 SIGNAL reg_wp : lpp_WaveformPicker_regs;
196
196
197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
197 SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
198
198
199 -----------------------------------------------------------------------------
199 -----------------------------------------------------------------------------
200 -- IRQ
200 -- IRQ
201 -----------------------------------------------------------------------------
201 -----------------------------------------------------------------------------
202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
202 CONSTANT IRQ_WFP_SIZE : INTEGER := 12;
203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
203 SIGNAL irq_wfp_ZERO : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
204 SIGNAL irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
205 SIGNAL irq_wfp_reg : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
206 SIGNAL irq_wfp : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
207 SIGNAL ored_irq_wfp : STD_LOGIC;
207 SIGNAL ored_irq_wfp : STD_LOGIC;
208
208
209 BEGIN -- beh
209 BEGIN -- beh
210
210
211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
211 status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0;
212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
212 status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1;
213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
213 status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
214 status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
215 status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo;
216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
216 status_error_bad_component_error <= reg_sp.status_error_bad_component_error;
217
217
218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
218 config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
219 config_active_interruption_onError <= reg_sp.config_active_interruption_onError;
220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
220 addr_matrix_f0_0 <= reg_sp.addr_matrix_f0_0;
221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
221 addr_matrix_f0_1 <= reg_sp.addr_matrix_f0_1;
222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
222 addr_matrix_f1 <= reg_sp.addr_matrix_f1;
223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
223 addr_matrix_f2 <= reg_sp.addr_matrix_f2;
224
224
225
225
226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
226 data_shaping_BW <= NOT reg_wp.data_shaping_BW;
227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
227 data_shaping_SP0 <= reg_wp.data_shaping_SP0;
228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
228 data_shaping_SP1 <= reg_wp.data_shaping_SP1;
229 data_shaping_R0 <= reg_wp.data_shaping_R0;
229 data_shaping_R0 <= reg_wp.data_shaping_R0;
230 data_shaping_R1 <= reg_wp.data_shaping_R1;
230 data_shaping_R1 <= reg_wp.data_shaping_R1;
231
231
232 delta_snapshot <= reg_wp.delta_snapshot;
232 delta_snapshot <= reg_wp.delta_snapshot;
233 delta_f0 <= reg_wp.delta_f0;
233 delta_f0 <= reg_wp.delta_f0;
234 delta_f0_2 <= reg_wp.delta_f0_2;
234 delta_f0_2 <= reg_wp.delta_f0_2;
235 delta_f1 <= reg_wp.delta_f1;
235 delta_f1 <= reg_wp.delta_f1;
236 delta_f2 <= reg_wp.delta_f2;
236 delta_f2 <= reg_wp.delta_f2;
237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
237 nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
238 nb_word_by_buffer <= reg_wp.nb_word_by_buffer;
239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
239 nb_snapshot_param <= reg_wp.nb_snapshot_param;
240
240
241 enable_f0 <= reg_wp.enable_f0;
241 enable_f0 <= reg_wp.enable_f0;
242 enable_f1 <= reg_wp.enable_f1;
242 enable_f1 <= reg_wp.enable_f1;
243 enable_f2 <= reg_wp.enable_f2;
243 enable_f2 <= reg_wp.enable_f2;
244 enable_f3 <= reg_wp.enable_f3;
244 enable_f3 <= reg_wp.enable_f3;
245
245
246 burst_f0 <= reg_wp.burst_f0;
246 burst_f0 <= reg_wp.burst_f0;
247 burst_f1 <= reg_wp.burst_f1;
247 burst_f1 <= reg_wp.burst_f1;
248 burst_f2 <= reg_wp.burst_f2;
248 burst_f2 <= reg_wp.burst_f2;
249
249
250 run <= reg_wp.run;
250 run <= reg_wp.run;
251
251
252 addr_data_f0 <= reg_wp.addr_data_f0;
252 addr_data_f0 <= reg_wp.addr_data_f0;
253 addr_data_f1 <= reg_wp.addr_data_f1;
253 addr_data_f1 <= reg_wp.addr_data_f1;
254 addr_data_f2 <= reg_wp.addr_data_f2;
254 addr_data_f2 <= reg_wp.addr_data_f2;
255 addr_data_f3 <= reg_wp.addr_data_f3;
255 addr_data_f3 <= reg_wp.addr_data_f3;
256
256
257 start_date <= reg_wp.start_date;
257 start_date <= reg_wp.start_date;
258
258
259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
259 lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
260 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
261 BEGIN -- PROCESS lpp_dma_top
261 BEGIN -- PROCESS lpp_dma_top
262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
262 IF HRESETn = '0' THEN -- asynchronous reset (active low)
263 reg_sp.config_active_interruption_onNewMatrix <= '0';
263 reg_sp.config_active_interruption_onNewMatrix <= '0';
264 reg_sp.config_active_interruption_onError <= '0';
264 reg_sp.config_active_interruption_onError <= '0';
265 reg_sp.status_ready_matrix_f0_0 <= '0';
265 reg_sp.status_ready_matrix_f0_0 <= '0';
266 reg_sp.status_ready_matrix_f0_1 <= '0';
266 reg_sp.status_ready_matrix_f0_1 <= '0';
267 reg_sp.status_ready_matrix_f1 <= '0';
267 reg_sp.status_ready_matrix_f1 <= '0';
268 reg_sp.status_ready_matrix_f2 <= '0';
268 reg_sp.status_ready_matrix_f2 <= '0';
269 reg_sp.status_error_anticipating_empty_fifo <= '0';
269 reg_sp.status_error_anticipating_empty_fifo <= '0';
270 reg_sp.status_error_bad_component_error <= '0';
270 reg_sp.status_error_bad_component_error <= '0';
271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
271 reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
272 reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
273 reg_sp.addr_matrix_f1 <= (OTHERS => '0');
274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
274 reg_sp.addr_matrix_f2 <= (OTHERS => '0');
275 prdata <= (OTHERS => '0');
275 prdata <= (OTHERS => '0');
276
276
277 apbo.pirq <= (OTHERS => '0');
277 apbo.pirq <= (OTHERS => '0');
278
278
279 status_full_ack <= (OTHERS => '0');
279 status_full_ack <= (OTHERS => '0');
280
280
281 reg_wp.data_shaping_BW <= '0';
281 reg_wp.data_shaping_BW <= '0';
282 reg_wp.data_shaping_SP0 <= '0';
282 reg_wp.data_shaping_SP0 <= '0';
283 reg_wp.data_shaping_SP1 <= '0';
283 reg_wp.data_shaping_SP1 <= '0';
284 reg_wp.data_shaping_R0 <= '0';
284 reg_wp.data_shaping_R0 <= '0';
285 reg_wp.data_shaping_R1 <= '0';
285 reg_wp.data_shaping_R1 <= '0';
286 reg_wp.enable_f0 <= '0';
286 reg_wp.enable_f0 <= '0';
287 reg_wp.enable_f1 <= '0';
287 reg_wp.enable_f1 <= '0';
288 reg_wp.enable_f2 <= '0';
288 reg_wp.enable_f2 <= '0';
289 reg_wp.enable_f3 <= '0';
289 reg_wp.enable_f3 <= '0';
290 reg_wp.burst_f0 <= '0';
290 reg_wp.burst_f0 <= '0';
291 reg_wp.burst_f1 <= '0';
291 reg_wp.burst_f1 <= '0';
292 reg_wp.burst_f2 <= '0';
292 reg_wp.burst_f2 <= '0';
293 reg_wp.run <= '0';
293 reg_wp.run <= '0';
294 reg_wp.addr_data_f0 <= (OTHERS => '0');
294 reg_wp.addr_data_f0 <= (OTHERS => '0');
295 reg_wp.addr_data_f1 <= (OTHERS => '0');
295 reg_wp.addr_data_f1 <= (OTHERS => '0');
296 reg_wp.addr_data_f2 <= (OTHERS => '0');
296 reg_wp.addr_data_f2 <= (OTHERS => '0');
297 reg_wp.addr_data_f3 <= (OTHERS => '0');
297 reg_wp.addr_data_f3 <= (OTHERS => '0');
298 reg_wp.status_full <= (OTHERS => '0');
298 reg_wp.status_full <= (OTHERS => '0');
299 reg_wp.status_full_err <= (OTHERS => '0');
299 reg_wp.status_full_err <= (OTHERS => '0');
300 reg_wp.status_new_err <= (OTHERS => '0');
300 reg_wp.status_new_err <= (OTHERS => '0');
301 reg_wp.delta_snapshot <= (OTHERS => '0');
301 reg_wp.delta_snapshot <= (OTHERS => '0');
302 reg_wp.delta_f0 <= (OTHERS => '0');
302 reg_wp.delta_f0 <= (OTHERS => '0');
303 reg_wp.delta_f0_2 <= (OTHERS => '0');
303 reg_wp.delta_f0_2 <= (OTHERS => '0');
304 reg_wp.delta_f1 <= (OTHERS => '0');
304 reg_wp.delta_f1 <= (OTHERS => '0');
305 reg_wp.delta_f2 <= (OTHERS => '0');
305 reg_wp.delta_f2 <= (OTHERS => '0');
306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
306 reg_wp.nb_data_by_buffer <= (OTHERS => '0');
307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
307 reg_wp.nb_snapshot_param <= (OTHERS => '0');
308 reg_wp.start_date <= (OTHERS => '0');
308 reg_wp.start_date <= (OTHERS => '0');
309
309
310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
310 ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge
311 status_full_ack <= (OTHERS => '0');
311 status_full_ack <= (OTHERS => '0');
312
312
313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
313 reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR ready_matrix_f0_0;
314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
314 reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR ready_matrix_f0_1;
315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
315 reg_sp.status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1 OR ready_matrix_f1;
316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
316 reg_sp.status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2 OR ready_matrix_f2;
317
317
318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
318 reg_sp.status_error_anticipating_empty_fifo <= reg_sp.status_error_anticipating_empty_fifo OR error_anticipating_empty_fifo;
319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
319 reg_sp.status_error_bad_component_error <= reg_sp.status_error_bad_component_error OR error_bad_component_error;
320 all_status: FOR I IN 3 DOWNTO 0 LOOP
320 all_status: FOR I IN 3 DOWNTO 0 LOOP
321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
321 --reg_wp.status_full(I) <= (reg_wp.status_full(I) OR status_full(I)) AND reg_wp.run;
322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
322 --reg_wp.status_full_err(I) <= (reg_wp.status_full_err(I) OR status_full_err(I)) AND reg_wp.run;
323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
323 --reg_wp.status_new_err(I) <= (reg_wp.status_new_err(I) OR status_new_err(I)) AND reg_wp.run ;
324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
324 reg_wp.status_full(I) <= status_full(I) AND reg_wp.run;
325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
325 reg_wp.status_full_err(I) <= status_full_err(I) AND reg_wp.run;
326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
326 reg_wp.status_new_err(I) <= status_new_err(I) AND reg_wp.run ;
327 END LOOP all_status;
327 END LOOP all_status;
328
328
329 paddr := "000000";
329 paddr := "000000";
330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
330 paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
331 prdata <= (OTHERS => '0');
331 prdata <= (OTHERS => '0');
332 IF apbi.psel(pindex) = '1' THEN
332 IF apbi.psel(pindex) = '1' THEN
333 -- APB DMA READ --
333 -- APB DMA READ --
334 CASE paddr(7 DOWNTO 2) IS
334 CASE paddr(7 DOWNTO 2) IS
335 --
335 --
336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
336 WHEN "000000" => prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
337 prdata(1) <= reg_sp.config_active_interruption_onError;
337 prdata(1) <= reg_sp.config_active_interruption_onError;
338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
338 WHEN "000001" => prdata(0) <= reg_sp.status_ready_matrix_f0_0;
339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
339 prdata(1) <= reg_sp.status_ready_matrix_f0_1;
340 prdata(2) <= reg_sp.status_ready_matrix_f1;
340 prdata(2) <= reg_sp.status_ready_matrix_f1;
341 prdata(3) <= reg_sp.status_ready_matrix_f2;
341 prdata(3) <= reg_sp.status_ready_matrix_f2;
342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
342 prdata(4) <= reg_sp.status_error_anticipating_empty_fifo;
343 prdata(5) <= reg_sp.status_error_bad_component_error;
343 prdata(5) <= reg_sp.status_error_bad_component_error;
344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
344 WHEN "000010" => prdata <= reg_sp.addr_matrix_f0_0;
345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
345 WHEN "000011" => prdata <= reg_sp.addr_matrix_f0_1;
346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
346 WHEN "000100" => prdata <= reg_sp.addr_matrix_f1;
347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
347 WHEN "000101" => prdata <= reg_sp.addr_matrix_f2;
348 WHEN "000110" => prdata <= debug_reg;
348 WHEN "000110" => prdata <= debug_reg;
349 --
349 --
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
350 WHEN "001000" => prdata(0) <= reg_wp.data_shaping_BW;
351 prdata(1) <= reg_wp.data_shaping_SP0;
351 prdata(1) <= reg_wp.data_shaping_SP0;
352 prdata(2) <= reg_wp.data_shaping_SP1;
352 prdata(2) <= reg_wp.data_shaping_SP1;
353 prdata(3) <= reg_wp.data_shaping_R0;
353 prdata(3) <= reg_wp.data_shaping_R0;
354 prdata(4) <= reg_wp.data_shaping_R1;
354 prdata(4) <= reg_wp.data_shaping_R1;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
355 WHEN "001001" => prdata(0) <= reg_wp.enable_f0;
356 prdata(1) <= reg_wp.enable_f1;
356 prdata(1) <= reg_wp.enable_f1;
357 prdata(2) <= reg_wp.enable_f2;
357 prdata(2) <= reg_wp.enable_f2;
358 prdata(3) <= reg_wp.enable_f3;
358 prdata(3) <= reg_wp.enable_f3;
359 prdata(4) <= reg_wp.burst_f0;
359 prdata(4) <= reg_wp.burst_f0;
360 prdata(5) <= reg_wp.burst_f1;
360 prdata(5) <= reg_wp.burst_f1;
361 prdata(6) <= reg_wp.burst_f2;
361 prdata(6) <= reg_wp.burst_f2;
362 prdata(7) <= reg_wp.run;
362 prdata(7) <= reg_wp.run;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
363 WHEN "001010" => prdata <= reg_wp.addr_data_f0;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
364 WHEN "001011" => prdata <= reg_wp.addr_data_f1;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
365 WHEN "001100" => prdata <= reg_wp.addr_data_f2;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
366 WHEN "001101" => prdata <= reg_wp.addr_data_f3;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
367 WHEN "001110" => prdata(3 DOWNTO 0) <= reg_wp.status_full;
368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
368 prdata(7 DOWNTO 4) <= reg_wp.status_full_err;
369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
369 prdata(11 DOWNTO 8) <= reg_wp.status_new_err;
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
370 WHEN "001111" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot;
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
371 WHEN "010000" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0;
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
372 WHEN "010001" => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
373 WHEN "010010" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1;
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
374 WHEN "010011" => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2;
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
375 WHEN "010100" => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
376 WHEN "010101" => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
377 WHEN "010110" => prdata(30 DOWNTO 0) <= reg_wp.start_date;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
378 WHEN "010111" => prdata(nb_word_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_word_by_buffer;
379 ----------------------------------------------------
379 ----------------------------------------------------
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
380 WHEN "100000" => prdata(31 DOWNTO 0) <= debug_reg0(31 DOWNTO 0);
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
381 WHEN "100001" => prdata(31 DOWNTO 0) <= debug_reg1(31 DOWNTO 0);
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
382 WHEN "100010" => prdata(31 DOWNTO 0) <= debug_reg2(31 DOWNTO 0);
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
383 WHEN "100011" => prdata(31 DOWNTO 0) <= debug_reg3(31 DOWNTO 0);
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
384 WHEN "100100" => prdata(31 DOWNTO 0) <= debug_reg4(31 DOWNTO 0);
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
385 WHEN "100101" => prdata(31 DOWNTO 0) <= debug_reg5(31 DOWNTO 0);
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
386 WHEN "100110" => prdata(31 DOWNTO 0) <= debug_reg6(31 DOWNTO 0);
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
387 WHEN "100111" => prdata(31 DOWNTO 0) <= debug_reg7(31 DOWNTO 0);
388 ----------------------------------------------------
388 ----------------------------------------------------
389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
389 WHEN "111100" => prdata(31 DOWNTO 0) <= top_lfr_version(31 DOWNTO 0);
390 WHEN OTHERS => NULL;
390 WHEN OTHERS => NULL;
391 END CASE;
391 END CASE;
392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
392 IF (apbi.pwrite AND apbi.penable) = '1' THEN
393 -- APB DMA WRITE --
393 -- APB DMA WRITE --
394 CASE paddr(7 DOWNTO 2) IS
394 CASE paddr(7 DOWNTO 2) IS
395 --
395 --
396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
396 WHEN "000000" => reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
397 reg_sp.config_active_interruption_onError <= apbi.pwdata(1);
398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
398 WHEN "000001" => reg_sp.status_ready_matrix_f0_0 <= apbi.pwdata(0);
399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
399 reg_sp.status_ready_matrix_f0_1 <= apbi.pwdata(1);
400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
400 reg_sp.status_ready_matrix_f1 <= apbi.pwdata(2);
401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
401 reg_sp.status_ready_matrix_f2 <= apbi.pwdata(3);
402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
402 reg_sp.status_error_anticipating_empty_fifo <= apbi.pwdata(4);
403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
403 reg_sp.status_error_bad_component_error <= apbi.pwdata(5);
404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
404 WHEN "000010" => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
405 WHEN "000011" => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
406 WHEN "000100" => reg_sp.addr_matrix_f1 <= apbi.pwdata;
407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
407 WHEN "000101" => reg_sp.addr_matrix_f2 <= apbi.pwdata;
408 --
408 --
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
409 WHEN "001000" => reg_wp.data_shaping_BW <= apbi.pwdata(0);
410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
410 reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
411 reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
412 reg_wp.data_shaping_R0 <= apbi.pwdata(3);
413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
413 reg_wp.data_shaping_R1 <= apbi.pwdata(4);
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
414 WHEN "001001" => reg_wp.enable_f0 <= apbi.pwdata(0);
415 reg_wp.enable_f1 <= apbi.pwdata(1);
415 reg_wp.enable_f1 <= apbi.pwdata(1);
416 reg_wp.enable_f2 <= apbi.pwdata(2);
416 reg_wp.enable_f2 <= apbi.pwdata(2);
417 reg_wp.enable_f3 <= apbi.pwdata(3);
417 reg_wp.enable_f3 <= apbi.pwdata(3);
418 reg_wp.burst_f0 <= apbi.pwdata(4);
418 reg_wp.burst_f0 <= apbi.pwdata(4);
419 reg_wp.burst_f1 <= apbi.pwdata(5);
419 reg_wp.burst_f1 <= apbi.pwdata(5);
420 reg_wp.burst_f2 <= apbi.pwdata(6);
420 reg_wp.burst_f2 <= apbi.pwdata(6);
421 reg_wp.run <= apbi.pwdata(7);
421 reg_wp.run <= apbi.pwdata(7);
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
422 WHEN "001010" => reg_wp.addr_data_f0 <= apbi.pwdata;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
423 WHEN "001011" => reg_wp.addr_data_f1 <= apbi.pwdata;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
424 WHEN "001100" => reg_wp.addr_data_f2 <= apbi.pwdata;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
425 WHEN "001101" => reg_wp.addr_data_f3 <= apbi.pwdata;
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
426 WHEN "001110" => reg_wp.status_full <= apbi.pwdata(3 DOWNTO 0);
427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
427 reg_wp.status_full_err <= apbi.pwdata(7 DOWNTO 4);
428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
428 reg_wp.status_new_err <= apbi.pwdata(11 DOWNTO 8);
429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
429 status_full_ack(0) <= reg_wp.status_full(0) AND NOT apbi.pwdata(0);
430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
430 status_full_ack(1) <= reg_wp.status_full(1) AND NOT apbi.pwdata(1);
431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
431 status_full_ack(2) <= reg_wp.status_full(2) AND NOT apbi.pwdata(2);
432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
432 status_full_ack(3) <= reg_wp.status_full(3) AND NOT apbi.pwdata(3);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
433 WHEN "001111" => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
434 WHEN "010000" => reg_wp.delta_f0 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
435 WHEN "010001" => reg_wp.delta_f0_2 <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
436 WHEN "010010" => reg_wp.delta_f1 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
437 WHEN "010011" => reg_wp.delta_f2 <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
438 WHEN "010100" => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
439 WHEN "010101" => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
440 WHEN "010110" => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0);
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
441 WHEN "010111" => reg_wp.nb_word_by_buffer <= apbi.pwdata(nb_word_by_buffer_size-1 DOWNTO 0);
442 --
442 --
443 WHEN OTHERS => NULL;
443 WHEN OTHERS => NULL;
444 END CASE;
444 END CASE;
445 END IF;
445 END IF;
446 END IF;
446 END IF;
447
447
448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
448 apbo.pirq(pirq_ms) <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0_0 OR
449 ready_matrix_f0_1 OR
449 ready_matrix_f0_1 OR
450 ready_matrix_f1 OR
450 ready_matrix_f1 OR
451 ready_matrix_f2)
451 ready_matrix_f2)
452 )
452 )
453 OR
453 OR
454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
454 (reg_sp.config_active_interruption_onError AND (error_anticipating_empty_fifo OR
455 error_bad_component_error)
455 error_bad_component_error)
456 ));
456 ));
457
457
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
458 --apbo.pirq(pirq_wfp) <= (status_full(0) OR status_full_err(0) OR status_new_err(0) OR
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
459 -- status_full(1) OR status_full_err(1) OR status_new_err(1) OR
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
460 -- status_full(2) OR status_full_err(2) OR status_new_err(2) OR
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
461 -- status_full(3) OR status_full_err(3) OR status_new_err(3)
462 -- );
462 -- );
463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
463 apbo.pirq(pirq_wfp) <= ored_irq_wfp;
464
464
465 END IF;
465 END IF;
466 END PROCESS lpp_lfr_apbreg;
466 END PROCESS lpp_lfr_apbreg;
467
467
468 apbo.pindex <= pindex;
468 apbo.pindex <= pindex;
469 apbo.pconfig <= pconfig;
469 apbo.pconfig <= pconfig;
470 apbo.prdata <= prdata;
470 apbo.prdata <= prdata;
471
471
472 -----------------------------------------------------------------------------
472 -----------------------------------------------------------------------------
473 -- IRQ
473 -- IRQ
474 -----------------------------------------------------------------------------
474 -----------------------------------------------------------------------------
475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
475 irq_wfp_reg_s <= status_full & status_full_err & status_new_err;
476
476
477 PROCESS (HCLK, HRESETn)
477 PROCESS (HCLK, HRESETn)
478 BEGIN -- PROCESS
478 BEGIN -- PROCESS
479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
479 IF HRESETn = '0' THEN -- asynchronous reset (active low)
480 irq_wfp_reg <= (OTHERS => '0');
480 irq_wfp_reg <= (OTHERS => '0');
481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
481 ELSIF HCLK'event AND HCLK = '1' THEN -- rising clock edge
482 irq_wfp_reg <= irq_wfp_reg_s;
482 irq_wfp_reg <= irq_wfp_reg_s;
483 END IF;
483 END IF;
484 END PROCESS;
484 END PROCESS;
485
485
486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
486 all_irq_wfp: FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
487 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
488 END GENERATE all_irq_wfp;
488 END GENERATE all_irq_wfp;
489
489
490 irq_wfp_ZERO <= (OTHERS => '0');
490 irq_wfp_ZERO <= (OTHERS => '0');
491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
491 ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
492
492
493 END beh;
493 END beh;
Show file before | Show file after | Hide comments
@@ -1,221 +1,252
1 LIBRARY ieee;
1 LIBRARY ieee;
2 USE ieee.std_logic_1164.ALL;
2 USE ieee.std_logic_1164.ALL;
3
3
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6
6
7 LIBRARY lpp;
7 LIBRARY lpp;
8 USE lpp.lpp_ad_conv.ALL;
8 USE lpp.lpp_ad_conv.ALL;
9 USE lpp.iir_filter.ALL;
9 USE lpp.iir_filter.ALL;
10 USE lpp.FILTERcfg.ALL;
10 USE lpp.FILTERcfg.ALL;
11 USE lpp.lpp_memory.ALL;
11 USE lpp.lpp_memory.ALL;
12 LIBRARY techmap;
12 LIBRARY techmap;
13 USE techmap.gencomp.ALL;
13 USE techmap.gencomp.ALL;
14
14
15 PACKAGE lpp_lfr_pkg IS
15 PACKAGE lpp_lfr_pkg IS
16
16
17 COMPONENT lpp_lfr_ms
17 COMPONENT lpp_lfr_ms
18 GENERIC (
18 GENERIC (
19 hindex : INTEGER);
19 hindex : INTEGER);
20 PORT (
20 PORT (
21 clk : IN STD_LOGIC;
21 clk : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
22 rstn : IN STD_LOGIC;
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
23 sample_f0_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
24 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
25 sample_f1_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
26 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
27 sample_f3_wen : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
28 sample_f3_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
29 AHB_Master_In : IN AHB_Mst_In_Type;
29 AHB_Master_In : IN AHB_Mst_In_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
30 AHB_Master_Out : OUT AHB_Mst_Out_Type;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
31 ready_matrix_f0_0 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
33 ready_matrix_f1 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
36 error_bad_component_error : OUT STD_LOGIC;
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
38 status_ready_matrix_f0_0 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
39 status_ready_matrix_f0_1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
40 status_ready_matrix_f1 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
41 status_ready_matrix_f2 : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
42 status_error_anticipating_empty_fifo : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
43 status_error_bad_component_error : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
44 config_active_interruption_onNewMatrix : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
45 config_active_interruption_onError : IN STD_LOGIC;
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
46 addr_matrix_f0_0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
47 addr_matrix_f0_1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
48 addr_matrix_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
49 addr_matrix_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
50 END COMPONENT;
50 END COMPONENT;
51
51
52 COMPONENT lpp_lfr_filter
52 COMPONENT lpp_lfr_filter
53 GENERIC (
53 GENERIC (
54 Mem_use : INTEGER);
54 Mem_use : INTEGER);
55 PORT (
55 PORT (
56 sample : IN Samples(7 DOWNTO 0);
56 sample : IN Samples(7 DOWNTO 0);
57 sample_val : IN STD_LOGIC;
57 sample_val : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
58 clk : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
59 rstn : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
60 data_shaping_SP0 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
61 data_shaping_SP1 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
62 data_shaping_R0 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
63 data_shaping_R1 : IN STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
64 sample_f0_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
65 sample_f1_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
66 sample_f2_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
67 sample_f3_val : OUT STD_LOGIC;
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
68 sample_f0_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
69 sample_f1_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
70 sample_f2_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
71 sample_f3_wdata : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
72 END COMPONENT;
72 END COMPONENT;
73
73
74 COMPONENT lpp_lfr
74 COMPONENT lpp_lfr
75 GENERIC (
75 GENERIC (
76 Mem_use : INTEGER;
76 Mem_use : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
77 nb_data_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
78 nb_word_by_buffer_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
79 nb_snapshot_param_size : INTEGER;
80 delta_vector_size : INTEGER;
80 delta_vector_size : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
81 delta_vector_size_f0_2 : INTEGER;
82 pindex : INTEGER;
82 pindex : INTEGER;
83 paddr : INTEGER;
83 paddr : INTEGER;
84 pmask : INTEGER;
84 pmask : INTEGER;
85 pirq_ms : INTEGER;
85 pirq_ms : INTEGER;
86 pirq_wfp : INTEGER;
86 pirq_wfp : INTEGER;
87 hindex : INTEGER;
87 hindex : INTEGER;
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
88 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0)
89 );
89 );
90 PORT (
90 PORT (
91 clk : IN STD_LOGIC;
91 clk : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
92 rstn : IN STD_LOGIC;
93 sample_B : IN Samples14v(2 DOWNTO 0);
93 sample_B : IN Samples14v(2 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
94 sample_E : IN Samples14v(4 DOWNTO 0);
95 sample_val : IN STD_LOGIC;
95 sample_val : IN STD_LOGIC;
96 apbi : IN apb_slv_in_type;
96 apbi : IN apb_slv_in_type;
97 apbo : OUT apb_slv_out_type;
97 apbo : OUT apb_slv_out_type;
98 ahbi : IN AHB_Mst_In_Type;
98 ahbi : IN AHB_Mst_In_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
99 ahbo : OUT AHB_Mst_Out_Type;
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
100 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 data_shaping_BW : OUT STD_LOGIC;
102 data_shaping_BW : OUT STD_LOGIC;
103
103
104 --debug
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC );
112 debug_f3_data_valid : OUT STD_LOGIC;
113
114 -- debug FIFO_IN
115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123
124 --debug FIFO OUT
125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133
134 --debug DMA IN
135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 );
113 END COMPONENT;
144 END COMPONENT;
114
145
115 COMPONENT lpp_lfr_apbreg
146 COMPONENT lpp_lfr_apbreg
116 GENERIC (
147 GENERIC (
117 nb_data_by_buffer_size : INTEGER;
148 nb_data_by_buffer_size : INTEGER;
118 nb_word_by_buffer_size : INTEGER;
149 nb_word_by_buffer_size : INTEGER;
119 nb_snapshot_param_size : INTEGER;
150 nb_snapshot_param_size : INTEGER;
120 delta_vector_size : INTEGER;
151 delta_vector_size : INTEGER;
121 delta_vector_size_f0_2 : INTEGER;
152 delta_vector_size_f0_2 : INTEGER;
122 pindex : INTEGER;
153 pindex : INTEGER;
123 paddr : INTEGER;
154 paddr : INTEGER;
124 pmask : INTEGER;
155 pmask : INTEGER;
125 pirq_ms : INTEGER;
156 pirq_ms : INTEGER;
126 pirq_wfp : INTEGER;
157 pirq_wfp : INTEGER;
127 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
158 top_lfr_version : STD_LOGIC_VECTOR(31 DOWNTO 0));
128 PORT (
159 PORT (
129 HCLK : IN STD_ULOGIC;
160 HCLK : IN STD_ULOGIC;
130 HRESETn : IN STD_ULOGIC;
161 HRESETn : IN STD_ULOGIC;
131 apbi : IN apb_slv_in_type;
162 apbi : IN apb_slv_in_type;
132 apbo : OUT apb_slv_out_type;
163 apbo : OUT apb_slv_out_type;
133 ready_matrix_f0_0 : IN STD_LOGIC;
164 ready_matrix_f0_0 : IN STD_LOGIC;
134 ready_matrix_f0_1 : IN STD_LOGIC;
165 ready_matrix_f0_1 : IN STD_LOGIC;
135 ready_matrix_f1 : IN STD_LOGIC;
166 ready_matrix_f1 : IN STD_LOGIC;
136 ready_matrix_f2 : IN STD_LOGIC;
167 ready_matrix_f2 : IN STD_LOGIC;
137 error_anticipating_empty_fifo : IN STD_LOGIC;
168 error_anticipating_empty_fifo : IN STD_LOGIC;
138 error_bad_component_error : IN STD_LOGIC;
169 error_bad_component_error : IN STD_LOGIC;
139 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
170 debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
140 status_ready_matrix_f0_0 : OUT STD_LOGIC;
171 status_ready_matrix_f0_0 : OUT STD_LOGIC;
141 status_ready_matrix_f0_1 : OUT STD_LOGIC;
172 status_ready_matrix_f0_1 : OUT STD_LOGIC;
142 status_ready_matrix_f1 : OUT STD_LOGIC;
173 status_ready_matrix_f1 : OUT STD_LOGIC;
143 status_ready_matrix_f2 : OUT STD_LOGIC;
174 status_ready_matrix_f2 : OUT STD_LOGIC;
144 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
175 status_error_anticipating_empty_fifo : OUT STD_LOGIC;
145 status_error_bad_component_error : OUT STD_LOGIC;
176 status_error_bad_component_error : OUT STD_LOGIC;
146 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
177 config_active_interruption_onNewMatrix : OUT STD_LOGIC;
147 config_active_interruption_onError : OUT STD_LOGIC;
178 config_active_interruption_onError : OUT STD_LOGIC;
148 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_matrix_f0_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
149 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_matrix_f0_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
182 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
183 status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
153 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
184 status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
154 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
185 status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
155 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
186 status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
156 data_shaping_BW : OUT STD_LOGIC;
187 data_shaping_BW : OUT STD_LOGIC;
157 data_shaping_SP0 : OUT STD_LOGIC;
188 data_shaping_SP0 : OUT STD_LOGIC;
158 data_shaping_SP1 : OUT STD_LOGIC;
189 data_shaping_SP1 : OUT STD_LOGIC;
159 data_shaping_R0 : OUT STD_LOGIC;
190 data_shaping_R0 : OUT STD_LOGIC;
160 data_shaping_R1 : OUT STD_LOGIC;
191 data_shaping_R1 : OUT STD_LOGIC;
161 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
192 delta_snapshot : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
162 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
193 delta_f0 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
163 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
194 delta_f0_2 : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
164 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
195 delta_f1 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
165 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
196 delta_f2 : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
166 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
197 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
167 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
198 nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
168 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
199 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
169 enable_f0 : OUT STD_LOGIC;
200 enable_f0 : OUT STD_LOGIC;
170 enable_f1 : OUT STD_LOGIC;
201 enable_f1 : OUT STD_LOGIC;
171 enable_f2 : OUT STD_LOGIC;
202 enable_f2 : OUT STD_LOGIC;
172 enable_f3 : OUT STD_LOGIC;
203 enable_f3 : OUT STD_LOGIC;
173 burst_f0 : OUT STD_LOGIC;
204 burst_f0 : OUT STD_LOGIC;
174 burst_f1 : OUT STD_LOGIC;
205 burst_f1 : OUT STD_LOGIC;
175 burst_f2 : OUT STD_LOGIC;
206 burst_f2 : OUT STD_LOGIC;
176 run : OUT STD_LOGIC;
207 run : OUT STD_LOGIC;
177 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
208 addr_data_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
178 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
209 addr_data_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
179 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
210 addr_data_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
180 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
211 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
212 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
182 ---------------------------------------------------------------------------
213 ---------------------------------------------------------------------------
183 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
214 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
218 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
219 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
220 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
190 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
221 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
191 END COMPONENT;
222 END COMPONENT;
192
223
193 COMPONENT lpp_top_ms
224 COMPONENT lpp_top_ms
194 GENERIC (
225 GENERIC (
195 Mem_use : INTEGER;
226 Mem_use : INTEGER;
196 nb_burst_available_size : INTEGER;
227 nb_burst_available_size : INTEGER;
197 nb_snapshot_param_size : INTEGER;
228 nb_snapshot_param_size : INTEGER;
198 delta_snapshot_size : INTEGER;
229 delta_snapshot_size : INTEGER;
199 delta_f2_f0_size : INTEGER;
230 delta_f2_f0_size : INTEGER;
200 delta_f2_f1_size : INTEGER;
231 delta_f2_f1_size : INTEGER;
201 pindex : INTEGER;
232 pindex : INTEGER;
202 paddr : INTEGER;
233 paddr : INTEGER;
203 pmask : INTEGER;
234 pmask : INTEGER;
204 pirq_ms : INTEGER;
235 pirq_ms : INTEGER;
205 pirq_wfp : INTEGER;
236 pirq_wfp : INTEGER;
206 hindex_wfp : INTEGER;
237 hindex_wfp : INTEGER;
207 hindex_ms : INTEGER);
238 hindex_ms : INTEGER);
208 PORT (
239 PORT (
209 clk : IN STD_LOGIC;
240 clk : IN STD_LOGIC;
210 rstn : IN STD_LOGIC;
241 rstn : IN STD_LOGIC;
211 sample_B : IN Samples14v(2 DOWNTO 0);
242 sample_B : IN Samples14v(2 DOWNTO 0);
212 sample_E : IN Samples14v(4 DOWNTO 0);
243 sample_E : IN Samples14v(4 DOWNTO 0);
213 sample_val : IN STD_LOGIC;
244 sample_val : IN STD_LOGIC;
214 apbi : IN apb_slv_in_type;
245 apbi : IN apb_slv_in_type;
215 apbo : OUT apb_slv_out_type;
246 apbo : OUT apb_slv_out_type;
216 ahbi_ms : IN AHB_Mst_In_Type;
247 ahbi_ms : IN AHB_Mst_In_Type;
217 ahbo_ms : OUT AHB_Mst_Out_Type;
248 ahbo_ms : OUT AHB_Mst_Out_Type;
218 data_shaping_BW : OUT STD_LOGIC);
249 data_shaping_BW : OUT STD_LOGIC);
219 END COMPONENT;
250 END COMPONENT;
220
251
221 END lpp_lfr_pkg;
252 END lpp_lfr_pkg;
Show file before | Show file after | Hide comments
@@ -1,472 +1,495
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25 USE ieee.numeric_std.ALL;
25 USE ieee.numeric_std.ALL;
26
26
27 LIBRARY grlib;
27 LIBRARY grlib;
28 USE grlib.amba.ALL;
28 USE grlib.amba.ALL;
29 USE grlib.stdlib.ALL;
29 USE grlib.stdlib.ALL;
30 USE grlib.devices.ALL;
30 USE grlib.devices.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
31 USE GRLIB.DMA2AHB_Package.ALL;
32
32
33 LIBRARY lpp;
33 LIBRARY lpp;
34 USE lpp.lpp_waveform_pkg.ALL;
34 USE lpp.lpp_waveform_pkg.ALL;
35
35
36 LIBRARY techmap;
36 LIBRARY techmap;
37 USE techmap.gencomp.ALL;
37 USE techmap.gencomp.ALL;
38
38
39 ENTITY lpp_waveform IS
39 ENTITY lpp_waveform IS
40
40
41 GENERIC (
41 GENERIC (
42 tech : INTEGER := inferred;
42 tech : INTEGER := inferred;
43 data_size : INTEGER := 96; --16*6
43 data_size : INTEGER := 96; --16*6
44 nb_data_by_buffer_size : INTEGER := 11;
44 nb_data_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
45 nb_word_by_buffer_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
46 nb_snapshot_param_size : INTEGER := 11;
47 delta_vector_size : INTEGER := 20;
47 delta_vector_size : INTEGER := 20;
48 delta_vector_size_f0_2 : INTEGER := 3);
48 delta_vector_size_f0_2 : INTEGER := 3);
49
49
50 PORT (
50 PORT (
51 clk : IN STD_LOGIC;
51 clk : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
52 rstn : IN STD_LOGIC;
53
53
54 ---- AMBA AHB Master Interface
54 ---- AMBA AHB Master Interface
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
55 --AHB_Master_In : IN AHB_Mst_In_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
56 --AHB_Master_Out : OUT AHB_Mst_Out_Type; -- TODO
57
57
58 --config
58 --config
59 reg_run : IN STD_LOGIC;
59 reg_run : IN STD_LOGIC;
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
60 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
61 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
62 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
63 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
64 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
65 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
66
66
67 enable_f0 : IN STD_LOGIC;
67 enable_f0 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
68 enable_f1 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
69 enable_f2 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
70 enable_f3 : IN STD_LOGIC;
71
71
72 burst_f0 : IN STD_LOGIC;
72 burst_f0 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
73 burst_f1 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
74 burst_f2 : IN STD_LOGIC;
75
75
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
76 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
77 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
78 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
79 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
80 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
81 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
82 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); -- New data f(i) before the current data is write by dma
83 ---------------------------------------------------------------------------
83 ---------------------------------------------------------------------------
84 -- INPUT
84 -- INPUT
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
85 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
86 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
87
87
88 --f0
88 --f0
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
89 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
90 data_f0_in_valid : IN STD_LOGIC;
90 data_f0_in_valid : IN STD_LOGIC;
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
91 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
92 --f1
92 --f1
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
93 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
94 data_f1_in_valid : IN STD_LOGIC;
94 data_f1_in_valid : IN STD_LOGIC;
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
95 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
96 --f2
96 --f2
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
98 data_f2_in_valid : IN STD_LOGIC;
98 data_f2_in_valid : IN STD_LOGIC;
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
99 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
100 --f3
100 --f3
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
101 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 data_f3_in_valid : IN STD_LOGIC;
102 data_f3_in_valid : IN STD_LOGIC;
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
103 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
104
104
105 ---------------------------------------------------------------------------
105 ---------------------------------------------------------------------------
106 -- OUTPUT
106 -- OUTPUT
107 --f0
107 --f0
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
108 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
109 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
110 data_f0_data_out_valid : OUT STD_LOGIC;
110 data_f0_data_out_valid : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
111 data_f0_data_out_valid_burst : OUT STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
112 data_f0_data_out_ren : IN STD_LOGIC;
113 --f1
113 --f1
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
114 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
115 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 data_f1_data_out_valid : OUT STD_LOGIC;
116 data_f1_data_out_valid : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
117 data_f1_data_out_valid_burst : OUT STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
118 data_f1_data_out_ren : IN STD_LOGIC;
119 --f2
119 --f2
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
121 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 data_f2_data_out_valid : OUT STD_LOGIC;
122 data_f2_data_out_valid : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
123 data_f2_data_out_valid_burst : OUT STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
124 data_f2_data_out_ren : IN STD_LOGIC;
125 --f3
125 --f3
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
127 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 data_f3_data_out_valid : OUT STD_LOGIC;
128 data_f3_data_out_valid : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
130 data_f3_data_out_ren : IN STD_LOGIC;
131
131
132 --debug
132 --debug SNAPSHOT OUT
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 debug_f0_data_valid : OUT STD_LOGIC;
134 debug_f0_data_valid : OUT STD_LOGIC;
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
136 debug_f1_data_valid : OUT STD_LOGIC;
136 debug_f1_data_valid : OUT STD_LOGIC;
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 debug_f2_data_valid : OUT STD_LOGIC;
138 debug_f2_data_valid : OUT STD_LOGIC;
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 debug_f3_data_valid : OUT STD_LOGIC
140 debug_f3_data_valid : OUT STD_LOGIC;
141
142 --debug FIFO IN
143 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
144 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
145 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
146 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
147 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
149 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
151
141 );
152 );
142
153
143 END lpp_waveform;
154 END lpp_waveform;
144
155
145 ARCHITECTURE beh OF lpp_waveform IS
156 ARCHITECTURE beh OF lpp_waveform IS
146 SIGNAL start_snapshot_f0 : STD_LOGIC;
157 SIGNAL start_snapshot_f0 : STD_LOGIC;
147 SIGNAL start_snapshot_f1 : STD_LOGIC;
158 SIGNAL start_snapshot_f1 : STD_LOGIC;
148 SIGNAL start_snapshot_f2 : STD_LOGIC;
159 SIGNAL start_snapshot_f2 : STD_LOGIC;
149
160
150 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
161 SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
151 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
162 SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
152 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
163 SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
153 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
164 SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
154
165
155 SIGNAL data_f0_out_valid : STD_LOGIC;
166 SIGNAL data_f0_out_valid : STD_LOGIC;
156 SIGNAL data_f1_out_valid : STD_LOGIC;
167 SIGNAL data_f1_out_valid : STD_LOGIC;
157 SIGNAL data_f2_out_valid : STD_LOGIC;
168 SIGNAL data_f2_out_valid : STD_LOGIC;
158 SIGNAL data_f3_out_valid : STD_LOGIC;
169 SIGNAL data_f3_out_valid : STD_LOGIC;
159 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
170 SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
160 --
171 --
161 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL valid_in : STD_LOGIC_VECTOR(3 DOWNTO 0);
162 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL valid_out : STD_LOGIC_VECTOR(3 DOWNTO 0);
163 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 SIGNAL valid_ack : STD_LOGIC_VECTOR(3 DOWNTO 0);
164 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
175 SIGNAL time_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
165 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL data_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
166 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL ready_arb : STD_LOGIC_VECTOR(3 DOWNTO 0);
167 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
178 SIGNAL data_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
168 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 SIGNAL time_wen : STD_LOGIC_VECTOR(3 DOWNTO 0);
169 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
180 SIGNAL wdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
170 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
181 SIGNAL full_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
171 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
182 SIGNAL full : STD_LOGIC_VECTOR(3 DOWNTO 0);
172 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
183 SIGNAL empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);
173 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
184 SIGNAL empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
174 --
185 --
175 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
186 SIGNAL data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
176 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
187 SIGNAL time_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
177 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
188 SIGNAL rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
178 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
189 SIGNAL enable : STD_LOGIC_VECTOR(3 DOWNTO 0);
179 --
190 --
180 SIGNAL run : STD_LOGIC;
191 SIGNAL run : STD_LOGIC;
181 --
192 --
182 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
193 TYPE TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
183 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
194 SIGNAL data_out : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
184 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
195 SIGNAL time_out_2 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
185 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
196 SIGNAL time_out : TIME_VECTOR(3 DOWNTO 0);
186 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
197 SIGNAL time_out_debug : TIME_VECTOR(3 DOWNTO 0); -- TODO : debug
187 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
198 SIGNAL time_reg1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
188 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
199 SIGNAL time_reg2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
189 --
200 --
190
201
191 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
202 SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0); --occupancy is lesser than 16 * 32b
192 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
203 SIGNAL s_empty : STD_LOGIC_VECTOR(3 DOWNTO 0);
193 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
204 SIGNAL s_data_ren : STD_LOGIC_VECTOR(3 DOWNTO 0);
194 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
205 SIGNAL s_rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
195
206
196 BEGIN -- beh
207 BEGIN -- beh
197
208
198 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
209 lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
199 GENERIC MAP (
210 GENERIC MAP (
200 delta_vector_size => delta_vector_size,
211 delta_vector_size => delta_vector_size,
201 delta_vector_size_f0_2 => delta_vector_size_f0_2
212 delta_vector_size_f0_2 => delta_vector_size_f0_2
202 )
213 )
203 PORT MAP (
214 PORT MAP (
204 clk => clk,
215 clk => clk,
205 rstn => rstn,
216 rstn => rstn,
206 reg_run => reg_run,
217 reg_run => reg_run,
207 reg_start_date => reg_start_date,
218 reg_start_date => reg_start_date,
208 reg_delta_snapshot => reg_delta_snapshot,
219 reg_delta_snapshot => reg_delta_snapshot,
209 reg_delta_f0 => reg_delta_f0,
220 reg_delta_f0 => reg_delta_f0,
210 reg_delta_f0_2 => reg_delta_f0_2,
221 reg_delta_f0_2 => reg_delta_f0_2,
211 reg_delta_f1 => reg_delta_f1,
222 reg_delta_f1 => reg_delta_f1,
212 reg_delta_f2 => reg_delta_f2,
223 reg_delta_f2 => reg_delta_f2,
213 coarse_time => coarse_time(30 DOWNTO 0),
224 coarse_time => coarse_time(30 DOWNTO 0),
214 data_f0_valid => data_f0_in_valid,
225 data_f0_valid => data_f0_in_valid,
215 data_f2_valid => data_f2_in_valid,
226 data_f2_valid => data_f2_in_valid,
216 start_snapshot_f0 => start_snapshot_f0,
227 start_snapshot_f0 => start_snapshot_f0,
217 start_snapshot_f1 => start_snapshot_f1,
228 start_snapshot_f1 => start_snapshot_f1,
218 start_snapshot_f2 => start_snapshot_f2,
229 start_snapshot_f2 => start_snapshot_f2,
219 wfp_on => run);
230 wfp_on => run);
220
231
221 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
232 lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
222 GENERIC MAP (
233 GENERIC MAP (
223 data_size => data_size,
234 data_size => data_size,
224 nb_snapshot_param_size => nb_snapshot_param_size)
235 nb_snapshot_param_size => nb_snapshot_param_size)
225 PORT MAP (
236 PORT MAP (
226 clk => clk,
237 clk => clk,
227 rstn => rstn,
238 rstn => rstn,
228 run => run,
239 run => run,
229 enable => enable_f0,
240 enable => enable_f0,
230 burst_enable => burst_f0,
241 burst_enable => burst_f0,
231 nb_snapshot_param => nb_snapshot_param,
242 nb_snapshot_param => nb_snapshot_param,
232 start_snapshot => start_snapshot_f0,
243 start_snapshot => start_snapshot_f0,
233 data_in => data_f0_in,
244 data_in => data_f0_in,
234 data_in_valid => data_f0_in_valid,
245 data_in_valid => data_f0_in_valid,
235 data_out => data_f0_out,
246 data_out => data_f0_out,
236 data_out_valid => data_f0_out_valid);
247 data_out_valid => data_f0_out_valid);
237
248
238 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
249 nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) + 1;
239
250
240 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
251 lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
241 GENERIC MAP (
252 GENERIC MAP (
242 data_size => data_size,
253 data_size => data_size,
243 nb_snapshot_param_size => nb_snapshot_param_size+1)
254 nb_snapshot_param_size => nb_snapshot_param_size+1)
244 PORT MAP (
255 PORT MAP (
245 clk => clk,
256 clk => clk,
246 rstn => rstn,
257 rstn => rstn,
247 run => run,
258 run => run,
248 enable => enable_f1,
259 enable => enable_f1,
249 burst_enable => burst_f1,
260 burst_enable => burst_f1,
250 nb_snapshot_param => nb_snapshot_param_more_one,
261 nb_snapshot_param => nb_snapshot_param_more_one,
251 start_snapshot => start_snapshot_f1,
262 start_snapshot => start_snapshot_f1,
252 data_in => data_f1_in,
263 data_in => data_f1_in,
253 data_in_valid => data_f1_in_valid,
264 data_in_valid => data_f1_in_valid,
254 data_out => data_f1_out,
265 data_out => data_f1_out,
255 data_out_valid => data_f1_out_valid);
266 data_out_valid => data_f1_out_valid);
256
267
257 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
268 lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
258 GENERIC MAP (
269 GENERIC MAP (
259 data_size => data_size,
270 data_size => data_size,
260 nb_snapshot_param_size => nb_snapshot_param_size+1)
271 nb_snapshot_param_size => nb_snapshot_param_size+1)
261 PORT MAP (
272 PORT MAP (
262 clk => clk,
273 clk => clk,
263 rstn => rstn,
274 rstn => rstn,
264 run => run,
275 run => run,
265 enable => enable_f2,
276 enable => enable_f2,
266 burst_enable => burst_f2,
277 burst_enable => burst_f2,
267 nb_snapshot_param => nb_snapshot_param_more_one,
278 nb_snapshot_param => nb_snapshot_param_more_one,
268 start_snapshot => start_snapshot_f2,
279 start_snapshot => start_snapshot_f2,
269 data_in => data_f2_in,
280 data_in => data_f2_in,
270 data_in_valid => data_f2_in_valid,
281 data_in_valid => data_f2_in_valid,
271 data_out => data_f2_out,
282 data_out => data_f2_out,
272 data_out_valid => data_f2_out_valid);
283 data_out_valid => data_f2_out_valid);
273
284
274 lpp_waveform_burst_f3 : lpp_waveform_burst
285 lpp_waveform_burst_f3 : lpp_waveform_burst
275 GENERIC MAP (
286 GENERIC MAP (
276 data_size => data_size)
287 data_size => data_size)
277 PORT MAP (
288 PORT MAP (
278 clk => clk,
289 clk => clk,
279 rstn => rstn,
290 rstn => rstn,
280 run => run,
291 run => run,
281 enable => enable_f3,
292 enable => enable_f3,
282 data_in => data_f3_in,
293 data_in => data_f3_in,
283 data_in_valid => data_f3_in_valid,
294 data_in_valid => data_f3_in_valid,
284 data_out => data_f3_out,
295 data_out => data_f3_out,
285 data_out_valid => data_f3_out_valid);
296 data_out_valid => data_f3_out_valid);
286
297
287 -----------------------------------------------------------------------------
298 -----------------------------------------------------------------------------
288 -- DEBUG
299 -- DEBUG -- SNAPSHOT OUT
289 debug_f0_data_valid <= data_f0_out_valid;
300 debug_f0_data_valid <= data_f0_out_valid;
290 debug_f0_data <= data_f0_out;
301 debug_f0_data <= data_f0_out;
291 debug_f1_data_valid <= data_f1_out_valid;
302 debug_f1_data_valid <= data_f1_out_valid;
292 debug_f1_data <= data_f1_out;
303 debug_f1_data <= data_f1_out;
293 debug_f2_data_valid <= data_f2_out_valid;
304 debug_f2_data_valid <= data_f2_out_valid;
294 debug_f2_data <= data_f2_out;
305 debug_f2_data <= data_f2_out;
295 debug_f3_data_valid <= data_f3_out_valid;
306 debug_f3_data_valid <= data_f3_out_valid;
296 debug_f3_data <= data_f3_out;
307 debug_f3_data <= data_f3_out;
297 -----------------------------------------------------------------------------
308 -----------------------------------------------------------------------------
298
309
299 PROCESS (clk, rstn)
310 PROCESS (clk, rstn)
300 BEGIN -- PROCESS
311 BEGIN -- PROCESS
301 IF rstn = '0' THEN -- asynchronous reset (active low)
312 IF rstn = '0' THEN -- asynchronous reset (active low)
302 time_reg1 <= (OTHERS => '0');
313 time_reg1 <= (OTHERS => '0');
303 time_reg2 <= (OTHERS => '0');
314 time_reg2 <= (OTHERS => '0');
304 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
315 ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge
305 time_reg1 <= fine_time & coarse_time;
316 time_reg1 <= fine_time & coarse_time;
306 time_reg2 <= time_reg1;
317 time_reg2 <= time_reg1;
307 END IF;
318 END IF;
308 END PROCESS;
319 END PROCESS;
309
320
310 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
321 valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
311 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
322 all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
312 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
323 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
313 PORT MAP (
324 PORT MAP (
314 HCLK => clk,
325 HCLK => clk,
315 HRESETn => rstn,
326 HRESETn => rstn,
316 run => run,
327 run => run,
317 valid_in => valid_in(I),
328 valid_in => valid_in(I),
318 ack_in => valid_ack(I),
329 ack_in => valid_ack(I),
319 time_in => time_reg2, -- Todo
330 time_in => time_reg2, -- Todo
320 valid_out => valid_out(I),
331 valid_out => valid_out(I),
321 time_out => time_out(I), -- Todo
332 time_out => time_out(I), -- Todo
322 error => status_new_err(I));
333 error => status_new_err(I));
323 END GENERATE all_input_valid;
334 END GENERATE all_input_valid;
324
335
325 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
336 all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
326 data_out(0, I) <= data_f0_out(I);
337 data_out(0, I) <= data_f0_out(I);
327 data_out(1, I) <= data_f1_out(I);
338 data_out(1, I) <= data_f1_out(I);
328 data_out(2, I) <= data_f2_out(I);
339 data_out(2, I) <= data_f2_out(I);
329 data_out(3, I) <= data_f3_out(I);
340 data_out(3, I) <= data_f3_out(I);
330 END GENERATE all_bit_of_data_out;
341 END GENERATE all_bit_of_data_out;
331
342
332 -----------------------------------------------------------------------------
343 -----------------------------------------------------------------------------
333 -- TODO : debug
344 -- TODO : debug
334 -----------------------------------------------------------------------------
345 -----------------------------------------------------------------------------
335 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
346 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
336 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
347 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
337 time_out_2(J,I) <= time_out(J)(I);
348 time_out_2(J, I) <= time_out(J)(I);
338 END GENERATE all_sample_of_time_out;
349 END GENERATE all_sample_of_time_out;
339 END GENERATE all_bit_of_time_out;
350 END GENERATE all_bit_of_time_out;
340
351
341 -- DEBUG --
352 -- DEBUG --
342 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
353 --time_out_debug(0) <= x"0A0A" & x"0A0A0A0A";
343 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
354 --time_out_debug(1) <= x"1B1B" & x"1B1B1B1B";
344 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
355 --time_out_debug(2) <= x"2C2C" & x"2C2C2C2C";
345 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
356 --time_out_debug(3) <= x"3D3D" & x"3D3D3D3D";
346
357
347 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
358 --all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
348 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
359 -- all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
349 -- time_out_2(J, I) <= time_out_debug(J)(I);
360 -- time_out_2(J, I) <= time_out_debug(J)(I);
350 -- END GENERATE all_sample_of_time_out;
361 -- END GENERATE all_sample_of_time_out;
351 --END GENERATE all_bit_of_time_out;
362 --END GENERATE all_bit_of_time_out;
352 -- DEBUG --
363 -- DEBUG --
353
364
354 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
365 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
355 GENERIC MAP (tech => tech,
366 GENERIC MAP (tech => tech,
356 nb_data_by_buffer_size => nb_data_by_buffer_size)
367 nb_data_by_buffer_size => nb_data_by_buffer_size)
357 PORT MAP (
368 PORT MAP (
358 clk => clk,
369 clk => clk,
359 rstn => rstn,
370 rstn => rstn,
360 run => run,
371 run => run,
361 nb_data_by_buffer => nb_data_by_buffer,
372 nb_data_by_buffer => nb_data_by_buffer,
362 data_in_valid => valid_out,
373 data_in_valid => valid_out,
363 data_in_ack => valid_ack,
374 data_in_ack => valid_ack,
364 data_in => data_out,
375 data_in => data_out,
365 time_in => time_out_2,
376 time_in => time_out_2,
366
377
367 data_out => wdata,
378 data_out => wdata,
368 data_out_wen => data_wen,
379 data_out_wen => data_wen,
369 full_almost => full_almost,
380 full_almost => full_almost,
370 full => full);
381 full => full);
371
382
383 -----------------------------------------------------------------------------
384 -- DEBUG -- SNAPSHOT IN
385 debug_f0_data_fifo_in_valid <= NOT data_wen(0);
386 debug_f0_data_fifo_in <= wdata;
387 debug_f1_data_fifo_in_valid <= NOT data_wen(1);
388 debug_f1_data_fifo_in <= wdata;
389 debug_f2_data_fifo_in_valid <= NOT data_wen(2);
390 debug_f2_data_fifo_in <= wdata;
391 debug_f3_data_fifo_in_valid <= NOT data_wen(3);
392 debug_f3_data_fifo_in <= wdata;
393 -----------------------------------------------------------------------------
394
372 lpp_waveform_fifo_1 : lpp_waveform_fifo
395 lpp_waveform_fifo_1 : lpp_waveform_fifo
373 GENERIC MAP (tech => tech)
396 GENERIC MAP (tech => tech)
374 PORT MAP (
397 PORT MAP (
375 clk => clk,
398 clk => clk,
376 rstn => rstn,
399 rstn => rstn,
377 run => run,
400 run => run,
378
401
379 empty => s_empty,
402 empty => s_empty,
380 empty_almost => s_empty_almost,
403 empty_almost => s_empty_almost,
381 data_ren => s_data_ren,
404 data_ren => s_data_ren,
382 rdata => s_rdata,
405 rdata => s_rdata,
383
406
384
407
385 full_almost => full_almost,
408 full_almost => full_almost,
386 full => full,
409 full => full,
387 data_wen => data_wen,
410 data_wen => data_wen,
388 wdata => wdata);
411 wdata => wdata);
389
412
390 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
413 lpp_waveform_fifo_headreg_1 : lpp_waveform_fifo_headreg
391 GENERIC MAP (tech => tech)
414 GENERIC MAP (tech => tech)
392 PORT MAP (
415 PORT MAP (
393 clk => clk,
416 clk => clk,
394 rstn => rstn,
417 rstn => rstn,
395 run => run,
418 run => run,
396 o_empty_almost => empty_almost,
419 o_empty_almost => empty_almost,
397 o_empty => empty,
420 o_empty => empty,
398
421
399 o_data_ren => data_ren,
422 o_data_ren => data_ren,
400 o_rdata_0 => data_f0_data_out,
423 o_rdata_0 => data_f0_data_out,
401 o_rdata_1 => data_f1_data_out,
424 o_rdata_1 => data_f1_data_out,
402 o_rdata_2 => data_f2_data_out,
425 o_rdata_2 => data_f2_data_out,
403 o_rdata_3 => data_f3_data_out,
426 o_rdata_3 => data_f3_data_out,
404
427
405 i_empty_almost => s_empty_almost,
428 i_empty_almost => s_empty_almost,
406 i_empty => s_empty,
429 i_empty => s_empty,
407 i_data_ren => s_data_ren,
430 i_data_ren => s_data_ren,
408 i_rdata => s_rdata);
431 i_rdata => s_rdata);
409
432
410
433
411 --data_f0_data_out <= rdata;
434 --data_f0_data_out <= rdata;
412 --data_f1_data_out <= rdata;
435 --data_f1_data_out <= rdata;
413 --data_f2_data_out <= rdata;
436 --data_f2_data_out <= rdata;
414 --data_f3_data_out <= rdata;
437 --data_f3_data_out <= rdata;
415
438
416 data_ren <= data_f3_data_out_ren &
439 data_ren <= data_f3_data_out_ren &
417 data_f2_data_out_ren &
440 data_f2_data_out_ren &
418 data_f1_data_out_ren &
441 data_f1_data_out_ren &
419 data_f0_data_out_ren;
442 data_f0_data_out_ren;
420
443
421 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
444 lpp_waveform_gen_address_1 : lpp_waveform_genaddress
422 GENERIC MAP (
445 GENERIC MAP (
423 nb_data_by_buffer_size => nb_word_by_buffer_size)
446 nb_data_by_buffer_size => nb_word_by_buffer_size)
424 PORT MAP (
447 PORT MAP (
425 clk => clk,
448 clk => clk,
426 rstn => rstn,
449 rstn => rstn,
427 run => run,
450 run => run,
428
451
429 -------------------------------------------------------------------------
452 -------------------------------------------------------------------------
430 -- CONFIG
453 -- CONFIG
431 -------------------------------------------------------------------------
454 -------------------------------------------------------------------------
432 nb_data_by_buffer => nb_word_by_buffer,
455 nb_data_by_buffer => nb_word_by_buffer,
433
456
434 addr_data_f0 => addr_data_f0,
457 addr_data_f0 => addr_data_f0,
435 addr_data_f1 => addr_data_f1,
458 addr_data_f1 => addr_data_f1,
436 addr_data_f2 => addr_data_f2,
459 addr_data_f2 => addr_data_f2,
437 addr_data_f3 => addr_data_f3,
460 addr_data_f3 => addr_data_f3,
438 -------------------------------------------------------------------------
461 -------------------------------------------------------------------------
439 -- CTRL
462 -- CTRL
440 -------------------------------------------------------------------------
463 -------------------------------------------------------------------------
441 -- IN
464 -- IN
442 empty => empty,
465 empty => empty,
443 empty_almost => empty_almost,
466 empty_almost => empty_almost,
444 data_ren => data_ren,
467 data_ren => data_ren,
445
468
446 -------------------------------------------------------------------------
469 -------------------------------------------------------------------------
447 -- STATUS
470 -- STATUS
448 -------------------------------------------------------------------------
471 -------------------------------------------------------------------------
449 status_full => status_full,
472 status_full => status_full,
450 status_full_ack => status_full_ack,
473 status_full_ack => status_full_ack,
451 status_full_err => status_full_err,
474 status_full_err => status_full_err,
452
475
453 -------------------------------------------------------------------------
476 -------------------------------------------------------------------------
454 -- ADDR DATA OUT
477 -- ADDR DATA OUT
455 -------------------------------------------------------------------------
478 -------------------------------------------------------------------------
456 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
479 data_f0_data_out_valid_burst => data_f0_data_out_valid_burst,
457 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
480 data_f1_data_out_valid_burst => data_f1_data_out_valid_burst,
458 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
481 data_f2_data_out_valid_burst => data_f2_data_out_valid_burst,
459 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
482 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst,
460
483
461 data_f0_data_out_valid => data_f0_data_out_valid,
484 data_f0_data_out_valid => data_f0_data_out_valid,
462 data_f1_data_out_valid => data_f1_data_out_valid,
485 data_f1_data_out_valid => data_f1_data_out_valid,
463 data_f2_data_out_valid => data_f2_data_out_valid,
486 data_f2_data_out_valid => data_f2_data_out_valid,
464 data_f3_data_out_valid => data_f3_data_out_valid,
487 data_f3_data_out_valid => data_f3_data_out_valid,
465
488
466 data_f0_addr_out => data_f0_addr_out,
489 data_f0_addr_out => data_f0_addr_out,
467 data_f1_addr_out => data_f1_addr_out,
490 data_f1_addr_out => data_f1_addr_out,
468 data_f2_addr_out => data_f2_addr_out,
491 data_f2_addr_out => data_f2_addr_out,
469 data_f3_addr_out => data_f3_addr_out
492 data_f3_addr_out => data_f3_addr_out
470 );
493 );
471
494
472 END beh;
495 END beh;
Show file before | Show file after | Hide comments
@@ -1,394 +1,394
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY lpp_waveform_fifo_arbiter IS
30 ENTITY lpp_waveform_fifo_arbiter IS
31 GENERIC(
31 GENERIC(
32 tech : INTEGER := 0;
32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
33 nb_data_by_buffer_size : INTEGER := 11
34 );
34 );
35 PORT(
35 PORT(
36 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
40 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
41 ---------------------------------------------------------------------------
41 ---------------------------------------------------------------------------
42 -- SNAPSHOT INTERFACE (INPUT)
42 -- SNAPSHOT INTERFACE (INPUT)
43 ---------------------------------------------------------------------------
43 ---------------------------------------------------------------------------
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
44 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
45 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
46 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
47 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
48
48
49 ---------------------------------------------------------------------------
49 ---------------------------------------------------------------------------
50 -- FIFO INTERFACE (OUTPUT)
50 -- FIFO INTERFACE (OUTPUT)
51 ---------------------------------------------------------------------------
51 ---------------------------------------------------------------------------
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
52 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
53 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
54 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
54 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
55 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
56
56
57 );
57 );
58 END ENTITY;
58 END ENTITY;
59
59
60
60
61 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
61 ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
62 TYPE state_type_fifo_arbiter IS (IDLE,TIME1,TIME2,DATA1,DATA2,DATA3,LAST);
63 SIGNAL state : state_type_fifo_arbiter;
63 SIGNAL state : state_type_fifo_arbiter;
64
64
65 -----------------------------------------------------------------------------
65 -----------------------------------------------------------------------------
66 -- DATA MUX
66 -- DATA MUX
67 -----------------------------------------------------------------------------
67 -----------------------------------------------------------------------------
68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
68 SIGNAL data_0_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
69 SIGNAL data_1_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
70 SIGNAL data_2_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
71 SIGNAL data_3_v : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
72 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
72 TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
73 SIGNAL data_0 : WORD_VECTOR(4 DOWNTO 0);
74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
74 SIGNAL data_1 : WORD_VECTOR(4 DOWNTO 0);
75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
75 SIGNAL data_2 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
76 SIGNAL data_3 : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
77 SIGNAL data_sel : WORD_VECTOR(4 DOWNTO 0);
78
78
79 -----------------------------------------------------------------------------
79 -----------------------------------------------------------------------------
80 -- RR and SELECTION
80 -- RR and SELECTION
81 -----------------------------------------------------------------------------
81 -----------------------------------------------------------------------------
82 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
82 SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
83 SIGNAL sel : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
84 SIGNAL sel_s : STD_LOGIC_VECTOR(3 DOWNTO 0);
85 SIGNAL sel_reg : STD_LOGIC;
85 SIGNAL sel_reg : STD_LOGIC;
86 SIGNAL sel_ack : STD_LOGIC;
86 SIGNAL sel_ack : STD_LOGIC;
87 SIGNAL no_sel : STD_LOGIC;
87 SIGNAL no_sel : STD_LOGIC;
88
88
89 -----------------------------------------------------------------------------
89 -----------------------------------------------------------------------------
90 -- REG
90 -- REG
91 -----------------------------------------------------------------------------
91 -----------------------------------------------------------------------------
92 SIGNAL count_enable : STD_LOGIC;
92 SIGNAL count_enable : STD_LOGIC;
93 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
93 SIGNAL count : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
94 SIGNAL count_s : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
95
95
96 --SIGNAL shift_data_enable : STD_LOGIC;
96 --SIGNAL shift_data_enable : STD_LOGIC;
97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
97 --SIGNAL shift_data : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
98 --SIGNAL shift_data_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
99
99
100 --SIGNAL shift_time_enable : STD_LOGIC;
100 --SIGNAL shift_time_enable : STD_LOGIC;
101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
101 --SIGNAL shift_time : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
102 --SIGNAL shift_time_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
103
103
104 BEGIN
104 BEGIN
105
105
106 -----------------------------------------------------------------------------
106 -----------------------------------------------------------------------------
107 -- CONTROL
107 -- CONTROL
108 -----------------------------------------------------------------------------
108 -----------------------------------------------------------------------------
109 PROCESS (clk, rstn)
109 PROCESS (clk, rstn)
110 BEGIN -- PROCESS
110 BEGIN -- PROCESS
111 IF rstn = '0' THEN -- asynchronous reset (active low)
111 IF rstn = '0' THEN -- asynchronous reset (active low)
112 count_enable <= '0';
112 count_enable <= '0';
113 data_in_ack <= (OTHERS => '0');
113 data_in_ack <= (OTHERS => '0');
114 data_out_wen <= (OTHERS => '1');
114 data_out_wen <= (OTHERS => '1');
115 sel_ack <= '0';
115 sel_ack <= '0';
116 state <= IDLE;
116 state <= IDLE;
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
117 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
118 count_enable <= '0';
118 count_enable <= '0';
119 data_in_ack <= (OTHERS => '0');
119 data_in_ack <= (OTHERS => '0');
120 data_out_wen <= (OTHERS => '1');
120 data_out_wen <= (OTHERS => '1');
121 sel_ack <= '0';
121 sel_ack <= '0';
122 IF run = '0' THEN
122 IF run = '0' THEN
123 state <= IDLE;
123 state <= IDLE;
124 ELSE
124 ELSE
125 CASE state IS
125 CASE state IS
126 WHEN IDLE =>
126 WHEN IDLE =>
127 IF no_sel = '0' THEN
127 IF no_sel = '0' THEN
128 state <= TIME1;
128 state <= TIME1;
129 END IF;
129 END IF;
130 WHEN TIME1 =>
130 WHEN TIME1 =>
131 count_enable <= '1';
131 count_enable <= '1';
132 IF UNSIGNED(count) = 0 THEN
132 IF UNSIGNED(count) = 0 THEN
133 state <= TIME2;
133 state <= TIME2;
134 data_out_wen <= NOT sel;
134 data_out_wen <= NOT sel;
135 data_out <= data_sel(0);
135 data_out <= data_sel(0);
136 ELSE
136 ELSE
137 state <= DATA1;
137 state <= DATA1;
138 END IF;
138 END IF;
139 WHEN TIME2 =>
139 WHEN TIME2 =>
140 data_out_wen <= NOT sel;
140 data_out_wen <= NOT sel;
141 data_out <= data_sel(1) ;
141 data_out <= data_sel(1) ;
142 state <= DATA1;
142 state <= DATA1;
143 WHEN DATA1 =>
143 WHEN DATA1 =>
144 data_out_wen <= NOT sel;
144 data_out_wen <= NOT sel;
145 data_out <= data_sel(2);
145 data_out <= data_sel(2);
146 state <= DATA2;
146 state <= DATA2;
147 WHEN DATA2 =>
147 WHEN DATA2 =>
148 data_out_wen <= NOT sel;
148 data_out_wen <= NOT sel;
149 data_out <= data_sel(3);
149 data_out <= data_sel(3);
150 state <= DATA3;
150 state <= DATA3;
151 WHEN DATA3 =>
151 WHEN DATA3 =>
152 data_out_wen <= NOT sel;
152 data_out_wen <= NOT sel;
153 data_out <= data_sel(4);
153 data_out <= data_sel(4);
154 state <= LAST;
154 state <= LAST;
155 data_in_ack <= sel;
155 data_in_ack <= sel;
156 WHEN LAST =>
156 WHEN LAST =>
157 state <= IDLE;
157 state <= IDLE;
158 sel_ack <= '1';
158 sel_ack <= '1';
159
159
160 WHEN OTHERS => NULL;
160 WHEN OTHERS => NULL;
161 END CASE;
161 END CASE;
162 END IF;
162 END IF;
163 END IF;
163 END IF;
164 END PROCESS;
164 END PROCESS;
165 -----------------------------------------------------------------------------
165 -----------------------------------------------------------------------------
166
166
167
167
168 --PROCESS (clk, rstn)
168 --PROCESS (clk, rstn)
169 --BEGIN -- PROCESS
169 --BEGIN -- PROCESS
170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
170 -- IF rstn = '0' THEN -- asynchronous reset (active low)
171 -- count_enable <= '0';
171 -- count_enable <= '0';
172 -- shift_time_enable <= '0';
172 -- shift_time_enable <= '0';
173 -- shift_data_enable <= '0';
173 -- shift_data_enable <= '0';
174 -- data_in_ack <= (OTHERS => '0');
174 -- data_in_ack <= (OTHERS => '0');
175 -- data_out_wen <= (OTHERS => '1');
175 -- data_out_wen <= (OTHERS => '1');
176 -- sel_ack <= '0';
176 -- sel_ack <= '0';
177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
177 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
178 -- IF run = '0' OR no_sel = '1' THEN
178 -- IF run = '0' OR no_sel = '1' THEN
179 -- count_enable <= '0';
179 -- count_enable <= '0';
180 -- shift_time_enable <= '0';
180 -- shift_time_enable <= '0';
181 -- shift_data_enable <= '0';
181 -- shift_data_enable <= '0';
182 -- data_in_ack <= (OTHERS => '0');
182 -- data_in_ack <= (OTHERS => '0');
183 -- data_out_wen <= (OTHERS => '1');
183 -- data_out_wen <= (OTHERS => '1');
184 -- sel_ack <= '0';
184 -- sel_ack <= '0';
185 -- ELSE
185 -- ELSE
186 -- --COUNT
186 -- --COUNT
187 -- IF shift_data_s = "10" THEN
187 -- IF shift_data_s = "10" THEN
188 -- count_enable <= '1';
188 -- count_enable <= '1';
189 -- ELSE
189 -- ELSE
190 -- count_enable <= '0';
190 -- count_enable <= '0';
191 -- END IF;
191 -- END IF;
192 -- --DATA
192 -- --DATA
193 -- IF shift_time_s = "10" THEN
193 -- IF shift_time_s = "10" THEN
194 -- shift_data_enable <= '1';
194 -- shift_data_enable <= '1';
195 -- ELSE
195 -- ELSE
196 -- shift_data_enable <= '0';
196 -- shift_data_enable <= '0';
197 -- END IF;
197 -- END IF;
198
198
199 -- --TIME
199 -- --TIME
200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
200 -- IF ((shift_data_s = "10") AND (count = nb_data_by_buffer)) OR
201 -- shift_time_s = "00" OR
201 -- shift_time_s = "00" OR
202 -- shift_time_s = "01"
202 -- shift_time_s = "01"
203 -- THEN
203 -- THEN
204 -- shift_time_enable <= '1';
204 -- shift_time_enable <= '1';
205 -- ELSE
205 -- ELSE
206 -- shift_time_enable <= '0';
206 -- shift_time_enable <= '0';
207 -- END IF;
207 -- END IF;
208
208
209 -- --ACK
209 -- --ACK
210 -- IF shift_data_s = "10" THEN
210 -- IF shift_data_s = "10" THEN
211 -- data_in_ack <= sel;
211 -- data_in_ack <= sel;
212 -- sel_ack <= '1';
212 -- sel_ack <= '1';
213 -- ELSE
213 -- ELSE
214 -- data_in_ack <= (OTHERS => '0');
214 -- data_in_ack <= (OTHERS => '0');
215 -- sel_ack <= '0';
215 -- sel_ack <= '0';
216 -- END IF;
216 -- END IF;
217
217
218 -- --VALID OUT
218 -- --VALID OUT
219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
219 -- all_wen: FOR I IN 3 DOWNTO 0 LOOP
220 -- IF sel(I) = '1' AND count_enable = '0' THEN
220 -- IF sel(I) = '1' AND count_enable = '0' THEN
221 -- data_out_wen(I) <= '0';
221 -- data_out_wen(I) <= '0';
222 -- ELSE
222 -- ELSE
223 -- data_out_wen(I) <= '1';
223 -- data_out_wen(I) <= '1';
224 -- END IF;
224 -- END IF;
225 -- END LOOP all_wen;
225 -- END LOOP all_wen;
226
226
227 -- END IF;
227 -- END IF;
228 -- END IF;
228 -- END IF;
229 --END PROCESS;
229 --END PROCESS;
230
230
231 -----------------------------------------------------------------------------
231 -----------------------------------------------------------------------------
232 -- DATA MUX
232 -- DATA MUX
233 -----------------------------------------------------------------------------
233 -----------------------------------------------------------------------------
234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
234 all_bit_data_in: FOR I IN 32*5-1 DOWNTO 0 GENERATE
235 I_time_in: IF I < 48 GENERATE
235 I_time_in: IF I < 48 GENERATE
236 data_0_v(I) <= time_in(0,I);
236 data_0_v(I) <= time_in(0,I);
237 data_1_v(I) <= time_in(1,I);
237 data_1_v(I) <= time_in(1,I);
238 data_2_v(I) <= time_in(2,I);
238 data_2_v(I) <= time_in(2,I);
239 data_3_v(I) <= time_in(3,I);
239 data_3_v(I) <= time_in(3,I);
240 END GENERATE I_time_in;
240 END GENERATE I_time_in;
241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
241 I_null: IF (I > 47) AND (I < 32*2) GENERATE
242 data_0_v(I) <= '0';
242 data_0_v(I) <= '0';
243 data_1_v(I) <= '0';
243 data_1_v(I) <= '0';
244 data_2_v(I) <= '0';
244 data_2_v(I) <= '0';
245 data_3_v(I) <= '0';
245 data_3_v(I) <= '0';
246 END GENERATE I_null;
246 END GENERATE I_null;
247 I_data_in: IF I > 32*2-1 GENERATE
247 I_data_in: IF I > 32*2-1 GENERATE
248 data_0_v(I) <= data_in(0,I-32*2);
248 data_0_v(I) <= data_in(0,I-32*2);
249 data_1_v(I) <= data_in(1,I-32*2);
249 data_1_v(I) <= data_in(1,I-32*2);
250 data_2_v(I) <= data_in(2,I-32*2);
250 data_2_v(I) <= data_in(2,I-32*2);
251 data_3_v(I) <= data_in(3,I-32*2);
251 data_3_v(I) <= data_in(3,I-32*2);
252 END GENERATE I_data_in;
252 END GENERATE I_data_in;
253 END GENERATE all_bit_data_in;
253 END GENERATE all_bit_data_in;
254
254
255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
255 all_word: FOR J IN 4 DOWNTO 0 GENERATE
256 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
256 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
257 data_0(J)(I) <= data_0_v(J*32+I);
257 data_0(J)(I) <= data_0_v(J*32+I);
258 data_1(J)(I) <= data_1_v(J*32+I);
258 data_1(J)(I) <= data_1_v(J*32+I);
259 data_2(J)(I) <= data_2_v(J*32+I);
259 data_2(J)(I) <= data_2_v(J*32+I);
260 data_3(J)(I) <= data_3_v(J*32+I);
260 data_3(J)(I) <= data_3_v(J*32+I);
261 END GENERATE all_data_bit;
261 END GENERATE all_data_bit;
262 END GENERATE all_word;
262 END GENERATE all_word;
263
263
264 data_sel <= data_0 WHEN sel(0) = '1' ELSE
264 data_sel <= data_0 WHEN sel(0) = '1' ELSE
265 data_1 WHEN sel(1) = '1' ELSE
265 data_1 WHEN sel(1) = '1' ELSE
266 data_2 WHEN sel(2) = '1' ELSE
266 data_2 WHEN sel(2) = '1' ELSE
267 data_3;
267 data_3;
268
268
269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
269 --data_out <= data_sel(0) WHEN shift_time = "00" ELSE
270 -- data_sel(1) WHEN shift_time = "01" ELSE
270 -- data_sel(1) WHEN shift_time = "01" ELSE
271 -- data_sel(2) WHEN shift_data = "00" ELSE
271 -- data_sel(2) WHEN shift_data = "00" ELSE
272 -- data_sel(3) WHEN shift_data = "01" ELSE
272 -- data_sel(3) WHEN shift_data = "01" ELSE
273 -- data_sel(4);
273 -- data_sel(4);
274
274
275
275
276 -----------------------------------------------------------------------------
276 -----------------------------------------------------------------------------
277 -- RR and SELECTION
277 -- RR and SELECTION
278 -----------------------------------------------------------------------------
278 -----------------------------------------------------------------------------
279 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
279 all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
280 -- valid_in_rr(I) <= data_in_valid(I) AND NOT full(I);
281 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
281 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
282 END GENERATE all_input_rr;
282 END GENERATE all_input_rr;
283
283
284 RR_Arbiter_4_1 : RR_Arbiter_4
284 RR_Arbiter_4_1 : RR_Arbiter_4
285 PORT MAP (
285 PORT MAP (
286 clk => clk,
286 clk => clk,
287 rstn => rstn,
287 rstn => rstn,
288 in_valid => valid_in_rr,
288 in_valid => valid_in_rr,
289 out_grant => sel_s); --sel_s);
289 out_grant => sel_s); --sel_s);
290
290
291 -- sel <= sel_s;
291 -- sel <= sel_s;
292
292
293 PROCESS (clk, rstn)
293 PROCESS (clk, rstn)
294 BEGIN -- PROCESS
294 BEGIN -- PROCESS
295 IF rstn = '0' THEN -- asynchronous reset (active low)
295 IF rstn = '0' THEN -- asynchronous reset (active low)
296 sel <= "0000";
296 sel <= "0000";
297 sel_reg <= '0';
297 sel_reg <= '0';
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
298 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
299 -- sel_reg
299 -- sel_reg
300 -- sel_ack
300 -- sel_ack
301 -- sel_s
301 -- sel_s
302 -- sel = "0000 "
302 -- sel = "0000 "
303 --sel <= sel_s;
303 --sel <= sel_s;
304 IF sel_reg = '0' OR sel_ack = '1'
304 IF sel_reg = '0' OR sel_ack = '1'
305 --OR shift_data_s = "10"
305 --OR shift_data_s = "10"
306 THEN
306 THEN
307 sel <= sel_s;
307 sel <= sel_s;
308 IF sel_s = "0000" THEN
308 IF sel_s = "0000" THEN
309 sel_reg <= '0';
309 sel_reg <= '0';
310 ELSE
310 ELSE
311 sel_reg <= '1';
311 sel_reg <= '1';
312 END IF;
312 END IF;
313 END IF;
313 END IF;
314 END IF;
314 END IF;
315 END PROCESS;
315 END PROCESS;
316
316
317 no_sel <= '1' WHEN sel = "0000" ELSE '0';
317 no_sel <= '1' WHEN sel = "0000" ELSE '0';
318
318
319 -----------------------------------------------------------------------------
319 -----------------------------------------------------------------------------
320 -- REG
320 -- REG
321 -----------------------------------------------------------------------------
321 -----------------------------------------------------------------------------
322 reg_count_i: lpp_waveform_fifo_arbiter_reg
322 reg_count_i: lpp_waveform_fifo_arbiter_reg
323 GENERIC MAP (
323 GENERIC MAP (
324 data_size => nb_data_by_buffer_size,
324 data_size => nb_data_by_buffer_size,
325 data_nb => 4)
325 data_nb => 4)
326 PORT MAP (
326 PORT MAP (
327 clk => clk,
327 clk => clk,
328 rstn => rstn,
328 rstn => rstn,
329 run => run,
329 run => run,
330 max_count => nb_data_by_buffer,
330 max_count => nb_data_by_buffer,
331 enable => count_enable,
331 enable => count_enable,
332 sel => sel,
332 sel => sel,
333 data => count,
333 data => count,
334 data_s => count_s);
334 data_s => count_s);
335
335
336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
336 --reg_shift_data_i: lpp_waveform_fifo_arbiter_reg
337 -- GENERIC MAP (
337 -- GENERIC MAP (
338 -- data_size => 2,
338 -- data_size => 2,
339 -- data_nb => 4)
339 -- data_nb => 4)
340 -- PORT MAP (
340 -- PORT MAP (
341 -- clk => clk,
341 -- clk => clk,
342 -- rstn => rstn,
342 -- rstn => rstn,
343 -- run => run,
343 -- run => run,
344 -- max_count => "10", -- 2
344 -- max_count => "10", -- 2
345 -- enable => shift_data_enable,
345 -- enable => shift_data_enable,
346 -- sel => sel,
346 -- sel => sel,
347 -- data => shift_data,
347 -- data => shift_data,
348 -- data_s => shift_data_s);
348 -- data_s => shift_data_s);
349
349
350
350
351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
351 --reg_shift_time_i: lpp_waveform_fifo_arbiter_reg
352 -- GENERIC MAP (
352 -- GENERIC MAP (
353 -- data_size => 2,
353 -- data_size => 2,
354 -- data_nb => 4)
354 -- data_nb => 4)
355 -- PORT MAP (
355 -- PORT MAP (
356 -- clk => clk,
356 -- clk => clk,
357 -- rstn => rstn,
357 -- rstn => rstn,
358 -- run => run,
358 -- run => run,
359 -- max_count => "10", -- 2
359 -- max_count => "10", -- 2
360 -- enable => shift_time_enable,
360 -- enable => shift_time_enable,
361 -- sel => sel,
361 -- sel => sel,
362 -- data => shift_time,
362 -- data => shift_time,
363 -- data_s => shift_time_s);
363 -- data_s => shift_time_s);
364
364
365
365
366
366
367
367
368 END ARCHITECTURE;
368 END ARCHITECTURE;
369
369
370
370
371
371
372
372
373
373
374
374
375
375
376
376
377
377
378
378
379
379
380
380
381
381
382
382
383
383
384
384
385
385
386
386
387
387
388
388
389
389
390
390
391
391
392
392
393
393
394
394
Show file before | Show file after | Hide comments
@@ -1,117 +1,117
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Jean-christophe PELLION
19 -- Author : Jean-christophe PELLION
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 LIBRARY IEEE;
22 LIBRARY IEEE;
23 USE IEEE.std_logic_1164.ALL;
23 USE IEEE.std_logic_1164.ALL;
24 USE IEEE.numeric_std.ALL;
24 USE IEEE.numeric_std.ALL;
25
25
26 LIBRARY lpp;
26 LIBRARY lpp;
27 USE lpp.lpp_waveform_pkg.ALL;
27 USE lpp.lpp_waveform_pkg.ALL;
28 USE lpp.general_purpose.ALL;
28 USE lpp.general_purpose.ALL;
29
29
30 ENTITY lpp_waveform_fifo_arbiter_reg IS
30 ENTITY lpp_waveform_fifo_arbiter_reg IS
31 GENERIC(
31 GENERIC(
32 data_size : INTEGER;
32 data_size : INTEGER;
33 data_nb : INTEGER
33 data_nb : INTEGER
34 );
34 );
35 PORT(
35 PORT(
36 clk : IN STD_LOGIC;
36 clk : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
37 rstn : IN STD_LOGIC;
38 ---------------------------------------------------------------------------
38 ---------------------------------------------------------------------------
39 run : IN STD_LOGIC;
39 run : IN STD_LOGIC;
40
40
41 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
41 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
42
42
43 enable : IN STD_LOGIC;
43 enable : IN STD_LOGIC;
44 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
44 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
45
45
46 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
46 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
47 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
47 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
48 );
48 );
49 END ENTITY;
49 END ENTITY;
50
50
51
51
52 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
52 ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
53
53
54 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
54 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
55 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
55 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
56
56
57 SIGNAL reg_sel : INTEGER;
57 SIGNAL reg_sel : INTEGER := 0;
58 SIGNAL reg_sel_s : INTEGER;
58 SIGNAL reg_sel_s : INTEGER := 0;
59
59
60 BEGIN
60 BEGIN
61
61
62 all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE
62 all_reg: FOR I IN data_nb-1 DOWNTO 0 GENERATE
63 PROCESS (clk, rstn)
63 PROCESS (clk, rstn)
64 BEGIN -- PROCESS
64 BEGIN -- PROCESS
65 IF rstn = '0' THEN -- asynchronous reset (active low)
65 IF rstn = '0' THEN -- asynchronous reset (active low)
66 reg(I) <= 0;
66 reg(I) <= 0;
67 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
67 ELSIF clk'event AND clk = '1' THEN -- rising clock edge
68 IF run = '0' THEN
68 IF run = '0' THEN
69 reg(I) <= 0;
69 reg(I) <= 0;
70 ELSE
70 ELSE
71 IF sel(I) = '1' THEN
71 IF sel(I) = '1' THEN
72 reg(I) <= reg_sel_s;
72 reg(I) <= reg_sel_s;
73 END IF;
73 END IF;
74 END IF;
74 END IF;
75 END IF;
75 END IF;
76 END PROCESS;
76 END PROCESS;
77 END GENERATE all_reg;
77 END GENERATE all_reg;
78
78
79 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
79 reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
80 reg(1) WHEN sel(1) = '1' ELSE
80 reg(1) WHEN sel(1) = '1' ELSE
81 reg(2) WHEN sel(2) = '1' ELSE
81 reg(2) WHEN sel(2) = '1' ELSE
82 reg(3);
82 reg(3);
83
83
84 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
84 reg_sel_s <= reg_sel WHEN enable = '0' ELSE
85 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
85 reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
86 0;
86 0;
87
87
88 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size));
88 data <= STD_LOGIC_VECTOR(to_unsigned(reg_sel ,data_size));
89 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size));
89 data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s,data_size));
90
90
91 END ARCHITECTURE;
91 END ARCHITECTURE;
92
92
93
93
94
94
95
95
96
96
97
97
98
98
99
99
100
100
101
101
102
102
103
103
104
104
105
105
106
106
107
107
108
108
109
109
110
110
111
111
112
112
113
113
114
114
115
115
116
116
117
117
Show file before | Show file after | Hide comments
@@ -1,364 +1,375
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
21 -- jean-christophe.pellion@easii-ic.com
22 -------------------------------------------------------------------------------
22 -------------------------------------------------------------------------------
23 LIBRARY IEEE;
23 LIBRARY IEEE;
24 USE IEEE.STD_LOGIC_1164.ALL;
24 USE IEEE.STD_LOGIC_1164.ALL;
25
25
26 LIBRARY grlib;
26 LIBRARY grlib;
27 USE grlib.amba.ALL;
27 USE grlib.amba.ALL;
28 USE grlib.stdlib.ALL;
28 USE grlib.stdlib.ALL;
29 USE grlib.devices.ALL;
29 USE grlib.devices.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
30 USE GRLIB.DMA2AHB_Package.ALL;
31
31
32 LIBRARY techmap;
32 LIBRARY techmap;
33 USE techmap.gencomp.ALL;
33 USE techmap.gencomp.ALL;
34
34
35 PACKAGE lpp_waveform_pkg IS
35 PACKAGE lpp_waveform_pkg IS
36
36
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
37 TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
38
38
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
39 TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
40
40
41 -----------------------------------------------------------------------------
41 -----------------------------------------------------------------------------
42 -- SNAPSHOT
42 -- SNAPSHOT
43 -----------------------------------------------------------------------------
43 -----------------------------------------------------------------------------
44
44
45 COMPONENT lpp_waveform_snapshot
45 COMPONENT lpp_waveform_snapshot
46 GENERIC (
46 GENERIC (
47 data_size : INTEGER;
47 data_size : INTEGER;
48 nb_snapshot_param_size : INTEGER);
48 nb_snapshot_param_size : INTEGER);
49 PORT (
49 PORT (
50 clk : IN STD_LOGIC;
50 clk : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
51 rstn : IN STD_LOGIC;
52 run : IN STD_LOGIC;
52 run : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
53 enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
54 burst_enable : IN STD_LOGIC;
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
55 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
56 start_snapshot : IN STD_LOGIC;
56 start_snapshot : IN STD_LOGIC;
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
57 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
58 data_in_valid : IN STD_LOGIC;
58 data_in_valid : IN STD_LOGIC;
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
59 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
60 data_out_valid : OUT STD_LOGIC);
60 data_out_valid : OUT STD_LOGIC);
61 END COMPONENT;
61 END COMPONENT;
62
62
63 COMPONENT lpp_waveform_burst
63 COMPONENT lpp_waveform_burst
64 GENERIC (
64 GENERIC (
65 data_size : INTEGER);
65 data_size : INTEGER);
66 PORT (
66 PORT (
67 clk : IN STD_LOGIC;
67 clk : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
68 rstn : IN STD_LOGIC;
69 run : IN STD_LOGIC;
69 run : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
70 enable : IN STD_LOGIC;
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
71 data_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
72 data_in_valid : IN STD_LOGIC;
72 data_in_valid : IN STD_LOGIC;
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
73 data_out : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
74 data_out_valid : OUT STD_LOGIC);
74 data_out_valid : OUT STD_LOGIC);
75 END COMPONENT;
75 END COMPONENT;
76
76
77 COMPONENT lpp_waveform_snapshot_controler
77 COMPONENT lpp_waveform_snapshot_controler
78 GENERIC (
78 GENERIC (
79 delta_vector_size : INTEGER;
79 delta_vector_size : INTEGER;
80 delta_vector_size_f0_2 : INTEGER);
80 delta_vector_size_f0_2 : INTEGER);
81 PORT (
81 PORT (
82 clk : IN STD_LOGIC;
82 clk : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
83 rstn : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
84 reg_run : IN STD_LOGIC;
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
85 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
86 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
87 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
88 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
89 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
90 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
91 coarse_time : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
92 data_f0_valid : IN STD_LOGIC;
92 data_f0_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
93 data_f2_valid : IN STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
94 start_snapshot_f0 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
95 start_snapshot_f1 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
96 start_snapshot_f2 : OUT STD_LOGIC;
97 wfp_on : OUT STD_LOGIC);
97 wfp_on : OUT STD_LOGIC);
98 END COMPONENT;
98 END COMPONENT;
99
99
100 -----------------------------------------------------------------------------
100 -----------------------------------------------------------------------------
101 --
101 --
102 -----------------------------------------------------------------------------
102 -----------------------------------------------------------------------------
103 COMPONENT lpp_waveform
103 COMPONENT lpp_waveform
104 GENERIC (
104 GENERIC (
105 tech : INTEGER;
105 tech : INTEGER;
106 data_size : INTEGER;
106 data_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
107 nb_data_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
108 nb_word_by_buffer_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
109 nb_snapshot_param_size : INTEGER;
110 delta_vector_size : INTEGER;
110 delta_vector_size : INTEGER;
111 delta_vector_size_f0_2 : INTEGER);
111 delta_vector_size_f0_2 : INTEGER);
112 PORT (
112 PORT (
113 clk : IN STD_LOGIC;
113 clk : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
114 rstn : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
115 reg_run : IN STD_LOGIC;
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
116 reg_start_date : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
117 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
118 reg_delta_f0 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
119 reg_delta_f0_2 : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
120 reg_delta_f1 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
121 reg_delta_f2 : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
122 enable_f0 : IN STD_LOGIC;
122 enable_f0 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
123 enable_f1 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
124 enable_f2 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
125 enable_f3 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
126 burst_f0 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
127 burst_f1 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
128 burst_f2 : IN STD_LOGIC;
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
129 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
130 nb_word_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
131 nb_snapshot_param : IN STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
132 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
133 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
134 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
135 status_new_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
136 coarse_time : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
137 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
138 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
139 data_f0_in_valid : IN STD_LOGIC;
139 data_f0_in_valid : IN STD_LOGIC;
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 data_f0_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
141 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
142 data_f1_in_valid : IN STD_LOGIC;
142 data_f1_in_valid : IN STD_LOGIC;
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
143 data_f1_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
144 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
145 data_f2_in_valid : IN STD_LOGIC;
145 data_f2_in_valid : IN STD_LOGIC;
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
146 data_f2_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
147 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
148 data_f3_in_valid : IN STD_LOGIC;
148 data_f3_in_valid : IN STD_LOGIC;
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
149 data_f3_in : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
151 data_f0_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
152 data_f0_data_out_valid : OUT STD_LOGIC;
152 data_f0_data_out_valid : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
153 data_f0_data_out_valid_burst : OUT STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
154 data_f0_data_out_ren : IN STD_LOGIC;
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
155 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
156 data_f1_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
157 data_f1_data_out_valid : OUT STD_LOGIC;
157 data_f1_data_out_valid : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
158 data_f1_data_out_valid_burst : OUT STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
159 data_f1_data_out_ren : IN STD_LOGIC;
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
160 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
161 data_f2_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
162 data_f2_data_out_valid : OUT STD_LOGIC;
162 data_f2_data_out_valid : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
163 data_f2_data_out_valid_burst : OUT STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
164 data_f2_data_out_ren : IN STD_LOGIC;
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
165 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
166 data_f3_data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
167 data_f3_data_out_valid : OUT STD_LOGIC;
167 data_f3_data_out_valid : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
168 data_f3_data_out_valid_burst : OUT STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
169 data_f3_data_out_ren : IN STD_LOGIC;
170
170
171 --debug
171 --debug
172 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
172 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
173 debug_f0_data_valid : OUT STD_LOGIC;
173 debug_f0_data_valid : OUT STD_LOGIC;
174 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
174 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
175 debug_f1_data_valid : OUT STD_LOGIC;
175 debug_f1_data_valid : OUT STD_LOGIC;
176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177 debug_f2_data_valid : OUT STD_LOGIC;
177 debug_f2_data_valid : OUT STD_LOGIC;
178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 debug_f3_data_valid : OUT STD_LOGIC);
179 debug_f3_data_valid : OUT STD_LOGIC;
180
181 --debug FIFO IN
182 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
184 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
186 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
188 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
190 );
180 END COMPONENT;
191 END COMPONENT;
181
192
182 COMPONENT lpp_waveform_dma_genvalid
193 COMPONENT lpp_waveform_dma_genvalid
183 PORT (
194 PORT (
184 HCLK : IN STD_LOGIC;
195 HCLK : IN STD_LOGIC;
185 HRESETn : IN STD_LOGIC;
196 HRESETn : IN STD_LOGIC;
186 run : IN STD_LOGIC;
197 run : IN STD_LOGIC;
187 valid_in : IN STD_LOGIC;
198 valid_in : IN STD_LOGIC;
188 ack_in : IN STD_LOGIC;
199 ack_in : IN STD_LOGIC;
189 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
200 time_in : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
190 valid_out : OUT STD_LOGIC;
201 valid_out : OUT STD_LOGIC;
191 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
202 time_out : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
192 error : OUT STD_LOGIC);
203 error : OUT STD_LOGIC);
193 END COMPONENT;
204 END COMPONENT;
194
205
195 -----------------------------------------------------------------------------
206 -----------------------------------------------------------------------------
196 -- FIFO
207 -- FIFO
197 -----------------------------------------------------------------------------
208 -----------------------------------------------------------------------------
198 COMPONENT lpp_waveform_fifo_ctrl
209 COMPONENT lpp_waveform_fifo_ctrl
199 GENERIC (
210 GENERIC (
200 offset : INTEGER;
211 offset : INTEGER;
201 length : INTEGER);
212 length : INTEGER);
202 PORT (
213 PORT (
203 clk : IN STD_LOGIC;
214 clk : IN STD_LOGIC;
204 rstn : IN STD_LOGIC;
215 rstn : IN STD_LOGIC;
205 run : IN STD_LOGIC;
216 run : IN STD_LOGIC;
206 ren : IN STD_LOGIC;
217 ren : IN STD_LOGIC;
207 wen : IN STD_LOGIC;
218 wen : IN STD_LOGIC;
208 mem_re : OUT STD_LOGIC;
219 mem_re : OUT STD_LOGIC;
209 mem_we : OUT STD_LOGIC;
220 mem_we : OUT STD_LOGIC;
210 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
221 mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
211 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
222 mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
212 empty_almost : OUT STD_LOGIC;
223 empty_almost : OUT STD_LOGIC;
213 empty : OUT STD_LOGIC;
224 empty : OUT STD_LOGIC;
214 full_almost : OUT STD_LOGIC;
225 full_almost : OUT STD_LOGIC;
215 full : OUT STD_LOGIC);
226 full : OUT STD_LOGIC);
216 END COMPONENT;
227 END COMPONENT;
217
228
218 COMPONENT lpp_waveform_fifo_arbiter
229 COMPONENT lpp_waveform_fifo_arbiter
219 GENERIC (
230 GENERIC (
220 tech : INTEGER;
231 tech : INTEGER;
221 nb_data_by_buffer_size : INTEGER);
232 nb_data_by_buffer_size : INTEGER);
222 PORT (
233 PORT (
223 clk : IN STD_LOGIC;
234 clk : IN STD_LOGIC;
224 rstn : IN STD_LOGIC;
235 rstn : IN STD_LOGIC;
225 run : IN STD_LOGIC;
236 run : IN STD_LOGIC;
226 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
237 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
227 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
238 data_in_valid : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
228 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
239 data_in_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
229 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
240 data_in : IN Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
230 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
241 time_in : IN Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
231 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
242 data_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
232 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
243 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
233 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
244 full_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
234 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
245 full : IN STD_LOGIC_VECTOR(3 DOWNTO 0));
235 END COMPONENT;
246 END COMPONENT;
236
247
237 COMPONENT lpp_waveform_fifo
248 COMPONENT lpp_waveform_fifo
238 GENERIC (
249 GENERIC (
239 tech : INTEGER);
250 tech : INTEGER);
240 PORT (
251 PORT (
241 clk : IN STD_LOGIC;
252 clk : IN STD_LOGIC;
242 rstn : IN STD_LOGIC;
253 rstn : IN STD_LOGIC;
243 run : IN STD_LOGIC;
254 run : IN STD_LOGIC;
244 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
255 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
245 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
256 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
246 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
257 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
247 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
258 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
248 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
259 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
249 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
260 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
250 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
261 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
251 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
262 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
252 END COMPONENT;
263 END COMPONENT;
253
264
254 COMPONENT lpp_waveform_fifo_headreg
265 COMPONENT lpp_waveform_fifo_headreg
255 GENERIC (
266 GENERIC (
256 tech : INTEGER);
267 tech : INTEGER);
257 PORT (
268 PORT (
258 clk : IN STD_LOGIC;
269 clk : IN STD_LOGIC;
259 rstn : IN STD_LOGIC;
270 rstn : IN STD_LOGIC;
260 run : IN STD_LOGIC;
271 run : IN STD_LOGIC;
261 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
272 o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
262 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
273 o_empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
263 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
274 o_data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
264 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
275 o_rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
265 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
276 o_rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
266 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
277 o_rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
267 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
278 o_rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
268 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
279 i_empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
269 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
280 i_empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
270 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
281 i_data_ren : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
271 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
282 i_rdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
272 END COMPONENT;
283 END COMPONENT;
273
284
274 COMPONENT lpp_waveform_fifo_latencyCorrection
285 COMPONENT lpp_waveform_fifo_latencyCorrection
275 GENERIC (
286 GENERIC (
276 tech : INTEGER);
287 tech : INTEGER);
277 PORT (
288 PORT (
278 clk : IN STD_LOGIC;
289 clk : IN STD_LOGIC;
279 rstn : IN STD_LOGIC;
290 rstn : IN STD_LOGIC;
280 run : IN STD_LOGIC;
291 run : IN STD_LOGIC;
281 empty_almost : OUT STD_LOGIC;
292 empty_almost : OUT STD_LOGIC;
282 empty : OUT STD_LOGIC;
293 empty : OUT STD_LOGIC;
283 data_ren : IN STD_LOGIC;
294 data_ren : IN STD_LOGIC;
284 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
295 rdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
285 empty_almost_fifo : IN STD_LOGIC;
296 empty_almost_fifo : IN STD_LOGIC;
286 empty_fifo : IN STD_LOGIC;
297 empty_fifo : IN STD_LOGIC;
287 data_ren_fifo : OUT STD_LOGIC;
298 data_ren_fifo : OUT STD_LOGIC;
288 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
299 rdata_fifo : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
289 END COMPONENT;
300 END COMPONENT;
290
301
291 COMPONENT lpp_waveform_fifo_withoutLatency
302 COMPONENT lpp_waveform_fifo_withoutLatency
292 GENERIC (
303 GENERIC (
293 tech : INTEGER);
304 tech : INTEGER);
294 PORT (
305 PORT (
295 clk : IN STD_LOGIC;
306 clk : IN STD_LOGIC;
296 rstn : IN STD_LOGIC;
307 rstn : IN STD_LOGIC;
297 run : IN STD_LOGIC;
308 run : IN STD_LOGIC;
298 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
309 empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
299 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
310 empty : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
300 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
311 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
301 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
312 rdata_0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
302 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
313 rdata_1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
303 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
314 rdata_2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
304 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
315 rdata_3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
305 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
316 full_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
306 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
317 full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
307 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
318 data_wen : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
308 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
319 wdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
309 END COMPONENT;
320 END COMPONENT;
310
321
311 -----------------------------------------------------------------------------
322 -----------------------------------------------------------------------------
312 -- GEN ADDRESS
323 -- GEN ADDRESS
313 -----------------------------------------------------------------------------
324 -----------------------------------------------------------------------------
314 COMPONENT lpp_waveform_genaddress
325 COMPONENT lpp_waveform_genaddress
315 GENERIC (
326 GENERIC (
316 nb_data_by_buffer_size : INTEGER);
327 nb_data_by_buffer_size : INTEGER);
317 PORT (
328 PORT (
318 clk : IN STD_LOGIC;
329 clk : IN STD_LOGIC;
319 rstn : IN STD_LOGIC;
330 rstn : IN STD_LOGIC;
320 run : IN STD_LOGIC;
331 run : IN STD_LOGIC;
321 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
332 nb_data_by_buffer : IN STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
322 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
333 addr_data_f0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
323 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
334 addr_data_f1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
324 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
335 addr_data_f2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
325 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
336 addr_data_f3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
326 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
337 empty : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
327 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
338 empty_almost : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
328 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
339 data_ren : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
329 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
340 status_full : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
330 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
341 status_full_ack : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
331 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
342 status_full_err : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
332 data_f0_data_out_valid_burst : OUT STD_LOGIC;
343 data_f0_data_out_valid_burst : OUT STD_LOGIC;
333 data_f1_data_out_valid_burst : OUT STD_LOGIC;
344 data_f1_data_out_valid_burst : OUT STD_LOGIC;
334 data_f2_data_out_valid_burst : OUT STD_LOGIC;
345 data_f2_data_out_valid_burst : OUT STD_LOGIC;
335 data_f3_data_out_valid_burst : OUT STD_LOGIC;
346 data_f3_data_out_valid_burst : OUT STD_LOGIC;
336 data_f0_data_out_valid : OUT STD_LOGIC;
347 data_f0_data_out_valid : OUT STD_LOGIC;
337 data_f1_data_out_valid : OUT STD_LOGIC;
348 data_f1_data_out_valid : OUT STD_LOGIC;
338 data_f2_data_out_valid : OUT STD_LOGIC;
349 data_f2_data_out_valid : OUT STD_LOGIC;
339 data_f3_data_out_valid : OUT STD_LOGIC;
350 data_f3_data_out_valid : OUT STD_LOGIC;
340 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
351 data_f0_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
341 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
352 data_f1_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
342 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
353 data_f2_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
343 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
354 data_f3_addr_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
344 END COMPONENT;
355 END COMPONENT;
345
356
346 -----------------------------------------------------------------------------
357 -----------------------------------------------------------------------------
347 -- lpp_waveform_fifo_arbiter_reg
358 -- lpp_waveform_fifo_arbiter_reg
348 -----------------------------------------------------------------------------
359 -----------------------------------------------------------------------------
349 COMPONENT lpp_waveform_fifo_arbiter_reg
360 COMPONENT lpp_waveform_fifo_arbiter_reg
350 GENERIC (
361 GENERIC (
351 data_size : INTEGER;
362 data_size : INTEGER;
352 data_nb : INTEGER);
363 data_nb : INTEGER);
353 PORT (
364 PORT (
354 clk : IN STD_LOGIC;
365 clk : IN STD_LOGIC;
355 rstn : IN STD_LOGIC;
366 rstn : IN STD_LOGIC;
356 run : IN STD_LOGIC;
367 run : IN STD_LOGIC;
357 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
368 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
358 enable : IN STD_LOGIC;
369 enable : IN STD_LOGIC;
359 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
370 sel : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
360 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
371 data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
361 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
372 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
362 END COMPONENT;
373 END COMPONENT;
363
374
364 END lpp_waveform_pkg;
375 END lpp_waveform_pkg;
General Comments 0
You need to be logged in to leave comments. Login now