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Correction LPP_DMA - simulation ok avec une RAM externe (CY7C1061DV33)
pellion -
r286:8b7f4967459c JC
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@@ -32,7 +32,7 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 USE gaisler.spacewire.ALL; -- PLE
35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
@@ -61,15 +61,15 ENTITY MINI_LFR_top IS
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
64 nCTS1 : OUT STD_LOGIC;
65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
69 nCTS2 : OUT STD_LOGIC;
70 nDTR2 : IN STD_LOGIC;
71 nRTS2 : IN STD_LOGIC;
72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
@@ -86,19 +86,19 ENTITY MINI_LFR_top IS
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
@@ -113,36 +113,58 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
116 SIGNAL clk_50_s : STD_LOGIC := '0';
117 SIGNAL clk_25 : STD_LOGIC := '0';
118 118 -----------------------------------------------------------------------------
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
119 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
120 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
121 121 --
122 SIGNAL errorn : STD_LOGIC;
122 SIGNAL errorn : STD_LOGIC;
123 123 -- UART AHB ---------------------------------------------------------------
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
124 SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
125 SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
126 126
127 127 -- UART APB ---------------------------------------------------------------
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
131 SIGNAL I00_s : STD_LOGIC;
128 SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
129 SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
130 --
131 SIGNAL I00_s : STD_LOGIC;
132 132 --
133 CONSTANT NB_APB_SLAVE : INTEGER := 1;
133 CONSTANT NB_APB_SLAVE : INTEGER := 4; -- previous value 1, 3 takes the waveform picker and the time manager into account
134 134 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
135 CONSTANT NB_AHB_MASTER : INTEGER := 1;
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5):= (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3):= (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1):= (OTHERS => ahbm_none);
143 --
144 SIGNAL IO_s : STD_LOGIC_VECTOR(11 DOWNTO 0);
145
135 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- previous value 1, 2 takes the waveform picker into account
136
137 SIGNAL apbi_ext : apb_slv_in_type;
138 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
139 SIGNAL ahbi_s_ext : ahb_slv_in_type;
140 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
141 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
142 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
143
144 -- Spacewire signals
145 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
146 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
147 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
148 SIGNAL spw_rxtxclk : STD_ULOGIC;
149 SIGNAL spw_rxclkn : STD_ULOGIC;
150 SIGNAL spw_clk : STD_LOGIC;
151 SIGNAL swni : grspw_in_type;
152 SIGNAL swno : grspw_out_type;
153 -- SIGNAL clkmn : STD_ULOGIC;
154 -- SIGNAL txclk : STD_ULOGIC;
155
156 -- AD Converter RHF1401
157 SIGNAL sample : Samples14v(7 DOWNTO 0);
158 SIGNAL sample_val : STD_LOGIC;
159 -- ADC --------------------------------------------------------------------
160 SIGNAL ADC_OEB_bar_CH_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
161 SIGNAL ADC_smpclk_sig : STD_LOGIC;
162 SIGNAL ADC_data_sig : STD_LOGIC_VECTOR(13 DOWNTO 0);
163
164 SIGNAL bias_fail_sw_sig : STD_LOGIC;
165 -----------------------------------------------------------------------------
166 SIGNAL sample_val_s : STD_LOGIC;
167 SIGNAL sample_val_s2 : STD_LOGIC;
146 168 BEGIN -- beh
147 169
148 170 -----------------------------------------------------------------------------
@@ -155,7 +177,7 BEGIN -- beh
155 177 clk_50_s <= NOT clk_50_s;
156 178 END IF;
157 179 END PROCESS;
158
180
159 181 PROCESS(clk_50_s)
160 182 BEGIN
161 183 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
@@ -164,15 +186,16 BEGIN -- beh
164 186 END PROCESS;
165 187
166 188 -----------------------------------------------------------------------------
167
189
168 190 PROCESS (clk_25, reset)
169 191 BEGIN -- PROCESS
170 192 IF reset = '0' THEN -- asynchronous reset (active low)
171 193 LED0 <= '0';
172 194 LED1 <= '0';
173 195 LED2 <= '0';
174 IO1 <= '0';
175 IO2 <= '1';
196 IO0 <= '0';
197 --IO1 <= '0';
198 IO2 <= '1';
176 199 IO3 <= '0';
177 200 IO4 <= '0';
178 201 IO5 <= '0';
@@ -182,75 +205,49 BEGIN -- beh
182 205 IO9 <= '0';
183 206 IO10 <= '0';
184 207 IO11 <= '0';
185 ELSIF clk_25'event AND clk_25 = '1' THEN -- rising clock edge
208 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
186 209 LED0 <= '0';
187 210 LED1 <= '1';
188 211 LED2 <= BP0;
189 IO1 <= '1';
190 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
191 IO3 <= ADC_SDO(0) OR ADC_SDO(1);
192 IO4 <= ADC_SDO(2) OR ADC_SDO(1);
193 IO5 <= ADC_SDO(3) OR ADC_SDO(4);
194 IO6 <= ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
195 IO7 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
196 IO8 <= IO_s(8);
197 IO9 <= IO_s(9);
198 IO10 <= IO_s(10);
199 IO11 <= IO_s(11);
212 IO0 <= '1';
213 --IO1 <= '1';
214 IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
215 IO3 <= ADC_SDO(0) OR ADC_SDO(1) OR ADC_SDO(2) OR ADC_SDO(3) OR ADC_SDO(4) OR ADC_SDO(5) OR ADC_SDO(6) OR ADC_SDO(7);
216 IO4 <= sample_val;
217 IO5 <= ahbi_m_ext.HREADY;
218 IO6 <= ahbi_m_ext.HRESP(0);
219 IO7 <= ahbi_m_ext.HRESP(1);
220 IO8 <= ahbi_m_ext.HGRANT(2);
221 IO9 <= ahbo_m_ext(2).HLOCK;
222 IO10 <= ahbo_m_ext(2).HBUSREQ;
223 IO11 <= sample_val_s2;
200 224 END IF;
201 225 END PROCESS;
202
203 PROCESS (clk_49, reset)
204 BEGIN -- PROCESS
205 IF reset = '0' THEN -- asynchronous reset (active low)
206 I00_s <= '0';
207 ELSIF clk_49'event AND clk_49 = '1' THEN -- rising clock edge
208 I00_s <= NOT I00_s;
209 END IF;
210 END PROCESS;
211 IO0 <= I00_s;
226
227 --PROCESS (clk_49, reset)
228 --BEGIN -- PROCESS
229 -- IF reset = '0' THEN -- asynchronous reset (active low)
230 -- I00_s <= '0';
231 -- ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
232 -- I00_s <= NOT I00_s;
233 -- END IF;
234 --END PROCESS;
235 --IO0 <= I00_s;
212 236
213 237 --UARTs
214 nCTS1 <= '1';
215 nCTS2 <= '1';
216 nDCD2 <= '1';
238 nCTS1 <= '1';
239 nCTS2 <= '1';
240 nDCD2 <= '1';
241
242 --EXT CONNECTOR
217 243
218 244 --SPACE WIRE
219 SPW_EN <= '0'; -- 0 => off
220
221 SPW_NOM_DOUT <= '0';
222 SPW_NOM_SOUT <= '0';
223 SPW_RED_DOUT <= '0';
224 SPW_RED_SOUT <= '0';
225
226 ADC_nCS <= '0';
227 ADC_CLK <= '0';
228 245
229
230 -----------------------------------------------------------------------------
231 lpp_debug_dma_singleOrBurst_1: lpp_debug_dma_singleOrBurst
232 GENERIC MAP (
233 tech => apa3e,
234 hindex => 1,
235 pindex => 5,
236 paddr => 5,
237 pmask => 16#fff#)
238 PORT MAP (
239 HCLK => clk_25,
240 HRESETn => reset ,
241 ahbmi => ahbi_m_ext ,
242 ahbmo => ahbo_m_ext(1),
243 apbi => apbi_ext,
244 apbo => apbo_ext(5),
245 out_ren => IO_s(11),
246 out_send => IO_s(10),
247 out_done => IO_s(9),
248 out_dmaout_okay => IO_s(8)
249 );
250
251 -----------------------------------------------------------------------------
246 ADC_nCS <= '0';
247 ADC_CLK <= '0';
252 248
253 leon3_soc_1: leon3_soc
249
250 leon3_soc_1 : leon3_soc
254 251 GENERIC MAP (
255 252 fabtech => apa3e,
256 253 memtech => apa3e,
@@ -270,30 +267,213 BEGIN -- beh
270 267 ENABLE_GPT => 1,
271 268 NB_AHB_MASTER => NB_AHB_MASTER,
272 269 NB_AHB_SLAVE => NB_AHB_SLAVE,
273 NB_APB_SLAVE => NB_APB_SLAVE)
270 NB_APB_SLAVE => NB_APB_SLAVE)
274 271 PORT MAP (
275 clk => clk_25,
276 reset => reset,
277 errorn => errorn,
278 ahbrxd => TXD1,
279 ahbtxd => RXD1,
280 urxd1 => TXD2,
281 utxd1 => RXD2,
282 address => SRAM_A,
283 data => SRAM_DQ,
284 nSRAM_BE0 => SRAM_nBE(0),
285 nSRAM_BE1 => SRAM_nBE(1),
286 nSRAM_BE2 => SRAM_nBE(2),
287 nSRAM_BE3 => SRAM_nBE(3),
288 nSRAM_WE => SRAM_nWE,
289 nSRAM_CE => SRAM_CE,
290 nSRAM_OE => SRAM_nOE,
291
272 clk => clk_25,
273 reset => reset,
274 errorn => errorn,
275 ahbrxd => TXD1,
276 ahbtxd => RXD1,
277 urxd1 => TXD2,
278 utxd1 => RXD2,
279 address => SRAM_A,
280 data => SRAM_DQ,
281 nSRAM_BE0 => SRAM_nBE(0),
282 nSRAM_BE1 => SRAM_nBE(1),
283 nSRAM_BE2 => SRAM_nBE(2),
284 nSRAM_BE3 => SRAM_nBE(3),
285 nSRAM_WE => SRAM_nWE,
286 nSRAM_CE => SRAM_CE,
287 nSRAM_OE => SRAM_nOE,
288
292 289 apbi_ext => apbi_ext,
293 290 apbo_ext => apbo_ext,
294 291 ahbi_s_ext => ahbi_s_ext,
295 292 ahbo_s_ext => ahbo_s_ext,
296 293 ahbi_m_ext => ahbi_m_ext,
297 294 ahbo_m_ext => ahbo_m_ext);
295
296 -------------------------------------------------------------------------------
297 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
298 -------------------------------------------------------------------------------
299 apb_lfr_time_management_1 : apb_lfr_time_management
300 GENERIC MAP (
301 pindex => 7,
302 paddr => 7,
303 pmask => 16#fff#,
304 pirq => 12)
305 PORT MAP (
306 clk25MHz => clk_25,
307 clk49_152MHz => clk_49,
308 resetn => reset,
309 grspw_tick => swno.tickout,
310 apbi => apbi_ext,
311 apbo => apbo_ext(7),
312 coarse_time => coarse_time,
313 fine_time => fine_time);
314
315 -----------------------------------------------------------------------
316 --- SpaceWire --------------------------------------------------------
317 -----------------------------------------------------------------------
318
319 SPW_EN <= '1';
320
321 spw_clk <= clk_50_s;
322 spw_rxtxclk <= spw_clk;
323 spw_rxclkn <= NOT spw_rxtxclk;
324
325 -- PADS for SPW1
326 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
327 PORT MAP (SPW_NOM_DIN, dtmp(0));
328 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
329 PORT MAP (SPW_NOM_SIN, stmp(0));
330 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
331 PORT MAP (SPW_NOM_DOUT, swno.d(0));
332 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
333 PORT MAP (SPW_NOM_SOUT, swno.s(0));
334 -- PADS FOR SPW2
335 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
336 PORT MAP (SPW_RED_SIN, dtmp(1));
337 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
338 PORT MAP (SPW_RED_DIN, stmp(1));
339 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
340 PORT MAP (SPW_RED_DOUT, swno.d(1));
341 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
342 PORT MAP (SPW_RED_SOUT, swno.s(1));
343
344 -- GRSPW PHY
345 --spw1_input: if CFG_SPW_GRSPW = 1 generate
346 spw_inputloop : FOR j IN 0 TO 1 GENERATE
347 spw_phy0 : grspw_phy
348 GENERIC MAP(
349 tech => apa3e,
350 rxclkbuftype => 1,
351 scantest => 0)
352 PORT MAP(
353 rxrst => swno.rxrst,
354 di => dtmp(j),
355 si => stmp(j),
356 rxclko => spw_rxclk(j),
357 do => swni.d(j),
358 ndo => swni.nd(j*5+4 DOWNTO j*5),
359 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
360 END GENERATE spw_inputloop;
361
362 -- SPW core
363 sw0 : grspwm GENERIC MAP(
364 tech => apa3e,
365 hindex => 1,
366 pindex => 5,
367 paddr => 5,
368 pirq => 11,
369 sysfreq => 25000, -- CPU_FREQ
370 rmap => 1,
371 rmapcrc => 1,
372 fifosize1 => 16,
373 fifosize2 => 16,
374 rxclkbuftype => 1,
375 rxunaligned => 0,
376 rmapbufs => 4,
377 ft => 0,
378 netlist => 0,
379 ports => 2,
380 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
381 memtech => apa3e,
382 destkey => 2,
383 spwcore => 1
384 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
385 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
386 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
387 )
388 PORT MAP(reset, clk_25, spw_rxclk(0),
389 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
390 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
391 swni, swno);
392
393 swni.tickin <= '0';
394 swni.rmapen <= '1';
395 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
396 swni.tickinraw <= '0';
397 swni.timein <= (OTHERS => '0');
398 swni.dcrstval <= (OTHERS => '0');
399 swni.timerrstval <= (OTHERS => '0');
400
401 -------------------------------------------------------------------------------
402 -- LFR ------------------------------------------------------------------------
403 -------------------------------------------------------------------------------
404 lpp_lfr_1 : lpp_lfr
405 GENERIC MAP (
406 Mem_use => use_RAM,
407 nb_data_by_buffer_size => 32,
408 nb_word_by_buffer_size => 30,
409 nb_snapshot_param_size => 32,
410 delta_vector_size => 32,
411 delta_vector_size_f0_2 => 7, -- log2(96)
412 pindex => 6,
413 paddr => 6,
414 pmask => 16#fff#,
415 pirq_ms => 6,
416 pirq_wfp => 14,
417 hindex => 2,
418 top_lfr_version => X"00000009")
419 PORT MAP (
420 clk => clk_25,
421 rstn => reset,
422 sample_B => sample(2 DOWNTO 0),
423 sample_E => sample(7 DOWNTO 3),
424 sample_val => sample_val,
425 apbi => apbi_ext,
426 apbo => apbo_ext(6),
427 ahbi => ahbi_m_ext,
428 ahbo => ahbo_m_ext(2),
429 coarse_time => coarse_time,
430 fine_time => fine_time,
431 data_shaping_BW => bias_fail_sw_sig);
432
433 top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
434 GENERIC MAP (
435 ChanelCount => 8,
436 ncycle_cnv_high => 79,
437 ncycle_cnv => 500)
438 PORT MAP (
439 cnv_clk => clk_49,
440 cnv_rstn => reset,
441 cnv => ADC_smpclk_sig,
442 clk => clk_25,
443 rstn => reset,
444 ADC_data => ADC_data_sig,
445 ADC_nOE => ADC_OEB_bar_CH_sig,
446 sample => OPEN,
447 sample_val => sample_val);--OPEN );--
448
449 ADC_data_sig <= (OTHERS => '1');
450
451 lpp_debug_lfr_1 : lpp_debug_lfr
452 GENERIC MAP (
453 pindex => 8,
454 paddr => 8,
455 pmask => 16#fff#)
456 PORT MAP (
457 HCLK => clk_25,
458 HRESETn => reset,
459 apbi => apbi_ext,
460 apbo => apbo_ext(8),
461 sample_B => sample(2 DOWNTO 0),
462 sample_E => sample(7 DOWNTO 3));
463
464 PROCESS (clk_25, reset)
465 BEGIN -- PROCESS
466 IF reset = '0' THEN -- asynchronous reset (active low)
467 sample_val_s2 <= '0';
468 sample_val_s <= '0';
469 --sample_val <= '0';
470 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
471 sample_val_s <= IO1;
472 sample_val_s2 <= sample_val_s;
473 --sample_val <= (NOT sample_val_s2) AND sample_val_s;
474 END IF;
475 END PROCESS;
476
477
298 478
299 479 END beh;
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@@ -19,7 +19,7 CLEAN=soft-clean
19 19 TECHLIBS = proasic3e
20 20
21 21 LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
22 tmtc openchip hynix ihp gleichmann micron usbhc
22 tmtc openchip hynix ihp gleichmann micron usbhc
23 23
24 24 DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
25 25 pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
@@ -35,6 +35,7 DIRSKIP = b1553 pcif leon2 leon2ft crypt
35 35 ./lpp_uart \
36 36 ./lpp_usb \
37 37 ./lpp_Header \
38 ./lpp_sim/CY7C1061DV33 \
38 39
39 40 FILESKIP =lpp_lfr_ms.vhd \
40 41 i2cmst.vhd \
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@@ -23,3 +23,4
23 23 ./lpp_Header
24 24 ./lpp_leon3_soc
25 25 ./lpp_debug_lfr
26 ./lpp_sim/CY7C1061DV33
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@@ -30,14 +30,12 PACKAGE lpp_lfr_time_management IS
30 30 -- APB_LFR_TIME_MANAGEMENT
31 31
32 32 COMPONENT apb_lfr_time_management IS
33
34 33 GENERIC(
35 34 pindex : INTEGER := 0; --! APB slave index
36 35 paddr : INTEGER := 0; --! ADDR field of the APB BAR
37 36 pmask : INTEGER := 16#fff#; --! MASK field of the APB BAR
38 37 pirq : INTEGER := 0
39 38 );
40
41 39 PORT (
42 40 clk25MHz : IN STD_LOGIC; --! Clock
43 41 clk49_152MHz : IN STD_LOGIC; --! secondary clock
@@ -48,7 +46,6 PACKAGE lpp_lfr_time_management IS
48 46 coarse_time : OUT STD_LOGIC_VECTOR(31 DOWNTO 0); --! coarse time
49 47 fine_time : OUT STD_LOGIC_VECTOR(15 DOWNTO 0) --! fine time
50 48 );
51
52 49 END COMPONENT;
53 50
54 51 COMPONENT lfr_time_management
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@@ -39,5 +39,6 PACKAGE apb_devices_list IS
39 39 CONSTANT LPP_LFR : amba_device_type := 16#19#;
40 40
41 41 CONSTANT LPP_DEBUG_DMA : amba_device_type := 16#A0#;
42 CONSTANT LPP_DEBUG_LFR : amba_device_type := 16#A1#;
42 43
43 44 END;
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@@ -1,51 +1,71
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27
28 PACKAGE lpp_debug_lfr_pkg IS
29
30 COMPONENT lpp_debug_dma_singleOrBurst
31 GENERIC (
32 tech : INTEGER;
33 hindex : INTEGER;
34 pindex : INTEGER;
35 paddr : INTEGER;
36 pmask : INTEGER);
37 PORT (
38 HCLK : IN STD_ULOGIC;
39 HRESETn : IN STD_ULOGIC;
40 ahbmi : IN AHB_Mst_In_Type;
41 ahbmo : OUT AHB_Mst_Out_Type;
42 apbi : IN apb_slv_in_type;
43 apbo : OUT apb_slv_out_type;
44 out_ren : OUT STD_LOGIC;
45 out_send : OUT STD_LOGIC;
46 out_done : OUT STD_LOGIC;
47 out_dmaout_okay : OUT STD_LOGIC
48 );
49 END COMPONENT;
50
51 END;
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
19 -- Author : Jean-christophe Pellion
20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 -- jean-christophe.pellion@easii-ic.com
22 ----------------------------------------------------------------------------
23 LIBRARY ieee;
24 USE ieee.std_logic_1164.ALL;
25 LIBRARY grlib;
26 USE grlib.amba.ALL;
27 LIBRARY lpp;
28 USE lpp.lpp_lfr_pkg.ALL;
29 USE lpp.lpp_ad_conv.ALL;
30
31 PACKAGE lpp_debug_lfr_pkg IS
32
33 COMPONENT lpp_debug_dma_singleOrBurst
34 GENERIC (
35 tech : INTEGER;
36 hindex : INTEGER;
37 pindex : INTEGER;
38 paddr : INTEGER;
39 pmask : INTEGER);
40 PORT (
41 HCLK : IN STD_ULOGIC;
42 HRESETn : IN STD_ULOGIC;
43 ahbmi : IN AHB_Mst_In_Type;
44 ahbmo : OUT AHB_Mst_Out_Type;
45 apbi : IN apb_slv_in_type;
46 apbo : OUT apb_slv_out_type;
47 out_ren : OUT STD_LOGIC;
48 out_send : OUT STD_LOGIC;
49 out_done : OUT STD_LOGIC;
50 out_dmaout_okay : OUT STD_LOGIC
51 );
52 END COMPONENT;
53
54 COMPONENT lpp_debug_lfr
55 GENERIC (
56 tech : INTEGER;
57 hindex : INTEGER;
58 pindex : INTEGER;
59 paddr : INTEGER;
60 pmask : INTEGER);
61 PORT (
62 HCLK : IN STD_ULOGIC;
63 HRESETn : IN STD_ULOGIC;
64 apbi : IN apb_slv_in_type;
65 apbo : OUT apb_slv_out_type;
66 sample_B : OUT Samples14v(2 DOWNTO 0);
67 sample_E : OUT Samples14v(4 DOWNTO 0));
68 END COMPONENT;
69
70
71 END; No newline at end of file
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@@ -1,2 +1,3
1 1 lpp_debug_lfr_pkg.vhd
2 2 lpp_debug_dma_singleOrBurst.vhd
3 lpp_debug_lfr.vhd
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@@ -167,9 +167,14 BEGIN -- beh
167 167 END PROCESS;
168 168
169 169 DMAIn.Data <= data;
170
171 ren <= NOT (DMAOut.OKAY OR DMAOut.GRANT) WHEN state = SEND_DATA ELSE
172 '1';
170 173
171 ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
172 '1';
174 -- \/ JC - 20/01/2014 \/
175 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE --AND (state = SEND_DATA OR state = WAIT_LAST_READY) ELSE
176 -- '1';
177 -- /\ JC - 20/01/2014 /\
173 178
174 179 -- \/ JC - 11/12/2013 \/
175 180 --ren <= '0' WHEN DMAOut.OKAY = '1' AND state = SEND_DATA ELSE
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@@ -140,8 +140,14 BEGIN
140 140 -- NOT single_send_ok;
141 141 --ren <= burst_ren AND single_ren;
142 142
143 ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
144 '1';
143 -- \/ JC - 20/01/2014 \/
144 ren <= burst_ren WHEN valid_burst = '1' ELSE
145 single_ren;
146
147
148 --ren <= '0' WHEN DMAOut.OKAY = '1' ELSE
149 -- '1';
150 -- /\ JC - 20/01/2014 /\
145 151
146 152 -----------------------------------------------------------------------------
147 153 -- SEND 1 word by DMA
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@@ -413,7 +413,7 BEGIN
413 413 END GENERATE all_ahbs;
414 414 -- AHB_Master -------------------------------------------------------------
415 415 ahbi_m_ext <= ahbmi;
416 all_ahbm: FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE
416 all_ahbm: FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE
417 417 max_16_ahbm: IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE
418 418 ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU);
419 419 END GENERATE max_16_ahbm;
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@@ -69,7 +69,37 ENTITY lpp_lfr IS
69 69 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
70 70 debug_f2_data_valid : OUT STD_LOGIC;
71 71 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
72 debug_f3_data_valid : OUT STD_LOGIC
72 debug_f3_data_valid : OUT STD_LOGIC;
73
74 -- debug FIFO_IN
75 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
76 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
77 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
78 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
79 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
80 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
81 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
82 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
83
84 --debug FIFO OUT
85 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
86 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
87 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
88 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
89 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
90 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
91 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
92 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
93
94 --debug DMA IN
95 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
96 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
97 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
98 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
99 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
100 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
101 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
102 debug_f3_data_dma_in_valid : OUT STD_LOGIC
73 103 );
74 104 END lpp_lfr;
75 105
@@ -405,19 +435,19 BEGIN
405 435 --f0
406 436 addr_data_f0 => addr_data_f0,
407 437 data_f0_in_valid => sample_f0_val,
408 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
438 data_f0_in => sample_f0_data, -- sample_f0_data_debug, -- TODO : debug
409 439 --f1
410 440 addr_data_f1 => addr_data_f1,
411 441 data_f1_in_valid => sample_f1_val,
412 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
442 data_f1_in => sample_f1_data, -- sample_f1_data_debug, -- TODO : debug,
413 443 --f2
414 444 addr_data_f2 => addr_data_f2,
415 445 data_f2_in_valid => sample_f2_val,
416 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
446 data_f2_in => sample_f2_data, -- sample_f2_data_debug, -- TODO : debug,
417 447 --f3
418 448 addr_data_f3 => addr_data_f3,
419 449 data_f3_in_valid => sample_f3_val,
420 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
450 data_f3_in => sample_f3_data, -- sample_f3_data_debug, -- TODO : debug,
421 451 -- OUTPUT -- DMA interface
422 452 --f0
423 453 data_f0_addr_out => data_f0_addr_out_s,
@@ -444,7 +474,7 BEGIN
444 474 data_f3_data_out_valid_burst => data_f3_data_out_valid_burst_s,
445 475 data_f3_data_out_ren => data_f3_data_out_ren,
446 476
447 --debug
477 -- debug SNAPSHOT_OUT
448 478 debug_f0_data => debug_f0_data,
449 479 debug_f0_data_valid => debug_f0_data_valid ,
450 480 debug_f1_data => debug_f1_data ,
@@ -452,12 +482,35 BEGIN
452 482 debug_f2_data => debug_f2_data ,
453 483 debug_f2_data_valid => debug_f2_data_valid ,
454 484 debug_f3_data => debug_f3_data ,
455 debug_f3_data_valid => debug_f3_data_valid
485 debug_f3_data_valid => debug_f3_data_valid,
486
487 -- debug FIFO_IN
488 debug_f0_data_fifo_in => debug_f0_data_fifo_in ,
489 debug_f0_data_fifo_in_valid => debug_f0_data_fifo_in_valid,
490 debug_f1_data_fifo_in => debug_f1_data_fifo_in ,
491 debug_f1_data_fifo_in_valid => debug_f1_data_fifo_in_valid,
492 debug_f2_data_fifo_in => debug_f2_data_fifo_in ,
493 debug_f2_data_fifo_in_valid => debug_f2_data_fifo_in_valid,
494 debug_f3_data_fifo_in => debug_f3_data_fifo_in ,
495 debug_f3_data_fifo_in_valid => debug_f3_data_fifo_in_valid
456 496
457 497 );
458 498
459 499
460 500 -----------------------------------------------------------------------------
501 -- DEBUG -- WFP OUT
502 debug_f0_data_fifo_out_valid <= NOT data_f0_data_out_ren;
503 debug_f0_data_fifo_out <= data_f0_data_out;
504 debug_f1_data_fifo_out_valid <= NOT data_f1_data_out_ren;
505 debug_f1_data_fifo_out <= data_f1_data_out;
506 debug_f2_data_fifo_out_valid <= NOT data_f2_data_out_ren;
507 debug_f2_data_fifo_out <= data_f2_data_out;
508 debug_f3_data_fifo_out_valid <= NOT data_f3_data_out_ren;
509 debug_f3_data_fifo_out <= data_f3_data_out;
510 -----------------------------------------------------------------------------
511
512
513 -----------------------------------------------------------------------------
461 514 -- TEMP
462 515 -----------------------------------------------------------------------------
463 516
@@ -557,71 +610,31 BEGIN
557 610 data_f1_data_out WHEN dma_sel(1) = '1' ELSE
558 611 data_f2_data_out WHEN dma_sel(2) = '1' ELSE
559 612 data_f3_data_out;
560
561 --dma_valid_burst <= data_f0_data_out_valid_burst WHEN dma_sel(0) = '1' ELSE
562 -- data_f1_data_out_valid_burst WHEN dma_sel(1) = '1' ELSE
563 -- data_f2_data_out_valid_burst WHEN dma_sel(2) = '1' ELSE
564 -- data_f3_data_out_valid_burst WHEN dma_sel(3) = '1' ELSE
565 -- '0';
566
567 --dma_sel_valid <= data_f0_data_out_valid WHEN dma_sel(0) = '1' ELSE
568 -- data_f1_data_out_valid WHEN dma_sel(1) = '1' ELSE
569 -- data_f2_data_out_valid WHEN dma_sel(2) = '1' ELSE
570 -- data_f3_data_out_valid WHEN dma_sel(3) = '1' ELSE
571 -- '0';
572
573 -- TODO
574 --dma_send <= dma_sel_valid OR dma_valid_burst;
575
576 --data_f0_data_out_ren <= dma_ren WHEN dma_sel_reg(0) = '1' ELSE '1';
577 --data_f1_data_out_ren <= dma_ren WHEN dma_sel_reg(1) = '1' ELSE '1';
578 --data_f2_data_out_ren <= dma_ren WHEN dma_sel_reg(2) = '1' ELSE '1';
579 --data_f3_data_out_ren <= dma_ren WHEN dma_sel_reg(3) = '1' ELSE '1';
580 613
581 614 data_f0_data_out_ren <= dma_ren WHEN dma_sel(0) = '1' ELSE '1';
582 615 data_f1_data_out_ren <= dma_ren WHEN dma_sel(1) = '1' ELSE '1';
583 616 data_f2_data_out_ren <= dma_ren WHEN dma_sel(2) = '1' ELSE '1';
584 617 data_f3_data_out_ren <= dma_ren WHEN dma_sel(3) = '1' ELSE '1';
585 618
619 dma_data_2 <= dma_data;
586 620
587 --PROCESS (clk, rstn)
588 --BEGIN -- PROCESS
589 -- IF rstn = '0' THEN -- asynchronous reset (active low)
590 -- ongoing_reg <= '0';
591 -- dma_sel_reg <= (OTHERS => '0');
592 -- dma_send_reg <= '0';
593 -- dma_valid_burst_reg <= '0';
594 -- dma_address_reg <= (OTHERS => '0');
595 -- dma_data_reg <= (OTHERS => '0');
596 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
597 -- IF (dma_send = '1' AND ongoing_reg = '0') OR (dma_send = '1' AND dma_done = '1')THEN
598 -- ongoing_reg <= '1';
599 -- dma_valid_burst_reg <= dma_valid_burst;
600 -- dma_sel_reg <= dma_sel;
601 -- ELSE
602 -- IF dma_done = '1' THEN
603 -- ongoing_reg <= '0';
604 -- END IF;
605 -- END IF;
606 -- dma_send_reg <= dma_send;
607 -- dma_address_reg <= dma_address;
608 -- dma_data_reg <= dma_data;
609 -- END IF;
610 --END PROCESS;
611 621
612 dma_data_2 <= dma_data;
613 --PROCESS (clk, rstn)
614 --BEGIN -- PROCESS
615 -- IF rstn = '0' THEN -- asynchronous reset (active low)
616 -- dma_data_2 <= (OTHERS => '0');
617 -- ELSIF clk'event AND clk = '1' THEN -- rising clock edge
618 -- dma_data_2 <= dma_data;
619
620 -- END IF;
621 --END PROCESS;
622
622 623
623 624
624 625 -----------------------------------------------------------------------------
626 -- DEBUG -- DMA IN
627 debug_f0_data_dma_in_valid <= NOT data_f0_data_out_ren;
628 debug_f0_data_dma_in <= dma_data;
629 debug_f1_data_dma_in_valid <= NOT data_f1_data_out_ren;
630 debug_f1_data_dma_in <= dma_data;
631 debug_f2_data_dma_in_valid <= NOT data_f2_data_out_ren;
632 debug_f2_data_dma_in <= dma_data;
633 debug_f3_data_dma_in_valid <= NOT data_f3_data_out_ren;
634 debug_f3_data_dma_in <= dma_data;
635 -----------------------------------------------------------------------------
636
637 -----------------------------------------------------------------------------
625 638 -- DMA
626 639 -----------------------------------------------------------------------------
627 640 lpp_dma_singleOrBurst_1 : lpp_dma_singleOrBurst
@@ -635,12 +648,12 BEGIN
635 648 AHB_Master_In => ahbi,
636 649 AHB_Master_Out => ahbo,
637 650
638 send => dma_send, --_reg,
639 valid_burst => dma_valid_burst, --_reg,
651 send => dma_send,
652 valid_burst => dma_valid_burst,
640 653 done => dma_done,
641 654 ren => dma_ren,
642 address => dma_address, --_reg,
643 data => dma_data_2); --_reg);
655 address => dma_address,
656 data => dma_data_2);
644 657
645 658 -----------------------------------------------------------------------------
646 659 -- Matrix Spectral - TODO
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@@ -142,7 +142,7 ARCHITECTURE beh OF lpp_lfr_apbreg IS
142 142 CONSTANT REVISION : INTEGER := 1;
143 143
144 144 CONSTANT pconfig : apb_config_type := (
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 2, REVISION, pirq_wfp),
145 0 => ahb_device_reg (VENDOR_LPP, LPP_LFR, 0, REVISION, pirq_wfp),
146 146 1 => apb_iobar(paddr, pmask));
147 147
148 148 TYPE lpp_SpectralMatrix_regs IS RECORD
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@@ -32,7 +32,7 PACKAGE lpp_lfr_pkg IS
32 32 ready_matrix_f0_1 : OUT STD_LOGIC;
33 33 ready_matrix_f1 : OUT STD_LOGIC;
34 34 ready_matrix_f2 : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
35 error_anticipating_empty_fifo : OUT STD_LOGIC;
36 36 error_bad_component_error : OUT STD_LOGIC;
37 37 debug_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
38 38 status_ready_matrix_f0_0 : IN STD_LOGIC;
@@ -101,15 +101,46 PACKAGE lpp_lfr_pkg IS
101 101 fine_time : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
102 102 data_shaping_BW : OUT STD_LOGIC;
103 103
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC );
104 --debug
105 debug_f0_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
106 debug_f0_data_valid : OUT STD_LOGIC;
107 debug_f1_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
108 debug_f1_data_valid : OUT STD_LOGIC;
109 debug_f2_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
110 debug_f2_data_valid : OUT STD_LOGIC;
111 debug_f3_data : OUT STD_LOGIC_VECTOR(95 DOWNTO 0);
112 debug_f3_data_valid : OUT STD_LOGIC;
113
114 -- debug FIFO_IN
115 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
116 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
117 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
118 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
119 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
120 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
121 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
122 debug_f3_data_fifo_in_valid : OUT STD_LOGIC;
123
124 --debug FIFO OUT
125 debug_f0_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
126 debug_f0_data_fifo_out_valid : OUT STD_LOGIC;
127 debug_f1_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
128 debug_f1_data_fifo_out_valid : OUT STD_LOGIC;
129 debug_f2_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
130 debug_f2_data_fifo_out_valid : OUT STD_LOGIC;
131 debug_f3_data_fifo_out : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
132 debug_f3_data_fifo_out_valid : OUT STD_LOGIC;
133
134 --debug DMA IN
135 debug_f0_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
136 debug_f0_data_dma_in_valid : OUT STD_LOGIC;
137 debug_f1_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
138 debug_f1_data_dma_in_valid : OUT STD_LOGIC;
139 debug_f2_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
140 debug_f2_data_dma_in_valid : OUT STD_LOGIC;
141 debug_f3_data_dma_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
142 debug_f3_data_dma_in_valid : OUT STD_LOGIC
143 );
113 144 END COMPONENT;
114 145
115 146 COMPONENT lpp_lfr_apbreg
@@ -180,16 +211,16 PACKAGE lpp_lfr_pkg IS
180 211 addr_data_f3 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
181 212 start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
182 213 ---------------------------------------------------------------------------
183 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
184 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
186 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
188 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
190 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
214 debug_reg0 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
215 debug_reg1 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
216 debug_reg2 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
217 debug_reg3 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
218 debug_reg4 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
219 debug_reg5 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
220 debug_reg6 : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
221 debug_reg7 : IN STD_LOGIC_VECTOR(31 DOWNTO 0));
191 222 END COMPONENT;
192
223
193 224 COMPONENT lpp_top_ms
194 225 GENERIC (
195 226 Mem_use : INTEGER;
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@@ -129,7 +129,7 ENTITY lpp_waveform IS
129 129 data_f3_data_out_valid_burst : OUT STD_LOGIC;
130 130 data_f3_data_out_ren : IN STD_LOGIC;
131 131
132 --debug
132 --debug SNAPSHOT OUT
133 133 debug_f0_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
134 134 debug_f0_data_valid : OUT STD_LOGIC;
135 135 debug_f1_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
@@ -137,7 +137,18 ENTITY lpp_waveform IS
137 137 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
138 138 debug_f2_data_valid : OUT STD_LOGIC;
139 139 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
140 debug_f3_data_valid : OUT STD_LOGIC
140 debug_f3_data_valid : OUT STD_LOGIC;
141
142 --debug FIFO IN
143 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
144 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
145 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
146 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
147 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
148 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
149 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
150 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
151
141 152 );
142 153
143 154 END lpp_waveform;
@@ -285,7 +296,7 BEGIN -- beh
285 296 data_out_valid => data_f3_out_valid);
286 297
287 298 -----------------------------------------------------------------------------
288 -- DEBUG
299 -- DEBUG -- SNAPSHOT OUT
289 300 debug_f0_data_valid <= data_f0_out_valid;
290 301 debug_f0_data <= data_f0_out;
291 302 debug_f1_data_valid <= data_f1_out_valid;
@@ -332,9 +343,9 BEGIN -- beh
332 343 -----------------------------------------------------------------------------
333 344 -- TODO : debug
334 345 -----------------------------------------------------------------------------
335 all_bit_of_time_out: FOR I IN 47 DOWNTO 0 GENERATE
336 all_sample_of_time_out: FOR J IN 3 DOWNTO 0 GENERATE
337 time_out_2(J,I) <= time_out(J)(I);
346 all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
347 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
348 time_out_2(J, I) <= time_out(J)(I);
338 349 END GENERATE all_sample_of_time_out;
339 350 END GENERATE all_bit_of_time_out;
340 351
@@ -350,7 +361,7 BEGIN -- beh
350 361 -- END GENERATE all_sample_of_time_out;
351 362 --END GENERATE all_bit_of_time_out;
352 363 -- DEBUG --
353
364
354 365 lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
355 366 GENERIC MAP (tech => tech,
356 367 nb_data_by_buffer_size => nb_data_by_buffer_size)
@@ -369,6 +380,18 BEGIN -- beh
369 380 full_almost => full_almost,
370 381 full => full);
371 382
383 -----------------------------------------------------------------------------
384 -- DEBUG -- SNAPSHOT IN
385 debug_f0_data_fifo_in_valid <= NOT data_wen(0);
386 debug_f0_data_fifo_in <= wdata;
387 debug_f1_data_fifo_in_valid <= NOT data_wen(1);
388 debug_f1_data_fifo_in <= wdata;
389 debug_f2_data_fifo_in_valid <= NOT data_wen(2);
390 debug_f2_data_fifo_in <= wdata;
391 debug_f3_data_fifo_in_valid <= NOT data_wen(3);
392 debug_f3_data_fifo_in <= wdata;
393 -----------------------------------------------------------------------------
394
372 395 lpp_waveform_fifo_1 : lpp_waveform_fifo
373 396 GENERIC MAP (tech => tech)
374 397 PORT MAP (
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@@ -30,7 +30,7 USE lpp.general_purpose.ALL;
30 30 ENTITY lpp_waveform_fifo_arbiter IS
31 31 GENERIC(
32 32 tech : INTEGER := 0;
33 nb_data_by_buffer_size : INTEGER
33 nb_data_by_buffer_size : INTEGER := 11
34 34 );
35 35 PORT(
36 36 clk : IN STD_LOGIC;
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@@ -54,8 +54,8 ARCHITECTURE ar_lpp_waveform_fifo_arbite
54 54 TYPE Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
55 55 SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
56 56
57 SIGNAL reg_sel : INTEGER;
58 SIGNAL reg_sel_s : INTEGER;
57 SIGNAL reg_sel : INTEGER := 0;
58 SIGNAL reg_sel_s : INTEGER := 0;
59 59
60 60 BEGIN
61 61
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@@ -176,7 +176,18 PACKAGE lpp_waveform_pkg IS
176 176 debug_f2_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
177 177 debug_f2_data_valid : OUT STD_LOGIC;
178 178 debug_f3_data : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
179 debug_f3_data_valid : OUT STD_LOGIC);
179 debug_f3_data_valid : OUT STD_LOGIC;
180
181 --debug FIFO IN
182 debug_f0_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
183 debug_f0_data_fifo_in_valid : OUT STD_LOGIC;
184 debug_f1_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
185 debug_f1_data_fifo_in_valid : OUT STD_LOGIC;
186 debug_f2_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
187 debug_f2_data_fifo_in_valid : OUT STD_LOGIC;
188 debug_f3_data_fifo_in : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
189 debug_f3_data_fifo_in_valid : OUT STD_LOGIC
190 );
180 191 END COMPONENT;
181 192
182 193 COMPONENT lpp_waveform_dma_genvalid
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