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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 library proasic3l;
49 use proasic3l.all;
48 --library proasic3l;
49 --use proasic3l.all;
50 50
51 51 ENTITY LFR_EQM IS
52 GENERIC (
53 Mem_use : INTEGER := use_RAM);
52 --GENERIC (
53 -- Mem_use : INTEGER := use_RAM);
54 54
55 55 PORT (
56 56 clk50MHz : IN STD_ULOGIC;
57 57 clk49_152MHz : IN STD_ULOGIC;
58 58 reset : IN STD_ULOGIC;
59 59
60 60 -- TAG --------------------------------------------------------------------
61 61 TAG1 : IN STD_ULOGIC; -- DSU rx data
62 62 TAG3 : OUT STD_ULOGIC; -- DSU tx data
63 63 -- UART APB ---------------------------------------------------------------
64 64 TAG2 : IN STD_ULOGIC; -- UART1 rx data
65 65 TAG4 : OUT STD_ULOGIC; -- UART1 tx data
66 66 -- RAM --------------------------------------------------------------------
67 67 address : OUT STD_LOGIC_VECTOR(18 DOWNTO 0);
68 68 data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
69 69
70 70 nSRAM_MBE : INOUT STD_LOGIC; -- new
71 71 nSRAM_E1 : OUT STD_LOGIC; -- new
72 72 nSRAM_E2 : OUT STD_LOGIC; -- new
73 73 -- nSRAM_SCRUB : OUT STD_LOGIC; -- new
74 74 nSRAM_W : OUT STD_LOGIC; -- new
75 75 nSRAM_G : OUT STD_LOGIC; -- new
76 76 nSRAM_BUSY : IN STD_LOGIC; -- new
77 77 -- SPW --------------------------------------------------------------------
78 78 spw1_en : OUT STD_LOGIC; -- new
79 79 spw1_din : IN STD_LOGIC;
80 80 spw1_sin : IN STD_LOGIC;
81 81 spw1_dout : OUT STD_LOGIC;
82 82 spw1_sout : OUT STD_LOGIC;
83 83 spw2_en : OUT STD_LOGIC; -- new
84 84 spw2_din : IN STD_LOGIC;
85 85 spw2_sin : IN STD_LOGIC;
86 86 spw2_dout : OUT STD_LOGIC;
87 87 spw2_sout : OUT STD_LOGIC;
88 88 -- ADC --------------------------------------------------------------------
89 89 bias_fail_sw : OUT STD_LOGIC;
90 90 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
91 91 ADC_smpclk : OUT STD_LOGIC;
92 92 ADC_data : IN STD_LOGIC_VECTOR(13 DOWNTO 0);
93 93 -- DAC --------------------------------------------------------------------
94 94 DAC_SDO : OUT STD_LOGIC;
95 95 DAC_SCK : OUT STD_LOGIC;
96 96 DAC_SYNC : OUT STD_LOGIC;
97 97 DAC_CAL_EN : OUT STD_LOGIC;
98 98 -- HK ---------------------------------------------------------------------
99 99 HK_smpclk : OUT STD_LOGIC;
100 100 ADC_OEB_bar_HK : OUT STD_LOGIC;
101 101 HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
102 102 ---------------------------------------------------------------------------
103 103 TAG8 : OUT STD_LOGIC
104 104 );
105 105
106 106 END LFR_EQM;
107 107
108 108
109 109 ARCHITECTURE beh OF LFR_EQM IS
110 110
111 111 SIGNAL clk_25 : STD_LOGIC := '0';
112 112 SIGNAL clk_24 : STD_LOGIC := '0';
113 113 -----------------------------------------------------------------------------
114 114 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
115 115 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
116 116
117 117 -- CONSTANTS
118 118 CONSTANT CFG_PADTECH : INTEGER := inferred;
119 119 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
120 120 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
121 121 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
122 122
123 123 SIGNAL apbi_ext : apb_slv_in_type;
124 124 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5) := (OTHERS => apb_none);
125 125 SIGNAL ahbi_s_ext : ahb_slv_in_type;
126 126 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3) := (OTHERS => ahbs_none);
127 127 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
128 128 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
129 129
130 130 -- Spacewire signals
131 131 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
132 132 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
133 133 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
134 134 SIGNAL spw_rxtxclk : STD_ULOGIC;
135 135 SIGNAL spw_rxclkn : STD_ULOGIC;
136 136 SIGNAL spw_clk : STD_LOGIC;
137 137 SIGNAL swni : grspw_in_type;
138 138 SIGNAL swno : grspw_out_type;
139 139
140 140 --GPIO
141 141 SIGNAL gpioi : gpio_in_type;
142 142 SIGNAL gpioo : gpio_out_type;
143 143
144 144 -- AD Converter ADS7886
145 145 SIGNAL sample : Samples14v(8 DOWNTO 0);
146 146 SIGNAL sample_s : Samples(8 DOWNTO 0);
147 147 SIGNAL sample_val : STD_LOGIC;
148 148 SIGNAL ADC_OEB_bar_CH_s : STD_LOGIC_VECTOR(8 DOWNTO 0);
149 149
150 150 -----------------------------------------------------------------------------
151 151 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
152 152
153 153 -----------------------------------------------------------------------------
154 154 SIGNAL rstn_25 : STD_LOGIC;
155 155 SIGNAL rstn_24 : STD_LOGIC;
156 156
157 157 SIGNAL LFR_soft_rstn : STD_LOGIC;
158 158 SIGNAL LFR_rstn : STD_LOGIC;
159 159
160 160 SIGNAL ADC_smpclk_s : STD_LOGIC;
161 161
162 162 SIGNAL nSRAM_CE : STD_LOGIC_VECTOR(1 DOWNTO 0);
163 163
164 164 SIGNAL clk50MHz_int : STD_LOGIC := '0';
165 165 SIGNAL clk_25_int : STD_LOGIC := '0';
166 166
167 167 component clkint port(A : in std_ulogic; Y :out std_ulogic); end component;
168 168
169 169 BEGIN -- beh
170 170
171 171 -----------------------------------------------------------------------------
172 172 -- CLK
173 173 -----------------------------------------------------------------------------
174 174 rst_domain25 : rstgen PORT MAP (reset, clk_25, '1', rstn_25, OPEN);
175 175 rst_domain24 : rstgen PORT MAP (reset, clk_24, '1', rstn_24, OPEN);
176 176
177 177 --clk_pad : clkint port map (A => clk50MHz, Y => clk50MHz_int );
178 178 clk50MHz_int <= clk50MHz;
179 179
180 180 PROCESS(clk50MHz_int)
181 181 BEGIN
182 182 IF clk50MHz_int'EVENT AND clk50MHz_int = '1' THEN
183 183 --clk_25_int <= NOT clk_25_int;
184 184 clk_25 <= NOT clk_25;
185 185 END IF;
186 186 END PROCESS;
187 187 --clk_pad_25 : clkint port map (A => clk_25_int, Y => clk_25 );
188 188
189 189 PROCESS(clk49_152MHz)
190 190 BEGIN
191 191 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
192 192 clk_24 <= NOT clk_24;
193 193 END IF;
194 194 END PROCESS;
195 195
196 196 -----------------------------------------------------------------------------
197 197 --
198 198 leon3_soc_1 : leon3_soc
199 199 GENERIC MAP (
200 fabtech => apa3e,
201 memtech => apa3e,
200 fabtech => apa3l,
201 memtech => apa3l,
202 202 padtech => inferred,
203 203 clktech => inferred,
204 204 disas => 0,
205 205 dbguart => 0,
206 206 pclow => 2,
207 207 clk_freq => 25000,
208 208 IS_RADHARD => 0,
209 209 NB_CPU => 1,
210 210 ENABLE_FPU => 1,
211 211 FPU_NETLIST => 0,
212 212 ENABLE_DSU => 1,
213 213 ENABLE_AHB_UART => 1,
214 214 ENABLE_APB_UART => 1,
215 215 ENABLE_IRQMP => 1,
216 216 ENABLE_GPT => 1,
217 217 NB_AHB_MASTER => NB_AHB_MASTER,
218 218 NB_AHB_SLAVE => NB_AHB_SLAVE,
219 219 NB_APB_SLAVE => NB_APB_SLAVE,
220 220 ADDRESS_SIZE => 19,
221 221 USES_IAP_MEMCTRLR => 1,
222 BYPASS_EDAC_MEMCTRLR => '1')
222 BYPASS_EDAC_MEMCTRLR => '0',
223 SRBANKSZ => 8)
223 224 PORT MAP (
224 225 clk => clk_25,
225 226 reset => rstn_25,
226 227 errorn => OPEN,
227 228
228 229 ahbrxd => TAG1,
229 230 ahbtxd => TAG3,
230 231 urxd1 => TAG2,
231 232 utxd1 => TAG4,
232 233
233 234 address => address,
234 235 data => data,
235 236 nSRAM_BE0 => OPEN,
236 237 nSRAM_BE1 => OPEN,
237 238 nSRAM_BE2 => OPEN,
238 239 nSRAM_BE3 => OPEN,
239 240 nSRAM_WE => nSRAM_W,
240 241 nSRAM_CE => nSRAM_CE,
241 242 nSRAM_OE => nSRAM_G,
242 243 nSRAM_READY => nSRAM_BUSY,
243 244 SRAM_MBE => nSRAM_MBE,
244 245
245 246 apbi_ext => apbi_ext,
246 247 apbo_ext => apbo_ext,
247 248 ahbi_s_ext => ahbi_s_ext,
248 249 ahbo_s_ext => ahbo_s_ext,
249 250 ahbi_m_ext => ahbi_m_ext,
250 251 ahbo_m_ext => ahbo_m_ext);
251 252
252 253
253 254 nSRAM_E1 <= nSRAM_CE(0);
254 255 nSRAM_E2 <= nSRAM_CE(1);
255 256
256 257 -------------------------------------------------------------------------------
257 258 -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
258 259 -------------------------------------------------------------------------------
259 260 apb_lfr_management_1 : apb_lfr_management
260 261 GENERIC MAP (
261 tech => apa3e,
262 tech => apa3l,
262 263 pindex => 6,
263 264 paddr => 6,
264 265 pmask => 16#fff#,
265 266 --FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
266 267 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
267 268 PORT MAP (
268 269 clk25MHz => clk_25,
269 270 resetn_25MHz => rstn_25, -- TODO
270 271 --clk24_576MHz => clk_24, -- 49.152MHz/2
271 272 --resetn_24_576MHz => rstn_24, -- TODO
272 273
273 274 grspw_tick => swno.tickout,
274 275 apbi => apbi_ext,
275 276 apbo => apbo_ext(6),
276 277
277 278 HK_sample => sample_s(8),
278 279 HK_val => sample_val,
279 280 HK_sel => HK_SEL,
280 281
281 282 DAC_SDO => DAC_SDO,
282 283 DAC_SCK => DAC_SCK,
283 284 DAC_SYNC => DAC_SYNC,
284 285 DAC_CAL_EN => DAC_CAL_EN,
285 286
286 287 coarse_time => coarse_time,
287 288 fine_time => fine_time,
288 289 LFR_soft_rstn => LFR_soft_rstn
289 290 );
290 291
291 292 -----------------------------------------------------------------------
292 293 --- SpaceWire --------------------------------------------------------
293 294 -----------------------------------------------------------------------
294 295
295 296 ------------------------------------------------------------------------------
296 297 -- \/\/\/\/ TODO : spacewire enable should be controled by the SPW IP \/\/\/\/
297 298 ------------------------------------------------------------------------------
298 299 spw1_en <= '1';
299 300 spw2_en <= '1';
300 301 ------------------------------------------------------------------------------
301 302 -- /\/\/\/\ --------------------------------------------------------- /\/\/\/\
302 303 ------------------------------------------------------------------------------
303 304
304 305 --spw_clk <= clk50MHz;
305 306 --spw_rxtxclk <= spw_clk;
306 307 --spw_rxclkn <= NOT spw_rxtxclk;
307 308
308 309 -- PADS for SPW1
309 310 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
310 311 PORT MAP (spw1_din, dtmp(0));
311 312 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
312 313 PORT MAP (spw1_sin, stmp(0));
313 314 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
314 315 PORT MAP (spw1_dout, swno.d(0));
315 316 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
316 317 PORT MAP (spw1_sout, swno.s(0));
317 318 -- PADS FOR SPW2
318 319 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
319 320 PORT MAP (spw2_din, dtmp(1));
320 321 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
321 322 PORT MAP (spw2_sin, stmp(1));
322 323 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
323 324 PORT MAP (spw2_dout, swno.d(1));
324 325 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
325 326 PORT MAP (spw2_sout, swno.s(1));
326 327
327 328 -- GRSPW PHY
328 329 --spw1_input: if CFG_SPW_GRSPW = 1 generate
329 330 spw_inputloop : FOR j IN 0 TO 1 GENERATE
330 331 spw_phy0 : grspw_phy
331 332 GENERIC MAP(
332 tech => apa3e,
333 tech => apa3l,
333 334 rxclkbuftype => 1,
334 335 scantest => 0)
335 336 PORT MAP(
336 337 rxrst => swno.rxrst,
337 338 di => dtmp(j),
338 339 si => stmp(j),
339 340 rxclko => spw_rxclk(j),
340 341 do => swni.d(j),
341 342 ndo => swni.nd(j*5+4 DOWNTO j*5),
342 343 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
343 344 END GENERATE spw_inputloop;
344 345
345 346 -- SPW core
346 347 sw0 : grspwm GENERIC MAP(
347 tech => apa3e,
348 tech => apa3l,
348 349 hindex => 1,
349 350 pindex => 5,
350 351 paddr => 5,
351 352 pirq => 11,
352 353 sysfreq => 25000, -- CPU_FREQ
353 354 rmap => 1,
354 355 rmapcrc => 1,
355 356 fifosize1 => 16,
356 357 fifosize2 => 16,
357 358 rxclkbuftype => 1,
358 359 rxunaligned => 0,
359 360 rmapbufs => 4,
360 361 ft => 0,
361 362 netlist => 0,
362 363 ports => 2,
363 364 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
364 memtech => apa3e,
365 memtech => apa3l,
365 366 destkey => 2,
366 367 spwcore => 1
367 368 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
368 369 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
369 370 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
370 371 )
371 372 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
372 373 spw_rxclk(1),
373 374 clk50MHz_int,
374 375 clk50MHz_int,
375 376 -- spw_rxtxclk, spw_rxtxclk, spw_rxtxclk, spw_rxtxclk,
376 377 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
377 378 swni, swno);
378 379
379 380 swni.tickin <= '0';
380 381 swni.rmapen <= '1';
381 382 swni.clkdiv10 <= "00000100"; -- 50 MHz / (4 + 1) = 10 MHz
382 383 swni.tickinraw <= '0';
383 384 swni.timein <= (OTHERS => '0');
384 385 swni.dcrstval <= (OTHERS => '0');
385 386 swni.timerrstval <= (OTHERS => '0');
386 387
387 388 -------------------------------------------------------------------------------
388 389 -- LFR ------------------------------------------------------------------------
389 390 -------------------------------------------------------------------------------
390 391 LFR_rstn <= LFR_soft_rstn AND rstn_25;
391 392
392 393 lpp_lfr_1 : lpp_lfr
393 394 GENERIC MAP (
394 Mem_use => Mem_use,
395 Mem_use => use_RAM,
395 396 nb_data_by_buffer_size => 32,
396 397 --nb_word_by_buffer_size => 30,
397 398 nb_snapshot_param_size => 32,
398 399 delta_vector_size => 32,
399 400 delta_vector_size_f0_2 => 7, -- log2(96)
400 401 pindex => 15,
401 402 paddr => 15,
402 403 pmask => 16#fff#,
403 404 pirq_ms => 6,
404 405 pirq_wfp => 14,
405 406 hindex => 2,
406 top_lfr_version => X"020144") -- aa.bb.cc version
407 top_lfr_version => X"020145") -- aa.bb.cc version
407 408 -- AA : BOARD NUMBER
408 409 -- 0 => MINI_LFR
409 410 -- 1 => EM
410 411 -- 2 => EQM (with A3PE3000)
411 412 PORT MAP (
412 413 clk => clk_25,
413 414 rstn => LFR_rstn,
414 415 sample_B => sample_s(2 DOWNTO 0),
415 416 sample_E => sample_s(7 DOWNTO 3),
416 417 sample_val => sample_val,
417 418 apbi => apbi_ext,
418 419 apbo => apbo_ext(15),
419 420 ahbi => ahbi_m_ext,
420 421 ahbo => ahbo_m_ext(2),
421 422 coarse_time => coarse_time,
422 423 fine_time => fine_time,
423 424 data_shaping_BW => bias_fail_sw,
424 425 debug_vector => OPEN,
425 426 debug_vector_ms => OPEN); --,
426 427 --observation_vector_0 => OPEN,
427 428 --observation_vector_1 => OPEN,
428 429 --observation_reg => observation_reg);
429 430
430 431
431 432 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
432 433 sample_s(I) <= sample(I) & '0' & '0';
433 434 END GENERATE all_sample;
434 435 sample_s(8) <= sample(8)(13) & sample(8)(13) & sample(8);
435 436
436 437 -----------------------------------------------------------------------------
437 438 --
438 439 -----------------------------------------------------------------------------
439 440 top_ad_conv_RHF1401_withFilter_1 : top_ad_conv_RHF1401_withFilter
440 441 GENERIC MAP (
441 442 ChanelCount => 9,
442 443 ncycle_cnv_high => 13,
443 444 ncycle_cnv => 25,
444 445 FILTER_ENABLED => 16#FF#)
445 446 PORT MAP (
446 447 cnv_clk => clk_24,
447 448 cnv_rstn => rstn_24,
448 449 cnv => ADC_smpclk_s,
449 450 clk => clk_25,
450 451 rstn => rstn_25,
451 452 ADC_data => ADC_data,
452 453 ADC_nOE => ADC_OEB_bar_CH_s,
453 454 sample => sample,
454 455 sample_val => sample_val);
455 456
456 457 ADC_OEB_bar_CH <= ADC_OEB_bar_CH_s(7 DOWNTO 0);
457 458
458 459 ADC_smpclk <= ADC_smpclk_s;
459 460 HK_smpclk <= ADC_smpclk_s;
460 461
461 462 TAG8 <= nSRAM_BUSY;
462 463
463 464 -----------------------------------------------------------------------------
464 465 -- HK
465 466 -----------------------------------------------------------------------------
466 467 ADC_OEB_bar_HK <= ADC_OEB_bar_CH_s(8);
467 468
468 469 END beh;
Show file before | Show file after | Hide comments
@@ -1,757 +1,758
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 -- Author : Jean-christophe Pellion
20 20 -- Mail : jean-christophe.pellion@lpp.polytechnique.fr
21 21 -------------------------------------------------------------------------------
22 22 LIBRARY IEEE;
23 23 USE IEEE.numeric_std.ALL;
24 24 USE IEEE.std_logic_1164.ALL;
25 25 LIBRARY grlib;
26 26 USE grlib.amba.ALL;
27 27 USE grlib.stdlib.ALL;
28 28 LIBRARY techmap;
29 29 USE techmap.gencomp.ALL;
30 30 LIBRARY gaisler;
31 31 USE gaisler.memctrl.ALL;
32 32 USE gaisler.leon3.ALL;
33 33 USE gaisler.uart.ALL;
34 34 USE gaisler.misc.ALL;
35 35 USE gaisler.spacewire.ALL;
36 36 LIBRARY esa;
37 37 USE esa.memoryctrl.ALL;
38 38 LIBRARY lpp;
39 39 USE lpp.lpp_memory.ALL;
40 40 USE lpp.lpp_ad_conv.ALL;
41 41 USE lpp.lpp_lfr_pkg.ALL; -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
42 42 USE lpp.lpp_top_lfr_pkg.ALL; -- contains top_wf_picker
43 43 USE lpp.iir_filter.ALL;
44 44 USE lpp.general_purpose.ALL;
45 45 USE lpp.lpp_lfr_management.ALL;
46 46 USE lpp.lpp_leon3_soc_pkg.ALL;
47 47
48 48 ENTITY MINI_LFR_top IS
49 49
50 50 PORT (
51 51 clk_50 : IN STD_LOGIC;
52 52 clk_49 : IN STD_LOGIC;
53 53 reset : IN STD_LOGIC;
54 54 --BPs
55 55 BP0 : IN STD_LOGIC;
56 56 BP1 : IN STD_LOGIC;
57 57 --LEDs
58 58 LED0 : OUT STD_LOGIC;
59 59 LED1 : OUT STD_LOGIC;
60 60 LED2 : OUT STD_LOGIC;
61 61 --UARTs
62 62 TXD1 : IN STD_LOGIC;
63 63 RXD1 : OUT STD_LOGIC;
64 64 nCTS1 : OUT STD_LOGIC;
65 65 nRTS1 : IN STD_LOGIC;
66 66
67 67 TXD2 : IN STD_LOGIC;
68 68 RXD2 : OUT STD_LOGIC;
69 69 nCTS2 : OUT STD_LOGIC;
70 70 nDTR2 : IN STD_LOGIC;
71 71 nRTS2 : IN STD_LOGIC;
72 72 nDCD2 : OUT STD_LOGIC;
73 73
74 74 --EXT CONNECTOR
75 75 IO0 : INOUT STD_LOGIC;
76 76 IO1 : INOUT STD_LOGIC;
77 77 IO2 : INOUT STD_LOGIC;
78 78 IO3 : INOUT STD_LOGIC;
79 79 IO4 : INOUT STD_LOGIC;
80 80 IO5 : INOUT STD_LOGIC;
81 81 IO6 : INOUT STD_LOGIC;
82 82 IO7 : INOUT STD_LOGIC;
83 83 IO8 : INOUT STD_LOGIC;
84 84 IO9 : INOUT STD_LOGIC;
85 85 IO10 : INOUT STD_LOGIC;
86 86 IO11 : INOUT STD_LOGIC;
87 87
88 88 --SPACE WIRE
89 89 SPW_EN : OUT STD_LOGIC; -- 0 => off
90 90 SPW_NOM_DIN : IN STD_LOGIC; -- NOMINAL LINK
91 91 SPW_NOM_SIN : IN STD_LOGIC;
92 92 SPW_NOM_DOUT : OUT STD_LOGIC;
93 93 SPW_NOM_SOUT : OUT STD_LOGIC;
94 94 SPW_RED_DIN : IN STD_LOGIC; -- REDUNDANT LINK
95 95 SPW_RED_SIN : IN STD_LOGIC;
96 96 SPW_RED_DOUT : OUT STD_LOGIC;
97 97 SPW_RED_SOUT : OUT STD_LOGIC;
98 98 -- MINI LFR ADC INPUTS
99 99 ADC_nCS : OUT STD_LOGIC;
100 100 ADC_CLK : OUT STD_LOGIC;
101 101 ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
102 102
103 103 -- SRAM
104 104 SRAM_nWE : OUT STD_LOGIC;
105 105 SRAM_CE : OUT STD_LOGIC;
106 106 SRAM_nOE : OUT STD_LOGIC;
107 107 SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
108 108 SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
109 109 SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
110 110 );
111 111
112 112 END MINI_LFR_top;
113 113
114 114
115 115 ARCHITECTURE beh OF MINI_LFR_top IS
116 116
117 117 --==========================================================================
118 118 -- USE_IAP_MEMCTRL allow to use the srctrle-0ws on MINILFR board
119 119 -- when enabled, chip enable polarity should be reversed and bank size also
120 120 -- MINILFR -> 1 bank of 4MBytes -> SRBANKSZ=9
121 121 -- LFR EQM & FM -> 2 banks of 2MBytes -> SRBANKSZ=8
122 122 --==========================================================================
123 123 CONSTANT USE_IAP_MEMCTRL : integer := 1;
124 124 --==========================================================================
125 125
126 126 SIGNAL clk_50_s : STD_LOGIC := '0';
127 127 SIGNAL clk_25 : STD_LOGIC := '0';
128 128 SIGNAL clk_24 : STD_LOGIC := '0';
129 129 -----------------------------------------------------------------------------
130 130 SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
131 131 SIGNAL fine_time : STD_LOGIC_VECTOR(15 DOWNTO 0);
132 132 --
133 133 SIGNAL errorn : STD_LOGIC;
134 134 -- UART AHB ---------------------------------------------------------------
135 135 -- SIGNAL ahbrxd : STD_ULOGIC; -- DSU rx data
136 136 -- SIGNAL ahbtxd : STD_ULOGIC; -- DSU tx data
137 137
138 138 -- UART APB ---------------------------------------------------------------
139 139 -- SIGNAL urxd1 : STD_ULOGIC; -- UART1 rx data
140 140 -- SIGNAL utxd1 : STD_ULOGIC; -- UART1 tx data
141 141 --
142 142 SIGNAL I00_s : STD_LOGIC;
143 143
144 144 -- CONSTANTS
145 145 CONSTANT CFG_PADTECH : INTEGER := inferred;
146 146 --
147 147 CONSTANT NB_APB_SLAVE : INTEGER := 11; -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
148 148 CONSTANT NB_AHB_SLAVE : INTEGER := 1;
149 149 CONSTANT NB_AHB_MASTER : INTEGER := 2; -- 2 = grspw + waveform picker
150 150
151 151 SIGNAL apbi_ext : apb_slv_in_type;
152 152 SIGNAL apbo_ext : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); -- := (OTHERS => apb_none);
153 153 SIGNAL ahbi_s_ext : ahb_slv_in_type;
154 154 SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); -- := (OTHERS => ahbs_none);
155 155 SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
156 156 SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1); -- := (OTHERS => ahbm_none);
157 157
158 158 -- Spacewire signals
159 159 SIGNAL dtmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
160 160 SIGNAL stmp : STD_LOGIC_VECTOR(1 DOWNTO 0);
161 161 SIGNAL spw_rxclk : STD_LOGIC_VECTOR(1 DOWNTO 0);
162 162 SIGNAL spw_rxtxclk : STD_ULOGIC;
163 163 SIGNAL spw_rxclkn : STD_ULOGIC;
164 164 SIGNAL spw_clk : STD_LOGIC;
165 165 SIGNAL swni : grspw_in_type;
166 166 SIGNAL swno : grspw_out_type;
167 167 -- SIGNAL clkmn : STD_ULOGIC;
168 168 -- SIGNAL txclk : STD_ULOGIC;
169 169
170 170 --GPIO
171 171 SIGNAL gpioi : gpio_in_type;
172 172 SIGNAL gpioo : gpio_out_type;
173 173
174 174 -- AD Converter ADS7886
175 175 SIGNAL sample : Samples14v(7 DOWNTO 0);
176 176 SIGNAL sample_s : Samples(7 DOWNTO 0);
177 177 SIGNAL sample_val : STD_LOGIC;
178 178 SIGNAL ADC_nCS_sig : STD_LOGIC;
179 179 SIGNAL ADC_CLK_sig : STD_LOGIC;
180 180 SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
181 181
182 182 SIGNAL bias_fail_sw_sig : STD_LOGIC;
183 183
184 184 SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
185 185 SIGNAL observation_vector_0 : STD_LOGIC_VECTOR(11 DOWNTO 0);
186 186 SIGNAL observation_vector_1 : STD_LOGIC_VECTOR(11 DOWNTO 0);
187 187 -----------------------------------------------------------------------------
188 188
189 189 SIGNAL LFR_soft_rstn : STD_LOGIC;
190 190 SIGNAL LFR_rstn : STD_LOGIC;
191 191
192 192
193 193 SIGNAL rstn_25 : STD_LOGIC;
194 194 SIGNAL rstn_25_d1 : STD_LOGIC;
195 195 SIGNAL rstn_25_d2 : STD_LOGIC;
196 196 SIGNAL rstn_25_d3 : STD_LOGIC;
197 197
198 198 SIGNAL rstn_24 : STD_LOGIC;
199 199 SIGNAL rstn_24_d1 : STD_LOGIC;
200 200 SIGNAL rstn_24_d2 : STD_LOGIC;
201 201 SIGNAL rstn_24_d3 : STD_LOGIC;
202 202
203 203 SIGNAL rstn_50 : STD_LOGIC;
204 204 SIGNAL rstn_50_d1 : STD_LOGIC;
205 205 SIGNAL rstn_50_d2 : STD_LOGIC;
206 206 SIGNAL rstn_50_d3 : STD_LOGIC;
207 207
208 208 SIGNAL lfr_debug_vector : STD_LOGIC_VECTOR(11 DOWNTO 0);
209 209 SIGNAL lfr_debug_vector_ms : STD_LOGIC_VECTOR(11 DOWNTO 0);
210 210
211 211 --
212 212 SIGNAL SRAM_CE_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
213 213
214 214 --
215 215 SIGNAL sample_hk : STD_LOGIC_VECTOR(15 DOWNTO 0);
216 216 SIGNAL HK_SEL : STD_LOGIC_VECTOR(1 DOWNTO 0);
217 217
218 218 BEGIN -- beh
219 219
220 220 -----------------------------------------------------------------------------
221 221 -- CLK
222 222 -----------------------------------------------------------------------------
223 223
224 224 --PROCESS(clk_50)
225 225 --BEGIN
226 226 -- IF clk_50'EVENT AND clk_50 = '1' THEN
227 227 -- clk_50_s <= NOT clk_50_s;
228 228 -- END IF;
229 229 --END PROCESS;
230 230
231 231 --PROCESS(clk_50_s)
232 232 --BEGIN
233 233 -- IF clk_50_s'EVENT AND clk_50_s = '1' THEN
234 234 -- clk_25 <= NOT clk_25;
235 235 -- END IF;
236 236 --END PROCESS;
237 237
238 238 --PROCESS(clk_49)
239 239 --BEGIN
240 240 -- IF clk_49'EVENT AND clk_49 = '1' THEN
241 241 -- clk_24 <= NOT clk_24;
242 242 -- END IF;
243 243 --END PROCESS;
244 244
245 245 --PROCESS(clk_25)
246 246 --BEGIN
247 247 -- IF clk_25'EVENT AND clk_25 = '1' THEN
248 248 -- rstn_25 <= reset;
249 249 -- END IF;
250 250 --END PROCESS;
251 251
252 252 PROCESS (clk_50, reset)
253 253 BEGIN -- PROCESS
254 254 IF clk_50'EVENT AND clk_50 = '1' THEN -- rising clock edge
255 255 clk_50_s <= NOT clk_50_s;
256 256 END IF;
257 257 END PROCESS;
258 258
259 259 PROCESS (clk_50_s, reset)
260 260 BEGIN -- PROCESS
261 261 IF reset = '0' THEN -- asynchronous reset (active low)
262 262 clk_25 <= '0';
263 263 rstn_25 <= '0';
264 264 rstn_25_d1 <= '0';
265 265 rstn_25_d2 <= '0';
266 266 rstn_25_d3 <= '0';
267 267 ELSIF clk_50_s'EVENT AND clk_50_s = '1' THEN -- rising clock edge
268 268 clk_25 <= NOT clk_25;
269 269 rstn_25_d1 <= '1';
270 270 rstn_25_d2 <= rstn_25_d1;
271 271 rstn_25_d3 <= rstn_25_d2;
272 272 rstn_25 <= rstn_25_d3;
273 273 END IF;
274 274 END PROCESS;
275 275
276 276 PROCESS (clk_49, reset)
277 277 BEGIN -- PROCESS
278 278 IF reset = '0' THEN -- asynchronous reset (active low)
279 279 clk_24 <= '0';
280 280 rstn_24_d1 <= '0';
281 281 rstn_24_d2 <= '0';
282 282 rstn_24_d3 <= '0';
283 283 rstn_24 <= '0';
284 284 ELSIF clk_49'EVENT AND clk_49 = '1' THEN -- rising clock edge
285 285 clk_24 <= NOT clk_24;
286 286 rstn_24_d1 <= '1';
287 287 rstn_24_d2 <= rstn_24_d1;
288 288 rstn_24_d3 <= rstn_24_d2;
289 289 rstn_24 <= rstn_24_d3;
290 290 END IF;
291 291 END PROCESS;
292 292
293 293 -----------------------------------------------------------------------------
294 294
295 295 PROCESS (clk_25, rstn_25)
296 296 BEGIN -- PROCESS
297 297 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
298 298 LED0 <= '0';
299 299 LED1 <= '0';
300 300 LED2 <= '0';
301 301 --IO1 <= '0';
302 302 --IO2 <= '1';
303 303 --IO3 <= '0';
304 304 --IO4 <= '0';
305 305 --IO5 <= '0';
306 306 --IO6 <= '0';
307 307 --IO7 <= '0';
308 308 --IO8 <= '0';
309 309 --IO9 <= '0';
310 310 --IO10 <= '0';
311 311 --IO11 <= '0';
312 312 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
313 313 LED0 <= '0';
314 314 LED1 <= '1';
315 315 LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
316 316 --IO1 <= '1';
317 317 --IO2 <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
318 318 --IO3 <= ADC_SDO(0);
319 319 --IO4 <= ADC_SDO(1);
320 320 --IO5 <= ADC_SDO(2);
321 321 --IO6 <= ADC_SDO(3);
322 322 --IO7 <= ADC_SDO(4);
323 323 --IO8 <= ADC_SDO(5);
324 324 --IO9 <= ADC_SDO(6);
325 325 --IO10 <= ADC_SDO(7);
326 326 --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
327 327 END IF;
328 328 END PROCESS;
329 329
330 330 PROCESS (clk_24, rstn_24)
331 331 BEGIN -- PROCESS
332 332 IF rstn_24 = '0' THEN -- asynchronous reset (active low)
333 333 I00_s <= '0';
334 334 ELSIF clk_24'EVENT AND clk_24 = '1' THEN -- rising clock edge
335 335 I00_s <= NOT I00_s;
336 336 END IF;
337 337 END PROCESS;
338 338 -- IO0 <= I00_s;
339 339
340 340 --UARTs
341 341 nCTS1 <= '1';
342 342 nCTS2 <= '1';
343 343 nDCD2 <= '1';
344 344
345 345 --
346 346
347 347 leon3_soc_1 : leon3_soc
348 348 GENERIC MAP (
349 349 fabtech => apa3e,
350 350 memtech => apa3e,
351 351 padtech => inferred,
352 352 clktech => inferred,
353 353 disas => 0,
354 354 dbguart => 0,
355 355 pclow => 2,
356 356 clk_freq => 25000,
357 357 IS_RADHARD => 0,
358 358 NB_CPU => 1,
359 359 ENABLE_FPU => 1,
360 360 FPU_NETLIST => 0,
361 361 ENABLE_DSU => 1,
362 362 ENABLE_AHB_UART => 1,
363 363 ENABLE_APB_UART => 1,
364 364 ENABLE_IRQMP => 1,
365 365 ENABLE_GPT => 1,
366 366 NB_AHB_MASTER => NB_AHB_MASTER,
367 367 NB_AHB_SLAVE => NB_AHB_SLAVE,
368 368 NB_APB_SLAVE => NB_APB_SLAVE,
369 369 ADDRESS_SIZE => 20,
370 370 USES_IAP_MEMCTRLR => USE_IAP_MEMCTRL,
371 BYPASS_EDAC_MEMCTRLR => '1',
371 372 SRBANKSZ => 9)
372 373 PORT MAP (
373 374 clk => clk_25,
374 375 reset => rstn_25,
375 376 errorn => errorn,
376 377 ahbrxd => TXD1,
377 378 ahbtxd => RXD1,
378 379 urxd1 => TXD2,
379 380 utxd1 => RXD2,
380 381 address => SRAM_A,
381 382 data => SRAM_DQ,
382 383 nSRAM_BE0 => SRAM_nBE(0),
383 384 nSRAM_BE1 => SRAM_nBE(1),
384 385 nSRAM_BE2 => SRAM_nBE(2),
385 386 nSRAM_BE3 => SRAM_nBE(3),
386 387 nSRAM_WE => SRAM_nWE,
387 388 nSRAM_CE => SRAM_CE_s,
388 389 nSRAM_OE => SRAM_nOE,
389 390 nSRAM_READY => '1',
390 391 SRAM_MBE => OPEN,
391 392 apbi_ext => apbi_ext,
392 393 apbo_ext => apbo_ext,
393 394 ahbi_s_ext => ahbi_s_ext,
394 395 ahbo_s_ext => ahbo_s_ext,
395 396 ahbi_m_ext => ahbi_m_ext,
396 397 ahbo_m_ext => ahbo_m_ext);
397 398
398 399 IAP:if USE_IAP_MEMCTRL = 1 GENERATE
399 400 SRAM_CE <= not SRAM_CE_s(0);
400 401 END GENERATE;
401 402
402 403 NOIAP:if USE_IAP_MEMCTRL = 0 GENERATE
403 404 SRAM_CE <= SRAM_CE_s(0);
404 405 END GENERATE;
405 406 -------------------------------------------------------------------------------
406 407 -- APB_LFR_MANAGEMENT ---------------------------------------------------------
407 408 -------------------------------------------------------------------------------
408 409 apb_lfr_management_1 : apb_lfr_management
409 410 GENERIC MAP (
410 411 tech => apa3e,
411 412 pindex => 6,
412 413 paddr => 6,
413 414 pmask => 16#fff#,
414 415 FIRST_DIVISION => 374, -- ((49.152/2) /2^16) - 1 = 375 - 1 = 374
415 416 NB_SECOND_DESYNC => 60) -- 60 secondes of desynchronization before CoarseTime's MSB is Set
416 417 PORT MAP (
417 418 clk25MHz => clk_25,
418 419 resetn_25MHz => rstn_25, -- TODO
419 420 clk24_576MHz => clk_24, -- 49.152MHz/2
420 421 resetn_24_576MHz => rstn_24, -- TODO
421 422 grspw_tick => swno.tickout,
422 423 apbi => apbi_ext,
423 424 apbo => apbo_ext(6),
424 425 HK_sample => sample_hk,
425 426 HK_val => sample_val,
426 427 HK_sel => HK_SEL,
427 428 DAC_SDO => OPEN,
428 429 DAC_SCK => OPEN,
429 430 DAC_SYNC => OPEN,
430 431 DAC_CAL_EN => OPEN,
431 432 coarse_time => coarse_time,
432 433 fine_time => fine_time,
433 434 LFR_soft_rstn => LFR_soft_rstn
434 435 );
435 436
436 437 -----------------------------------------------------------------------
437 438 --- SpaceWire --------------------------------------------------------
438 439 -----------------------------------------------------------------------
439 440
440 441 SPW_EN <= '1';
441 442
442 443 spw_clk <= clk_50_s;
443 444 spw_rxtxclk <= spw_clk;
444 445 spw_rxclkn <= NOT spw_rxtxclk;
445 446
446 447 -- PADS for SPW1
447 448 spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
448 449 PORT MAP (SPW_NOM_DIN, dtmp(0));
449 450 spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
450 451 PORT MAP (SPW_NOM_SIN, stmp(0));
451 452 spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
452 453 PORT MAP (SPW_NOM_DOUT, swno.d(0));
453 454 spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
454 455 PORT MAP (SPW_NOM_SOUT, swno.s(0));
455 456 -- PADS FOR SPW2
456 457 spw2_rxd_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
457 458 PORT MAP (SPW_RED_SIN, dtmp(1));
458 459 spw2_rxs_pad : inpad GENERIC MAP (tech => inferred) -- bad naming of the MINI-LFR /!\
459 460 PORT MAP (SPW_RED_DIN, stmp(1));
460 461 spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
461 462 PORT MAP (SPW_RED_DOUT, swno.d(1));
462 463 spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
463 464 PORT MAP (SPW_RED_SOUT, swno.s(1));
464 465
465 466 -- GRSPW PHY
466 467 --spw1_input: if CFG_SPW_GRSPW = 1 generate
467 468 spw_inputloop : FOR j IN 0 TO 1 GENERATE
468 469 spw_phy0 : grspw_phy
469 470 GENERIC MAP(
470 471 tech => apa3e,
471 472 rxclkbuftype => 1,
472 473 scantest => 0)
473 474 PORT MAP(
474 475 rxrst => swno.rxrst,
475 476 di => dtmp(j),
476 477 si => stmp(j),
477 478 rxclko => spw_rxclk(j),
478 479 do => swni.d(j),
479 480 ndo => swni.nd(j*5+4 DOWNTO j*5),
480 481 dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
481 482 END GENERATE spw_inputloop;
482 483
483 484 swni.rmapnodeaddr <= (OTHERS => '0');
484 485
485 486 -- SPW core
486 487 sw0 : grspwm GENERIC MAP(
487 488 tech => apa3e,
488 489 hindex => 1,
489 490 pindex => 5,
490 491 paddr => 5,
491 492 pirq => 11,
492 493 sysfreq => 25000, -- CPU_FREQ
493 494 rmap => 1,
494 495 rmapcrc => 1,
495 496 fifosize1 => 16,
496 497 fifosize2 => 16,
497 498 rxclkbuftype => 1,
498 499 rxunaligned => 0,
499 500 rmapbufs => 4,
500 501 ft => 0,
501 502 netlist => 0,
502 503 ports => 2,
503 504 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
504 505 memtech => apa3e,
505 506 destkey => 2,
506 507 spwcore => 1
507 508 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
508 509 --output_type => CFG_SPW_OUTPUT, -- not used byt the spw core 1
509 510 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
510 511 )
511 512 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
512 513 spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
513 514 ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
514 515 swni, swno);
515 516
516 517 swni.tickin <= '0';
517 518 swni.rmapen <= '1';
518 519 swni.clkdiv10 <= "00000100"; -- 10 MHz / (4 + 1) = 10 MHz
519 520 swni.tickinraw <= '0';
520 521 swni.timein <= (OTHERS => '0');
521 522 swni.dcrstval <= (OTHERS => '0');
522 523 swni.timerrstval <= (OTHERS => '0');
523 524
524 525 -------------------------------------------------------------------------------
525 526 -- LFR ------------------------------------------------------------------------
526 527 -------------------------------------------------------------------------------
527 528
528 529
529 530 LFR_rstn <= LFR_soft_rstn AND rstn_25;
530 531 --LFR_rstn <= rstn_25;
531 532
532 533 lpp_lfr_1 : lpp_lfr
533 534 GENERIC MAP (
534 535 Mem_use => use_RAM,
535 536 nb_data_by_buffer_size => 32,
536 537 nb_snapshot_param_size => 32,
537 538 delta_vector_size => 32,
538 539 delta_vector_size_f0_2 => 7, -- log2(96)
539 540 pindex => 15,
540 541 paddr => 15,
541 542 pmask => 16#fff#,
542 543 pirq_ms => 6,
543 544 pirq_wfp => 14,
544 545 hindex => 2,
545 546 top_lfr_version => X"000144") -- aa.bb.cc version
546 547 PORT MAP (
547 548 clk => clk_25,
548 549 rstn => LFR_rstn,
549 550 sample_B => sample_s(2 DOWNTO 0),
550 551 sample_E => sample_s(7 DOWNTO 3),
551 552 sample_val => sample_val,
552 553 apbi => apbi_ext,
553 554 apbo => apbo_ext(15),
554 555 ahbi => ahbi_m_ext,
555 556 ahbo => ahbo_m_ext(2),
556 557 coarse_time => coarse_time,
557 558 fine_time => fine_time,
558 559 data_shaping_BW => bias_fail_sw_sig,
559 560 debug_vector => lfr_debug_vector,
560 561 debug_vector_ms => lfr_debug_vector_ms
561 562 );
562 563
563 564 observation_reg(11 DOWNTO 0) <= lfr_debug_vector;
564 565 observation_reg(31 DOWNTO 12) <= (OTHERS => '0');
565 566 observation_vector_0(11 DOWNTO 0) <= lfr_debug_vector;
566 567 observation_vector_1(11 DOWNTO 0) <= lfr_debug_vector;
567 568 IO0 <= rstn_25;
568 569 IO1 <= lfr_debug_vector_ms(0); -- LFR MS FFT data_valid
569 570 IO2 <= lfr_debug_vector_ms(0); -- LFR MS FFT ready
570 571 IO3 <= lfr_debug_vector(0); -- LFR APBREG error_buffer_full
571 572 IO4 <= lfr_debug_vector(1); -- LFR APBREG reg_sp.status_error_buffer_full
572 573 IO5 <= lfr_debug_vector(8); -- LFR APBREG ready_matrix_f2
573 574 IO6 <= lfr_debug_vector(9); -- LFR APBREG reg0_ready_matrix_f2
574 575 IO7 <= lfr_debug_vector(10); -- LFR APBREG reg0_ready_matrix_f2
575 576
576 577 all_sample : FOR I IN 7 DOWNTO 0 GENERATE
577 578 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
578 579 END GENERATE all_sample;
579 580
580 581 top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
581 582 GENERIC MAP(
582 583 ChannelCount => 8,
583 584 SampleNbBits => 14,
584 585 ncycle_cnv_high => 40, -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
585 586 ncycle_cnv => 249) -- 49 152 000 / 98304 /2
586 587 PORT MAP (
587 588 -- CONV
588 589 cnv_clk => clk_24,
589 590 cnv_rstn => rstn_24,
590 591 cnv => ADC_nCS_sig,
591 592 -- DATA
592 593 clk => clk_25,
593 594 rstn => rstn_25,
594 595 sck => ADC_CLK_sig,
595 596 sdo => ADC_SDO_sig,
596 597 -- SAMPLE
597 598 sample => sample,
598 599 sample_val => sample_val);
599 600
600 601 --IO10 <= ADC_SDO_sig(5);
601 602 --IO9 <= ADC_SDO_sig(4);
602 603 --IO8 <= ADC_SDO_sig(3);
603 604
604 605 ADC_nCS <= ADC_nCS_sig;
605 606 ADC_CLK <= ADC_CLK_sig;
606 607 ADC_SDO_sig <= ADC_SDO;
607 608
608 609 sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE
609 610 "0010001000100010" WHEN HK_SEL = "01" ELSE
610 611 "0100010001000100" WHEN HK_SEL = "10" ELSE
611 612 (OTHERS => '0');
612 613
613 614
614 615 ----------------------------------------------------------------------
615 616 --- GPIO -----------------------------------------------------------
616 617 ----------------------------------------------------------------------
617 618
618 619 grgpio0 : grgpio
619 620 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
620 621 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
621 622
622 623 gpioi.sig_en <= (OTHERS => '0');
623 624 gpioi.sig_in <= (OTHERS => '0');
624 625 gpioi.din <= (OTHERS => '0');
625 626 --pio_pad_0 : iopad
626 627 -- GENERIC MAP (tech => CFG_PADTECH)
627 628 -- PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
628 629 --pio_pad_1 : iopad
629 630 -- GENERIC MAP (tech => CFG_PADTECH)
630 631 -- PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
631 632 --pio_pad_2 : iopad
632 633 -- GENERIC MAP (tech => CFG_PADTECH)
633 634 -- PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
634 635 --pio_pad_3 : iopad
635 636 -- GENERIC MAP (tech => CFG_PADTECH)
636 637 -- PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
637 638 --pio_pad_4 : iopad
638 639 -- GENERIC MAP (tech => CFG_PADTECH)
639 640 -- PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
640 641 --pio_pad_5 : iopad
641 642 -- GENERIC MAP (tech => CFG_PADTECH)
642 643 -- PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
643 644 --pio_pad_6 : iopad
644 645 -- GENERIC MAP (tech => CFG_PADTECH)
645 646 -- PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
646 647 --pio_pad_7 : iopad
647 648 -- GENERIC MAP (tech => CFG_PADTECH)
648 649 -- PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
649 650
650 651 PROCESS (clk_25, rstn_25)
651 652 BEGIN -- PROCESS
652 653 IF rstn_25 = '0' THEN -- asynchronous reset (active low)
653 654 -- --IO0 <= '0';
654 655 -- IO1 <= '0';
655 656 -- IO2 <= '0';
656 657 -- IO3 <= '0';
657 658 -- IO4 <= '0';
658 659 -- IO5 <= '0';
659 660 -- IO6 <= '0';
660 661 -- IO7 <= '0';
661 662 IO8 <= '0';
662 663 IO9 <= '0';
663 664 IO10 <= '0';
664 665 IO11 <= '0';
665 666 ELSIF clk_25'EVENT AND clk_25 = '1' THEN -- rising clock edge
666 667 CASE gpioo.dout(2 DOWNTO 0) IS
667 668 WHEN "011" =>
668 669 -- --IO0 <= observation_reg(0 );
669 670 -- IO1 <= observation_reg(1 );
670 671 -- IO2 <= observation_reg(2 );
671 672 -- IO3 <= observation_reg(3 );
672 673 -- IO4 <= observation_reg(4 );
673 674 -- IO5 <= observation_reg(5 );
674 675 -- IO6 <= observation_reg(6 );
675 676 -- IO7 <= observation_reg(7 );
676 677 IO8 <= observation_reg(8);
677 678 IO9 <= observation_reg(9);
678 679 IO10 <= observation_reg(10);
679 680 IO11 <= observation_reg(11);
680 681 WHEN "001" =>
681 682 -- --IO0 <= observation_reg(0 + 12);
682 683 -- IO1 <= observation_reg(1 + 12);
683 684 -- IO2 <= observation_reg(2 + 12);
684 685 -- IO3 <= observation_reg(3 + 12);
685 686 -- IO4 <= observation_reg(4 + 12);
686 687 -- IO5 <= observation_reg(5 + 12);
687 688 -- IO6 <= observation_reg(6 + 12);
688 689 -- IO7 <= observation_reg(7 + 12);
689 690 IO8 <= observation_reg(8 + 12);
690 691 IO9 <= observation_reg(9 + 12);
691 692 IO10 <= observation_reg(10 + 12);
692 693 IO11 <= observation_reg(11 + 12);
693 694 WHEN "010" =>
694 695 -- --IO0 <= observation_reg(0 + 12 + 12);
695 696 -- IO1 <= observation_reg(1 + 12 + 12);
696 697 -- IO2 <= observation_reg(2 + 12 + 12);
697 698 -- IO3 <= observation_reg(3 + 12 + 12);
698 699 -- IO4 <= observation_reg(4 + 12 + 12);
699 700 -- IO5 <= observation_reg(5 + 12 + 12);
700 701 -- IO6 <= observation_reg(6 + 12 + 12);
701 702 -- IO7 <= observation_reg(7 + 12 + 12);
702 703 IO8 <= '0';
703 704 IO9 <= '0';
704 705 IO10 <= '0';
705 706 IO11 <= '0';
706 707 WHEN "000" =>
707 708 -- --IO0 <= observation_vector_0(0 );
708 709 -- IO1 <= observation_vector_0(1 );
709 710 -- IO2 <= observation_vector_0(2 );
710 711 -- IO3 <= observation_vector_0(3 );
711 712 -- IO4 <= observation_vector_0(4 );
712 713 -- IO5 <= observation_vector_0(5 );
713 714 -- IO6 <= observation_vector_0(6 );
714 715 -- IO7 <= observation_vector_0(7 );
715 716 IO8 <= observation_vector_0(8);
716 717 IO9 <= observation_vector_0(9);
717 718 IO10 <= observation_vector_0(10);
718 719 IO11 <= observation_vector_0(11);
719 720 WHEN "100" =>
720 721 -- --IO0 <= observation_vector_1(0 );
721 722 -- IO1 <= observation_vector_1(1 );
722 723 -- IO2 <= observation_vector_1(2 );
723 724 -- IO3 <= observation_vector_1(3 );
724 725 -- IO4 <= observation_vector_1(4 );
725 726 -- IO5 <= observation_vector_1(5 );
726 727 -- IO6 <= observation_vector_1(6 );
727 728 -- IO7 <= observation_vector_1(7 );
728 729 IO8 <= observation_vector_1(8);
729 730 IO9 <= observation_vector_1(9);
730 731 IO10 <= observation_vector_1(10);
731 732 IO11 <= observation_vector_1(11);
732 733 WHEN OTHERS => NULL;
733 734 END CASE;
734 735
735 736 END IF;
736 737 END PROCESS;
737 738 -----------------------------------------------------------------------------
738 739 --
739 740 -----------------------------------------------------------------------------
740 741 all_apbo_ext : FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
741 742 apbo_ext_not_used : IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
742 743 apbo_ext(I) <= apb_none;
743 744 END GENERATE apbo_ext_not_used;
744 745 END GENERATE all_apbo_ext;
745 746
746 747
747 748 all_ahbo_ext : FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
748 749 ahbo_s_ext(I) <= ahbs_none;
749 750 END GENERATE all_ahbo_ext;
750 751
751 752 all_ahbo_m_ext : FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
752 753 ahbo_m_ext_not_used : IF I /= 1 AND I /= 2 GENERATE
753 754 ahbo_m_ext(I) <= ahbm_none;
754 755 END GENERATE ahbo_m_ext_not_used;
755 756 END GENERATE all_ahbo_m_ext;
756 757
757 758 END beh;
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