HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r463:832e74562224

1.1.34 : idem 1.1.33 avec reset soft pour LFR subsystem

pellion -

r463:832e74562224 (LFR-EM) WFP_MS-1-1-34 JC

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r463:832e74562224

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designs/LFR-em-WFP_MS/LFR-em.vhd +11 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;      -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY LFR_em IS
               PORT (
                 clk100MHz    : IN STD_ULOGIC;
                 clk49_152MHz : IN STD_ULOGIC;
                 reset        : IN STD_ULOGIC;
                 -- TAG --------------------------------------------------------------------
                 TAG1 : IN  STD_ULOGIC;            -- DSU rx data
                 TAG3 : OUT STD_ULOGIC;            -- DSU tx data
                 -- UART APB ---------------------------------------------------------------
                 TAG2 : IN  STD_ULOGIC;            -- UART1 rx data
                 TAG4 : OUT STD_ULOGIC;            -- UART1 tx data
                 -- RAM --------------------------------------------------------------------
                 address   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 data      : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 nSRAM_BE0 : OUT   STD_LOGIC;
                 nSRAM_BE1 : OUT   STD_LOGIC;
                 nSRAM_BE2 : OUT   STD_LOGIC;
                 nSRAM_BE3 : OUT   STD_LOGIC;
                 nSRAM_WE  : OUT   STD_LOGIC;
                 nSRAM_CE  : OUT   STD_LOGIC;
                 nSRAM_OE  : OUT   STD_LOGIC;
                 -- SPW --------------------------------------------------------------------
                 spw1_din  : IN  STD_LOGIC;
                 spw1_sin  : IN  STD_LOGIC;
                 spw1_dout : OUT STD_LOGIC;
                 spw1_sout : OUT STD_LOGIC;
                 spw2_din  : IN  STD_LOGIC;
                 spw2_sin  : IN  STD_LOGIC;
                 spw2_dout : OUT STD_LOGIC;
                 spw2_sout : OUT STD_LOGIC;
                 -- ADC --------------------------------------------------------------------
                 bias_fail_sw   : OUT STD_LOGIC;
                 ADC_OEB_bar_CH : OUT STD_LOGIC_VECTOR(7 DOWNTO 0);
                 ADC_smpclk     : OUT STD_LOGIC;
                 ADC_data       : IN  STD_LOGIC_VECTOR(13 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 TAG8 : OUT STD_LOGIC;
                 led : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)
                 );
             END LFR_em;
             ARCHITECTURE beh OF LFR_em IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5)  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3)  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1) := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL rstn : STD_LOGIC;
+              SIGNAL LFR_soft_rstn  : STD_LOGIC;
+              SIGNAL LFR_rstn       : STD_LOGIC;
               SIGNAL ADC_smpclk_s : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               rst0 : rstgen PORT MAP (reset, clk_25, '1', rstn, OPEN);
               PROCESS(clk100MHz)
               BEGIN
                 IF clk100MHz'EVENT AND clk100MHz = '1' THEN
                   clk_50_s <= NOT clk_50_s;
                 END IF;
               END PROCESS;
               PROCESS(clk_50_s)
               BEGIN
                 IF clk_50_s'EVENT AND clk_50_s = '1' THEN
                   clk_25 <= NOT clk_25;
                 END IF;
               END PROCESS;
               PROCESS(clk49_152MHz)
               BEGIN
                 IF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                 -- asynchronous reset (active low)
                   led(0) <= '0';
                   led(1) <= '0';
                   led(2) <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   led(0) <= '0';
                   led(1) <= '1';
                   led(2) <= '1';
                 END IF;
               END PROCESS;
               --
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn,
                   errorn    => OPEN,
                   ahbrxd    => TAG1,
                   ahbtxd    => TAG3,
                   urxd1     => TAG2,
                   utxd1     => TAG4,
                   address   => address,
                   data      => data,
                   nSRAM_BE0 => nSRAM_BE0,
                   nSRAM_BE1 => nSRAM_BE1,
                   nSRAM_BE2 => nSRAM_BE2,
                   nSRAM_BE3 => nSRAM_BE3,
                   nSRAM_WE  => nSRAM_WE,
                   nSRAM_CE  => nSRAM_CE,
                   nSRAM_OE  => nSRAM_OE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_time_management_1 : apb_lfr_time_management
                 GENERIC MAP (
                   pindex => 6,
                   paddr  => 6,
                   pmask  => 16#fff#,
                   FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz     => clk_25,
                   clk24_576MHz => clk_24,           -- 49.152MHz/2
                   resetn       => rstn,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                   coarse_time  => coarse_time,
-                  fine_time    => fine_time);
+                  fine_time    => fine_time,
+                  LFR_soft_rstn => LFR_soft_rstn
+                  );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
             --  SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_din, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sin, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_dout, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw1_sout, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_din, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (spw2_sin, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_dout, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (spw2_sout, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
+              LFR_rstn <= LFR_soft_rstn AND rstn;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   --nb_word_by_buffer_size => 30,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,      -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
-                  top_lfr_version        => X"010121")  -- aa.bb.cc version
+                  top_lfr_version        => X"010122")  -- aa.bb.cc version
                                                         -- AA : BOARD NUMBER
                                                         --      0 => MINI_LFR
                                                         --      1 => EM
                 PORT MAP (
                   clk             => clk_25,
-                  rstn            => rstn,
+                  rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw);--,
               --observation_vector_0 => OPEN,
               --observation_vector_1 => OPEN,
               --observation_reg => observation_reg);
               all_sample: FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I) & '0' & '0';
               END GENERATE all_sample;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               top_ad_conv_RHF1401_withFilter_1: top_ad_conv_RHF1401_withFilter
                 GENERIC MAP (
                   ChanelCount     => 8,
                   ncycle_cnv_high => 13,
                   ncycle_cnv      => 25)
                 PORT MAP (
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn,
                   cnv        => ADC_smpclk_s,
                   clk        => clk_25,
                   rstn       => rstn,
                   ADC_data   => ADC_data,
                   ADC_nOE    => ADC_OEB_bar_CH,
                   sample     => sample,
                   sample_val => sample_val);
               --top_ad_conv_RHF1401_1 : top_ad_conv_RHF1401
               --  GENERIC MAP (
               --    ChanelCount     => 8,
               --    ncycle_cnv_high => 40,            -- TODO : 79
               --    ncycle_cnv      => 250)           -- TODO : 500
               --  PORT MAP (
               --    cnv_clk    => clk_24,             -- TODO : 49.152
               --    cnv_rstn   => rstn,               -- ok
               --    cnv        => ADC_smpclk_s,         -- ok
               --    clk        => clk_25,             -- ok
               --    rstn       => rstn,               -- ok
               --    ADC_data   => ADC_data,           -- ok
               --    ADC_nOE    => ADC_OEB_bar_CH,     -- ok
               --    sample     => sample,             -- ok
               --    sample_val => sample_val);        -- ok
               ADC_smpclk <= ADC_smpclk_s;
               TAG8 <= ADC_smpclk_s;
             END beh;

designs/MINI-LFR_WFP_MS/MINI_LFR_top.vhd +14 -7

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                     Mail : jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY gaisler;
             USE gaisler.memctrl.ALL;
             USE gaisler.leon3.ALL;
             USE gaisler.uart.ALL;
             USE gaisler.misc.ALL;
             USE gaisler.spacewire.ALL;
             LIBRARY esa;
             USE esa.memoryctrl.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.lpp_lfr_pkg.ALL;      -- contains lpp_lfr, not in the 206 rev of the VHD_Lib
             USE lpp.lpp_top_lfr_pkg.ALL;            -- contains top_wf_picker
             USE lpp.iir_filter.ALL;
             USE lpp.general_purpose.ALL;
             USE lpp.lpp_lfr_time_management.ALL;
             USE lpp.lpp_leon3_soc_pkg.ALL;
             ENTITY MINI_LFR_top IS
               PORT (
                 clk_50 : IN  STD_LOGIC;
                 clk_49 : IN  STD_LOGIC;
                 reset  : IN  STD_LOGIC;
                 --BPs
                 BP0    : IN  STD_LOGIC;
                 BP1    : IN  STD_LOGIC;
                 --LEDs
                 LED0   : OUT STD_LOGIC;
                 LED1   : OUT STD_LOGIC;
                 LED2   : OUT STD_LOGIC;
                 --UARTs
                 TXD1   : IN  STD_LOGIC;
                 RXD1   : OUT STD_LOGIC;
                 nCTS1  : OUT STD_LOGIC;
                 nRTS1  : IN  STD_LOGIC;
                 TXD2  : IN  STD_LOGIC;
                 RXD2  : OUT STD_LOGIC;
                 nCTS2 : OUT STD_LOGIC;
                 nDTR2 : IN  STD_LOGIC;
                 nRTS2 : IN  STD_LOGIC;
                 nDCD2 : OUT STD_LOGIC;
                 --EXT CONNECTOR
                 IO0  : INOUT STD_LOGIC;
                 IO1  : INOUT STD_LOGIC;
                 IO2  : INOUT STD_LOGIC;
                 IO3  : INOUT STD_LOGIC;
                 IO4  : INOUT STD_LOGIC;
                 IO5  : INOUT STD_LOGIC;
                 IO6  : INOUT STD_LOGIC;
                 IO7  : INOUT STD_LOGIC;
                 IO8  : INOUT STD_LOGIC;
                 IO9  : INOUT STD_LOGIC;
                 IO10 : INOUT STD_LOGIC;
                 IO11 : INOUT STD_LOGIC;
                 --SPACE WIRE
                 SPW_EN       : OUT STD_LOGIC;       -- 0 => off
                 SPW_NOM_DIN  : IN  STD_LOGIC;       -- NOMINAL LINK
                 SPW_NOM_SIN  : IN  STD_LOGIC;
                 SPW_NOM_DOUT : OUT STD_LOGIC;
                 SPW_NOM_SOUT : OUT STD_LOGIC;
                 SPW_RED_DIN  : IN  STD_LOGIC;       -- REDUNDANT LINK
                 SPW_RED_SIN  : IN  STD_LOGIC;
                 SPW_RED_DOUT : OUT STD_LOGIC;
                 SPW_RED_SOUT : OUT STD_LOGIC;
                 -- MINI LFR ADC INPUTS
                 ADC_nCS      : OUT STD_LOGIC;
                 ADC_CLK      : OUT STD_LOGIC;
                 ADC_SDO      : IN  STD_LOGIC_VECTOR(7 DOWNTO 0);
                 -- SRAM
                 SRAM_nWE : OUT   STD_LOGIC;
                 SRAM_CE  : OUT   STD_LOGIC;
                 SRAM_nOE : OUT   STD_LOGIC;
                 SRAM_nBE : OUT   STD_LOGIC_VECTOR(3 DOWNTO 0);
                 SRAM_A   : OUT   STD_LOGIC_VECTOR(19 DOWNTO 0);
                 SRAM_DQ  : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0)
                 );
             END MINI_LFR_top;
             ARCHITECTURE beh OF MINI_LFR_top IS
               SIGNAL clk_50_s    : STD_LOGIC := '0';
               SIGNAL clk_25      : STD_LOGIC := '0';
               SIGNAL clk_24      : STD_LOGIC := '0';
               -----------------------------------------------------------------------------
               SIGNAL coarse_time : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL fine_time   : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL errorn      : STD_LOGIC;
               -- UART AHB ---------------------------------------------------------------
-              SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
+            --  SIGNAL ahbrxd      : STD_ULOGIC;      -- DSU rx data
-              SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
+            --  SIGNAL ahbtxd      : STD_ULOGIC;      -- DSU tx data
               -- UART APB ---------------------------------------------------------------
-              SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
+            --  SIGNAL urxd1 : STD_ULOGIC;            -- UART1 rx data
-              SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
+            --  SIGNAL utxd1 : STD_ULOGIC;            -- UART1 tx data
                                                     --
               SIGNAL I00_s : STD_LOGIC;
               -- CONSTANTS
               CONSTANT CFG_PADTECH   : INTEGER := inferred;
               --
               CONSTANT NB_APB_SLAVE  : INTEGER := 11;  -- 3 = grspw + waveform picker + time manager, 11 allows pindex = f
               CONSTANT NB_AHB_SLAVE  : INTEGER := 1;
               CONSTANT NB_AHB_MASTER : INTEGER := 2;   -- 2 = grspw + waveform picker
               SIGNAL apbi_ext   : apb_slv_in_type;
               SIGNAL apbo_ext   : soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5);--  := (OTHERS => apb_none);
               SIGNAL ahbi_s_ext : ahb_slv_in_type;
               SIGNAL ahbo_s_ext : soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3);--  := (OTHERS => ahbs_none);
               SIGNAL ahbi_m_ext : AHB_Mst_In_Type;
               SIGNAL ahbo_m_ext : soc_ahb_mst_out_vector(NB_AHB_MASTER-1+1 DOWNTO 1);-- := (OTHERS => ahbm_none);
             -- Spacewire signals
               SIGNAL dtmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL stmp        : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxclk   : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL spw_rxtxclk : STD_ULOGIC;
               SIGNAL spw_rxclkn  : STD_ULOGIC;
               SIGNAL spw_clk     : STD_LOGIC;
               SIGNAL swni        : grspw_in_type;
               SIGNAL swno        : grspw_out_type;
             --  SIGNAL clkmn                : STD_ULOGIC;
             --  SIGNAL txclk                : STD_ULOGIC;
             --GPIO
               SIGNAL gpioi : gpio_in_type;
               SIGNAL gpioo : gpio_out_type;
             -- AD Converter ADS7886
               SIGNAL sample      : Samples14v(7 DOWNTO 0);
               SIGNAL sample_s    : Samples(7 DOWNTO 0);
               SIGNAL sample_val  : STD_LOGIC;
               SIGNAL ADC_nCS_sig : STD_LOGIC;
               SIGNAL ADC_CLK_sig : STD_LOGIC;
               SIGNAL ADC_SDO_sig : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL bias_fail_sw_sig : STD_LOGIC;
               SIGNAL observation_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL observation_vector_0: STD_LOGIC_VECTOR(11 DOWNTO 0);
               SIGNAL observation_vector_1: STD_LOGIC_VECTOR(11 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL LFR_soft_rstn : STD_LOGIC;
               SIGNAL LFR_rstn : STD_LOGIC;
               SIGNAL rstn_25    : STD_LOGIC;
               SIGNAL rstn_25_d1 : STD_LOGIC;
               SIGNAL rstn_25_d2 : STD_LOGIC;
               SIGNAL rstn_25_d3 : STD_LOGIC;
               SIGNAL rstn_50    : STD_LOGIC;
               SIGNAL rstn_50_d1 : STD_LOGIC;
               SIGNAL rstn_50_d2 : STD_LOGIC;
               SIGNAL rstn_50_d3 : STD_LOGIC;
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               -- CLK
               -----------------------------------------------------------------------------
               --PROCESS(clk_50)
               --BEGIN
               --  IF clk_50'EVENT AND clk_50 = '1' THEN
               --    clk_50_s <= NOT clk_50_s;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_50_s)
               --BEGIN
               --  IF clk_50_s'EVENT AND clk_50_s = '1' THEN
               --    clk_25 <= NOT clk_25;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_49)
               --BEGIN
               --  IF clk_49'EVENT AND clk_49 = '1' THEN
               --    clk_24 <= NOT clk_24;
               --  END IF;
               --END PROCESS;
               --PROCESS(clk_25)
               --BEGIN
               --  IF clk_25'EVENT AND clk_25 = '1' THEN
               --    rstn_25 <= reset;
               --  END IF;
               --END PROCESS;
               PROCESS (clk_50, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_50_s   <= '0';
                   rstn_50    <= '0';
                   rstn_50_d1 <= '0';
                   rstn_50_d2 <= '0';
                   rstn_50_d3 <= '0';
                 ELSIF clk_50'event AND clk_50 = '1' THEN  -- rising clock edge
                   clk_50_s  <= NOT clk_50_s;
                   rstn_50_d1 <= '1';
                   rstn_50_d2 <= rstn_50_d1;
                   rstn_50_d3 <= rstn_50_d2;
                   rstn_50    <= rstn_50_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_50_s, rstn_50)
               BEGIN  -- PROCESS
                 IF rstn_50 = '0' THEN               -- asynchronous reset (active low)
                   clk_25   <= '0';
                   rstn_25    <= '0';
                   rstn_25_d1 <= '0';
                   rstn_25_d2 <= '0';
                   rstn_25_d3 <= '0';
                 ELSIF clk_50_s'event AND clk_50_s = '1' THEN  -- rising clock edge
                   clk_25     <= NOT clk_25;
                   rstn_25_d1 <= '1';
                   rstn_25_d2 <= rstn_25_d1;
                   rstn_25_d3 <= rstn_25_d2;
                   rstn_25    <= rstn_25_d3;
                 END IF;
               END PROCESS;
               PROCESS (clk_49, reset)
               BEGIN  -- PROCESS
                 IF reset = '0' THEN                 -- asynchronous reset (active low)
                   clk_24 <= '0';
                 ELSIF clk_49'event AND clk_49 = '1' THEN  -- rising clock edge
                   clk_24 <= NOT clk_24;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN                 -- asynchronous reset (active low)
                   LED0 <= '0';
                   LED1 <= '0';
                   LED2 <= '0';
                   --IO1  <= '0';
                   --IO2  <= '1';
                   --IO3  <= '0';
                   --IO4  <= '0';
                   --IO5  <= '0';
                   --IO6  <= '0';
                   --IO7  <= '0';
                   --IO8  <= '0';
                   --IO9  <= '0';
                   --IO10 <= '0';
                   --IO11 <= '0';
                 ELSIF clk_25'EVENT AND clk_25 = '1' THEN  -- rising clock edge
                   LED0 <= '0';
                   LED1 <= '1';
                   LED2 <= BP0 OR BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                   --IO1  <= '1';
                   --IO2  <= SPW_NOM_DIN OR SPW_NOM_SIN OR SPW_RED_DIN OR SPW_RED_SIN;
                   --IO3  <= ADC_SDO(0);
                   --IO4  <= ADC_SDO(1);
                   --IO5  <= ADC_SDO(2);
                   --IO6  <= ADC_SDO(3);
                   --IO7  <= ADC_SDO(4);
                   --IO8  <= ADC_SDO(5);
                   --IO9  <= ADC_SDO(6);
                   --IO10 <= ADC_SDO(7);
                   --IO11 <= BP1 OR nDTR2 OR nRTS2 OR nRTS1;
                 END IF;
               END PROCESS;
               PROCESS (clk_24, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN                 -- asynchronous reset (active low)
                   I00_s <= '0';
                 ELSIF clk_24'EVENT AND clk_24 = '1' THEN  -- rising clock edge
                   I00_s <= NOT I00_s ;
                 END IF;
               END PROCESS;
             --  IO0 <= I00_s;
               --UARTs
               nCTS1 <= '1';
               nCTS2 <= '1';
               nDCD2 <= '1';
               --EXT CONNECTOR
               --SPACE WIRE
               leon3_soc_1 : leon3_soc
                 GENERIC MAP (
                   fabtech         => apa3e,
                   memtech         => apa3e,
                   padtech         => inferred,
                   clktech         => inferred,
                   disas           => 0,
                   dbguart         => 0,
                   pclow           => 2,
                   clk_freq        => 25000,
                   NB_CPU          => 1,
                   ENABLE_FPU      => 1,
                   FPU_NETLIST     => 0,
                   ENABLE_DSU      => 1,
                   ENABLE_AHB_UART => 1,
                   ENABLE_APB_UART => 1,
                   ENABLE_IRQMP    => 1,
                   ENABLE_GPT      => 1,
                   NB_AHB_MASTER   => NB_AHB_MASTER,
                   NB_AHB_SLAVE    => NB_AHB_SLAVE,
                   NB_APB_SLAVE    => NB_APB_SLAVE,
                   ADDRESS_SIZE    => 20)
                 PORT MAP (
                   clk       => clk_25,
                   reset     => rstn_25,
                   errorn    => errorn,
                   ahbrxd    => TXD1,
                   ahbtxd    => RXD1,
                   urxd1     => TXD2,
                   utxd1     => RXD2,
                   address   => SRAM_A,
                   data      => SRAM_DQ,
                   nSRAM_BE0 => SRAM_nBE(0),
                   nSRAM_BE1 => SRAM_nBE(1),
                   nSRAM_BE2 => SRAM_nBE(2),
                   nSRAM_BE3 => SRAM_nBE(3),
                   nSRAM_WE  => SRAM_nWE,
                   nSRAM_CE  => SRAM_CE,
                   nSRAM_OE  => SRAM_nOE,
                   apbi_ext   => apbi_ext,
                   apbo_ext   => apbo_ext,
                   ahbi_s_ext => ahbi_s_ext,
                   ahbo_s_ext => ahbo_s_ext,
                   ahbi_m_ext => ahbi_m_ext,
                   ahbo_m_ext => ahbo_m_ext);
             -------------------------------------------------------------------------------
             -- APB_LFR_TIME_MANAGEMENT ----------------------------------------------------
             -------------------------------------------------------------------------------
               apb_lfr_time_management_1 : apb_lfr_time_management
                 GENERIC MAP (
                   pindex => 6,
                   paddr  => 6,
                   pmask  => 16#fff#,
                   FIRST_DIVISION   => 374, -- ((49.152/2) /2^16) - 1  = 375 - 1 = 374
                   NB_SECOND_DESYNC => 60)  -- 60 secondes of desynchronization before CoarseTime's MSB is Set
                 PORT MAP (
                   clk25MHz     => clk_25,
                   clk24_576MHz => clk_24,           -- 49.152MHz/2
                   resetn       => rstn_25,
                   grspw_tick   => swno.tickout,
                   apbi         => apbi_ext,
                   apbo         => apbo_ext(6),
                   coarse_time  => coarse_time,
                   fine_time    => fine_time,
                   LFR_soft_rstn => LFR_soft_rstn
                   );
             -----------------------------------------------------------------------
             ---  SpaceWire --------------------------------------------------------
             -----------------------------------------------------------------------
               SPW_EN <= '1';
               spw_clk     <= clk_50_s;
               spw_rxtxclk <= spw_clk;
               spw_rxclkn  <= NOT spw_rxtxclk;
               -- PADS for SPW1
               spw1_rxd_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DIN, dtmp(0));
               spw1_rxs_pad : inpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SIN, stmp(0));
               spw1_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_DOUT, swno.d(0));
               spw1_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_NOM_SOUT, swno.s(0));
               -- PADS FOR SPW2
               spw2_rxd_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_SIN, dtmp(1));
               spw2_rxs_pad : inpad GENERIC MAP (tech => inferred)  -- bad naming of the MINI-LFR /!\
                 PORT MAP (SPW_RED_DIN, stmp(1));
               spw2_txd_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_DOUT, swno.d(1));
               spw2_txs_pad : outpad GENERIC MAP (tech => inferred)
                 PORT MAP (SPW_RED_SOUT, swno.s(1));
               -- GRSPW PHY
               --spw1_input: if CFG_SPW_GRSPW = 1 generate
               spw_inputloop : FOR j IN 0 TO 1 GENERATE
                 spw_phy0 : grspw_phy
                   GENERIC MAP(
                     tech         => apa3e,
                     rxclkbuftype => 1,
                     scantest     => 0)
                   PORT MAP(
                     rxrst    => swno.rxrst,
                     di       => dtmp(j),
                     si       => stmp(j),
                     rxclko   => spw_rxclk(j),
                     do       => swni.d(j),
                     ndo      => swni.nd(j*5+4 DOWNTO j*5),
                     dconnect => swni.dconnect(j*2+1 DOWNTO j*2));
               END GENERATE spw_inputloop;
+              swni.rmapnodeaddr <= (others => '0');
               -- SPW core
               sw0 : grspwm GENERIC MAP(
                 tech         => apa3e,
                 hindex       => 1,
                 pindex       => 5,
                 paddr        => 5,
                 pirq         => 11,
                 sysfreq      => 25000,              -- CPU_FREQ
                 rmap         => 1,
                 rmapcrc      => 1,
                 fifosize1    => 16,
                 fifosize2    => 16,
                 rxclkbuftype => 1,
                 rxunaligned  => 0,
                 rmapbufs     => 4,
                 ft           => 0,
                 netlist      => 0,
                 ports        => 2,
                 --dmachan => CFG_SPW_DMACHAN, -- not used byt the spw core 1
                 memtech      => apa3e,
                 destkey      => 2,
                 spwcore      => 1
                 --input_type => CFG_SPW_INPUT, -- not used byt the spw core 1
                 --output_type => CFG_SPW_OUTPUT,  -- not used byt the spw core 1
                 --rxtx_sameclk => CFG_SPW_RTSAME -- not used byt the spw core 1
                 )
                 PORT MAP(rstn_25, clk_25, spw_rxclk(0),
                          spw_rxclk(1), spw_rxtxclk, spw_rxtxclk,
                          ahbi_m_ext, ahbo_m_ext(1), apbi_ext, apbo_ext(5),
                          swni, swno);
               swni.tickin      <= '0';
               swni.rmapen      <= '1';
               swni.clkdiv10    <= "00000100";       -- 10 MHz / (4 + 1) = 10 MHz
               swni.tickinraw   <= '0';
               swni.timein      <= (OTHERS => '0');
               swni.dcrstval    <= (OTHERS => '0');
               swni.timerrstval <= (OTHERS => '0');
             -------------------------------------------------------------------------------
             -- LFR ------------------------------------------------------------------------
             -------------------------------------------------------------------------------
               --LFR_rstn <= LFR_soft_rstn AND rstn_25;
               LFR_rstn <= rstn_25;
               lpp_lfr_1 : lpp_lfr
                 GENERIC MAP (
                   Mem_use                => use_RAM,
                   nb_data_by_buffer_size => 32,
                   nb_snapshot_param_size => 32,
                   delta_vector_size      => 32,
                   delta_vector_size_f0_2 => 7,      -- log2(96)
                   pindex                 => 15,
                   paddr                  => 15,
                   pmask                  => 16#fff#,
                   pirq_ms                => 6,
                   pirq_wfp               => 14,
                   hindex                 => 2,
                   top_lfr_version        => X"000122")  -- aa.bb.cc version
                 PORT MAP (
                   clk             => clk_25,
                   rstn            => LFR_rstn,
                   sample_B        => sample_s(2 DOWNTO 0),
                   sample_E        => sample_s(7 DOWNTO 3),
                   sample_val      => sample_val,
                   apbi            => apbi_ext,
                   apbo            => apbo_ext(15),
                   ahbi            => ahbi_m_ext,
                   ahbo            => ahbo_m_ext(2),
                   coarse_time     => coarse_time,
                   fine_time       => fine_time,
                   data_shaping_BW => bias_fail_sw_sig);
+              observation_reg      <= (others => '0');
+              observation_vector_0 <= (others => '0');
+              observation_vector_1 <= (others => '0');
               all_sample: FOR I IN 7 DOWNTO 0 GENERATE
                 sample_s(I) <= sample(I)(11 DOWNTO 0) & '0' & '0' & '0' & '0';
               END GENERATE all_sample;
               top_ad_conv_ADS7886_v2_1 : top_ad_conv_ADS7886_v2
                 GENERIC MAP(
                   ChannelCount    => 8,
                   SampleNbBits    => 14,
                   ncycle_cnv_high => 40,  -- at least 32 cycles at 25 MHz, 32 * 49.152 / 25 /2 = 31.5
                   ncycle_cnv      => 249) -- 49 152 000 / 98304 /2
                 PORT MAP (
                   -- CONV
                   cnv_clk    => clk_24,
                   cnv_rstn   => rstn_25,
                   cnv        => ADC_nCS_sig,
                   -- DATA
                   clk        => clk_25,
                   rstn       => rstn_25,
                   sck        => ADC_CLK_sig,
                   sdo        => ADC_SDO_sig,
                   -- SAMPLE
                   sample     => sample,
                   sample_val => sample_val);
               --IO10 <= ADC_SDO_sig(5);
               --IO9  <= ADC_SDO_sig(4);
               --IO8  <= ADC_SDO_sig(3);
               ADC_nCS     <= ADC_nCS_sig;
               ADC_CLK     <= ADC_CLK_sig;
               ADC_SDO_sig <= ADC_SDO;
             ----------------------------------------------------------------------
             ---  GPIO  -----------------------------------------------------------
             ----------------------------------------------------------------------
               grgpio0 : grgpio
                 GENERIC MAP(pindex => 11, paddr => 11, imask => 16#0000#, nbits => 8)
                 PORT MAP(rstn_25, clk_25, apbi_ext, apbo_ext(11), gpioi, gpioo);
+              gpioi.sig_en <= (others => '0');
+              gpioi.sig_in <= (others => '0');
+              gpioi.din    <= (others => '0');
               --pio_pad_0 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO0, gpioo.dout(0), gpioo.oen(0), gpioi.din(0));
               --pio_pad_1 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO1, gpioo.dout(1), gpioo.oen(1), gpioi.din(1));
               --pio_pad_2 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO2, gpioo.dout(2), gpioo.oen(2), gpioi.din(2));
               --pio_pad_3 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO3, gpioo.dout(3), gpioo.oen(3), gpioi.din(3));
               --pio_pad_4 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO4, gpioo.dout(4), gpioo.oen(4), gpioi.din(4));
               --pio_pad_5 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO5, gpioo.dout(5), gpioo.oen(5), gpioi.din(5));
               --pio_pad_6 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO6, gpioo.dout(6), gpioo.oen(6), gpioi.din(6));
               --pio_pad_7 : iopad
               --  GENERIC MAP (tech => CFG_PADTECH)
               --  PORT MAP (IO7, gpioo.dout(7), gpioo.oen(7), gpioi.din(7));
               PROCESS (clk_25, rstn_25)
               BEGIN  -- PROCESS
                 IF rstn_25 = '0' THEN                  -- asynchronous reset (active low)
                   IO0  <= '0';
                   IO1  <= '0';
                   IO2  <= '0';
                   IO3  <= '0';
                   IO4  <= '0';
                   IO5  <= '0';
                   IO6  <= '0';
                   IO7  <= '0';
                   IO8  <= '0';
                   IO9  <= '0';
                   IO10 <= '0';
                   IO11 <= '0';
                 ELSIF clk_25'event AND clk_25 = '1' THEN  -- rising clock edge
                   CASE gpioo.dout(2 DOWNTO 0) IS
                     WHEN "011" =>
                       IO0  <= observation_reg(0 );
                       IO1  <= observation_reg(1 );
                       IO2  <= observation_reg(2 );
                       IO3  <= observation_reg(3 );
                       IO4  <= observation_reg(4 );
                       IO5  <= observation_reg(5 );
                       IO6  <= observation_reg(6 );
                       IO7  <= observation_reg(7 );
                       IO8  <= observation_reg(8 );
                       IO9  <= observation_reg(9 );
                       IO10 <= observation_reg(10);
                       IO11 <= observation_reg(11);
                     WHEN "001" =>
                       IO0  <= observation_reg(0  + 12);
                       IO1  <= observation_reg(1  + 12);
                       IO2  <= observation_reg(2  + 12);
                       IO3  <= observation_reg(3  + 12);
                       IO4  <= observation_reg(4  + 12);
                       IO5  <= observation_reg(5  + 12);
                       IO6  <= observation_reg(6  + 12);
                       IO7  <= observation_reg(7  + 12);
                       IO8  <= observation_reg(8  + 12);
                       IO9  <= observation_reg(9  + 12);
                       IO10 <= observation_reg(10 + 12);
                       IO11 <= observation_reg(11 + 12);
                     WHEN "010" =>
                       IO0  <= observation_reg(0  + 12 + 12);
                       IO1  <= observation_reg(1  + 12 + 12);
                       IO2  <= observation_reg(2  + 12 + 12);
                       IO3  <= observation_reg(3  + 12 + 12);
                       IO4  <= observation_reg(4  + 12 + 12);
                       IO5  <= observation_reg(5  + 12 + 12);
                       IO6  <= observation_reg(6  + 12 + 12);
                       IO7  <= observation_reg(7  + 12 + 12);
                       IO8  <= '0';
                       IO9  <= '0';
                       IO10 <= '0';
                       IO11 <= '0';
                     WHEN "000" =>
                       IO0  <= observation_vector_0(0 );
                       IO1  <= observation_vector_0(1 );
                       IO2  <= observation_vector_0(2 );
                       IO3  <= observation_vector_0(3 );
                       IO4  <= observation_vector_0(4 );
                       IO5  <= observation_vector_0(5 );
                       IO6  <= observation_vector_0(6 );
                       IO7  <= observation_vector_0(7 );
                       IO8  <= observation_vector_0(8 );
                       IO9  <= observation_vector_0(9 );
                       IO10 <= observation_vector_0(10);
                       IO11 <= observation_vector_0(11);
                     WHEN "100" =>
                       IO0  <= observation_vector_1(0 );
                       IO1  <= observation_vector_1(1 );
                       IO2  <= observation_vector_1(2 );
                       IO3  <= observation_vector_1(3 );
                       IO4  <= observation_vector_1(4 );
                       IO5  <= observation_vector_1(5 );
                       IO6  <= observation_vector_1(6 );
                       IO7  <= observation_vector_1(7 );
                       IO8  <= observation_vector_1(8 );
                       IO9  <= observation_vector_1(9 );
                       IO10 <= observation_vector_1(10);
                       IO11 <= observation_vector_1(11);
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_apbo_ext: FOR I IN NB_APB_SLAVE-1+5 DOWNTO 5 GENERATE
                 apbo_ext_not_used: IF I /= 5 AND I /= 6 AND I /= 11 AND I /= 15 GENERATE
                   apbo_ext(I) <= apb_none;
                 END GENERATE apbo_ext_not_used;
               END GENERATE all_apbo_ext;
               all_ahbo_ext: FOR I IN NB_AHB_SLAVE-1+3 DOWNTO 3 GENERATE
                 ahbo_s_ext(I) <= ahbs_none;
               END GENERATE all_ahbo_ext;
               all_ahbo_m_ext: FOR I IN NB_AHB_MASTER-1+1 DOWNTO 1 GENERATE
                 ahbo_m_ext_not_used: IF I /=1 AND I /= 2 GENERATE
                   ahbo_m_ext(I) <= ahbm_none;
                 END GENERATE ahbo_m_ext_not_used;
               END GENERATE all_ahbo_m_ext;
-            END beh;
+            END beh;
  No newline at end of file

designs/MINI-LFR_WFP_MS/testbench.vhd +273 -270

This diff has been collapsed as it changes many lines, (543 lines changed) Show them Hide them
	@@ -1,270 +1,273
	1	LIBRARY ieee;	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;	2	USE ieee.std_logic_1164.ALL;
	3	USE ieee.numeric_std.ALL;	3	USE ieee.numeric_std.ALL;
	4	use IEEE.std_logic_textio.all;	4	use IEEE.std_logic_textio.all;
	5	LIBRARY STD;	5	LIBRARY STD;
	6	use std.textio.all;	6	use std.textio.all;
	7		7
	8	LIBRARY grlib;	8	LIBRARY grlib;
	9	USE grlib.stdlib.ALL;	9	USE grlib.stdlib.ALL;
	10	LIBRARY gaisler;	10	LIBRARY gaisler;
	11	USE gaisler.libdcom.ALL;	11	USE gaisler.libdcom.ALL;
	12	USE gaisler.sim.ALL;	12	USE gaisler.sim.ALL;
	13	USE gaisler.jtagtst.ALL;	13	USE gaisler.jtagtst.ALL;
	14	LIBRARY techmap;	14	LIBRARY techmap;
	15	USE techmap.gencomp.ALL;	15	USE techmap.gencomp.ALL;
	16		16
	17	LIBRARY lpp;	17	LIBRARY lpp;
	18	USE lpp.lpp_sim_pkg.ALL;	18	USE lpp.lpp_sim_pkg.ALL;
	19	USE lpp.lpp_lfr_apbreg_pkg.ALL;	19	USE lpp.lpp_lfr_apbreg_pkg.ALL;
	20	USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;	20	USE lpp.lpp_lfr_time_management_apbreg_pkg.ALL;
	21		21
	22	ENTITY testbench IS	22	LIBRARY postlayout;
	23	END;	23	USE postlayout.ALL;
	24		24
	25	ARCHITECTURE behav OF testbench IS	25	ENTITY testbench IS
	26		26	END;
	27	COMPONENT MINI_LFR_top	27
	28	PORT (	28	ARCHITECTURE behav OF testbench IS
	29	clk_50 : IN STD_LOGIC;	29
	30	clk_49 : IN STD_LOGIC;	30	COMPONENT MINI_LFR_top
	31	reset : IN STD_LOGIC;	31	PORT (
	32	~~BP0~~ : IN STD_LOGIC;	32	clk_50 : IN STD_LOGIC;
	33	~~BP1~~ : IN STD_LOGIC;	33	clk_49 : IN STD_LOGIC;
	34	~~LED0~~ : ~~OUT~~ STD_LOGIC;	34	reset : IN STD_LOGIC;
	35	~~LED1~~ : ~~OUT~~ STD_LOGIC;	35	BP0 : IN STD_LOGIC;
	36	~~LED2~~ : ~~OUT~~ STD_LOGIC;	36	BP1 : IN STD_LOGIC;
	37	~~TXD1~~ : IN STD_LOGIC;	37	LED0 : OUT STD_LOGIC;
	38	RXD1 : OUT STD_LOGIC;	38	LED1 : OUT STD_LOGIC;
	39	~~nCTS1~~ : OUT STD_LOGIC;	39	LED2 : OUT STD_LOGIC;
	40	~~nRTS1~~ : IN STD_LOGIC;	40	TXD1 : IN STD_LOGIC;
	41	~~TXD2~~ : IN STD_LOGIC;	41	RXD1 : OUT STD_LOGIC;
	42	~~RXD2~~ : OUT STD_LOGIC;	42	nCTS1 : OUT STD_LOGIC;
	43	n~~CTS2~~ : ~~OUT~~ STD_LOGIC;	43	nRTS1 : IN STD_LOGIC;
	44	~~nDTR2~~ : IN STD_LOGIC;	44	TXD2 : IN STD_LOGIC;
	45	~~nRTS2~~ : IN STD_LOGIC;	45	RXD2 : OUT STD_LOGIC;
	46	n~~DCD~~2 : OUT STD_LOGIC;	46	nCTS2 : OUT STD_LOGIC;
	47	~~IO0~~ : IN~~OUT~~ STD_LOGIC;	47	nDTR2 : IN STD_LOGIC;
	48	~~IO1~~ : IN~~OUT~~ STD_LOGIC;	48	nRTS2 : IN STD_LOGIC;
	49	~~IO2~~ : INOUT STD_LOGIC;	49	nDCD2 : OUT STD_LOGIC;
	50	IO3 : INOUT STD_LOGIC;	50	IO0 : INOUT STD_LOGIC;
	51	IO4 : INOUT STD_LOGIC;	51	IO1 : INOUT STD_LOGIC;
	52	IO5 : INOUT STD_LOGIC;	52	IO2 : INOUT STD_LOGIC;
	53	IO6 : INOUT STD_LOGIC;	53	IO3 : INOUT STD_LOGIC;
	54	IO7 : INOUT STD_LOGIC;	54	IO4 : INOUT STD_LOGIC;
	55	IO8 : INOUT STD_LOGIC;	55	IO5 : INOUT STD_LOGIC;
	56	IO9 : INOUT STD_LOGIC;	56	IO6 : INOUT STD_LOGIC;
	57	IO10 : INOUT STD_LOGIC;	57	IO7 : INOUT STD_LOGIC;
	58	IO11 : INOUT STD_LOGIC;	58	IO8 : INOUT STD_LOGIC;
	59	~~SPW_EN~~ : OUT STD_LOGIC;	59	IO9 : INOUT STD_LOGIC;
	60	~~SPW_NOM_DIN~~ : IN STD_LOGIC;	60	IO10 : INOUT STD_LOGIC;
	61	~~SPW_NOM_SIN~~ : IN STD_LOGIC;	61	IO11 : INOUT STD_LOGIC;
	62	SPW_~~NOM_DOUT~~ : OUT STD_LOGIC;	62	SPW_EN : OUT STD_LOGIC;
	63	SPW_NOM_~~SOUT~~ : ~~OUT~~ STD_LOGIC;	63	SPW_NOM_DIN : IN STD_LOGIC;
	64	SPW_~~RED_D~~IN : IN STD_LOGIC;	64	SPW_NOM_SIN : IN STD_LOGIC;
	65	SPW_~~RED_SIN~~ : IN STD_LOGIC;	65	SPW_NOM_DOUT : OUT STD_LOGIC;
	66	SPW_~~RED_D~~OUT : OUT STD_LOGIC;	66	SPW_NOM_SOUT : OUT STD_LOGIC;
	67	SPW_RED_~~SOUT~~ : ~~OUT~~ STD_LOGIC;	67	SPW_RED_DIN : IN STD_LOGIC;
	68	~~ADC_nCS~~ : ~~OUT~~ STD_LOGIC;	68	SPW_RED_SIN : IN STD_LOGIC;
	69	~~ADC_CLK~~ : OUT STD_LOGIC;	69	SPW_RED_DOUT : OUT STD_LOGIC;
	70	ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);	70	SPW_RED_SOUT : OUT STD_LOGIC;
	71	~~SRAM_nWE~~ : OUT STD_LOGIC;	71	ADC_nCS : OUT STD_LOGIC;
	72	~~SRAM_CE~~ : OUT STD_LOGIC;	72	ADC_CLK : OUT STD_LOGIC;
	73	~~SRAM_nOE~~ : ~~OUT~~ STD_LOGIC;	73	ADC_SDO : IN STD_LOGIC_VECTOR(7 DOWNTO 0);
	74	SRAM_nBE : OUT STD_LOGIC~~_VECTOR~~(3 ~~DOWNTO~~ 0);	74	SRAM_nWE : OUT STD_LOGIC;
	75	SRAM_A : OUT STD_LOGIC~~_VECTOR~~(19 ~~DOWNTO~~ 0);	75	SRAM_CE : OUT STD_LOGIC;
	76	SRAM_DQ : INOUT STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0));	76	SRAM_nOE : OUT STD_LOGIC;
	77	END COMPONENT;	77	SRAM_nBE : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
	78		78	SRAM_A : OUT STD_LOGIC_VECTOR(19 DOWNTO 0);
	79	-----------------------------------------------------------------------------	79	SRAM_DQ : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0));
	80	SIGNAL clk_50 : STD_LOGIC := '0';	80	END COMPONENT;
	81	SIGNAL clk_49 : STD_LOGIC := '0';	81
	82	SIGNAL reset : STD_LOGIC;	82	-----------------------------------------------------------------------------
	83	SIGNAL ~~BP0~~ : STD_LOGIC;	83	SIGNAL clk_50 : STD_LOGIC := '0';
	84	SIGNAL ~~BP1~~ : STD_LOGIC;	84	SIGNAL clk_49 : STD_LOGIC := '0';
	85	SIGNAL ~~LED0~~ : STD_LOGIC;	85	SIGNAL reset : STD_LOGIC;
	86	SIGNAL ~~LED1~~ : STD_LOGIC;	86	SIGNAL BP0 : STD_LOGIC;
	87	SIGNAL ~~LED2~~ : STD_LOGIC;	87	SIGNAL BP1 : STD_LOGIC;
	88	SIGNAL ~~TXD1~~ : STD_LOGIC;	88	SIGNAL LED0 : STD_LOGIC;
	89	SIGNAL RXD1 : STD_LOGIC;	89	SIGNAL LED1 : STD_LOGIC;
	90	SIGNAL ~~nCTS1~~ : STD_LOGIC;	90	SIGNAL LED2 : STD_LOGIC;
	91	SIGNAL ~~nRTS1~~ : STD_LOGIC;	91	SIGNAL TXD1 : STD_LOGIC;
	92	SIGNAL ~~TXD2~~ : STD_LOGIC;	92	SIGNAL RXD1 : STD_LOGIC;
	93	SIGNAL ~~RXD2~~ : STD_LOGIC;	93	SIGNAL nCTS1 : STD_LOGIC;
	94	SIGNAL n~~CTS2~~ : STD_LOGIC;	94	SIGNAL nRTS1 : STD_LOGIC;
	95	SIGNAL ~~nDTR2~~ : STD_LOGIC;	95	SIGNAL TXD2 : STD_LOGIC;
	96	SIGNAL ~~nRTS2~~ : STD_LOGIC;	96	SIGNAL RXD2 : STD_LOGIC;
	97	SIGNAL n~~DCD~~2 : STD_LOGIC;	97	SIGNAL nCTS2 : STD_LOGIC;
	98	SIGNAL ~~IO0~~ : STD_LOGIC;	98	SIGNAL nDTR2 : STD_LOGIC;
	99	SIGNAL ~~IO1~~ : STD_LOGIC;	99	SIGNAL nRTS2 : STD_LOGIC;
	100	SIGNAL ~~IO2~~ : STD_LOGIC;	100	SIGNAL nDCD2 : STD_LOGIC;
	101	SIGNAL IO3 : STD_LOGIC;	101	SIGNAL IO0 : STD_LOGIC;
	102	SIGNAL IO4 : STD_LOGIC;	102	SIGNAL IO1 : STD_LOGIC;
	103	SIGNAL IO5 : STD_LOGIC;	103	SIGNAL IO2 : STD_LOGIC;
	104	SIGNAL IO6 : STD_LOGIC;	104	SIGNAL IO3 : STD_LOGIC;
	105	SIGNAL IO7 : STD_LOGIC;	105	SIGNAL IO4 : STD_LOGIC;
	106	SIGNAL IO8 : STD_LOGIC;	106	SIGNAL IO5 : STD_LOGIC;
	107	SIGNAL IO9 : STD_LOGIC;	107	SIGNAL IO6 : STD_LOGIC;
	108	SIGNAL IO10 : STD_LOGIC;	108	SIGNAL IO7 : STD_LOGIC;
	109	SIGNAL IO11 : STD_LOGIC;	109	SIGNAL IO8 : STD_LOGIC;
	110	SIGNAL ~~SPW_EN~~ : STD_LOGIC;	110	SIGNAL IO9 : STD_LOGIC;
	111	SIGNAL ~~SPW_NOM_DIN~~ : STD_LOGIC;	111	SIGNAL IO10 : STD_LOGIC;
	112	SIGNAL ~~SPW_NOM_SIN~~ : STD_LOGIC;	112	SIGNAL IO11 : STD_LOGIC;
	113	SIGNAL SPW_~~NOM_DOUT~~ : STD_LOGIC;	113	SIGNAL SPW_EN : STD_LOGIC;
	114	SIGNAL SPW_NOM_~~SOUT~~ : STD_LOGIC;	114	SIGNAL SPW_NOM_DIN : STD_LOGIC;
	115	SIGNAL SPW_~~RED_D~~IN : STD_LOGIC;	115	SIGNAL SPW_NOM_SIN : STD_LOGIC;
	116	SIGNAL SPW_~~RED_SIN~~ : STD_LOGIC;	116	SIGNAL SPW_NOM_DOUT : STD_LOGIC;
	117	SIGNAL SPW_~~RED_D~~OUT : STD_LOGIC;	117	SIGNAL SPW_NOM_SOUT : STD_LOGIC;
	118	SIGNAL SPW_RED_~~SOUT~~ : STD_LOGIC;	118	SIGNAL SPW_RED_DIN : STD_LOGIC;
	119	SIGNAL ~~ADC_nCS~~ : STD_LOGIC;	119	SIGNAL SPW_RED_SIN : STD_LOGIC;
	120	SIGNAL ~~ADC_CLK~~ : STD_LOGIC;	120	SIGNAL SPW_RED_DOUT : STD_LOGIC;
	121	SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);	121	SIGNAL SPW_RED_SOUT : STD_LOGIC;
	122	SIGNAL ~~SRAM_nWE~~ : STD_LOGIC;	122	SIGNAL ADC_nCS : STD_LOGIC;
	123	SIGNAL ~~SRAM_CE~~ : STD_LOGIC;	123	SIGNAL ADC_CLK : STD_LOGIC;
	124	SIGNAL ~~SRAM_nOE~~ : STD_LOGIC;	124	SIGNAL ADC_SDO : STD_LOGIC_VECTOR(7 DOWNTO 0);
	125	SIGNAL SRAM_nBE : STD_LOGIC~~_VECTOR~~(3 ~~DOWNTO~~ 0);	125	SIGNAL SRAM_nWE : STD_LOGIC;
	126	SIGNAL SRAM_A : STD_LOGIC~~_VECTOR~~(19 ~~DOWNTO~~ 0);	126	SIGNAL SRAM_CE : STD_LOGIC;
	127	SIGNAL SRAM_DQ : STD_LOGIC~~_VECTOR~~(31 ~~DOWNTO~~ 0);	127	SIGNAL SRAM_nOE : STD_LOGIC;
	128	-----------------------------------------------------------------------------	128	SIGNAL SRAM_nBE : STD_LOGIC_VECTOR(3 DOWNTO 0);
	129		129	SIGNAL SRAM_A : STD_LOGIC_VECTOR(19 DOWNTO 0);
	130	~~CONSTANT~~ ~~ADDR_BASE_LFR~~ : STD_LOGIC_VECTOR(31 DOWNTO 8) := ~~X"80000F"~~;	130	SIGNAL SRAM_DQ : STD_LOGIC_VECTOR(31 DOWNTO 0);
	131	CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";	131	-----------------------------------------------------------------------------
	132	CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";	132
	133		133	CONSTANT ADDR_BASE_LFR : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000F";
	134		134	CONSTANT ADDR_BASE_TIME_MANAGMENT : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"800006";
	135	SIGNAL message_simu : STRING(1 TO 15) := "---------------";	135	CONSTANT ADDR_BASE_GPIO : STD_LOGIC_VECTOR(31 DOWNTO 8) := X"80000B";
	136		136
	137	BEGIN	137
	138		138	SIGNAL message_simu : STRING(1 TO 15) := "---------------";
	139	-----------------------------------------------------------------------------	139
	140	-- TB	140	BEGIN
	141	-----------------------------------------------------------------------------	141
	142	PROCESS	142	-----------------------------------------------------------------------------
	143	CONSTANT txp : TIME := 320 ns;	143	-- TB
	144	BEGIN -- PROCESS	144	-----------------------------------------------------------------------------
	145	TXD1 <= '1';	145	PROCESS
	146	reset <= '0';	146	CONSTANT txp : TIME := 320 ns;
	147	WAIT FOR 500 ns;	147	BEGIN -- PROCESS
	148	~~reset~~ <= '1';	148	TXD1 <= '1';
	149	WAIT FOR 10000 ns;	149	reset <= '0';
	150	message_simu <= "0 - UART init ";	150	WAIT FOR 500 ns;
	151	UART_INIT(TXD1,txp);	151	reset <= '1';
	152		152	WAIT FOR 10000 ns;
	153	message_simu <= "~~1 - UART tes~~t ";	153	message_simu <= "0 - UART init ";
	154	UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");	154	UART_INIT(TXD1,txp);
	155	UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");	155
	156	UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");	156	message_simu <= "1 - UART test ";
	157		157	UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000010",X"0000FFFF");
	158	-- UNSET the LFR reset	158	UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000A0A");
	159	message_simu <= "2 - LFR UNRESET";	159	UART_WRITE(TXD1,txp,ADDR_BASE_GPIO & "000001",X"00000B0B");
	160	UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");	160
	161	UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");	161	-- UNSET the LFR reset
	162	--	162	message_simu <= "2 - LFR UNRESET";
	163	message_simu <= "3 - LFR CONFIG ";	163	UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_CONTROL , X"00000000");
	164	UART_WRITE(TXD1,txp,ADDR_BASE_~~LFR~~ & ADDR_LFR_~~SM_F0_0_ADDR~~ , X"00000~~B0B~~");	164	UART_WRITE(TXD1,txp,ADDR_BASE_TIME_MANAGMENT & ADDR_LFR_TM_TIME_LOAD , X"00000000");
	165		165	--
	166	WAIT;	166	message_simu <= "3 - LFR CONFIG ";
	167	END PROCESS;	167	UART_WRITE(TXD1,txp,ADDR_BASE_LFR & ADDR_LFR_SM_F0_0_ADDR , X"00000B0B");
	168		168
	169	-----------------------------------------------------------------------------	169	WAIT;
	170	-- CLOCK	170	END PROCESS;
	171	-----------------------------------------------------------------------------	171
	172	clk_50 <= NOT clk_50 AFTER 5 ns;	172	-----------------------------------------------------------------------------
	173	clk_49 <= NOT clk_49 AFTER 10172 ps;	173	-- CLOCK
	174		174	-----------------------------------------------------------------------------
	175	-----------------------------------------------------------------------------	175	clk_50 <= NOT clk_50 AFTER 5 ns;
	176	-- DON'T CARE	176	clk_49 <= NOT clk_49 AFTER 10172 ps;
	177	-----------------------------------------------------------------------------	177
	178	BP0 <= '0';	178	-----------------------------------------------------------------------------
	179	BP1 <= '0';	179	-- DON'T CARE
	180	nRTS1 <= '0' ;	180	-----------------------------------------------------------------------------
	181		181	BP0 <= '0';
	182	~~TXD2~~ <= '1';	182	BP1 <= '0';
	183	nRTS2 <= '1';	183	nRTS1 <= '0' ;
	184	nDTR2 <= '1';	184
	185		185	TXD2 <= '1';
	186	SPW_NOM_DIN <= '1';	186	nRTS2 <= '1';
	187	SPW_NOM_SIN <= '1';	187	nDTR2 <= '1';
	188	SPW_RED_DIN <= '1';	188
	189	SPW_~~RED_S~~IN <= '1';	189	SPW_NOM_DIN <= '1';
	190		190	SPW_NOM_SIN <= '1';
	191	ADC_SDO <= x"AA";	191	SPW_RED_DIN <= '1';
	192		192	SPW_RED_SIN <= '1';
	193	SRAM_DQ <= (OTHERS => 'Z');	193
	194	IO0 <= 'Z';	194	ADC_SDO <= x"AA";
	195	IO1 <= 'Z';	195
	196	IO2 <= 'Z';	196	SRAM_DQ <= (OTHERS => 'Z');
	197	IO3 <= 'Z';	197	IO0 <= 'Z';
	198	IO4 <= 'Z';	198	IO1 <= 'Z';
	199	IO5 <= 'Z';	199	IO2 <= 'Z';
	200	IO6 <= 'Z';	200	IO3 <= 'Z';
	201	IO7 <= 'Z';	201	IO4 <= 'Z';
	202	IO8 <= 'Z';	202	IO5 <= 'Z';
	203	IO9 <= 'Z';	203	IO6 <= 'Z';
	204	IO10 <= 'Z';	204	IO7 <= 'Z';
	205	IO11 <= 'Z';	205	IO8 <= 'Z';
	206		206	IO9 <= 'Z';
	207	-----------------------------------------------------------------------------	207	IO10 <= 'Z';
	208	-- DUT	208	IO11 <= 'Z';
	209	-----------------------------------------------------------------------------	209
	210	MINI_LFR_top_1: MINI_LFR_top	210	-----------------------------------------------------------------------------
	211	PORT MAP (	211	-- DUT
	212	clk_50 => clk_50,	212	-----------------------------------------------------------------------------
	213	clk_49 => clk_49,	213	MINI_LFR_top_1: MINI_LFR_top
	214	reset => reset,	214	PORT MAP (
	215		215	clk_50 => clk_50,
	216	~~BP0~~ => ~~BP0~~,	216	clk_49 => clk_49,
	217	~~BP1~~ => ~~BP1~~,	217	reset => reset,
	218		218
	219	~~LED0~~ => ~~LED~~0,	219	BP0 => BP0,
	220	~~LED1~~ => ~~LED~~1,	220	BP1 => BP1,
	221	LED2 => LED2,	221
	222		222	LED0 => LED0,
	223	TXD1 => TXD1,	223	LED1 => LED1,
	224	~~RXD1~~ => ~~RXD1~~,	224	LED2 => LED2,
	225	nCTS1 => nCTS1,	225
	226	~~nRTS1~~ => ~~nRTS~~1,	226	TXD1 => TXD1,
	227		227	RXD1 => RXD1,
	228	~~TXD2~~ => ~~TXD2~~,	228	nCTS1 => nCTS1,
	229	~~RXD2~~ => ~~RXD2~~,	229	nRTS1 => nRTS1,
	230	nCTS2 => nCTS2,	230
	231	~~nDTR2~~ => ~~nDTR~~2,	231	TXD2 => TXD2,
	232	~~nRTS2~~ => ~~nRTS~~2,	232	RXD2 => RXD2,
	233	n~~DCD~~2 => n~~DCD~~2,	233	nCTS2 => nCTS2,
	234		234	nDTR2 => nDTR2,
	235	~~IO0~~ => ~~IO0~~,	235	nRTS2 => nRTS2,
	236	~~IO1~~ => ~~IO1~~,	236	nDCD2 => nDCD2,
	237	IO2 => IO2,	237
	238	IO3 => IO3,	238	IO0 => IO0,
	239	IO4 => IO4,	239	IO1 => IO1,
	240	IO5 => IO5,	240	IO2 => IO2,
	241	IO6 => IO6,	241	IO3 => IO3,
	242	IO7 => IO7,	242	IO4 => IO4,
	243	IO8 => IO8,	243	IO5 => IO5,
	244	IO9 => IO9,	244	IO6 => IO6,
	245	IO10 => IO10,	245	IO7 => IO7,
	246	IO11 => IO11,	246	IO8 => IO8,
	247		247	IO9 => IO9,
	248	~~SPW_EN~~ => ~~SPW_EN~~,	248	IO10 => IO10,
	249	SPW_NOM_DIN => SPW_NOM_DIN,	249	IO11 => IO11,
	250	SPW_NOM_SIN => SPW_NOM_SIN,	250
	251	SPW_~~NOM_DOUT~~ => SPW_N~~OM_DOUT~~,	251	SPW_EN => SPW_EN,
	252	SPW_NOM_~~SOUT~~ => SPW_NOM_~~SOUT~~,	252	SPW_NOM_DIN => SPW_NOM_DIN,
	253	SPW_~~RED_D~~IN => SPW_~~RED_D~~IN,	253	SPW_NOM_SIN => SPW_NOM_SIN,
	254	SPW_~~RED_SIN~~ => SPW_~~RED_SIN~~,	254	SPW_NOM_DOUT => SPW_NOM_DOUT,
	255	SPW_~~RED_D~~OUT => SPW_~~RED_D~~OUT,	255	SPW_NOM_SOUT => SPW_NOM_SOUT,
	256	SPW_RED_~~SOUT~~ => SPW_RED_~~SOUT~~,	256	SPW_RED_DIN => SPW_RED_DIN,
	257		257	SPW_RED_SIN => SPW_RED_SIN,
	258	ADC_nCS => ADC_nCS,	258	SPW_RED_DOUT => SPW_RED_DOUT,
	259	ADC_CLK => ADC_CLK,	259	SPW_RED_SOUT => SPW_RED_SOUT,
	260	ADC_SDO => ADC_SDO,	260
	261		261	ADC_nCS => ADC_nCS,
	262	~~SRAM_nWE~~ => ~~SRAM_nWE~~,	262	ADC_CLK => ADC_CLK,
	263	~~SRAM_CE~~ => ~~SRAM_CE~~,	263	ADC_SDO => ADC_SDO,
	264	SRAM_nOE => SRAM_nOE,	264
	265	SRAM_nBE => SRAM_nBE,	265	SRAM_nWE => SRAM_nWE,
	266	SRAM_A => SRAM_A,	266	SRAM_CE => SRAM_CE,
	267	SRAM_DQ => SRAM_DQ);	267	SRAM_nOE => SRAM_nOE,
	268		268	SRAM_nBE => SRAM_nBE,
	269		269	SRAM_A => SRAM_A,
	270	END;	270	SRAM_DQ => SRAM_DQ);
			271
			272
			273	END;

lib/lpp/general_purpose/MAC.vhd +33 -34

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.numeric_std.ALL;
             USE IEEE.std_logic_1164.ALL;
             LIBRARY lpp;
             USE lpp.general_purpose.ALL;
             --TODO
             --terminer le testbensh puis changer le resize dans les instanciations
             --par un resize sur un vecteur en combi
             ENTITY MAC IS
               GENERIC(
                 Input_SZ_A : INTEGER := 8;
                 Input_SZ_B : INTEGER := 8;
                 COMP_EN    : INTEGER := 0           -- 1 =>  No Comp
                 );
               PORT(
                 clk         : IN  STD_LOGIC;
                 reset       : IN  STD_LOGIC;
                 clr_MAC     : IN  STD_LOGIC;
                 MAC_MUL_ADD : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                 Comp_2C     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                 OP1         : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                 OP2         : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                 RES         : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
                 );
             END MAC;
             ARCHITECTURE ar_MAC OF MAC IS
               SIGNAL clr_MAC_s     : STD_LOGIC;
               SIGNAL MAC_MUL_ADD_s : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL add, mult : STD_LOGIC;
               SIGNAL MULTout   : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
               SIGNAL ADDERinA : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
               SIGNAL ADDERinB : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
               SIGNAL ADDERout : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
               SIGNAL MACMUXsel     : STD_LOGIC;
               SIGNAL OP1_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
               SIGNAL OP2_2C_D_Resz : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
               SIGNAL OP1_2C : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
               SIGNAL OP2_2C : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
               SIGNAL MACMUX2sel : STD_LOGIC;
-              SIGNAL add_D            : STD_LOGIC;
+              SIGNAL add_D          : STD_LOGIC;
-              SIGNAL OP1_2C_D         : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
+              SIGNAL OP1_2C_D       : STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
-              SIGNAL OP2_2C_D         : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
+              SIGNAL OP2_2C_D       : STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
-              SIGNAL MULTout_D        : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
+              SIGNAL MULTout_D      : STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0);
-              SIGNAL MACMUXsel_D      : STD_LOGIC;
+              SIGNAL MACMUXsel_D    : STD_LOGIC;
-              SIGNAL MACMUX2sel_D     : STD_LOGIC;
+              SIGNAL MACMUX2sel_D   : STD_LOGIC;
-              SIGNAL MACMUX2sel_D_D   : STD_LOGIC;
+              SIGNAL MACMUX2sel_D_D : STD_LOGIC;
-              SIGNAL clr_MAC_D        : STD_LOGIC;
+              SIGNAL clr_MAC_D      : STD_LOGIC;
             --  SIGNAL clr_MAC_D_D      : STD_LOGIC;
             --  SIGNAL MAC_MUL_ADD_2C_D : STD_LOGIC_VECTOR(1 DOWNTO 0);
-              SIGNAL load_mult_result   : STD_LOGIC;
+            --  SIGNAL load_mult_result   : STD_LOGIC;
-              SIGNAL load_mult_result_D : STD_LOGIC;
+            --  SIGNAL load_mult_result_D : STD_LOGIC;
             BEGIN
             --==============================================================
             --=============M A C  C O N T R O L E R=========================
             --==============================================================
               MAC_CONTROLER1 : MAC_CONTROLER
                 PORT MAP(
                   ctrl        => MAC_MUL_ADD_s,
                   MULT        => mult,
                   ADD         => add,
-                  LOAD_ADDER  => load_mult_result,
+                  --LOAD_ADDER  => load_mult_result,
                   MACMUX_sel  => MACMUXsel,
                   MACMUX2_sel => MACMUX2sel
                   );
             --==============================================================
             --==============================================================
             --=============M U L T I P L I E R==============================
             --==============================================================
               Multiplieri_nst : Multiplier
                 GENERIC MAP(
                   Input_SZ_A => Input_SZ_A,
                   Input_SZ_B => Input_SZ_B
                   )
                 PORT MAP(
                   clk   => clk,
                   reset => reset,
                   mult  => mult,
                   OP1   => OP1_2C,
                   OP2   => OP2_2C,
                   RES   => MULTout
                   );
             --==============================================================
-              PROCESS (clk, reset)
+              --PROCESS (clk, reset)
-              BEGIN  -- PROCESS
+              --BEGIN  -- PROCESS
-                IF reset = '0' THEN                 -- asynchronous reset (active low)
+              --  IF reset = '0' THEN                 -- asynchronous reset (active low)
-                  load_mult_result_D <= '0';
+              --    load_mult_result_D <= '0';
-                ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
+              --  ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
-                  load_mult_result_D <= load_mult_result;
+              --    load_mult_result_D <= load_mult_result;
-                END IF;
+              --  END IF;
-              END PROCESS;
+              --END PROCESS;
             --==============================================================
             --======================A D D E R ==============================
             --==============================================================
               adder_inst : Adder
                 GENERIC MAP(
                   Input_SZ_A => Input_SZ_A+Input_SZ_B,
                   Input_SZ_B => Input_SZ_A+Input_SZ_B
                   )
                 PORT MAP(
                   clk   => clk,
                   reset => reset,
                   clr   => clr_MAC_D,
-                  load  => load_mult_result_D,
+                  load  => MACMUX2sel_D,            --load_mult_result_D,
                   add   => add_D,
                   OP1   => ADDERinA,
                   OP2   => ADDERinB,
                   RES   => ADDERout
                   );
             --==============================================================
             --===================TWO COMPLEMENTERS==========================
             --==============================================================
               gen_comp : IF COMP_EN = 0 GENERATE
                 TWO_COMPLEMENTER1 : TwoComplementer
                   GENERIC MAP(
                     Input_SZ => Input_SZ_A
                     )
                   PORT MAP(
                     clk     => clk,
                     reset   => reset,
-                    clr     => '0',--clr_MAC,
+                    clr     => '0',                 --clr_MAC,
                     TwoComp => Comp_2C(0),
                     OP      => OP1,
                     RES     => OP1_2C
                     );
                 TWO_COMPLEMENTER2 : TwoComplementer
                   GENERIC MAP(
                     Input_SZ => Input_SZ_B
                     )
                   PORT MAP(
                     clk     => clk,
                     reset   => reset,
-                    clr     => '0',--clr_MAC,
+                    clr     => '0',                 --clr_MAC,
                     TwoComp => Comp_2C(1),
                     OP      => OP2,
                     RES     => OP2_2C
                     );
                 clr_MACREG_comp : MAC_REG
                   GENERIC MAP(size => 1)
                   PORT MAP(
                     reset => reset,
                     clk   => clk,
                     D(0)  => clr_MAC,
                     Q(0)  => clr_MAC_s
                     );
                 MAC_MUL_ADD_REG : MAC_REG
-                GENERIC MAP(size => 2)
+                  GENERIC MAP(size => 2)
-                PORT MAP(
+                  PORT MAP(
-                  reset => reset,
+                    reset => reset,
-                  clk   => clk,
+                    clk   => clk,
-                  D     => MAC_MUL_ADD,
+                    D     => MAC_MUL_ADD,
-                  Q     => MAC_MUL_ADD_s
+                    Q     => MAC_MUL_ADD_s
-                  );
+                    );
               END GENERATE gen_comp;
               no_gen_comp : IF COMP_EN = 1 GENERATE
                 OP2_2C <= OP2;
                 OP1_2C <= OP1;
                 clr_MAC_s     <= clr_MAC;
                 MAC_MUL_ADD_s <= MAC_MUL_ADD;
               END GENERATE no_gen_comp;
             --==============================================================
               clr_MACREG1 : MAC_REG
                 GENERIC MAP(size => 1)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D(0)  => clr_MAC_s,
                   Q(0)  => clr_MAC_D
                   );
               addREG : MAC_REG
                 GENERIC MAP(size => 1)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D(0)  => add,
                   Q(0)  => add_D
                   );
               OP1REG : MAC_REG
                 GENERIC MAP(size => Input_SZ_A)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D     => OP1_2C,
                   Q     => OP1_2C_D
                   );
               OP2REG : MAC_REG
                 GENERIC MAP(size => Input_SZ_B)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D     => OP2_2C,
                   Q     => OP2_2C_D
                   );
               MULToutREG : MAC_REG
                 GENERIC MAP(size => Input_SZ_A+Input_SZ_B)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D     => MULTout,
                   Q     => MULTout_D
                   );
               MACMUXselREG : MAC_REG
                 GENERIC MAP(size => 1)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D(0)  => MACMUXsel,
                   Q(0)  => MACMUXsel_D
                   );
               MACMUX2selREG : MAC_REG
                 GENERIC MAP(size => 1)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D(0)  => MACMUX2sel,
                   Q(0)  => MACMUX2sel_D
                   );
               MACMUX2selREG2 : MAC_REG
                 GENERIC MAP(size => 1)
                 PORT MAP(
                   reset => reset,
                   clk   => clk,
                   D(0)  => MACMUX2sel_D,
                   Q(0)  => MACMUX2sel_D_D
                   );
             --==============================================================
             --======================M A C  M U X ===========================
             --==============================================================
               MACMUX_inst : MAC_MUX
                 GENERIC MAP(
                   Input_SZ_A => Input_SZ_A+Input_SZ_B,
                   Input_SZ_B => Input_SZ_A+Input_SZ_B
                   )
                 PORT MAP(
                   sel  => MACMUXsel_D,
                   INA1 => ADDERout,
                   INA2 => OP2_2C_D_Resz,
                   INB1 => MULTout,
                   INB2 => OP1_2C_D_Resz,
                   OUTA => ADDERinA,
                   OUTB => ADDERinB
                   );
               OP1_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP1_2C_D), Input_SZ_A+Input_SZ_B));
               OP2_2C_D_Resz <= STD_LOGIC_VECTOR(resize(SIGNED(OP2_2C_D), Input_SZ_A+Input_SZ_B));
             --==============================================================
             --==============================================================
             --======================M A C  M U X2 ==========================
             --==============================================================
               MAC_MUX2_inst : MAC_MUX2
                 GENERIC MAP(Input_SZ => Input_SZ_A+Input_SZ_B)
                 PORT MAP(
                   sel  => MACMUX2sel_D_D,
                   RES2 => MULTout_D,
                   RES1 => ADDERout,
                   RES  => RES
                   );
             --==============================================================
             END ar_MAC;

lib/lpp/general_purpose/MAC_CONTROLER.vhd +4 -4

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             library IEEE;
             use IEEE.numeric_std.all;
             use IEEE.std_logic_1164.all;
             --IDLE =00 MAC =01 MULT =10 ADD =11
             entity MAC_CONTROLER is
             port(
                 ctrl        :   in  std_logic_vector(1 downto 0);
                 MULT        :   out std_logic;
                 ADD         :   out std_logic;
-                LOAD_ADDER  :   out std_logic;
+            --    LOAD_ADDER  :   out std_logic;
                 MACMUX_sel  :   out std_logic;
                 MACMUX2_sel :   out std_logic
             );
             end MAC_CONTROLER;
             architecture ar_MAC_CONTROLER of MAC_CONTROLER is
             begin
             MULT        <=  '0' when (ctrl = "00" or ctrl = "11") else '1';
             ADD         <=  '0' when (ctrl = "00" or ctrl = "10") else '1';
-            LOAD_ADDER  <=  '1' when (ctrl = "10") else '0';  -- PATCH JC : mem mult result
+            --LOAD_ADDER  <=  '1' when (               ctrl = "10") else '0';  -- PATCH JC : mem mult result
-                                                              -- to permit to compute a
+                                                                             -- to permit to compute a
-                                                              -- MULT follow by a MAC
+                                                                             -- MULT follow by a MAC
             --MACMUX_sel  <=  '0' when (ctrl = "00" or ctrl = "01") else '1';
             MACMUX_sel  <=  '0' when (ctrl = "00" or ctrl = "01" OR ctrl = "10") else '1';
             MACMUX2_sel <=  '0' when (ctrl = "00" or ctrl = "01" or ctrl = "11") else '1';
             end ar_MAC_CONTROLER;

lib/lpp/general_purpose/general_purpose.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             --UPDATE
             -------------------------------------------------------------------------------
             -- 14-03-2013 - Jean-christophe Pellion
             -- ADD MUXN (a parametric multiplexor (N stage of MUX2))
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE IEEE.NUMERIC_STD.ALL;
             PACKAGE general_purpose IS
               COMPONENT general_counter
                 GENERIC (
                   CYCLIC          : STD_LOGIC;
                   NB_BITS_COUNTER : INTEGER);
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
                   RST_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   MAX_VALUE : IN STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   set       : IN  STD_LOGIC;
                   set_value : IN  STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0);
                   add1      : IN  STD_LOGIC;
                   counter   : OUT STD_LOGIC_VECTOR(NB_BITS_COUNTER-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT Clk_divider IS
                 GENERIC(OSC_freqHz    : INTEGER := 50000000;
                         TargetFreq_Hz : INTEGER := 50000);
                 PORT (clk          : IN  STD_LOGIC;
                        reset       : IN  STD_LOGIC;
                        clk_divided : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT Clk_divider2 IS
                 generic(N : integer := 16);
                 port(
                 clk_in  :   in  std_logic;
                 clk_out :   out std_logic);
               END COMPONENT;
               COMPONENT Adder IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 16;
                   Input_SZ_B : INTEGER := 16
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   clr   : IN  STD_LOGIC;
                   load  : IN STD_LOGIC;
                   add   : IN  STD_LOGIC;
                   OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0)
                   );
               END COMPONENT;
             COMPONENT Adder_V0 is
             generic(
                 Input_SZ_A     :   integer := 16;
                 Input_SZ_B     :   integer := 16
             );
             port(
                 clk     :   in  std_logic;
                 reset   :   in  std_logic;
                 clr     :   in  std_logic;
                 add     :   in  std_logic;
                 OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
                 OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
                 RES     :   out std_logic_vector(Input_SZ_A-1 downto 0)
             );
             end COMPONENT;
               COMPONENT ADDRcntr IS
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   count : IN  STD_LOGIC;
                   clr   : IN  STD_LOGIC;
                   Q     : OUT STD_LOGIC_VECTOR(7 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT ALU IS
                 GENERIC(
                   Arith_en   : INTEGER := 1;
                   Logic_en   : INTEGER := 1;
                   Input_SZ_1 : INTEGER := 16;
                   Input_SZ_2 : INTEGER := 9;
                   COMP_EN    : INTEGER := 0 -- 1 =>  No Comp
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   ctrl  : IN  STD_LOGIC_VECTOR(2 downto 0);
                   comp  : IN  STD_LOGIC_VECTOR(1 downto 0);
                   OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                   OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
                   );
               END COMPONENT;
             COMPONENT ALU_V0 IS
               GENERIC(
                 Arith_en   : INTEGER := 1;
                 Logic_en   : INTEGER := 1;
                 Input_SZ_1 : INTEGER := 16;
                 Input_SZ_2 : INTEGER := 9
                 );
               PORT(
                 clk   : IN  STD_LOGIC;
                 reset : IN  STD_LOGIC;
                 ctrl  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0);
                 OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_2-1 DOWNTO 0);
                 RES   : OUT STD_LOGIC_VECTOR(Input_SZ_1+Input_SZ_2-1 DOWNTO 0)
                 );
             END COMPONENT;
             COMPONENT MAC_V0 is
             generic(
                 Input_SZ_A     :   integer := 8;
                 Input_SZ_B     :   integer := 8
             );
             port(
                 clk     :   in  std_logic;
                 reset   :   in  std_logic;
                 clr_MAC :   in  std_logic;
                 MAC_MUL_ADD :   in  std_logic_vector(1 downto 0);
                 OP1     :   in  std_logic_vector(Input_SZ_A-1 downto 0);
                 OP2     :   in  std_logic_vector(Input_SZ_B-1 downto 0);
                 RES     :   out std_logic_vector(Input_SZ_A+Input_SZ_B-1 downto 0)
             );
             end COMPONENT;
             ---------------------------------------------------------
             -------- // Sélection grace a l'entrée "ctrl" \\ --------
             ---------------------------------------------------------
             Constant ctrl_IDLE   : std_logic_vector(2 downto 0) := "000";
             Constant ctrl_MAC    : std_logic_vector(2 downto 0) := "001";
             Constant ctrl_MULT   : std_logic_vector(2 downto 0) := "010";
             Constant ctrl_ADD    : std_logic_vector(2 downto 0) := "011";
             Constant ctrl_CLRMAC : std_logic_vector(2 downto 0) := "100";
             Constant IDLE_V0    : std_logic_vector(3 downto 0) := "0000";
             Constant MAC_op_V0  : std_logic_vector(3 downto 0) := "0001";
             Constant MULT_V0    : std_logic_vector(3 downto 0) := "0010";
             Constant ADD_V0     : std_logic_vector(3 downto 0) := "0011";
             Constant CLR_MAC_V0 : std_logic_vector(3 downto 0) := "0100";
             ---------------------------------------------------------
               COMPONENT MAC IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 8;
                   Input_SZ_B : INTEGER := 8;
                   COMP_EN    : INTEGER := 0 -- 1 =>  No Comp
                   );
                 PORT(
                   clk         : IN  STD_LOGIC;
                   reset       : IN  STD_LOGIC;
                   clr_MAC     : IN  STD_LOGIC;
                   MAC_MUL_ADD : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   Comp_2C     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   OP1         : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OP2         : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   RES         : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT TwoComplementer is
               generic(
                   Input_SZ : integer := 16);
               port(
                   clk     : in  std_logic;                                --! Horloge du composant
                   reset   : in  std_logic;                                --! Reset general du composant
                   clr     : in  std_logic;                                --! Un reset spécifique au programme
                   TwoComp : in  std_logic;                                --! Autorise l'utilisation du complément
                   OP      : in  std_logic_vector(Input_SZ-1 downto 0);    --! Opérande d'entrée
                   RES     : out std_logic_vector(Input_SZ-1 downto 0)     --! Résultat, opérande complémenté ou non
               );
               end COMPONENT;
               COMPONENT MAC_CONTROLER IS
                 PORT(
                   ctrl        : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   MULT        : OUT STD_LOGIC;
                   ADD         : OUT STD_LOGIC;
-                  LOAD_ADDER  : out std_logic;
+            --      LOAD_ADDER  : out std_logic;
                   MACMUX_sel  : OUT STD_LOGIC;
                   MACMUX2_sel : OUT STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT MAC_MUX IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 16;
                   Input_SZ_B : INTEGER := 16
                   );
                 PORT(
                   sel  : IN  STD_LOGIC;
                   INA1 : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   INA2 : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   INB1 : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   INB2 : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   OUTA : OUT STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OUTB : OUT STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT MAC_MUX2 IS
                 GENERIC(Input_SZ : INTEGER := 16);
                 PORT(
                   sel  : IN  STD_LOGIC;
                   RES1 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES2 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES  : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT MAC_REG IS
                 GENERIC(size : INTEGER := 16);
                 PORT(
                   reset : IN  STD_LOGIC;
                   clk   : IN  STD_LOGIC;
                   D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                   Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT MUX2 IS
                 GENERIC(Input_SZ : INTEGER := 16);
                 PORT(
                   sel : IN  STD_LOGIC;
                   IN1 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   IN2 : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               TYPE MUX_INPUT_TYPE IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
               TYPE MUX_OUTPUT_TYPE IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC;
               COMPONENT MUXN
                 GENERIC (
                   Input_SZ : INTEGER;
                   NbStage  : INTEGER);
                 PORT (
                   sel   : IN  STD_LOGIC_VECTOR(NbStage-1 DOWNTO 0);
                   INPUT : IN  MUX_INPUT_TYPE(0 TO (2**NbStage)-1,Input_SZ-1 DOWNTO 0);
                   --INPUT : IN  ARRAY (0 TO (2**NbStage)-1) OF STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   RES   : OUT MUX_OUTPUT_TYPE(Input_SZ-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT Multiplier IS
                 GENERIC(
                   Input_SZ_A : INTEGER := 16;
                   Input_SZ_B : INTEGER := 16
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   mult  : IN  STD_LOGIC;
                   OP1   : IN  STD_LOGIC_VECTOR(Input_SZ_A-1 DOWNTO 0);
                   OP2   : IN  STD_LOGIC_VECTOR(Input_SZ_B-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ_A+Input_SZ_B-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT REG IS
                 GENERIC(size : INTEGER := 16; initial_VALUE : INTEGER := 0);
                 PORT(
                   reset : IN  STD_LOGIC;
                   clk   : IN  STD_LOGIC;
                   D     : IN  STD_LOGIC_VECTOR(size-1 DOWNTO 0);
                   Q     : OUT STD_LOGIC_VECTOR(size-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT RShifter IS
                 GENERIC(
                   Input_SZ : INTEGER := 16;
                   shift_SZ : INTEGER := 4
                   );
                 PORT(
                   clk   : IN  STD_LOGIC;
                   reset : IN  STD_LOGIC;
                   shift : IN  STD_LOGIC;
                   OP    : IN  STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0);
                   cnt   : IN  STD_LOGIC_VECTOR(shift_SZ-1 DOWNTO 0);
                   RES   : OUT STD_LOGIC_VECTOR(Input_SZ-1 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT SYNC_FF
                 GENERIC (
                   NB_FF_OF_SYNC : INTEGER);
                 PORT (
                   clk    : IN  STD_LOGIC;
                   rstn   : IN  STD_LOGIC;
                   A      : IN  STD_LOGIC;
                   A_sync : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_front_to_level
                 PORT (
                   clk  : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_front_detection
                 PORT (
                   clk  : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_front_positive_detection
                 PORT (
                   clk  : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT SYNC_VALID_BIT
                 GENERIC (
                   NB_FF_OF_SYNC : INTEGER);
                 PORT (
                   clk_in  : IN  STD_LOGIC;
                   clk_out : IN  STD_LOGIC;
                   rstn : IN  STD_LOGIC;
                   sin  : IN  STD_LOGIC;
                   sout : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT RR_Arbiter_4
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
                   in_valid  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   out_grant : OUT STD_LOGIC_VECTOR(3 DOWNTO 0));
               END COMPONENT;
             COMPONENT Clock_Divider is
             generic(N :integer := 10);
             port(
                 clk, rst   : in std_logic;
                 sclk       : out std_logic);
             end COMPONENT;
             END;

lib/lpp/lpp_ad_Conv/ADS7886_drvr_v2.vhd +5 -5

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             -- MODIFIED by  Jean-christophe PELLION
             --              jean-christophe.pellion@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             -------------------------------------------------------------------------------
             -- MODIFIED by  Paul LEROY
             --              paul.leroy@lpp.polytechnique.fr
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             ENTITY ADS7886_drvr_v2 IS
               GENERIC(
                 ChannelCount	: INTEGER	:= 8;
                 NbBitsSamples	: INTEGER	:= 16);
               PORT (
                 -- CONV --
                 cnv_clk   : IN  STD_LOGIC;
                 cnv_rstn  : IN  STD_LOGIC;
                 -- DATA --
                 clk  : IN  STD_LOGIC;
                 rstn : IN  STD_LOGIC;
                 sck  : OUT STD_LOGIC;
                 sdo  : IN  STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
             	-- SAMPLE --
                 sample     : OUT Samples(ChannelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END ADS7886_drvr_v2;
             ARCHITECTURE ar_ADS7886_drvr_v2 OF ADS7886_drvr_v2 IS
               SIGNAL cnv_sync           : STD_LOGIC;
               SIGNAL cnv_sync_r         : STD_LOGIC;
               SIGNAL cnv_done           : STD_LOGIC;
               SIGNAL sample_bit_counter : INTEGER;
-              SIGNAL shift_reg          : Samples(ChannelCount-1 DOWNTO 0);
+              SIGNAL shift_reg          : Samples_15(ChannelCount-1 DOWNTO 0);
             BEGIN
             cnv_sync <= cnv_clk;
               PROCESS (clk, rstn)		-- falling edge detection on cnv_sync
               BEGIN
                 IF rstn = '0' THEN
                   cnv_sync_r <= '1';
                   cnv_done   <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   cnv_sync_r <= cnv_sync;
                   cnv_done   <= (NOT cnv_sync) AND cnv_sync_r;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- DATA
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN
                   FOR k IN 0 TO ChannelCount-1 LOOP
-                    shift_reg(k)(15 downto 0)	<= (OTHERS => '0');
+                    shift_reg(k)(14 downto 0)	<= (OTHERS => '0');
-            		sample(k)(15 downto 0) 		<= (OTHERS => '0');
+            	sample(k)(15 downto 0) 		<= (OTHERS => '0');
                   END LOOP;
                   sample_bit_counter <= 0;
                   sample_val         <= '0';
                   SCK                <= '1';
                 ELSIF clk'EVENT AND clk = '1' THEN
             	  IF (cnv_done = '1') AND (sample_bit_counter = 0) THEN
                     sample_bit_counter <= 1;
                   ELSIF sample_bit_counter > 0 AND sample_bit_counter < 31 THEN
                     sample_bit_counter <= sample_bit_counter + 1;
             	  ELSIF sample_bit_counter = 31 THEN
                     sample_val <= '1';
                     FOR k IN 0 TO ChannelCount-1 LOOP
                       sample(k)(0)           <= sdo(k);
                       sample(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
                     END LOOP;
             		sample_bit_counter <= 0;
                   ELSE
                     sample_val <= '0';
                   END IF;
                   IF (sample_bit_counter MOD 2) = 1 THEN	-- get data on each channel
                     FOR k IN 0 TO ChannelCount-1 LOOP
                       shift_reg(k)(0)           <= sdo(k);
-                      shift_reg(k)(15 DOWNTO 1) <= shift_reg(k)(14 DOWNTO 0);
+                      shift_reg(k)(14 DOWNTO 1) <= shift_reg(k)(13 DOWNTO 0);
                     END LOOP;
                     SCK <= '0';
                   ELSE
                     SCK <= '1';
                   END IF;
                 END IF;
               END PROCESS;
-            END ar_ADS7886_drvr_v2;
  No newline at end of file
+            END ar_ADS7886_drvr_v2;

lib/lpp/lpp_ad_Conv/lpp_ad_Conv.vhd +2 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Alexis Jeandet
             --                     Mail : alexis.jeandet@lpp.polytechnique.fr
             ----------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             PACKAGE lpp_ad_conv IS
               --CONSTANT AD7688  : INTEGER := 0;
               --CONSTANT ADS7886 : INTEGER := 1;
               --TYPE AD7688_out IS
               --RECORD
               --  CNV : STD_LOGIC;
               --  SCK : STD_LOGIC;
               --END RECORD;
               --TYPE AD7688_in_element IS
               --RECORD
               --  SDI : STD_LOGIC;
               --END RECORD;
               --TYPE AD7688_in IS ARRAY(NATURAL RANGE <>) OF AD7688_in_element;
-              TYPE Samples IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
+              TYPE Samples    IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(15 DOWNTO 0);
+              TYPE Samples_15 IS ARRAY(NATURAL RANGE <>) OF STD_LOGIC_VECTOR(14 DOWNTO 0);
               SUBTYPE Samples24 IS STD_LOGIC_VECTOR(23 DOWNTO 0);
               SUBTYPE Samples16 IS STD_LOGIC_VECTOR(15 DOWNTO 0);
               SUBTYPE Samples15 IS STD_LOGIC_VECTOR(14 DOWNTO 0);
               SUBTYPE Samples14 IS STD_LOGIC_VECTOR(13 DOWNTO 0);
               SUBTYPE Samples12 IS STD_LOGIC_VECTOR(11 DOWNTO 0);
               SUBTYPE Samples10 IS STD_LOGIC_VECTOR(9 DOWNTO 0);
               SUBTYPE Samples8 IS STD_LOGIC_VECTOR(7 DOWNTO 0);
               TYPE Samples24v IS ARRAY(NATURAL RANGE <>) OF Samples24;
               TYPE Samples16v IS ARRAY(NATURAL RANGE <>) OF Samples16;
               TYPE Samples15v IS ARRAY(NATURAL RANGE <>) OF Samples15;
               TYPE Samples14v IS ARRAY(NATURAL RANGE <>) OF Samples14;
               TYPE Samples12v IS ARRAY(NATURAL RANGE <>) OF Samples12;
               TYPE Samples10v IS ARRAY(NATURAL RANGE <>) OF Samples10;
               TYPE Samples8v IS ARRAY(NATURAL RANGE <>) OF Samples8;
               COMPONENT AD7688_drvr
                 GENERIC (
                   ChanelCount     : INTEGER;
                   ncycle_cnv_high : INTEGER := 79;
                   ncycle_cnv      : INTEGER := 500);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   cnv_rstn   : IN  STD_LOGIC;
                   cnv_run    : IN  STD_LOGIC;
                   cnv        : OUT STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   sck        : OUT STD_LOGIC;
                   sdo        : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT RHF1401_drvr IS
                 GENERIC(
                   ChanelCount : INTEGER := 8);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   ADC_data   : IN  Samples14;
                   --ADC_smpclk : OUT STD_LOGIC;
                   ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC
                   );
               END COMPONENT;
               COMPONENT top_ad_conv_RHF1401
                 GENERIC (
                   ChanelCount : INTEGER;
                   ncycle_cnv_high : INTEGER := 79;
                   ncycle_cnv      : INTEGER := 500);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   cnv_rstn   : IN  STD_LOGIC;
                   cnv        : OUT STD_LOGIC;
                   clk        : IN  STD_LOGIC;
                   rstn       : IN  STD_LOGIC;
                   ADC_data   : IN  Samples14;
                   ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT AD7688_drvr_sync
                 GENERIC (
                   ChanelCount     : INTEGER;
                   ncycle_cnv_high : INTEGER;
                   ncycle_cnv      : INTEGER);
                 PORT (
                   cnv_clk    : IN  STD_LOGIC;
                   cnv_rstn   : IN  STD_LOGIC;
                   cnv_run    : IN  STD_LOGIC;
                   cnv        : OUT STD_LOGIC;
                   sck        : OUT STD_LOGIC;
                   sdo        : IN  STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                   sample     : OUT Samples(ChanelCount-1 DOWNTO 0);
                   sample_val : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT TestModule_RHF1401
                 GENERIC (
                   freq      : INTEGER;
                   amplitude : INTEGER;
                   impulsion : INTEGER);
                 PORT (
                   ADC_smpclk  : IN  STD_LOGIC;
                   ADC_OEB_bar : IN  STD_LOGIC;
                   ADC_data    : OUT STD_LOGIC_VECTOR(13 DOWNTO 0));
               END COMPONENT;
               --COMPONENT AD7688_drvr IS
               --  GENERIC(ChanelCount : INTEGER;
               --          clkkHz      : INTEGER);
               --  PORT (clk        : IN  STD_LOGIC;
               --         rstn      : IN  STD_LOGIC;
               --         enable    : IN  STD_LOGIC;
               --         smplClk   : IN  STD_LOGIC;
               --         DataReady : OUT STD_LOGIC;
               --         smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0);
               --         AD_in     : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --         AD_out    : OUT AD7688_out);
               --END COMPONENT;
               --COMPONENT AD7688_spi_if IS
               --  GENERIC(ChanelCount : INTEGER);
               --  PORT(clk           : IN  STD_LOGIC;
               --           reset     : IN  STD_LOGIC;
               --           cnv       : IN  STD_LOGIC;
               --           DataReady : OUT STD_LOGIC;
               --           sdi       : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --           smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0)
               --           );
               --END COMPONENT;
               --COMPONENT lpp_apb_ad_conv
               --  GENERIC(
               --    pindex      : INTEGER := 0;
               --    paddr       : INTEGER := 0;
               --    pmask       : INTEGER := 16#fff#;
               --    pirq        : INTEGER := 0;
               --    abits       : INTEGER := 8;
               --    ChanelCount : INTEGER := 1;
               --    clkkHz      : INTEGER := 50000;
               --    smpClkHz    : INTEGER := 100;
               --    ADCref      : INTEGER := AD7688);
               --  PORT (
               --    clk    : IN  STD_LOGIC;
               --    reset  : IN  STD_LOGIC;
               --    apbi   : IN  apb_slv_in_type;
               --    apbo   : OUT apb_slv_out_type;
               --    AD_in  : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --    AD_out : OUT AD7688_out);
               --END COMPONENT;
               --COMPONENT ADS7886_drvr IS
               --  GENERIC(ChanelCount : INTEGER;
               --          clkkHz      : INTEGER);
               --  PORT (
               --    clk       : IN  STD_LOGIC;
               --    reset     : IN  STD_LOGIC;
               --    smplClk   : IN  STD_LOGIC;
               --    DataReady : OUT STD_LOGIC;
               --    smpout    : OUT Samples_out(ChanelCount-1 DOWNTO 0);
               --    AD_in     : IN  AD7688_in(ChanelCount-1 DOWNTO 0);
               --    AD_out    : OUT AD7688_out
               --    );
               --END COMPONENT;
               --COMPONENT WriteGen_ADC IS
               --  PORT(
               --    clk       : IN  STD_LOGIC;
               --    rstn      : IN  STD_LOGIC;
               --    SmplCLK   : IN  STD_LOGIC;
               --    DataReady : IN  STD_LOGIC;
               --    Full      : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
               --    ReUse     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
               --    Write     : OUT STD_LOGIC_VECTOR(4 DOWNTO 0)
               --    );
               --END COMPONENT;
             --===========================================================|
             --=======================  ADS 127X =========================|
             --===========================================================|
               TYPE     ADS127X_FORMAT_Type IS ARRAY(2 DOWNTO 0) OF STD_LOGIC;
               CONSTANT ADS127X_SPI_FORMAT   : ADS127X_FORMAT_Type := "010";
               CONSTANT ADS127X_FSYNC_FORMAT : ADS127X_FORMAT_Type := "101";
               TYPE     ADS127X_MODE_Type IS ARRAY(1 DOWNTO 0) OF STD_LOGIC;
               CONSTANT ADS127X_MODE_low_power       : ADS127X_MODE_Type := "10";
               CONSTANT ADS127X_MODE_low_speed       : ADS127X_MODE_Type := "11";
               CONSTANT ADS127X_MODE_high_resolution : ADS127X_MODE_Type := "01";
               TYPE ADS127X_config IS
               RECORD
                 SYNC   : STD_LOGIC;
                 CLKDIV : STD_LOGIC;
                 FORMAT : ADS127X_FORMAT_Type;
                 MODE   : ADS127X_MODE_Type;
               END RECORD;
               COMPONENT ADS1274_DRIVER IS
                 GENERIC(modeCfg : ADS127X_MODE_Type := ADS127X_MODE_low_power; formatCfg : ADS127X_FORMAT_Type := ADS127X_FSYNC_FORMAT);
                 PORT(
                   Clk     : IN  STD_LOGIC;
                   reset   : IN  STD_LOGIC;
                   SpiClk  : OUT STD_LOGIC;
                   DIN     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   Ready   : IN  STD_LOGIC;
                   Format  : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   Mode    : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                   ClkDiv  : OUT STD_LOGIC;
                   PWDOWN  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   SmplClk : IN  STD_LOGIC;
                   OUT0    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT1    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT2    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT3    : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   FSynch  : OUT STD_LOGIC;
                   test    : OUT STD_LOGIC
                   );
               END COMPONENT;
             -- todo clean file
               COMPONENT DUAL_ADS1278_DRIVER IS
                 PORT(
                   Clk     : IN  STD_LOGIC;
                   reset   : IN  STD_LOGIC;
                   SpiClk  : OUT STD_LOGIC;
                   DIN     : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   SmplClk : IN  STD_LOGIC;
                   OUT00   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT01   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT02   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT03   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT04   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT05   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT06   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT07   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT10   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT11   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT12   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT13   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT14   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT15   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT16   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   OUT17   : OUT STD_LOGIC_VECTOR(23 DOWNTO 0);
                   FSynch  : OUT STD_LOGIC
                   );
               END COMPONENT;
             --===========================================================|
             -- DRIVER ADS7886
             --===========================================================|
             COMPONENT top_ad_conv_ADS7886_v2 IS
               GENERIC(
                 ChannelCount 	: INTEGER := 8;
             	SampleNbBits	: INTEGER := 14;
                 ncycle_cnv_high : INTEGER := 40;	-- at least 32 cycles
                 ncycle_cnv      : INTEGER := 500);
               PORT (
             	-- CONV
                 cnv_clk  	: IN STD_LOGIC;
                 cnv_rstn 	: IN STD_LOGIC;
                 cnv 		: OUT STD_LOGIC;
             	-- DATA
                 clk        	: IN  STD_LOGIC;
                 rstn       	: IN  STD_LOGIC;
             	sck			: OUT STD_LOGIC;
             	sdo			: IN  STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
             	-- SAMPLE
                 sample     : OUT Samples14v(ChannelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END COMPONENT;
             COMPONENT ADS7886_drvr_v2 IS
               GENERIC(
                 ChannelCount	: INTEGER	:= 8;
                 NbBitsSamples	: INTEGER	:= 16);
               PORT (
                 -- CONV --
                 cnv_clk   : IN  STD_LOGIC;
                 cnv_rstn  : IN  STD_LOGIC;
                 -- DATA --
                 clk  : IN  STD_LOGIC;
                 rstn : IN  STD_LOGIC;
                 sck  : OUT STD_LOGIC;
                 sdo  : IN  STD_LOGIC_VECTOR(ChannelCount-1 DOWNTO 0);
             	-- SAMPLE --
                 sample     : OUT Samples(ChannelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC
                 );
             END COMPONENT;
             COMPONENT top_ad_conv_RHF1401_withFilter
               GENERIC (
                 ChanelCount     : INTEGER;
                 ncycle_cnv_high : INTEGER;
                 ncycle_cnv      : INTEGER);
               PORT (
                 cnv_clk    : IN  STD_LOGIC;
                 cnv_rstn   : IN  STD_LOGIC;
                 cnv        : OUT STD_LOGIC;
                 clk        : IN  STD_LOGIC;
                 rstn       : IN  STD_LOGIC;
                 ADC_data   : IN  Samples14;
                 ADC_nOE    : OUT STD_LOGIC_VECTOR(ChanelCount-1 DOWNTO 0);
                 sample     : OUT Samples14v(ChanelCount-1 DOWNTO 0);
                 sample_val : OUT STD_LOGIC);
             END COMPONENT;
             END lpp_ad_conv;

lib/lpp/lpp_top_lfr/lpp_lfr.vhd +44 -44

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_top_lfr_pkg.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.general_purpose.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             ENTITY lpp_lfr IS
               GENERIC (
                 Mem_use                : INTEGER := use_RAM;
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 7;
                 pindex   : INTEGER := 4;
                 paddr    : INTEGER := 4;
                 pmask    : INTEGER := 16#fff#;
                 pirq_ms  : INTEGER := 0;
                 pirq_wfp : INTEGER := 1;
                 hindex : INTEGER := 2;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := (OTHERS => '0')
                 );
               PORT (
                 clk             : IN  STD_LOGIC;
                 rstn            : IN  STD_LOGIC;
                 -- SAMPLE
                 sample_B        : IN  Samples(2 DOWNTO 0);
                 sample_E        : IN  Samples(4 DOWNTO 0);
                 sample_val      : IN  STD_LOGIC;
                 -- APB
                 apbi            : IN  apb_slv_in_type;
                 apbo            : OUT apb_slv_out_type;
                 -- AHB
                 ahbi            : IN  AHB_Mst_In_Type;
                 ahbo            : OUT AHB_Mst_Out_Type;
                 -- TIME
                 coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 data_shaping_BW : OUT STD_LOGIC
                 );
             END lpp_lfr;
             ARCHITECTURE beh OF lpp_lfr IS
               SIGNAL sample_s         : Samples(7 DOWNTO 0);
               --
               SIGNAL data_shaping_SP0 : STD_LOGIC;
               SIGNAL data_shaping_SP1 : STD_LOGIC;
               SIGNAL data_shaping_R0  : STD_LOGIC;
               SIGNAL data_shaping_R1  : STD_LOGIC;
               SIGNAL data_shaping_R2  : STD_LOGIC;
               --
               SIGNAL sample_f0_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               --
               SIGNAL sample_f0_val    : STD_LOGIC;
               SIGNAL sample_f1_val    : STD_LOGIC;
               SIGNAL sample_f2_val    : STD_LOGIC;
               SIGNAL sample_f3_val    : STD_LOGIC;
               --
               SIGNAL sample_f0_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f1_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f2_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               SIGNAL sample_f3_data   : STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
               --
               SIGNAL sample_f0_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_wdata  : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -- SM
               SIGNAL ready_matrix_f0          : STD_LOGIC;
-              SIGNAL ready_matrix_f0_1        : STD_LOGIC;
+            --  SIGNAL ready_matrix_f0_1        : STD_LOGIC;
               SIGNAL ready_matrix_f1          : STD_LOGIC;
               SIGNAL ready_matrix_f2          : STD_LOGIC;
               SIGNAL status_ready_matrix_f0   : STD_LOGIC;
-              SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
+            --  SIGNAL status_ready_matrix_f0_1 : STD_LOGIC;
               SIGNAL status_ready_matrix_f1   : STD_LOGIC;
               SIGNAL status_ready_matrix_f2   : STD_LOGIC;
               SIGNAL addr_matrix_f0           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f1           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL addr_matrix_f2           : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL length_matrix_f0         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f1         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL length_matrix_f2         : STD_LOGIC_VECTOR(25 DOWNTO 0);
               -- WFP
               SIGNAL status_new_err  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL delta_snapshot  : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f0_2      : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
               SIGNAL delta_f1        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL delta_f2        : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
               SIGNAL nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
               SIGNAL enable_f0         : STD_LOGIC;
               SIGNAL enable_f1         : STD_LOGIC;
               SIGNAL enable_f2         : STD_LOGIC;
               SIGNAL enable_f3         : STD_LOGIC;
               SIGNAL burst_f0          : STD_LOGIC;
               SIGNAL burst_f1          : STD_LOGIC;
               SIGNAL burst_f2          : STD_LOGIC;
               --SIGNAL run        : STD_LOGIC;
               SIGNAL start_date : STD_LOGIC_VECTOR(30 DOWNTO 0);
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
-              SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f0_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f0_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f0_data_out_valid_burst_s : STD_LOGIC;
               --f1
-              SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f1_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f1_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f1_data_out_valid_burst_s : STD_LOGIC;
               --f2
-              SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f2_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f2_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f2_data_out_valid_burst_s : STD_LOGIC;
               --f3
-              SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_f3_addr_out_s             : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
+            --  SIGNAL data_f3_data_out_valid_s       : STD_LOGIC;
-              SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
+            --  SIGNAL data_f3_data_out_valid_burst_s : STD_LOGIC;
               SIGNAL wfp_status_buffer_ready : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+              SIGNAL wfp_addr_buffer         : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               SIGNAL wfp_length_buffer       : STD_LOGIC_VECTOR(25 DOWNTO 0);
               SIGNAL wfp_ready_buffer        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wfp_buffer_time         : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL wfp_error_buffer_full   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA RR
               -----------------------------------------------------------------------------
-              SIGNAL dma_sel_valid   : STD_LOGIC;
+            --  SIGNAL dma_sel_valid   : STD_LOGIC;
-              SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_valid    : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_grant_s  : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_grant_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_rr_valid_ms : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
+            --  SIGNAL dma_rr_grant : STD_LOGIC_VECTOR(4 DOWNTO 0);
-              SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
+            --  SIGNAL dma_sel      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA_REG
               -----------------------------------------------------------------------------
-              SIGNAL ongoing_reg         : STD_LOGIC;
+            --  SIGNAL ongoing_reg         : STD_LOGIC;
-              SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
+            --  SIGNAL dma_sel_reg         : STD_LOGIC_VECTOR(3 DOWNTO 0);
-              SIGNAL dma_send_reg        : STD_LOGIC;
+            --  SIGNAL dma_send_reg        : STD_LOGIC;
-              SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
+            --  SIGNAL dma_valid_burst_reg : STD_LOGIC;  -- (1 => BURST , 0 => SINGLE)
-              SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_address_reg     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_data_reg        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- DMA
               -----------------------------------------------------------------------------
-              SIGNAL dma_send        : STD_LOGIC;
+            --  SIGNAL dma_send        : STD_LOGIC;
-              SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
+            --  SIGNAL dma_valid_burst : STD_LOGIC;   -- (1 => BURST , 0 => SINGLE)
-              SIGNAL dma_done        : STD_LOGIC;
+            --  SIGNAL dma_done        : STD_LOGIC;
-              SIGNAL dma_ren         : STD_LOGIC;
+            --  SIGNAL dma_ren         : STD_LOGIC;
-              SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_address     : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL dma_data_2      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- MS
               -----------------------------------------------------------------------------
-              SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_ms_addr        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL data_ms_data        : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_ms_valid       : STD_LOGIC;
+            --  SIGNAL data_ms_valid       : STD_LOGIC;
-              SIGNAL data_ms_valid_burst : STD_LOGIC;
+            --  SIGNAL data_ms_valid_burst : STD_LOGIC;
-              SIGNAL data_ms_ren         : STD_LOGIC;
+            --  SIGNAL data_ms_ren         : STD_LOGIC;
-              SIGNAL data_ms_done        : STD_LOGIC;
+            --  SIGNAL data_ms_done        : STD_LOGIC;
-              SIGNAL dma_ms_ongoing      : STD_LOGIC;
+            --  SIGNAL dma_ms_ongoing      : STD_LOGIC;
             --  SIGNAL run_ms              : STD_LOGIC;
-              SIGNAL ms_softandhard_rstn : STD_LOGIC;
+            --  SIGNAL ms_softandhard_rstn : STD_LOGIC;
               SIGNAL matrix_time_f0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
             --  SIGNAL matrix_time_f0_1    : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL error_buffer_full      : STD_LOGIC;
               SIGNAL error_input_fifo_write : STD_LOGIC_VECTOR(2 DOWNTO 0);
             --  SIGNAL debug_ms : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL debug_signal : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL dma_fifo_burst_valid : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_fifo_data        : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_fifo_ren         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_new       : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_addr      : STD_LOGIC_VECTOR(32*5-1 DOWNTO 0);
               SIGNAL dma_buffer_length    : STD_LOGIC_VECTOR(26*5-1 DOWNTO 0);
               SIGNAL dma_buffer_full      : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_buffer_full_err  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL dma_grant_error      : STD_LOGIC;
               -----------------------------------------------------------------------------
             --  SIGNAL run_dma : STD_LOGIC;
             BEGIN
               sample_s(4 DOWNTO 0) <= sample_E(4 DOWNTO 0);
               sample_s(7 DOWNTO 5) <= sample_B(2 DOWNTO 0);
               --all_channel : FOR i IN 7 DOWNTO 0 GENERATE
               --  sample_s(i) <= sample(i)(13) & sample(i)(13) & sample(i);
               --END GENERATE all_channel;
               -----------------------------------------------------------------------------
               lpp_lfr_filter_1 : lpp_lfr_filter
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   sample           => sample_s,
                   sample_val       => sample_val,
                   clk              => clk,
                   rstn             => rstn,
                   data_shaping_SP0 => data_shaping_SP0,
                   data_shaping_SP1 => data_shaping_SP1,
                   data_shaping_R0  => data_shaping_R0,
                   data_shaping_R1  => data_shaping_R1,
                   data_shaping_R2  => data_shaping_R2,
                   sample_f0_val    => sample_f0_val,
                   sample_f1_val    => sample_f1_val,
                   sample_f2_val    => sample_f2_val,
                   sample_f3_val    => sample_f3_val,
                   sample_f0_wdata  => sample_f0_data,
                   sample_f1_wdata  => sample_f1_data,
                   sample_f2_wdata  => sample_f2_data,
                   sample_f3_wdata  => sample_f3_data);
               -----------------------------------------------------------------------------
               lpp_lfr_apbreg_1 : lpp_lfr_apbreg
                 GENERIC MAP (
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
             --      nb_word_by_buffer_size => nb_word_by_buffer_size, -- TODO
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2,
                   pindex                 => pindex,
                   paddr                  => paddr,
                   pmask                  => pmask,
                   pirq_ms                => pirq_ms,
                   pirq_wfp               => pirq_wfp,
                   top_lfr_version        => top_lfr_version)
                 PORT MAP (
                   HCLK    => clk,
                   HRESETn => rstn,
                   apbi    => apbi,
                   apbo    => apbo,
                   run_ms => OPEN,--run_ms,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,       -- TODO
                   error_input_fifo_write => error_input_fifo_write,  -- TODO
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2,
                   addr_matrix_f0 => addr_matrix_f0,
                   addr_matrix_f1 => addr_matrix_f1,
                   addr_matrix_f2 => addr_matrix_f2,
                   length_matrix_f0  => length_matrix_f0,
                   length_matrix_f1  => length_matrix_f1,
                   length_matrix_f2  => length_matrix_f2,
                   -------------------------------------------------------------------------
                   --status_full       => status_full,       --      TODo
                   --status_full_ack   => status_full_ack,   --      TODo
                   --status_full_err   => status_full_err,   --      TODo
                   status_new_err    => status_new_err,
                   data_shaping_BW   => data_shaping_BW,
                   data_shaping_SP0  => data_shaping_SP0,
                   data_shaping_SP1  => data_shaping_SP1,
                   data_shaping_R0   => data_shaping_R0,
                   data_shaping_R1   => data_shaping_R1,
                   data_shaping_R2   => data_shaping_R2,
                   delta_snapshot    => delta_snapshot,
                   delta_f0          => delta_f0,
                   delta_f0_2        => delta_f0_2,
                   delta_f1          => delta_f1,
                   delta_f2          => delta_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
             --      nb_word_by_buffer => nb_word_by_buffer, -- TODO
                   nb_snapshot_param => nb_snapshot_param,
                   enable_f0         => enable_f0,
                   enable_f1         => enable_f1,
                   enable_f2         => enable_f2,
                   enable_f3         => enable_f3,
                   burst_f0          => burst_f0,
                   burst_f1          => burst_f1,
                   burst_f2          => burst_f2,
                   run               => OPEN, --run,
                   start_date        => start_date,
             --      debug_signal      => debug_signal,
                   wfp_status_buffer_ready => wfp_status_buffer_ready,-- TODO
                   wfp_addr_buffer         => wfp_addr_buffer,-- TODO
                   wfp_length_buffer       => wfp_length_buffer,-- TODO
                   wfp_ready_buffer        => wfp_ready_buffer,-- TODO
                   wfp_buffer_time         => wfp_buffer_time,-- TODO
                   wfp_error_buffer_full   => wfp_error_buffer_full -- TODO
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               lpp_waveform_1 : lpp_waveform
                 GENERIC MAP (
                   tech                   => inferred,
                   data_size              => 6*16,
                   nb_data_by_buffer_size => nb_data_by_buffer_size,
                   nb_snapshot_param_size => nb_snapshot_param_size,
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   reg_run            => '1',--run,
                   reg_start_date     => start_date,
                   reg_delta_snapshot => delta_snapshot,
                   reg_delta_f0       => delta_f0,
                   reg_delta_f0_2     => delta_f0_2,
                   reg_delta_f1       => delta_f1,
                   reg_delta_f2       => delta_f2,
                   enable_f0 => enable_f0,
                   enable_f1 => enable_f1,
                   enable_f2 => enable_f2,
                   enable_f3 => enable_f3,
                   burst_f0  => burst_f0,
                   burst_f1  => burst_f1,
                   burst_f2  => burst_f2,
                   nb_data_by_buffer => nb_data_by_buffer,
                   nb_snapshot_param => nb_snapshot_param,
                   status_new_err    => status_new_err,
                   status_buffer_ready => wfp_status_buffer_ready,
                   addr_buffer         => wfp_addr_buffer,
                   length_buffer       => wfp_length_buffer,
                   ready_buffer        => wfp_ready_buffer,
                   buffer_time         => wfp_buffer_time,
                   error_buffer_full   => wfp_error_buffer_full,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   --f0
                   data_f0_in_valid             => sample_f0_val,
                   data_f0_in                   => sample_f0_data,
                   --f1
                   data_f1_in_valid             => sample_f1_val,
                   data_f1_in                   => sample_f1_data,
                   --f2
                   data_f2_in_valid             => sample_f2_val,
                   data_f2_in                   => sample_f2_data,
                   --f3
                   data_f3_in_valid             => sample_f3_val,
                   data_f3_in                   => sample_f3_data,
                   -- OUTPUT -- DMA interface
                   dma_fifo_valid_burst => dma_fifo_burst_valid(3 DOWNTO 0),
                   dma_fifo_data        => dma_fifo_data(32*4-1 DOWNTO 0),
                   dma_fifo_ren         => dma_fifo_ren(3 DOWNTO 0),
                   dma_buffer_new       => dma_buffer_new(3 DOWNTO 0),
                   dma_buffer_addr      => dma_buffer_addr(32*4-1 DOWNTO 0),
                   dma_buffer_length    => dma_buffer_length(26*4-1 DOWNTO 0),
                   dma_buffer_full      => dma_buffer_full(3 DOWNTO 0),
                   dma_buffer_full_err  => dma_buffer_full_err(3 DOWNTO 0)
                   );
               -----------------------------------------------------------------------------
               -- Matrix Spectral
               -----------------------------------------------------------------------------
               sample_f0_wen <= NOT(sample_f0_val) & NOT(sample_f0_val) & NOT(sample_f0_val) &
                                NOT(sample_f0_val) & NOT(sample_f0_val);
               sample_f1_wen <= NOT(sample_f1_val) & NOT(sample_f1_val) & NOT(sample_f1_val) &
                                NOT(sample_f1_val) & NOT(sample_f1_val);
               sample_f2_wen <= NOT(sample_f2_val) & NOT(sample_f2_val) & NOT(sample_f2_val) &
                                NOT(sample_f2_val) & NOT(sample_f2_val);
               sample_f0_wdata <= sample_f0_data((3*16)-1 DOWNTO (1*16)) & sample_f0_data((6*16)-1 DOWNTO (3*16));  -- (MSB) E2 E1 B2 B1 B0 (LSB)
               sample_f1_wdata <= sample_f1_data((3*16)-1 DOWNTO (1*16)) & sample_f1_data((6*16)-1 DOWNTO (3*16));
               sample_f2_wdata <= sample_f2_data((3*16)-1 DOWNTO (1*16)) & sample_f2_data((6*16)-1 DOWNTO (3*16));
               -------------------------------------------------------------------------------
               --ms_softandhard_rstn <= rstn AND run_ms AND run;
               -----------------------------------------------------------------------------
               lpp_lfr_ms_1 : lpp_lfr_ms
                 GENERIC MAP (
                   Mem_use => Mem_use)
                 PORT MAP (
                   clk  => clk,
                   --rstn => ms_softandhard_rstn,      --rstn,
                   rstn => rstn,
                   run  => '1',--run_ms,
                   start_date => start_date,
                   coarse_time => coarse_time,
                   fine_time   => fine_time,
                   sample_f0_wen   => sample_f0_wen,
                   sample_f0_wdata => sample_f0_wdata,
                   sample_f1_wen   => sample_f1_wen,
                   sample_f1_wdata => sample_f1_wdata,
                   sample_f2_wen   => sample_f2_wen,
                   sample_f2_wdata => sample_f2_wdata,
                   --DMA
                   dma_fifo_burst_valid => dma_fifo_burst_valid(4),                  -- OUT
                   dma_fifo_data        => dma_fifo_data((4+1)*32-1 DOWNTO 4*32),    -- OUT
                   dma_fifo_ren         => dma_fifo_ren(4),                          -- IN
                   dma_buffer_new       => dma_buffer_new(4),                        -- OUT
                   dma_buffer_addr      => dma_buffer_addr((4+1)*32-1 DOWNTO 4*32),  -- OUT
                   dma_buffer_length    => dma_buffer_length((4+1)*26-1 DOWNTO 4*26),  -- OUT
                   dma_buffer_full      => dma_buffer_full(4),                       -- IN
                   dma_buffer_full_err  => dma_buffer_full_err(4),                   -- IN
                   --REG
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   error_buffer_full      => error_buffer_full,
                   error_input_fifo_write => error_input_fifo_write,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0 => length_matrix_f0,
                   length_matrix_f1 => length_matrix_f1,
                   length_matrix_f2 => length_matrix_f2,
                   matrix_time_f0 => matrix_time_f0,
                   matrix_time_f1 => matrix_time_f1,
                   matrix_time_f2 => matrix_time_f2);
               -----------------------------------------------------------------------------
               --run_dma <= run_ms OR run;
               DMA_SubSystem_1 : DMA_SubSystem
                 GENERIC MAP (
                   hindex => hindex)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   run  => '1',--run_dma,
                   ahbi => ahbi,
                   ahbo => ahbo,
                   fifo_burst_valid => dma_fifo_burst_valid,  --fifo_burst_valid,
                   fifo_data        => dma_fifo_data,         --fifo_data,
                   fifo_ren         => dma_fifo_ren,          --fifo_ren,
                   buffer_new      => dma_buffer_new,       --buffer_new,
                   buffer_addr     => dma_buffer_addr,      --buffer_addr,
                   buffer_length   => dma_buffer_length,    --buffer_length,
                   buffer_full     => dma_buffer_full,      --buffer_full,
                   buffer_full_err => dma_buffer_full_err,  --buffer_full_err,
                   grant_error     => dma_grant_error);     --grant_error);
             END beh;

lib/lpp/lpp_top_lfr/lpp_lfr_apbreg.vhd +14 -14

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             LIBRARY lpp;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.apb_devices_list.ALL;
             USE lpp.lpp_memory.ALL;
             USE lpp.lpp_lfr_apbreg_pkg.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_lfr_apbreg IS
               GENERIC (
                 nb_data_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 3;
                 pindex          : INTEGER                       := 4;
                 paddr           : INTEGER                       := 4;
                 pmask           : INTEGER                       := 16#fff#;
                 pirq_ms         : INTEGER                       := 0;
                 pirq_wfp        : INTEGER                       := 1;
                 top_lfr_version : STD_LOGIC_VECTOR(23 DOWNTO 0) := X"000000");
               PORT (
                 -- AMBA AHB system signals
                 HCLK    : IN STD_ULOGIC;
                 HRESETn : IN STD_ULOGIC;
                 -- AMBA APB Slave Interface
                 apbi : IN  apb_slv_in_type;
                 apbo : OUT apb_slv_out_type;
                 ---------------------------------------------------------------------------
                 -- Spectral Matrix Reg
                 run_ms          : OUT STD_LOGIC;
                 -- IN
                 ready_matrix_f0 : IN  STD_LOGIC;
                 ready_matrix_f1 : IN  STD_LOGIC;
                 ready_matrix_f2 : IN  STD_LOGIC;
             --    error_bad_component_error : IN STD_LOGIC;
                 error_buffer_full         : IN STD_LOGIC;                     --  TODO
                 error_input_fifo_write    : IN STD_LOGIC_VECTOR(2 DOWNTO 0);  --  TODO
             --    debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
                 -- OUT
                 status_ready_matrix_f0 : OUT STD_LOGIC;
                 status_ready_matrix_f1 : OUT STD_LOGIC;
                 status_ready_matrix_f2 : OUT STD_LOGIC;
                 --config_active_interruption_onNewMatrix : OUT STD_LOGIC;
                 --config_active_interruption_onError     : OUT STD_LOGIC;
                 addr_matrix_f0 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2 : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 length_matrix_f0 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                 length_matrix_f1 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                 length_matrix_f2 : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                 matrix_time_f0 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f1 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 matrix_time_f2 : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 ---------------------------------------------------------------------------
                 -- WaveForm picker Reg
                 --status_full     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 --status_full_err : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 -- OUT
                 data_shaping_BW  : OUT STD_LOGIC;
                 data_shaping_SP0 : OUT STD_LOGIC;
                 data_shaping_SP1 : OUT STD_LOGIC;
                 data_shaping_R0  : OUT STD_LOGIC;
                 data_shaping_R1  : OUT STD_LOGIC;
                 data_shaping_R2  : OUT STD_LOGIC;
                 delta_snapshot    : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0_2        : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 delta_f1          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f2          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 nb_data_by_buffer : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                 --nb_word_by_buffer : OUT STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 enable_f0 : OUT STD_LOGIC;
                 enable_f1 : OUT STD_LOGIC;
                 enable_f2 : OUT STD_LOGIC;
                 enable_f3 : OUT STD_LOGIC;
                 burst_f0 : OUT STD_LOGIC;
                 burst_f1 : OUT STD_LOGIC;
                 burst_f2 : OUT STD_LOGIC;
                 run : OUT STD_LOGIC;
                 start_date   : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                 wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-                wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                 wfp_ready_buffer        : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
                 wfp_buffer_time         : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                 wfp_error_buffer_full   : IN STD_LOGIC_VECTOR(3 DOWNTO 0)
                 );
             END lpp_lfr_apbreg;
             ARCHITECTURE beh OF lpp_lfr_apbreg IS
               CONSTANT REVISION : INTEGER := 1;
               CONSTANT pconfig : apb_config_type := (
 => ahb_device_reg (lpp.apb_devices_list.VENDOR_LPP, lpp.apb_devices_list.LPP_LFR, 0, REVISION, pirq_wfp),
 => apb_iobar(paddr, pmask));
               --CONSTANT pconfig : apb_config_type := (
               --  0 => ahb_device_reg (16#19#, 16#19#, 0, REVISION, pirq_wfp),
               --  1 => apb_iobar(paddr, pmask));
               TYPE lpp_SpectralMatrix_regs IS RECORD
                 config_active_interruption_onNewMatrix : STD_LOGIC;
                 config_active_interruption_onError     : STD_LOGIC;
                 config_ms_run                          : STD_LOGIC;
                 status_ready_matrix_f0_0               : STD_LOGIC;
                 status_ready_matrix_f1_0               : STD_LOGIC;
                 status_ready_matrix_f2_0               : STD_LOGIC;
                 status_ready_matrix_f0_1               : STD_LOGIC;
                 status_ready_matrix_f1_1               : STD_LOGIC;
                 status_ready_matrix_f2_1               : STD_LOGIC;
             --    status_error_bad_component_error       : STD_LOGIC;
                 status_error_buffer_full               : STD_LOGIC;
                 status_error_input_fifo_write          : STD_LOGIC_VECTOR(2 DOWNTO 0);
                 addr_matrix_f0_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f0_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f1_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2_0 : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 addr_matrix_f2_1 : STD_LOGIC_VECTOR(31 DOWNTO 0);
                 length_matrix : STD_LOGIC_VECTOR(25 DOWNTO 0);
                 time_matrix_f0_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f0_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f1_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f1_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f2_0 : STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_matrix_f2_1 : STD_LOGIC_VECTOR(47 DOWNTO 0);
               END RECORD;
               SIGNAL reg_sp : lpp_SpectralMatrix_regs;
               TYPE lpp_WaveformPicker_regs IS RECORD
             --    status_full       : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --    status_full_err   : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 status_new_err    : STD_LOGIC_VECTOR(3 DOWNTO 0);
                 data_shaping_BW   : STD_LOGIC;
                 data_shaping_SP0  : STD_LOGIC;
                 data_shaping_SP1  : STD_LOGIC;
                 data_shaping_R0   : STD_LOGIC;
                 data_shaping_R1   : STD_LOGIC;
                 data_shaping_R2   : STD_LOGIC;
                 delta_snapshot    : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0          : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f0_2        : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 delta_f1          : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 delta_f2          : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
             --    nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 enable_f0         : STD_LOGIC;
                 enable_f1         : STD_LOGIC;
                 enable_f2         : STD_LOGIC;
                 enable_f3         : STD_LOGIC;
                 burst_f0          : STD_LOGIC;
                 burst_f1          : STD_LOGIC;
                 burst_f2          : STD_LOGIC;
                 run               : STD_LOGIC;
                 status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0);
                 addr_buffer_f         : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0);
                 time_buffer_f         : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0);
                 length_buffer         : STD_LOGIC_VECTOR(25 DOWNTO 0);
                 error_buffer_full   :  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 start_date        : STD_LOGIC_VECTOR(30 DOWNTO 0);
               END RECORD;
               SIGNAL reg_wp : lpp_WaveformPicker_regs;
               SIGNAL prdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               CONSTANT IRQ_WFP_SIZE  : INTEGER := 12;
               SIGNAL   irq_wfp_ZERO  : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   irq_wfp_reg_s : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   irq_wfp_reg   : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   irq_wfp       : STD_LOGIC_VECTOR(IRQ_WFP_SIZE-1 DOWNTO 0);
               SIGNAL   ored_irq_wfp  : STD_LOGIC;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               SIGNAL reg0_ready_matrix_f0 : STD_LOGIC;
-              SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg0_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg0_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f0 : STD_LOGIC;
-              SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg1_addr_matrix_f0  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg1_matrix_time_f0  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg0_ready_matrix_f1 : STD_LOGIC;
-              SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg0_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg0_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f1 : STD_LOGIC;
-              SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg1_addr_matrix_f1  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg1_matrix_time_f1  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg0_ready_matrix_f2 : STD_LOGIC;
-              SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg0_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg0_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL reg1_ready_matrix_f2 : STD_LOGIC;
-              SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
+            --  SIGNAL reg1_addr_matrix_f2  : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
+            --  SIGNAL reg1_matrix_time_f2  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL apbo_irq_ms : STD_LOGIC;
               SIGNAL apbo_irq_wfp : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( 2*4-1 DOWNTO 0);
               SIGNAL pirq_temp  : STD_LOGIC_VECTOR(31 DOWNTO 0);
             BEGIN  -- beh
             --  status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0;
             --  status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1;
             --  status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2;
             --  config_active_interruption_onNewMatrix <= reg_sp.config_active_interruption_onNewMatrix;
             --  config_active_interruption_onError     <= reg_sp.config_active_interruption_onError;
             --  addr_matrix_f0                         <= reg_sp.addr_matrix_f0;
             --  addr_matrix_f1                         <= reg_sp.addr_matrix_f1;
             --  addr_matrix_f2                         <= reg_sp.addr_matrix_f2;
               data_shaping_BW  <= NOT reg_wp.data_shaping_BW;
               data_shaping_SP0 <= reg_wp.data_shaping_SP0;
               data_shaping_SP1 <= reg_wp.data_shaping_SP1;
               data_shaping_R0  <= reg_wp.data_shaping_R0;
               data_shaping_R1  <= reg_wp.data_shaping_R1;
               data_shaping_R2  <= reg_wp.data_shaping_R2;
               delta_snapshot    <= reg_wp.delta_snapshot;
               delta_f0          <= reg_wp.delta_f0;
               delta_f0_2        <= reg_wp.delta_f0_2;
               delta_f1          <= reg_wp.delta_f1;
               delta_f2          <= reg_wp.delta_f2;
               nb_data_by_buffer <= reg_wp.nb_data_by_buffer;
               nb_snapshot_param <= reg_wp.nb_snapshot_param;
               enable_f0 <= reg_wp.enable_f0;
               enable_f1 <= reg_wp.enable_f1;
               enable_f2 <= reg_wp.enable_f2;
               enable_f3 <= reg_wp.enable_f3;
               burst_f0 <= reg_wp.burst_f0;
               burst_f1 <= reg_wp.burst_f1;
               burst_f2 <= reg_wp.burst_f2;
               run <= reg_wp.run;
               --addr_data_f0 <= reg_wp.addr_data_f0;
               --addr_data_f1 <= reg_wp.addr_data_f1;
               --addr_data_f2 <= reg_wp.addr_data_f2;
               --addr_data_f3 <= reg_wp.addr_data_f3;
               start_date <= reg_wp.start_date;
               length_matrix_f0 <= reg_sp.length_matrix;
               length_matrix_f1 <= reg_sp.length_matrix;
               length_matrix_f2 <= reg_sp.length_matrix;
               wfp_length_buffer <= reg_wp.length_buffer;
               lpp_lfr_apbreg : PROCESS (HCLK, HRESETn)
                 VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2);
               BEGIN  -- PROCESS lpp_dma_top
                 IF HRESETn = '0' THEN               -- asynchronous reset (active low)
                   reg_sp.config_active_interruption_onNewMatrix <= '0';
                   reg_sp.config_active_interruption_onError     <= '0';
                   reg_sp.config_ms_run                          <= '0';
                   reg_sp.status_ready_matrix_f0_0               <= '0';
                   reg_sp.status_ready_matrix_f1_0               <= '0';
                   reg_sp.status_ready_matrix_f2_0               <= '0';
                   reg_sp.status_ready_matrix_f0_1               <= '0';
                   reg_sp.status_ready_matrix_f1_1               <= '0';
                   reg_sp.status_ready_matrix_f2_1               <= '0';
                   reg_sp.status_error_buffer_full               <= '0';
                   reg_sp.status_error_input_fifo_write          <= (OTHERS => '0');
                   reg_sp.addr_matrix_f0_0 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f1_0 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f2_0 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f0_1 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f1_1 <= (OTHERS => '0');
                   reg_sp.addr_matrix_f2_1 <= (OTHERS => '0');
                   reg_sp.length_matrix <= (OTHERS => '0');
             --      reg_sp.time_matrix_f0_0 <= (OTHERS => '0');  -- ok
             --      reg_sp.time_matrix_f1_0 <= (OTHERS => '0');  -- ok
             --      reg_sp.time_matrix_f2_0 <= (OTHERS => '0');  -- ok
             --      reg_sp.time_matrix_f0_1 <= (OTHERS => '0');  -- ok
                   --reg_sp.time_matrix_f1_1 <= (OTHERS => '0');  -- ok
             --      reg_sp.time_matrix_f2_1 <= (OTHERS => '0');  -- ok
                   prdata <= (OTHERS => '0');
                   apbo_irq_ms <= '0';
                   apbo_irq_wfp <= '0';
             --      status_full_ack <= (OTHERS => '0');
                   reg_wp.data_shaping_BW   <= '0';
                   reg_wp.data_shaping_SP0  <= '0';
                   reg_wp.data_shaping_SP1  <= '0';
                   reg_wp.data_shaping_R0   <= '0';
                   reg_wp.data_shaping_R1   <= '0';
                   reg_wp.data_shaping_R2   <= '0';
                   reg_wp.enable_f0         <= '0';
                   reg_wp.enable_f1         <= '0';
                   reg_wp.enable_f2         <= '0';
                   reg_wp.enable_f3         <= '0';
                   reg_wp.burst_f0          <= '0';
                   reg_wp.burst_f1          <= '0';
                   reg_wp.burst_f2          <= '0';
                   reg_wp.run               <= '0';
             --      reg_wp.status_full       <= (OTHERS => '0');
             --      reg_wp.status_full_err   <= (OTHERS => '0');
                   reg_wp.status_new_err    <= (OTHERS => '0');
                   reg_wp.error_buffer_full <= (OTHERS => '0');
                   reg_wp.delta_snapshot    <= (OTHERS => '0');
                   reg_wp.delta_f0          <= (OTHERS => '0');
                   reg_wp.delta_f0_2        <= (OTHERS => '0');
                   reg_wp.delta_f1          <= (OTHERS => '0');
                   reg_wp.delta_f2          <= (OTHERS => '0');
                   reg_wp.nb_data_by_buffer <= (OTHERS => '0');
                   reg_wp.nb_snapshot_param <= (OTHERS => '0');
                   reg_wp.start_date        <= (OTHERS => '1');
                   reg_wp.status_ready_buffer_f <= (OTHERS => '0');
                   reg_wp.length_buffer <= (OTHERS => '0');
                   pirq_temp <= (OTHERS => '0');
                   reg_wp.addr_buffer_f <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
             --      status_full_ack <= (OTHERS => '0');
                   reg_sp.status_ready_matrix_f0_0 <= reg_sp.status_ready_matrix_f0_0 OR reg0_ready_matrix_f0;
                   reg_sp.status_ready_matrix_f1_0 <= reg_sp.status_ready_matrix_f1_0 OR reg0_ready_matrix_f1;
                   reg_sp.status_ready_matrix_f2_0 <= reg_sp.status_ready_matrix_f2_0 OR reg0_ready_matrix_f2;
                   reg_sp.status_ready_matrix_f0_1 <= reg_sp.status_ready_matrix_f0_1 OR reg1_ready_matrix_f0;
                   reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1;
                   reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2;
                   all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP
                     reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I);
                   END LOOP all_status_ready_buffer_bit;
                   reg_sp.status_error_buffer_full         <= reg_sp.status_error_buffer_full OR error_buffer_full;
                   reg_sp.status_error_input_fifo_write(0) <= reg_sp.status_error_input_fifo_write(0) OR error_input_fifo_write(0);
                   reg_sp.status_error_input_fifo_write(1) <= reg_sp.status_error_input_fifo_write(1) OR error_input_fifo_write(1);
                   reg_sp.status_error_input_fifo_write(2) <= reg_sp.status_error_input_fifo_write(2) OR error_input_fifo_write(2);
                   all_status : FOR I IN 3 DOWNTO 0 LOOP
                     reg_wp.error_buffer_full(I) <=  reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I);
                     reg_wp.status_new_err(I)    <=  reg_wp.status_new_err(I) OR status_new_err(I);
                   END LOOP all_status;
                   paddr             := "000000";
                   paddr(7 DOWNTO 2) := apbi.paddr(7 DOWNTO 2);
                   prdata            <= (OTHERS => '0');
                   IF apbi.psel(pindex) = '1' THEN
                     -- APB DMA READ  --
                     CASE paddr(7 DOWNTO 2) IS
                       WHEN ADDR_LFR_SM_CONFIG =>
                         prdata(0) <= reg_sp.config_active_interruption_onNewMatrix;
                         prdata(1) <= reg_sp.config_active_interruption_onError;
                         prdata(2) <= reg_sp.config_ms_run;
                       WHEN ADDR_LFR_SM_STATUS =>
                         prdata(0) <= reg_sp.status_ready_matrix_f0_0;
                         prdata(1)  <= reg_sp.status_ready_matrix_f0_1;
                         prdata(2)  <= reg_sp.status_ready_matrix_f1_0;
                         prdata(3)  <= reg_sp.status_ready_matrix_f1_1;
                         prdata(4)  <= reg_sp.status_ready_matrix_f2_0;
                         prdata(5)  <= reg_sp.status_ready_matrix_f2_1;
                         -- prdata(6)  <= reg_sp.status_error_bad_component_error;
                         prdata(7)  <= reg_sp.status_error_buffer_full;
                         prdata(8)  <= reg_sp.status_error_input_fifo_write(0);
                         prdata(9)  <= reg_sp.status_error_input_fifo_write(1);
                         prdata(10) <= reg_sp.status_error_input_fifo_write(2);
                       WHEN ADDR_LFR_SM_F0_0_ADDR        => prdata              <= reg_sp.addr_matrix_f0_0;
                       WHEN ADDR_LFR_SM_F0_1_ADDR        => prdata              <= reg_sp.addr_matrix_f0_1;
                       WHEN ADDR_LFR_SM_F1_0_ADDR        => prdata              <= reg_sp.addr_matrix_f1_0;
                       WHEN ADDR_LFR_SM_F1_1_ADDR        => prdata              <= reg_sp.addr_matrix_f1_1;
                       WHEN ADDR_LFR_SM_F2_0_ADDR        => prdata              <= reg_sp.addr_matrix_f2_0;
                       WHEN ADDR_LFR_SM_F2_1_ADDR        => prdata              <= reg_sp.addr_matrix_f2_1;
                       WHEN ADDR_LFR_SM_F0_0_TIME_COARSE => prdata              <= reg_sp.time_matrix_f0_0(47 DOWNTO 16);
                       WHEN ADDR_LFR_SM_F0_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_0(15 DOWNTO 0);
                       WHEN ADDR_LFR_SM_F0_1_TIME_COARSE => prdata              <= reg_sp.time_matrix_f0_1(47 DOWNTO 16);
                       WHEN ADDR_LFR_SM_F0_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f0_1(15 DOWNTO 0);
                       WHEN ADDR_LFR_SM_F1_0_TIME_COARSE => prdata              <= reg_sp.time_matrix_f1_0(47 DOWNTO 16);
                       WHEN ADDR_LFR_SM_F1_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_0(15 DOWNTO 0);
                       WHEN ADDR_LFR_SM_F1_1_TIME_COARSE => prdata              <= reg_sp.time_matrix_f1_1(47 DOWNTO 16);
                       WHEN ADDR_LFR_SM_F1_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f1_1(15 DOWNTO 0);
                       WHEN ADDR_LFR_SM_F2_0_TIME_COARSE => prdata              <= reg_sp.time_matrix_f2_0(47 DOWNTO 16);
                       WHEN ADDR_LFR_SM_F2_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_0(15 DOWNTO 0);
                       WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata              <= reg_sp.time_matrix_f2_1(47 DOWNTO 16);
                       WHEN ADDR_LFR_SM_F2_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0);
                       WHEN ADDR_LFR_SM_LENGTH           => prdata(25 DOWNTO 0) <= reg_sp.length_matrix;
                       ---------------------------------------------------------------------
                       WHEN ADDR_LFR_WP_DATASHAPING =>
                         prdata(0) <= reg_wp.data_shaping_BW;
                         prdata(1) <= reg_wp.data_shaping_SP0;
                         prdata(2) <= reg_wp.data_shaping_SP1;
                         prdata(3) <= reg_wp.data_shaping_R0;
                         prdata(4) <= reg_wp.data_shaping_R1;
                         prdata(5) <= reg_wp.data_shaping_R2;
                       WHEN ADDR_LFR_WP_CONTROL =>
                         prdata(0) <= reg_wp.enable_f0;
                         prdata(1) <= reg_wp.enable_f1;
                         prdata(2) <= reg_wp.enable_f2;
                         prdata(3) <= reg_wp.enable_f3;
                         prdata(4) <= reg_wp.burst_f0;
                         prdata(5) <= reg_wp.burst_f1;
                         prdata(6) <= reg_wp.burst_f2;
                         prdata(7) <= reg_wp.run;
                       WHEN ADDR_LFR_WP_F0_0_ADDR => prdata             <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0);--0
                       WHEN ADDR_LFR_WP_F0_1_ADDR => prdata             <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1);
                       WHEN ADDR_LFR_WP_F1_0_ADDR => prdata             <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2);--1
                       WHEN ADDR_LFR_WP_F1_1_ADDR => prdata             <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3);
                       WHEN ADDR_LFR_WP_F2_0_ADDR => prdata             <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4);--2
                       WHEN ADDR_LFR_WP_F2_1_ADDR => prdata             <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5);
                       WHEN ADDR_LFR_WP_F3_0_ADDR => prdata             <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6);--3
                       WHEN ADDR_LFR_WP_F3_1_ADDR => prdata             <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7);
                       WHEN ADDR_LFR_WP_STATUS =>
                         prdata(7  DOWNTO  0) <= reg_wp.status_ready_buffer_f;
                         prdata(11 DOWNTO  8) <= reg_wp.error_buffer_full;
                         prdata(15 DOWNTO 12) <= reg_wp.status_new_err;
                       WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_snapshot;
                       WHEN ADDR_LFR_WP_DELTA_F0      => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_f0;
                       WHEN ADDR_LFR_WP_DELTA_F0_2    => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2;
                       WHEN ADDR_LFR_WP_DELTA_F1      => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_f1;
                       WHEN ADDR_LFR_WP_DELTA_F2      => prdata(delta_vector_size-1 DOWNTO 0)      <= reg_wp.delta_f2;
                       WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer;
                       WHEN ADDR_LFR_WP_NBSNAPSHOT     => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param;
                       WHEN ADDR_LFR_WP_START_DATE     => prdata(30 DOWNTO 0)                       <= reg_wp.start_date;
                       WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0);
                       WHEN ADDR_LFR_WP_F0_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32);
                       WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1);
                       WHEN ADDR_LFR_WP_F0_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32);
                       WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2);
                       WHEN ADDR_LFR_WP_F1_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32);
                       WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3);
                       WHEN ADDR_LFR_WP_F1_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32);
                       WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4);
                       WHEN ADDR_LFR_WP_F2_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32);
                       WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5);
                       WHEN ADDR_LFR_WP_F2_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32);
                       WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6);
                       WHEN ADDR_LFR_WP_F3_0_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32);
                       WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7);
                       WHEN ADDR_LFR_WP_F3_1_TIME_FINE   => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32);
                       WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer;
                       ---------------------------------------------------------------------
                       WHEN ADDR_LFR_VERSION   => prdata(23 DOWNTO 0)                       <= top_lfr_version(23 DOWNTO 0);
                       WHEN OTHERS   => NULL;
                     END CASE;
                     IF (apbi.pwrite AND apbi.penable) = '1' THEN
                       -- APB DMA WRITE --
                       CASE paddr(7 DOWNTO 2) IS
                         --
                         WHEN ADDR_LFR_SM_CONFIG =>
                           reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0);
                           reg_sp.config_active_interruption_onError     <= apbi.pwdata(1);
                           reg_sp.config_ms_run                          <= apbi.pwdata(2);
                         WHEN ADDR_LFR_SM_STATUS =>
                           reg_sp.status_ready_matrix_f0_0         <= ((NOT apbi.pwdata(0) ) AND reg_sp.status_ready_matrix_f0_0        ) OR reg0_ready_matrix_f0;
                           reg_sp.status_ready_matrix_f0_1         <= ((NOT apbi.pwdata(1) ) AND reg_sp.status_ready_matrix_f0_1        ) OR reg1_ready_matrix_f0;
                           reg_sp.status_ready_matrix_f1_0         <= ((NOT apbi.pwdata(2) ) AND reg_sp.status_ready_matrix_f1_0        ) OR reg0_ready_matrix_f1;
                           reg_sp.status_ready_matrix_f1_1         <= ((NOT apbi.pwdata(3) ) AND reg_sp.status_ready_matrix_f1_1        ) OR reg1_ready_matrix_f1;
                           reg_sp.status_ready_matrix_f2_0         <= ((NOT apbi.pwdata(4) ) AND reg_sp.status_ready_matrix_f2_0        ) OR reg0_ready_matrix_f2;
                           reg_sp.status_ready_matrix_f2_1         <= ((NOT apbi.pwdata(5) ) AND reg_sp.status_ready_matrix_f2_1        ) OR reg1_ready_matrix_f2;
                           reg_sp.status_error_buffer_full         <= ((NOT apbi.pwdata(7) ) AND reg_sp.status_error_buffer_full        ) OR error_buffer_full;
                           reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) ) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0);
                           reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) ) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1);
                           reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2);
                         WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata;
                         WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata;
                         WHEN ADDR_LFR_SM_F1_0_ADDR => reg_sp.addr_matrix_f1_0 <= apbi.pwdata;
                         WHEN ADDR_LFR_SM_F1_1_ADDR => reg_sp.addr_matrix_f1_1 <= apbi.pwdata;
                         WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata;
                         WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata;
                         WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <=  apbi.pwdata(25 DOWNTO 0);
                         ---------------------------------------------------------------------
                         WHEN ADDR_LFR_WP_DATASHAPING =>
                           reg_wp.data_shaping_BW  <= apbi.pwdata(0);
                           reg_wp.data_shaping_SP0 <= apbi.pwdata(1);
                           reg_wp.data_shaping_SP1 <= apbi.pwdata(2);
                           reg_wp.data_shaping_R0  <= apbi.pwdata(3);
                           reg_wp.data_shaping_R1  <= apbi.pwdata(4);
                           reg_wp.data_shaping_R2  <= apbi.pwdata(5);
                         WHEN  ADDR_LFR_WP_CONTROL =>
                           reg_wp.enable_f0 <= apbi.pwdata(0);
                           reg_wp.enable_f1 <= apbi.pwdata(1);
                           reg_wp.enable_f2 <= apbi.pwdata(2);
                           reg_wp.enable_f3 <= apbi.pwdata(3);
                           reg_wp.burst_f0  <= apbi.pwdata(4);
                           reg_wp.burst_f1  <= apbi.pwdata(5);
                           reg_wp.burst_f2  <= apbi.pwdata(6);
                           reg_wp.run       <= apbi.pwdata(7);
                         WHEN ADDR_LFR_WP_F0_0_ADDR => reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F0_1_ADDR => reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F1_0_ADDR => reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F1_1_ADDR => reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F2_0_ADDR => reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata;
                         WHEN ADDR_LFR_WP_STATUS =>
                           all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP
                             reg_wp.status_ready_buffer_f(I*2)   <= ((NOT apbi.pwdata(I*2)  ) AND reg_wp.status_ready_buffer_f(I*2)  ) OR reg_ready_buffer_f(I*2);
                             reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1);
                             reg_wp.error_buffer_full(I)         <= ((NOT apbi.pwdata(I+8)  ) AND reg_wp.error_buffer_full(I)        ) OR wfp_error_buffer_full(I);
                             reg_wp.status_new_err(I)            <= ((NOT apbi.pwdata(I+12) ) AND reg_wp.status_new_err(I)           ) OR status_new_err(I);
                           END LOOP all_reg_wp_status_bit;
                         WHEN ADDR_LFR_WP_DELTASNAPSHOT  => reg_wp.delta_snapshot    <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_DELTA_F0       => reg_wp.delta_f0          <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_DELTA_F0_2     => reg_wp.delta_f0_2        <= apbi.pwdata(delta_vector_size_f0_2-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_DELTA_F1       => reg_wp.delta_f1          <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_DELTA_F2       => reg_wp.delta_f2          <= apbi.pwdata(delta_vector_size-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_NBSNAPSHOT     => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0);
                         WHEN ADDR_LFR_WP_START_DATE     => reg_wp.start_date        <= apbi.pwdata(30 DOWNTO 0);
                         WHEN ADDR_LFR_WP_LENGTH         => reg_wp.length_buffer    <=  apbi.pwdata(25 DOWNTO 0);
                         WHEN OTHERS   => NULL;
                       END CASE;
                     END IF;
                   END IF;
                   --apbo.pirq(pirq_ms) <=
                   pirq_temp( pirq_ms) <= apbo_irq_ms;
                   pirq_temp(pirq_wfp) <= apbo_irq_wfp;
                   apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR
                                                                                              ready_matrix_f1 OR
                                                                                              ready_matrix_f2)
                                           )
                                          OR
                                          (reg_sp.config_active_interruption_onError AND (
             --                               error_bad_component_error OR
                                            error_buffer_full
                                            OR error_input_fifo_write(0)
                                            OR error_input_fifo_write(1)
                                            OR error_input_fifo_write(2))
                                           ));
                   -- apbo.pirq(pirq_wfp)
                   apbo_irq_wfp<= ored_irq_wfp;
                 END IF;
               END PROCESS lpp_lfr_apbreg;
               apbo.pirq <= pirq_temp;
               --all_irq: FOR I IN 31 DOWNTO 0 GENERATE
               --  IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE
               --    apbo.pirq(I)  <= apbo_irq_ms;
               --  END GENERATE IRQ_is_PIRQ_MS;
               --  IRQ_is_PIRQ_WFP: IF I = pirq_wfp GENERATE
               --    apbo.pirq(I) <= apbo_irq_wfp;
               --  END GENERATE IRQ_is_PIRQ_WFP;
               --  IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE
               --    apbo.pirq(I) <= '0';
               --  END GENERATE IRQ_OTHERS;
               --END GENERATE all_irq;
               apbo.pindex  <= pindex;
               apbo.pconfig <= pconfig;
               apbo.prdata  <= prdata;
               -----------------------------------------------------------------------------
               -- IRQ
               -----------------------------------------------------------------------------
               irq_wfp_reg_s <= wfp_ready_buffer & wfp_error_buffer_full & status_new_err;
               PROCESS (HCLK, HRESETn)
               BEGIN  -- PROCESS
                 IF HRESETn = '0' THEN                 -- asynchronous reset (active low)
                   irq_wfp_reg <= (OTHERS => '0');
                 ELSIF HCLK'EVENT AND HCLK = '1' THEN  -- rising clock edge
                   irq_wfp_reg <= irq_wfp_reg_s;
                 END IF;
               END PROCESS;
               all_irq_wfp : FOR I IN IRQ_WFP_SIZE-1 DOWNTO 0 GENERATE
                 irq_wfp(I) <= (NOT irq_wfp_reg(I)) AND irq_wfp_reg_s(I);
               END GENERATE all_irq_wfp;
               irq_wfp_ZERO <= (OTHERS => '0');
               ored_irq_wfp <= '0' WHEN irq_wfp = irq_wfp_ZERO ELSE '1';
               run_ms <= reg_sp.config_ms_run;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               lpp_apbreg_ms_pointer_f0 : lpp_apbreg_ms_pointer
                 PORT MAP (
                   clk  => HCLK,
                   rstn => HRESETn,
                   run  => '1',--reg_sp.config_ms_run,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f0,
                   reg0_addr_matrix         => reg_sp.addr_matrix_f0_0,  --reg0_addr_matrix_f0,
                   reg0_matrix_time         => reg_sp.time_matrix_f0_0,  --reg0_matrix_time_f0,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f0_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f0,
                   reg1_addr_matrix         => reg_sp.addr_matrix_f0_1,  --reg1_addr_matrix_f0,
                   reg1_matrix_time         => reg_sp.time_matrix_f0_1,  --reg1_matrix_time_f0,
                   ready_matrix        => ready_matrix_f0,
                   status_ready_matrix => status_ready_matrix_f0,
                   addr_matrix         => addr_matrix_f0,
                   matrix_time         => matrix_time_f0);
               lpp_apbreg_ms_pointer_f1 : lpp_apbreg_ms_pointer
                 PORT MAP (
                   clk  => HCLK,
                   rstn => HRESETn,
                   run  => '1',--reg_sp.config_ms_run,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f1,
                   reg0_addr_matrix         => reg_sp.addr_matrix_f1_0,  --reg0_addr_matrix_f1,
                   reg0_matrix_time         => reg_sp.time_matrix_f1_0,  --reg0_matrix_time_f1,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f1_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f1,
                   reg1_addr_matrix         => reg_sp.addr_matrix_f1_1,  --reg1_addr_matrix_f1,
                   reg1_matrix_time         => reg_sp.time_matrix_f1_1,  --reg1_matrix_time_f1,
                   ready_matrix        => ready_matrix_f1,
                   status_ready_matrix => status_ready_matrix_f1,
                   addr_matrix         => addr_matrix_f1,
                   matrix_time         => matrix_time_f1);
               lpp_apbreg_ms_pointer_f2 : lpp_apbreg_ms_pointer
                 PORT MAP (
                   clk  => HCLK,
                   rstn => HRESETn,
                   run  => '1',--reg_sp.config_ms_run,
                   reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0,
                   reg0_ready_matrix        => reg0_ready_matrix_f2,
                   reg0_addr_matrix         => reg_sp.addr_matrix_f2_0,  --reg0_addr_matrix_f2,
                   reg0_matrix_time         => reg_sp.time_matrix_f2_0,  --reg0_matrix_time_f2,
                   reg1_status_ready_matrix => reg_sp.status_ready_matrix_f2_1,
                   reg1_ready_matrix        => reg1_ready_matrix_f2,
                   reg1_addr_matrix         => reg_sp.addr_matrix_f2_1,  --reg1_addr_matrix_f2,
                   reg1_matrix_time         => reg_sp.time_matrix_f2_1,  --reg1_matrix_time_f2,
                   ready_matrix        => ready_matrix_f2,
                   status_ready_matrix => status_ready_matrix_f2,
                   addr_matrix         => addr_matrix_f2,
                   matrix_time         => matrix_time_f2);
               -----------------------------------------------------------------------------
               all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE
                 lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer
                   PORT MAP (
                     clk  => HCLK,
                     rstn => HRESETn,
                     run  => '1',--reg_wp.run,
                     reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I),
                     reg0_ready_matrix        => reg_ready_buffer_f(2*I),
                     reg0_addr_matrix         => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32),
                     reg0_matrix_time         => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48),
                     reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1),
                     reg1_ready_matrix        => reg_ready_buffer_f(2*I+1),
                     reg1_addr_matrix         => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32),
                     reg1_matrix_time         => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48),
                     ready_matrix        => wfp_ready_buffer(I),
                     status_ready_matrix => wfp_status_buffer_ready(I),
                     addr_matrix         => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32),
                     matrix_time         => wfp_buffer_time((I+1)*48-1 DOWNTO I*48)
                     );
               END GENERATE all_wfp_pointer;
               -----------------------------------------------------------------------------
             END beh;
-            -------------------------------------------------------------------------------
+            -------------------------------------------------------------------------------
  No newline at end of file

lib/lpp/lpp_top_lfr/lpp_lfr_ms.vhd +53 -20

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_memory.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.spectral_matrix_package.ALL;
             USE lpp.lpp_dma_pkg.ALL;
             USE lpp.lpp_Header.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_matrix.ALL;
             USE lpp.lpp_lfr_pkg.ALL;
             USE lpp.lpp_fft.ALL;
             USE lpp.fft_components.ALL;
             ENTITY lpp_lfr_ms IS
               GENERIC (
                 Mem_use : INTEGER := use_RAM
                 );
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 run  : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 -- DATA INPUT
                 ---------------------------------------------------------------------------
                 start_date      : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 -- TIME
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA
                 ---------------------------------------------------------------------------
                 dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
                 dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
                 dma_buffer_new      : OUT STD_LOGIC;                      --TODOx
                 dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
                 dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
                 dma_buffer_full     : IN  STD_LOGIC;                      --TODO
                 dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
                 -- Reg out
                 ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
                 ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
             --    error_bad_component_error : OUT STD_LOGIC;                  -- TODO
                 error_buffer_full         : OUT STD_LOGIC;                  -- TODO
                 error_input_fifo_write    : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 -- Reg In
                 status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
                 status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
                 addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
                 length_matrix_f0                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f1                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 length_matrix_f2                         : IN STD_LOGIC_VECTOR(25 DOWNTO 0); -- TODO
                 matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
                 matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)  -- TODO
                 );
             END;
             ARCHITECTURE Behavioral OF lpp_lfr_ms IS
               SIGNAL sample_f0_A_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_A_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_A_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f0_B_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f0_B_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f1_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_almost_full : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_f2_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL error_wen_f0 : STD_LOGIC;
               SIGNAL error_wen_f1 : STD_LOGIC;
               SIGNAL error_wen_f2 : STD_LOGIC;
               SIGNAL one_sample_f1_full : STD_LOGIC;
               SIGNAL one_sample_f1_wen  : STD_LOGIC;
               SIGNAL one_sample_f2_full : STD_LOGIC;
               SIGNAL one_sample_f2_wen  : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- FSM / SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               TYPE   fsm_select_channel IS (IDLE, SWITCH_F0_A, SWITCH_F0_B, SWITCH_F1, SWITCH_F2);
               SIGNAL state_fsm_select_channel     : fsm_select_channel;
-              SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
+            --  SIGNAL pre_state_fsm_select_channel : fsm_select_channel;
+              SIGNAL select_channel     : STD_LOGIC_VECTOR(1 DOWNTO 0);
+              SIGNAL select_channel_reg : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL sample_rdata : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               SIGNAL sample_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               TYPE   fsm_load_FFT IS (IDLE, FIFO_1, FIFO_2, FIFO_3, FIFO_4, FIFO_5);
               SIGNAL state_fsm_load_FFT      : fsm_load_FFT;
-              SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
+            --  SIGNAL next_state_fsm_load_FFT : fsm_load_FFT;
+              SIGNAL select_fifo     : STD_LOGIC_VECTOR(2 DOWNTO 0);
+              SIGNAL select_fifo_reg : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_ren_s   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_load    : STD_LOGIC;
               SIGNAL sample_valid   : STD_LOGIC;
               SIGNAL sample_valid_r : STD_LOGIC;
               SIGNAL sample_data    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               SIGNAL fft_read                 : STD_LOGIC;
               SIGNAL fft_pong                 : STD_LOGIC;
               SIGNAL fft_data_im              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_re              : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL fft_data_valid           : STD_LOGIC;
               SIGNAL fft_ready                : STD_LOGIC;
               -----------------------------------------------------------------------------
             --  SIGNAL fft_linker_ReUse    : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE   fsm_load_MS_memory IS (IDLE, LOAD_FIFO, TRASH_FFT);
               SIGNAL state_fsm_load_MS_memory : fsm_load_MS_memory;
               SIGNAL current_fifo_load        : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL current_fifo_empty       : STD_LOGIC;
               SIGNAL current_fifo_locked      : STD_LOGIC;
               SIGNAL current_fifo_full        : STD_LOGIC;
               SIGNAL MEM_IN_SM_locked         : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL MEM_IN_SM_ReUse : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_ren   : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_wData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_rData : STD_LOGIC_VECTOR(16*2*5-1 DOWNTO 0);
               SIGNAL MEM_IN_SM_Full  : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL MEM_IN_SM_Empty : STD_LOGIC_VECTOR(4 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL SM_in_data      : STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
               SIGNAL SM_in_ren       : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_in_empty     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL SM_correlation_start     : STD_LOGIC;
               SIGNAL SM_correlation_auto      : STD_LOGIC;
               SIGNAL SM_correlation_done      : STD_LOGIC;
               SIGNAL SM_correlation_done_reg1 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg2 : STD_LOGIC;
               SIGNAL SM_correlation_done_reg3 : STD_LOGIC;
               SIGNAL SM_correlation_begin     : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Full_s    : STD_LOGIC;
               SIGNAL MEM_OUT_SM_Data_in_s : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Write_s   : STD_LOGIC;
               SIGNAL current_matrix_write      : STD_LOGIC;
               SIGNAL current_matrix_wait_empty : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fifo_0_ready              : STD_LOGIC;
               SIGNAL fifo_1_ready              : STD_LOGIC;
               SIGNAL fifo_ongoing              : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_ren    : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_empty_threshold  : STD_LOGIC;
               SIGNAL FSM_DMA_fifo_data   : STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 0);
+              SIGNAL FSM_DMA_fifo_status : STD_LOGIC_VECTOR(53 DOWNTO 4);
               -----------------------------------------------------------------------------
               SIGNAL MEM_OUT_SM_Write    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Read     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_in  : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Data_out : STD_LOGIC_VECTOR(63 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Full     : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL MEM_OUT_SM_Empty_Threshold    : STD_LOGIC_VECTOR(1 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- TIME REG & INFOs
               -----------------------------------------------------------------------------
               SIGNAL all_time : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL f_empty       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL f_empty_reg   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_update_f : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_reg_f    : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
               SIGNAL time_reg_f0_A : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f0_B : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f1   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg_f2   : STD_LOGIC_VECTOR(47 DOWNTO 0);
               --SIGNAL time_update_f0_A : STD_LOGIC;
               --SIGNAL time_update_f0_B : STD_LOGIC;
               --SIGNAL time_update_f1   : STD_LOGIC;
               --SIGNAL time_update_f2   : STD_LOGIC;
               --
               SIGNAL status_channel   : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_MS_input  : STD_LOGIC_VECTOR(49 DOWNTO 0);
               SIGNAL status_component : STD_LOGIC_VECTOR(53 DOWNTO 0);
-              SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 0);
+              SIGNAL status_component_fifo_0     : STD_LOGIC_VECTOR(53 DOWNTO 4);
-              SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 0);
+              SIGNAL status_component_fifo_1     : STD_LOGIC_VECTOR(53 DOWNTO 4);
               SIGNAL status_component_fifo_0_end : STD_LOGIC;
               SIGNAL status_component_fifo_1_end : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL fft_ongoing_counter : STD_LOGIC;--_VECTOR(1 DOWNTO 0);
               SIGNAL fft_ready_reg         : STD_LOGIC;
               SIGNAL fft_ready_rising_down : STD_LOGIC;
               SIGNAL sample_load_reg         : STD_LOGIC;
               SIGNAL sample_load_rising_down : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_f1_wen_head     : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_head_in  : STD_LOGIC;
               SIGNAL sample_f1_wen_head_out : STD_LOGIC;
               SIGNAL sample_f1_full_head_in : STD_LOGIC;
               SIGNAL sample_f1_full_head_out : STD_LOGIC;
               SIGNAL sample_f1_empty_head_in : STD_LOGIC;
               SIGNAL sample_f1_wdata_head   : STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_f0_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f1_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL sample_f2_wen_s : STD_LOGIC_VECTOR(4 DOWNTO 0);
               SIGNAL ongoing : STD_LOGIC;
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_f0_wen_s <= (OTHERS => '1');
                   sample_f1_wen_s <= (OTHERS => '1');
                   sample_f2_wen_s <= (OTHERS => '1');
                   ongoing <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF ongoing = '1' THEN
                     sample_f0_wen_s <= sample_f0_wen;
                     sample_f1_wen_s <= sample_f1_wen;
                     sample_f2_wen_s <= sample_f2_wen;
                   ELSE
                     IF start_date = coarse_time(30 DOWNTO 0) THEN
                       ongoing <= '1';
                     END IF;
                     sample_f0_wen_s <= (OTHERS => '1');
                     sample_f1_wen_s <= (OTHERS => '1');
                     sample_f2_wen_s <= (OTHERS => '1');
                   END IF;
                 END IF;
               END PROCESS;
               error_input_fifo_write <= error_wen_f2 & error_wen_f1 & error_wen_f0;
               switch_f0_inst : spectral_matrix_switch_f0
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   sample_wen => sample_f0_wen_s,
                   fifo_A_empty => sample_f0_A_empty,
                   fifo_A_full  => sample_f0_A_full,
                   fifo_A_wen   => sample_f0_A_wen,
                   fifo_B_empty => sample_f0_B_empty,
                   fifo_B_full  => sample_f0_B_full,
                   fifo_B_wen   => sample_f0_B_wen,
                   error_wen => error_wen_f0);       -- TODO
               -----------------------------------------------------------------------------
               -- FIFO IN
               -----------------------------------------------------------------------------
               lppFIFOxN_f0_a : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen   => sample_f0_A_wen,
                   wdata => sample_f0_wdata,
                   ren   => sample_f0_A_ren,
                   rdata => sample_f0_A_rdata,
                   empty       => sample_f0_A_empty,
                   full        => sample_f0_A_full,
                   almost_full => OPEN);
               lppFIFOxN_f0_b : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f0_B_wen,
                   wdata       => sample_f0_wdata,
                   ren         => sample_f0_B_ren,
                   rdata       => sample_f0_B_rdata,
                   empty       => sample_f0_B_empty,
                   full        => sample_f0_B_full,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               -- sample_f1_wen   in
               -- sample_f1_wdata in
               -- sample_f1_full  OUT
               sample_f1_wen_head_in   <= '0' WHEN sample_f1_wen_s   = "00000" ELSE '1';
               sample_f1_full_head_in  <= '0' WHEN sample_f1_full  = "00000" ELSE '1';
               sample_f1_empty_head_in <= '1' WHEN sample_f1_empty = "11111" ELSE '0';
               lpp_lfr_ms_reg_head_1:lpp_lfr_ms_reg_head
                 PORT MAP (
                   clk      => clk,
                   rstn     => rstn,
                   in_wen   => sample_f1_wen_head_in,
                   in_data  => sample_f1_wdata,
                   in_full  => sample_f1_full_head_in,
                   in_empty => sample_f1_empty_head_in,
                   out_wen  => sample_f1_wen_head_out,
                   out_data => sample_f1_wdata_head,
                   out_full => sample_f1_full_head_out);
               sample_f1_wen_head    <= sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out & sample_f1_wen_head_out;
               lppFIFOxN_f1 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f1_wen_head,
                   wdata       => sample_f1_wdata_head,
                   ren         => sample_f1_ren,
                   rdata       => sample_f1_rdata,
                   empty       => sample_f1_empty,
                   full        => sample_f1_full,
                   almost_full => sample_f1_almost_full);
               one_sample_f1_wen <= '0' WHEN sample_f1_wen_s = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f1_full <= '0';
                   error_wen_f1       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f1_full_head_out = '0' THEN
                     one_sample_f1_full <= '0';
                   ELSE
                     one_sample_f1_full <= '1';
                   END IF;
                   error_wen_f1 <= one_sample_f1_wen AND one_sample_f1_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               lppFIFOxN_f2 : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 16,
                   Addr_sz => 8,
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => (OTHERS => '0'),
                   run   => (OTHERS => '1'),
                   wen         => sample_f2_wen,
                   wdata       => sample_f2_wdata,
                   ren         => sample_f2_ren,
                   rdata       => sample_f2_rdata,
                   empty       => sample_f2_empty,
                   full        => sample_f2_full,
                   almost_full => OPEN);
               one_sample_f2_wen <= '0' WHEN sample_f2_wen_s = "11111" ELSE '1';
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   one_sample_f2_full <= '0';
                   error_wen_f2       <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   IF sample_f2_full = "00000" THEN
                     one_sample_f2_full <= '0';
                   ELSE
                     one_sample_f2_full <= '1';
                   END IF;
                   error_wen_f2 <= one_sample_f2_wen AND one_sample_f2_full;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- FSM SELECT CHANNEL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_select_channel <= IDLE;
+                  select_channel <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_select_channel IS
                     WHEN IDLE =>
                       IF sample_f1_full = "11111" THEN
                         state_fsm_select_channel <= SWITCH_F1;
+                        select_channel <= "10";
                       ELSIF sample_f1_almost_full = "00000" THEN
                         IF sample_f0_A_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_A;
+                          select_channel <= "00";
                         ELSIF sample_f0_B_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F0_B;
+                          select_channel <= "01";
                         ELSIF sample_f2_full = "11111" THEN
                           state_fsm_select_channel <= SWITCH_F2;
+                          select_channel <= "11";
                         END IF;
                       END IF;
                     WHEN SWITCH_F0_A =>
                       IF sample_f0_A_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F0_B =>
                       IF sample_f0_B_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F1 =>
                       IF sample_f1_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN SWITCH_F2 =>
                       IF sample_f2_empty = "11111" THEN
                         state_fsm_select_channel <= IDLE;
+                        select_channel <= (OTHERS => '0');
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
-                  pre_state_fsm_select_channel <= IDLE;
+                  select_channel_reg <= (OTHERS => '0');
+                  --pre_state_fsm_select_channel <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
-                  pre_state_fsm_select_channel <= state_fsm_select_channel;
+                  select_channel_reg <= select_channel;
+                  --pre_state_fsm_select_channel <= state_fsm_select_channel;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SWITCH SELECT CHANNEL
               -----------------------------------------------------------------------------
               sample_empty <= sample_f0_A_empty WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                               sample_f0_B_empty WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                               sample_f1_empty   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                               sample_f2_empty   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                               (OTHERS => '1');
               sample_full <= sample_f0_A_full WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                              sample_f0_B_full WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                              sample_f1_full   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                              sample_f2_full   WHEN state_fsm_select_channel = SWITCH_F2   ELSE
                              (OTHERS => '0');
-              sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
+              --sample_rdata <= sample_f0_A_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_A ELSE
-                              sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
+              --                sample_f0_B_rdata WHEN pre_state_fsm_select_channel = SWITCH_F0_B ELSE
-                              sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
+              --                sample_f1_rdata   WHEN pre_state_fsm_select_channel = SWITCH_F1   ELSE
+              --                sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
+              sample_rdata <= sample_f0_A_rdata WHEN select_channel_reg = "00" ELSE
+                              sample_f0_B_rdata WHEN select_channel_reg = "01" ELSE
+                              sample_f1_rdata   WHEN select_channel_reg = "10"   ELSE
                               sample_f2_rdata;  -- WHEN state_fsm_select_channel = SWITCH_F2   ELSE
               sample_f0_A_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_A ELSE (OTHERS => '1');
               sample_f0_B_ren <= sample_ren WHEN state_fsm_select_channel = SWITCH_F0_B ELSE (OTHERS => '1');
               sample_f1_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F1   ELSE (OTHERS => '1');
               sample_f2_ren   <= sample_ren WHEN state_fsm_select_channel = SWITCH_F2   ELSE (OTHERS => '1');
               status_channel <= time_reg_f0_A & "00" WHEN state_fsm_select_channel = SWITCH_F0_A ELSE
                                 time_reg_f0_B & "00" WHEN state_fsm_select_channel = SWITCH_F0_B ELSE
                                 time_reg_f1 & "01"   WHEN state_fsm_select_channel = SWITCH_F1   ELSE
                                 time_reg_f2 & "10";  -- WHEN state_fsm_select_channel = SWITCH_F2
               -----------------------------------------------------------------------------
               -- FSM LOAD FFT
               -----------------------------------------------------------------------------
               sample_ren <= (OTHERS => '1') WHEN fft_ongoing_counter = '1' ELSE
                             sample_ren_s    WHEN sample_load = '1' ELSE
                             (OTHERS => '1');
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_ren_s       <= (OTHERS => '1');
                   state_fsm_load_FFT <= IDLE;
                   status_MS_input    <= (OTHERS => '0');
+                  select_fifo        <= "000";
                   --next_state_fsm_load_FFT <= IDLE;
                   --sample_valid              <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_FFT IS
                     WHEN IDLE =>
                       --sample_valid <= '0';
                       sample_ren_s <= (OTHERS => '1');
                       IF sample_full = "11111" AND sample_load = '1' THEN
                         state_fsm_load_FFT <= FIFO_1;
                         status_MS_input    <= status_channel;
+                        select_fifo <= "000";
                       END IF;
                     WHEN FIFO_1 =>
                       sample_ren_s <= "1111" & NOT(sample_load);
                       IF sample_empty(0) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_2;
+                        select_fifo <= "001";
                       END IF;
                     WHEN FIFO_2 =>
                       sample_ren_s <= "111" & NOT(sample_load) & '1';
                       IF sample_empty(1) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_3;
+                        select_fifo <= "010";
                       END IF;
                     WHEN FIFO_3 =>
                       sample_ren_s <= "11" & NOT(sample_load) & "11";
                       IF sample_empty(2) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_4;
+                        select_fifo <= "011";
                       END IF;
                     WHEN FIFO_4 =>
                       sample_ren_s <= '1' & NOT(sample_load) & "111";
                       IF sample_empty(3) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= FIFO_5;
+                        select_fifo <= "100";
                       END IF;
                     WHEN FIFO_5 =>
                       sample_ren_s <= NOT(sample_load) & "1111";
                       IF sample_empty(4) = '1' THEN
                         sample_ren_s       <= (OTHERS => '1');
                         state_fsm_load_FFT <= IDLE;
+                        select_fifo <= "000";
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   sample_valid_r          <= '0';
-                  next_state_fsm_load_FFT <= IDLE;
+                  select_fifo_reg <= (OTHERS => '0');
+                  --next_state_fsm_load_FFT <= IDLE;
                 ELSIF clk'EVENT AND clk = '1' THEN
-                  next_state_fsm_load_FFT <= state_fsm_load_FFT;
+                  select_fifo_reg <= select_fifo;
+                  --next_state_fsm_load_FFT <= state_fsm_load_FFT;
                   IF sample_ren_s = "11111" THEN
                     sample_valid_r <= '0';
                   ELSE
                     sample_valid_r <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               sample_valid <= '0' WHEN fft_ongoing_counter = '1' ELSE sample_valid_r AND sample_load;
-              sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
+              --sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN next_state_fsm_load_FFT = FIFO_1 ELSE
-                             sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
+              --               sample_rdata(16*2-1 DOWNTO 16*1) WHEN next_state_fsm_load_FFT = FIFO_2 ELSE
-                             sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
+              --               sample_rdata(16*3-1 DOWNTO 16*2) WHEN next_state_fsm_load_FFT = FIFO_3 ELSE
-                             sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+              --               sample_rdata(16*4-1 DOWNTO 16*3) WHEN next_state_fsm_load_FFT = FIFO_4 ELSE
+              --               sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
+              sample_data <= sample_rdata(16*1-1 DOWNTO 16*0) WHEN select_fifo_reg = "000" ELSE
+                             sample_rdata(16*2-1 DOWNTO 16*1) WHEN select_fifo_reg = "001" ELSE
+                             sample_rdata(16*3-1 DOWNTO 16*2) WHEN select_fifo_reg = "010" ELSE
+                             sample_rdata(16*4-1 DOWNTO 16*3) WHEN select_fifo_reg = "011"  ELSE
                              sample_rdata(16*5-1 DOWNTO 16*4);  --WHEN next_state_fsm_load_FFT = FIFO_5 ELSE
               -----------------------------------------------------------------------------
               -- FFT
               -----------------------------------------------------------------------------
               lpp_lfr_ms_FFT_1 : lpp_lfr_ms_FFT
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   sample_valid   => sample_valid,
                   fft_read       => fft_read,
                   sample_data    => sample_data,
                   sample_load    => sample_load,
                   fft_pong       => fft_pong,
                   fft_data_im    => fft_data_im,
                   fft_data_re    => fft_data_re,
                   fft_data_valid => fft_data_valid,
                   fft_ready      => fft_ready);
               -----------------------------------------------------------------------------
               fft_ready_rising_down   <= fft_ready_reg AND NOT fft_ready;
               sample_load_rising_down <= sample_load_reg AND NOT sample_load;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fft_ready_reg     <= '0';
                   sample_load_reg   <= '0';
                   fft_ongoing_counter <= '0';
                 ELSIF clk'event AND clk = '1' THEN
                   fft_ready_reg    <= fft_ready;
                   sample_load_reg  <= sample_load;
                   IF fft_ready_rising_down = '1' AND sample_load_rising_down = '0' THEN
                     fft_ongoing_counter <= '0';
             --        CASE fft_ongoing_counter IS
             --          WHEN "01" => fft_ongoing_counter <= "00";
             ----          WHEN "10" => fft_ongoing_counter <= "01";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   ELSIF fft_ready_rising_down = '0' AND sample_load_rising_down = '1' THEN
                     fft_ongoing_counter <= '1';
             --        CASE fft_ongoing_counter IS
             --          WHEN "00" => fft_ongoing_counter <= "01";
             ----          WHEN "01" => fft_ongoing_counter <= "10";
             --          WHEN OTHERS => NULL;
             --        END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   state_fsm_load_MS_memory <= IDLE;
                   current_fifo_load        <= "00001";
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE state_fsm_load_MS_memory IS
                     WHEN IDLE =>
                       IF current_fifo_empty = '1' AND fft_ready = '1' AND current_fifo_locked = '0' THEN
                         state_fsm_load_MS_memory <= LOAD_FIFO;
                       END IF;
                     WHEN LOAD_FIFO =>
                       IF current_fifo_full = '1' THEN
                         state_fsm_load_MS_memory <= TRASH_FFT;
                       END IF;
                     WHEN TRASH_FFT =>
                       IF fft_ready = '0' THEN
                         state_fsm_load_MS_memory <= IDLE;
                         current_fifo_load        <= current_fifo_load(3 DOWNTO 0) & current_fifo_load(4);
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
               current_fifo_empty <= MEM_IN_SM_Empty(0) WHEN current_fifo_load(0) = '1' ELSE
                                     MEM_IN_SM_Empty(1) WHEN current_fifo_load(1) = '1' ELSE
                                     MEM_IN_SM_Empty(2) WHEN current_fifo_load(2) = '1' ELSE
                                     MEM_IN_SM_Empty(3) WHEN current_fifo_load(3) = '1' ELSE
                                     MEM_IN_SM_Empty(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_full <= MEM_IN_SM_Full(0) WHEN current_fifo_load(0) = '1' ELSE
                                    MEM_IN_SM_Full(1) WHEN current_fifo_load(1) = '1' ELSE
                                    MEM_IN_SM_Full(2) WHEN current_fifo_load(2) = '1' ELSE
                                    MEM_IN_SM_Full(3) WHEN current_fifo_load(3) = '1' ELSE
                                    MEM_IN_SM_Full(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               current_fifo_locked <= MEM_IN_SM_locked(0) WHEN current_fifo_load(0) = '1' ELSE
                                      MEM_IN_SM_locked(1) WHEN current_fifo_load(1) = '1' ELSE
                                      MEM_IN_SM_locked(2) WHEN current_fifo_load(2) = '1' ELSE
                                      MEM_IN_SM_locked(3) WHEN current_fifo_load(3) = '1' ELSE
                                      MEM_IN_SM_locked(4);  -- WHEN current_fifo_load(3) = '1' ELSE
               fft_read <= '0' WHEN state_fsm_load_MS_memory = IDLE ELSE '1';
               all_fifo : FOR I IN 4 DOWNTO 0 GENERATE
                 MEM_IN_SM_wen_s(I) <= '0' WHEN fft_data_valid = '1'
                                       AND state_fsm_load_MS_memory = LOAD_FIFO
                                       AND current_fifo_load(I) = '1'
                                       ELSE '1';
               END GENERATE all_fifo;
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   MEM_IN_SM_wen <= (OTHERS => '1');
                 ELSIF clk'EVENT AND clk = '1' THEN
                   MEM_IN_SM_wen <= MEM_IN_SM_wen_s;
                 END IF;
               END PROCESS;
               MEM_IN_SM_wData <= (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re) &
                                  (fft_data_im & fft_data_re);
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               Mem_In_SpectralMatrix : lppFIFOxN
                 GENERIC MAP (
                   tech    => 0,
                   Mem_use => Mem_use,
                   Data_sz => 32,                    --16,
                   Addr_sz => 7,                     --8
                   FifoCnt => 5)
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   ReUse => MEM_IN_SM_ReUse,
                   run   => (OTHERS => '1'),
                   wen   => MEM_IN_SM_wen,
                   wdata => MEM_IN_SM_wData,
                   ren         => MEM_IN_SM_ren,
                   rdata       => MEM_IN_SM_rData,
                   full        => MEM_IN_SM_Full,
                   empty       => MEM_IN_SM_Empty,
                   almost_full => OPEN);
               -----------------------------------------------------------------------------
               MS_control_1 : MS_control
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   current_status_ms => status_MS_input,
                   fifo_in_lock  => MEM_IN_SM_locked,
                   fifo_in_data  => MEM_IN_SM_rdata,
                   fifo_in_full  => MEM_IN_SM_Full,
                   fifo_in_empty => MEM_IN_SM_Empty,
                   fifo_in_ren   => MEM_IN_SM_ren,
                   fifo_in_reuse => MEM_IN_SM_ReUse,
                   fifo_out_data  => SM_in_data,
                   fifo_out_ren   => SM_in_ren,
                   fifo_out_empty => SM_in_empty,
                   current_status_component => status_component,
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_done  => SM_correlation_done);
               MS_calculation_1 : MS_calculation
                 PORT MAP (
                   clk  => clk,
                   rstn => rstn,
                   fifo_in_data  => SM_in_data,
                   fifo_in_ren   => SM_in_ren,
                   fifo_in_empty => SM_in_empty,
                   fifo_out_data => MEM_OUT_SM_Data_in_s,  --    TODO
                   fifo_out_wen  => MEM_OUT_SM_Write_s,    --      TODO
                   fifo_out_full => MEM_OUT_SM_Full_s,     --       TODO
                   correlation_start => SM_correlation_start,
                   correlation_auto  => SM_correlation_auto,
                   correlation_begin => SM_correlation_begin,
                   correlation_done  => SM_correlation_done);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   current_matrix_write        <= '0';
                   current_matrix_wait_empty   <= '1';
                   status_component_fifo_0     <= (OTHERS => '0');
                   status_component_fifo_1     <= (OTHERS => '0');
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   SM_correlation_done_reg1    <= '0';
                   SM_correlation_done_reg2    <= '0';
                   SM_correlation_done_reg3    <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   SM_correlation_done_reg1    <= SM_correlation_done;
                   SM_correlation_done_reg2    <= SM_correlation_done_reg1;
                   SM_correlation_done_reg3    <= SM_correlation_done_reg2;
                   status_component_fifo_0_end <= '0';
                   status_component_fifo_1_end <= '0';
                   IF SM_correlation_begin = '1' THEN
                     IF current_matrix_write = '0' THEN
-                      status_component_fifo_0 <= status_component;
+                      status_component_fifo_0 <= status_component(53 DOWNTO 4);
                     ELSE
-                      status_component_fifo_1 <= status_component;
+                      status_component_fifo_1 <= status_component(53 DOWNTO 4);
                     END IF;
                   END IF;
                   IF SM_correlation_done_reg3 = '1' THEN
                     IF current_matrix_write = '0' THEN
                       status_component_fifo_0_end <= '1';
                     ELSE
                       status_component_fifo_1_end <= '1';
                     END IF;
                     current_matrix_wait_empty <= '1';
                     current_matrix_write      <= NOT current_matrix_write;
                   END IF;
                   IF current_matrix_wait_empty <= '1' THEN
                     IF current_matrix_write = '0' THEN
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(0);
                     ELSE
                       current_matrix_wait_empty <= NOT MEM_OUT_SM_Empty(1);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Full_s <= '1' WHEN SM_correlation_done = '1' ELSE
                                    '1'                WHEN SM_correlation_done_reg1 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg2 = '1'  ELSE
                                    '1'                WHEN SM_correlation_done_reg3 = '1'  ELSE
                                    '1'                WHEN current_matrix_wait_empty = '1' ELSE
                                    MEM_OUT_SM_Full(0) WHEN current_matrix_write = '0'      ELSE
                                    MEM_OUT_SM_Full(1);
               MEM_OUT_SM_Write(0) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '0' ELSE '1';
               MEM_OUT_SM_Write(1) <= MEM_OUT_SM_Write_s WHEN current_matrix_write = '1' ELSE '1';
               MEM_OUT_SM_Data_in <= MEM_OUT_SM_Data_in_s & MEM_OUT_SM_Data_in_s;
               -----------------------------------------------------------------------------
               --Mem_Out_SpectralMatrix : lppFIFOxN
               --  GENERIC MAP (
               --    tech    => 0,
               --    Mem_use => Mem_use,
               --    Data_sz => 32,
               --    Addr_sz => 8,
               --    FifoCnt => 2)
               --  PORT MAP (
               --    clk  => clk,
               --    rstn => rstn,
               --    ReUse => (OTHERS => '0'),
               --    run   => (OTHERS => '1'),
               --    wen   => MEM_OUT_SM_Write,
               --    wdata => MEM_OUT_SM_Data_in,
               --    ren   => MEM_OUT_SM_Read,
               --    rdata => MEM_OUT_SM_Data_out,
               --    full        => MEM_OUT_SM_Full,
               --    empty       => MEM_OUT_SM_Empty,
               --    almost_full => OPEN);
               all_Mem_Out_SpectralMatrix: FOR I IN 1 DOWNTO 0 GENERATE
                 Mem_Out_SpectralMatrix_I: lpp_fifo
                   GENERIC MAP (
                     tech                  => 0,
                     Mem_use               => Mem_use,
                     EMPTY_THRESHOLD_LIMIT => 15,
                     FULL_THRESHOLD_LIMIT  => 1,
                     DataSz                => 32,
                     AddrSz                => 8)
                   PORT MAP (
                     clk             => clk,
                     rstn            => rstn,
                     reUse           => '0',
                     run             => run,
                     ren             => MEM_OUT_SM_Read(I),
                     rdata           => MEM_OUT_SM_Data_out(32*(I+1)-1 DOWNTO 32*i),
                     wen             => MEM_OUT_SM_Write(I),
                     wdata           => MEM_OUT_SM_Data_in(32*(I+1)-1 DOWNTO 32*i),
                     empty           => MEM_OUT_SM_Empty(I),
                     full            => MEM_OUT_SM_Full(I),
                     full_almost     => OPEN,
                     empty_threshold => MEM_OUT_SM_Empty_Threshold(I),
                     full_threshold  => OPEN);
               END GENERATE all_Mem_Out_SpectralMatrix;
               -----------------------------------------------------------------------------
             --  MEM_OUT_SM_Read <= "00";
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   fifo_0_ready <= '0';
                   fifo_1_ready <= '0';
                   fifo_ongoing <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   IF fifo_0_ready = '1' AND MEM_OUT_SM_Empty(0) = '1' THEN
                     fifo_ongoing <= '1';
                     fifo_0_ready <= '0';
                   ELSIF status_component_fifo_0_end = '1' THEN
                     fifo_0_ready <= '1';
                   END IF;
                   IF fifo_1_ready = '1' AND MEM_OUT_SM_Empty(1) = '1' THEN
                     fifo_ongoing <= '0';
                     fifo_1_ready <= '0';
                   ELSIF status_component_fifo_1_end = '1' THEN
                     fifo_1_ready <= '1';
                   END IF;
                 END IF;
               END PROCESS;
               MEM_OUT_SM_Read(0) <= '1' WHEN fifo_ongoing = '1' ELSE
                                     '1' WHEN fifo_0_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               MEM_OUT_SM_Read(1) <= '1' WHEN fifo_ongoing = '0' ELSE
                                     '1' WHEN fifo_1_ready = '0' ELSE
                                     FSM_DMA_fifo_ren;
               FSM_DMA_fifo_empty <= MEM_OUT_SM_Empty(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1' ELSE
                                     MEM_OUT_SM_Empty(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1' ELSE
                                     '1';
               FSM_DMA_fifo_status <= status_component_fifo_0 WHEN fifo_ongoing = '0' ELSE
                                      status_component_fifo_1;
               FSM_DMA_fifo_data <= MEM_OUT_SM_Data_out(31 DOWNTO 0) WHEN fifo_ongoing = '0' ELSE
                                    MEM_OUT_SM_Data_out(63 DOWNTO 32);
               FSM_DMA_fifo_empty_threshold <= MEM_OUT_SM_Empty_Threshold(0) WHEN fifo_ongoing = '0' AND fifo_0_ready = '1'  ELSE
                                               MEM_OUT_SM_Empty_Threshold(1) WHEN fifo_ongoing = '1' AND fifo_1_ready = '1'  ELSE
                                               '1';
               -----------------------------------------------------------------------------
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),       --IN
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),       --IN
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),      --IN
               --    fifo_data             => FSM_DMA_fifo_data,                     --IN
               --    fifo_empty            => FSM_DMA_fifo_empty,                    --IN
               --    fifo_empty_threshold  => FSM_DMA_fifo_empty_threshold,          --IN
               --    fifo_ren              => FSM_DMA_fifo_ren,                      --OUT
               lpp_lfr_ms_fsmdma_1: lpp_lfr_ms_fsmdma
                 PORT MAP (
                   clk                    => clk,
                   rstn                   => rstn,
                   run                    => run,
                   fifo_matrix_type       => FSM_DMA_fifo_status(5 DOWNTO 4),
                   fifo_matrix_time       => FSM_DMA_fifo_status(53 DOWNTO 6),
                   fifo_data              => FSM_DMA_fifo_data,
                   fifo_empty             => FSM_DMA_fifo_empty,
                   fifo_empty_threshold   => FSM_DMA_fifo_empty_threshold,
                   fifo_ren               => FSM_DMA_fifo_ren,
                   dma_fifo_valid_burst   => dma_fifo_burst_valid,
                   dma_fifo_data          => dma_fifo_data,
                   dma_fifo_ren           => dma_fifo_ren,
                   dma_buffer_new         => dma_buffer_new,
                   dma_buffer_addr        => dma_buffer_addr,
                   dma_buffer_length      => dma_buffer_length,
                   dma_buffer_full        => dma_buffer_full,
                   dma_buffer_full_err    => dma_buffer_full_err,
                   status_ready_matrix_f0 => status_ready_matrix_f0,
                   status_ready_matrix_f1 => status_ready_matrix_f1,
                   status_ready_matrix_f2 => status_ready_matrix_f2,
                   addr_matrix_f0         => addr_matrix_f0,
                   addr_matrix_f1         => addr_matrix_f1,
                   addr_matrix_f2         => addr_matrix_f2,
                   length_matrix_f0       => length_matrix_f0,
                   length_matrix_f1       => length_matrix_f1,
                   length_matrix_f2       => length_matrix_f2,
                   ready_matrix_f0        => ready_matrix_f0,
                   ready_matrix_f1        => ready_matrix_f1,
                   ready_matrix_f2        => ready_matrix_f2,
                   matrix_time_f0         => matrix_time_f0,
                   matrix_time_f1         => matrix_time_f1,
                   matrix_time_f2         => matrix_time_f2,
                   error_buffer_full      => error_buffer_full);
               --dma_fifo_burst_valid: OUT STD_LOGIC;                      --TODO
               --dma_fifo_data       : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_fifo_ren        : IN  STD_LOGIC;                      --TODO
               --dma_buffer_new      : OUT STD_LOGIC;                      --TODO
               --dma_buffer_addr     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);  --TODO
               --dma_buffer_length   : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);  --TODO
               --dma_buffer_full     : IN  STD_LOGIC;                      --TODO
               --dma_buffer_full_err : IN  STD_LOGIC;                      --TODO
               ---- Reg out
               --ready_matrix_f0           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f1           : OUT STD_LOGIC;                  -- TODO
               --ready_matrix_f2           : OUT STD_LOGIC;                  -- TODO
               --error_bad_component_error : OUT STD_LOGIC;                  -- TODO
               --error_buffer_full         : OUT STD_LOGIC;                  -- TODO
               ---- Reg In
               --status_ready_matrix_f0 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f1 : IN STD_LOGIC;                      -- TODO
               --status_ready_matrix_f2 : IN STD_LOGIC;                      -- TODO
               --addr_matrix_f0                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f1                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --addr_matrix_f2                         : IN STD_LOGIC_VECTOR(31 DOWNTO 0); -- TODO
               --matrix_time_f0 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f1 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0); -- TODO
               --matrix_time_f2 : OUT STD_LOGIC_VECTOR(47 DOWNTO 0)  -- TODO
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               --lpp_lfr_ms_fsmdma_1 : lpp_lfr_ms_fsmdma
               --  PORT MAP (
               --    HCLK    => clk,
               --    HRESETn => rstn,
               --    fifo_matrix_type      => FSM_DMA_fifo_status(5 DOWNTO 4),
               --    fifo_matrix_component => FSM_DMA_fifo_status(3 DOWNTO 0),
               --    fifo_matrix_time      => FSM_DMA_fifo_status(53 DOWNTO 6),
               --    fifo_data             => FSM_DMA_fifo_data,
               --    fifo_empty            => FSM_DMA_fifo_empty,
               --    fifo_ren              => FSM_DMA_fifo_ren,
               --    dma_addr        => dma_addr,
               --    dma_data        => dma_data,
               --    dma_valid       => dma_valid,
               --    dma_valid_burst => dma_valid_burst,
               --    dma_ren         => dma_ren,
               --    dma_done        => dma_done,
               --    ready_matrix_f0 => ready_matrix_f0,
               --    ready_matrix_f1 => ready_matrix_f1,
               --    ready_matrix_f2 => ready_matrix_f2,
               --    error_bad_component_error => error_bad_component_error,
               --    error_buffer_full         => error_buffer_full,
               --    debug_reg              => debug_reg,
               --    status_ready_matrix_f0 => status_ready_matrix_f0,
               --    status_ready_matrix_f1 => status_ready_matrix_f1,
               --    status_ready_matrix_f2 => status_ready_matrix_f2,
               --    config_active_interruption_onNewMatrix => config_active_interruption_onNewMatrix,
               --    config_active_interruption_onError     => config_active_interruption_onError,
               --    addr_matrix_f0 => addr_matrix_f0,
               --    addr_matrix_f1 => addr_matrix_f1,
               --    addr_matrix_f2 => addr_matrix_f2,
               --    matrix_time_f0 => matrix_time_f0,
               --    matrix_time_f1 => matrix_time_f1,
               --    matrix_time_f2 => matrix_time_f2
               --    );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- TIME MANAGMENT
               -----------------------------------------------------------------------------
               all_time         <= coarse_time & fine_time;
               --
               f_empty(0) <= '1' WHEN sample_f0_A_empty = "11111" ELSE '0';
               f_empty(1) <= '1' WHEN sample_f0_B_empty = "11111" ELSE '0';
               f_empty(2) <= '1' WHEN sample_f1_empty   = "11111" ELSE '0';
               f_empty(3) <= '1' WHEN sample_f2_empty   = "11111" ELSE '0';
               all_time_reg: FOR I IN 0 TO 3 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     f_empty_reg(I) <= '1';
                   ELSIF clk'event AND clk = '1' THEN
                     f_empty_reg(I) <= f_empty(I);
                   END IF;
                 END PROCESS;
                 time_update_f(I) <= '1' WHEN f_empty(I) = '0' AND f_empty_reg(I) = '1' ELSE '0';
                 s_m_t_m_f0_A : spectral_matrix_time_managment
                   PORT MAP (
                     clk      => clk,
                     rstn     => rstn,
                     time_in  => all_time,
                     update_1 => time_update_f(I),
                     time_out => time_reg_f((I+1)*48-1 DOWNTO I*48)
                     );
               END GENERATE all_time_reg;
               time_reg_f0_A <= time_reg_f((0+1)*48-1 DOWNTO 0*48);
               time_reg_f0_B <= time_reg_f((1+1)*48-1 DOWNTO 1*48);
               time_reg_f1   <= time_reg_f((2+1)*48-1 DOWNTO 2*48);
               time_reg_f2   <= time_reg_f((3+1)*48-1 DOWNTO 3*48);
               -----------------------------------------------------------------------------
             END Behavioral;

lib/lpp/lpp_top_lfr/lpp_lfr_pkg.vhd +1 -1

             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             LIBRARY lpp;
             USE lpp.lpp_ad_conv.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.FILTERcfg.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_lfr_pkg IS
               -----------------------------------------------------------------------------
               -- TEMP
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms_test
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                 -- TIME
                 coarse_time     : IN STD_LOGIC_VECTOR(31 DOWNTO 0);  -- todo
                 fine_time       : IN STD_LOGIC_VECTOR(15 DOWNTO 0);  -- todo
                 --
                 sample_f0_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f0_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f1_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f1_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --
                 sample_f2_wen   : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 sample_f2_wdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 error_input_fifo_write        : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                 --
                 --sample_ren   : OUT STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --sample_full  : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --sample_empty : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                 --sample_rdata : IN STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                 --status_channel : IN STD_LOGIC_VECTOR(49 DOWNTO 0);
                 -- IN
                 MEM_IN_SM_locked      : IN STD_LOGIC_VECTOR(4 DOWNTO 0);
                 -----------------------------------------------------------------------------
                 status_component : OUT STD_LOGIC_VECTOR(53 DOWNTO 0);
                 SM_in_data : OUT STD_LOGIC_VECTOR(32*2-1 DOWNTO 0);
                 SM_in_ren : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
                 SM_in_empty : OUT STD_LOGIC_VECTOR(1 DOWNTO 0);
                 SM_correlation_start : OUT STD_LOGIC;
                 SM_correlation_auto : OUT STD_LOGIC;
                 SM_correlation_done : IN STD_LOGIC
                 );
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_ms
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   clk                    : IN  STD_LOGIC;
                   rstn                   : IN  STD_LOGIC;
                   run                    : IN  STD_LOGIC;
                   start_date      : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                   coarse_time            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time              : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_f0_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f0_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f1_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f1_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   sample_f2_wen          : IN  STD_LOGIC_VECTOR(4 DOWNTO 0);
                   sample_f2_wdata        : IN  STD_LOGIC_VECTOR((5*16)-1 DOWNTO 0);
                   dma_fifo_burst_valid   : OUT STD_LOGIC;
                   dma_fifo_data          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren           : IN  STD_LOGIC;
                   dma_buffer_new         : OUT STD_LOGIC;
                   dma_buffer_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_buffer_length      : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   dma_buffer_full        : IN  STD_LOGIC;
                   dma_buffer_full_err    : IN  STD_LOGIC;
                   ready_matrix_f0        : OUT STD_LOGIC;
                   ready_matrix_f1        : OUT STD_LOGIC;
                   ready_matrix_f2        : OUT STD_LOGIC;
                   error_buffer_full      : OUT STD_LOGIC;
                   error_input_fifo_write : OUT STD_LOGIC_VECTOR(2 DOWNTO 0);
                   status_ready_matrix_f0 : IN  STD_LOGIC;
                   status_ready_matrix_f1 : IN  STD_LOGIC;
                   status_ready_matrix_f2 : IN  STD_LOGIC;
                   addr_matrix_f0         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_matrix_f0       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f1       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f2       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   matrix_time_f0         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr_ms_fsmdma
                 PORT (
                   clk                    : IN  STD_ULOGIC;
                   rstn                   : IN  STD_ULOGIC;
                   run                    : IN  STD_LOGIC;
                   fifo_matrix_type       : IN  STD_LOGIC_VECTOR(1 DOWNTO 0);
                   fifo_matrix_time       : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   fifo_data              : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty             : IN  STD_LOGIC;
                   fifo_empty_threshold   : IN  STD_LOGIC;
                   fifo_ren               : OUT STD_LOGIC;
                   dma_fifo_valid_burst   : OUT STD_LOGIC;
                   dma_fifo_data          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren           : IN  STD_LOGIC;
                   dma_buffer_new         : OUT STD_LOGIC;
                   dma_buffer_addr        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_buffer_length      : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   dma_buffer_full        : IN  STD_LOGIC;
                   dma_buffer_full_err    : IN  STD_LOGIC;
                   status_ready_matrix_f0 : IN  STD_LOGIC;
                   status_ready_matrix_f1 : IN  STD_LOGIC;
                   status_ready_matrix_f2 : IN  STD_LOGIC;
                   addr_matrix_f0         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_matrix_f0       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f1       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f2       : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_matrix_f0        : OUT STD_LOGIC;
                   ready_matrix_f1        : OUT STD_LOGIC;
                   ready_matrix_f2        : OUT STD_LOGIC;
                   matrix_time_f0         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   error_buffer_full      : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_lfr_ms_FFT
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   sample_valid   : IN  STD_LOGIC;
                   fft_read       : IN  STD_LOGIC;
                   sample_data    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   sample_load    : OUT STD_LOGIC;
                   fft_pong       : OUT STD_LOGIC;
                   fft_data_im    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fft_data_re    : OUT STD_LOGIC_VECTOR(15 DOWNTO 0);
                   fft_data_valid : OUT STD_LOGIC;
                   fft_ready      : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_lfr_filter
                 GENERIC (
                   Mem_use : INTEGER);
                 PORT (
                   sample           : IN  Samples(7 DOWNTO 0);
                   sample_val       : IN  STD_LOGIC;
                   clk              : IN  STD_LOGIC;
                   rstn             : IN  STD_LOGIC;
                   data_shaping_SP0 : IN  STD_LOGIC;
                   data_shaping_SP1 : IN  STD_LOGIC;
                   data_shaping_R0  : IN  STD_LOGIC;
                   data_shaping_R1  : IN  STD_LOGIC;
                   data_shaping_R2  : IN  STD_LOGIC;
                   sample_f0_val    : OUT STD_LOGIC;
                   sample_f1_val    : OUT STD_LOGIC;
                   sample_f2_val    : OUT STD_LOGIC;
                   sample_f3_val    : OUT STD_LOGIC;
                   sample_f0_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f1_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f2_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0);
                   sample_f3_wdata  : OUT STD_LOGIC_VECTOR((6*16)-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
             --      nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0)
                   );
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples(2 DOWNTO 0);
                   sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC
                   );
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- LPP_LFR with only WaveForm Picker (and without Spectral Matrix Sub System)
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_WFP_nMS
                 GENERIC (
                   Mem_use                : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_word_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   hindex                 : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples(2 DOWNTO 0);
                   sample_E        : IN  Samples(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi            : IN  AHB_Mst_In_Type;
                   ahbo            : OUT AHB_Mst_Out_Type;
                   coarse_time     : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time       : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_shaping_BW : OUT STD_LOGIC;
                   observation_reg : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               COMPONENT lpp_lfr_apbreg
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER;
                   pindex                 : INTEGER;
                   paddr                  : INTEGER;
                   pmask                  : INTEGER;
                   pirq_ms                : INTEGER;
                   pirq_wfp               : INTEGER;
                   top_lfr_version        : STD_LOGIC_VECTOR(23 DOWNTO 0));
                 PORT (
                   HCLK                    : IN  STD_ULOGIC;
                   HRESETn                 : IN  STD_ULOGIC;
                   apbi                    : IN  apb_slv_in_type;
                   apbo                    : OUT apb_slv_out_type;
                   run_ms                  : OUT STD_LOGIC;
                   ready_matrix_f0         : IN  STD_LOGIC;
                   ready_matrix_f1         : IN  STD_LOGIC;
                   ready_matrix_f2         : IN  STD_LOGIC;
                   error_buffer_full       : IN  STD_LOGIC;
                   error_input_fifo_write  : IN  STD_LOGIC_VECTOR(2 DOWNTO 0);
                   status_ready_matrix_f0  : OUT STD_LOGIC;
                   status_ready_matrix_f1  : OUT STD_LOGIC;
                   status_ready_matrix_f2  : OUT STD_LOGIC;
                   addr_matrix_f0          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f1          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_matrix_f2          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_matrix_f0        : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f1        : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   length_matrix_f2        : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   matrix_time_f0          : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1          : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2          : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   status_new_err          : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_shaping_BW         : OUT STD_LOGIC;
                   data_shaping_SP0        : OUT STD_LOGIC;
                   data_shaping_SP1        : OUT STD_LOGIC;
                   data_shaping_R0         : OUT STD_LOGIC;
                   data_shaping_R1         : OUT STD_LOGIC;
                   data_shaping_R2         : OUT STD_LOGIC;
                   delta_snapshot          : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0                : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f0_2              : OUT STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   delta_f1                : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   delta_f2                : OUT STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   nb_data_by_buffer       : OUT STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param       : OUT STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   enable_f0               : OUT STD_LOGIC;
                   enable_f1               : OUT STD_LOGIC;
                   enable_f2               : OUT STD_LOGIC;
                   enable_f3               : OUT STD_LOGIC;
                   burst_f0                : OUT STD_LOGIC;
                   burst_f1                : OUT STD_LOGIC;
                   burst_f2                : OUT STD_LOGIC;
                   run                     : OUT STD_LOGIC;
                   start_date              : OUT STD_LOGIC_VECTOR(30 DOWNTO 0);
                   wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
-                  wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                  wfp_addr_buffer         : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   wfp_length_buffer       : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   wfp_ready_buffer        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wfp_buffer_time         : IN  STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                   wfp_error_buffer_full   : IN  STD_LOGIC_VECTOR(3 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_top_ms
                 GENERIC (
                   Mem_use                 : INTEGER;
                   nb_burst_available_size : INTEGER;
                   nb_snapshot_param_size  : INTEGER;
                   delta_snapshot_size     : INTEGER;
                   delta_f2_f0_size        : INTEGER;
                   delta_f2_f1_size        : INTEGER;
                   pindex                  : INTEGER;
                   paddr                   : INTEGER;
                   pmask                   : INTEGER;
                   pirq_ms                 : INTEGER;
                   pirq_wfp                : INTEGER;
                   hindex_wfp              : INTEGER;
                   hindex_ms               : INTEGER);
                 PORT (
                   clk             : IN  STD_LOGIC;
                   rstn            : IN  STD_LOGIC;
                   sample_B        : IN  Samples14v(2 DOWNTO 0);
                   sample_E        : IN  Samples14v(4 DOWNTO 0);
                   sample_val      : IN  STD_LOGIC;
                   apbi            : IN  apb_slv_in_type;
                   apbo            : OUT apb_slv_out_type;
                   ahbi_ms         : IN  AHB_Mst_In_Type;
                   ahbo_ms         : OUT AHB_Mst_Out_Type;
                   data_shaping_BW : OUT STD_LOGIC;
                   matrix_time_f0_0                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f0_1                       : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f1                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0);
                   matrix_time_f2                         : IN STD_LOGIC_VECTOR(47 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_apbreg_ms_pointer
                 PORT (
                   clk                      : IN  STD_LOGIC;
                   rstn                     : IN  STD_LOGIC;
                   run                      : IN  STD_LOGIC;
                   reg0_status_ready_matrix : IN  STD_LOGIC;
                   reg0_ready_matrix        : OUT STD_LOGIC;
                   reg0_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   reg0_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   reg1_status_ready_matrix : IN  STD_LOGIC;
                   reg1_ready_matrix        : OUT STD_LOGIC;
                   reg1_addr_matrix         : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   reg1_matrix_time         : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   ready_matrix             : IN  STD_LOGIC;
                   status_ready_matrix      : OUT STD_LOGIC;
                   addr_matrix              : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   matrix_time              : IN  STD_LOGIC_VECTOR(47 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_lfr_ms_reg_head
                 PORT (
                   clk      : IN  STD_LOGIC;
                   rstn     : IN  STD_LOGIC;
                   in_wen   : IN  STD_LOGIC;
                   in_data  : IN  STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   in_full  : IN  STD_LOGIC;
                   in_empty : IN  STD_LOGIC;
                   out_wen  : OUT STD_LOGIC;
                   out_data : OUT STD_LOGIC_VECTOR(5*16-1 DOWNTO 0);
                   out_full : OUT STD_LOGIC);
               END COMPONENT;
             END lpp_lfr_pkg;

lib/lpp/lpp_waveform/lpp_waveform.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY lpp;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.iir_filter.ALL;
             USE lpp.lpp_memory.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY lpp_waveform IS
               GENERIC (
                 tech                   : INTEGER := inferred;
                 data_size              : INTEGER := 96;  --16*6
                 nb_data_by_buffer_size : INTEGER := 11;
             --    nb_word_by_buffer_size : INTEGER := 11;
                 nb_snapshot_param_size : INTEGER := 11;
                 delta_vector_size      : INTEGER := 20;
                 delta_vector_size_f0_2 : INTEGER := 3);
               PORT (
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 ---- AMBA AHB Master Interface
                 --AHB_Master_In  : IN  AHB_Mst_In_Type;   -- TODO
                 --AHB_Master_Out : OUT AHB_Mst_Out_Type;  -- TODO
                 --config
                 reg_run            : IN STD_LOGIC;
                 reg_start_date     : IN STD_LOGIC_VECTOR(30 DOWNTO 0);
                 reg_delta_snapshot : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 reg_delta_f0       : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 reg_delta_f0_2     : IN STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                 reg_delta_f1       : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 reg_delta_f2       : IN STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                 enable_f0 : IN STD_LOGIC;
                 enable_f1 : IN STD_LOGIC;
                 enable_f2 : IN STD_LOGIC;
                 enable_f3 : IN STD_LOGIC;
                 burst_f0 : IN STD_LOGIC;
                 burst_f1 : IN STD_LOGIC;
                 burst_f2 : IN STD_LOGIC;
                 nb_data_by_buffer : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
             --    nb_word_by_buffer : IN  STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0);
                 nb_snapshot_param : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                 status_new_err    : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);  -- New data f(i) before the current data is write by dma
                 -- REG DMA
                 status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-                addr_buffer         : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
                 ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                 error_buffer_full   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- INPUT
                 coarse_time       : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                 fine_time         : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                 --f0
                 data_f0_in_valid : IN STD_LOGIC;
                 data_f0_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                 --f1
                 data_f1_in_valid : IN STD_LOGIC;
                 data_f1_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                 --f2
                 data_f2_in_valid : IN STD_LOGIC;
                 data_f2_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                 --f3
                 data_f3_in_valid : IN STD_LOGIC;
                 data_f3_in       : IN STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- DMA --------------------------------------------------------------------
                 dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_fifo_data        : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 dma_fifo_ren         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_buffer_new       : OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_buffer_addr      : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                 dma_buffer_length    : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
                 dma_buffer_full      : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 dma_buffer_full_err  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0)
                 );
             END lpp_waveform;
             ARCHITECTURE beh OF lpp_waveform IS
               SIGNAL start_snapshot_f0 : STD_LOGIC;
               SIGNAL start_snapshot_f1 : STD_LOGIC;
               SIGNAL start_snapshot_f2 : STD_LOGIC;
               SIGNAL data_f0_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f1_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f2_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f3_out : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f0_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f1_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f2_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f3_out_swap : STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
               SIGNAL data_f0_out_valid          : STD_LOGIC;
               SIGNAL data_f1_out_valid          : STD_LOGIC;
               SIGNAL data_f2_out_valid          : STD_LOGIC;
               SIGNAL data_f3_out_valid          : STD_LOGIC;
               SIGNAL nb_snapshot_param_more_one : STD_LOGIC_VECTOR(nb_snapshot_param_size DOWNTO 0);
               --
               SIGNAL valid_in                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL valid_out                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL valid_ack                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_ready                 : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL data_ready                 : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL ready_arb                  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL data_wen                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_wen                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL wdata                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL full_almost                : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL full                       : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL empty_almost               : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL empty                      : STD_LOGIC_VECTOR(3 DOWNTO 0);
               --
               SIGNAL data_ren                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL time_ren                   : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL rdata                      : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL enable                     : STD_LOGIC_VECTOR(3 DOWNTO 0);
               --
               SIGNAL run                        : STD_LOGIC;
               --
               TYPE   TIME_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL data_out                   : Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
               SIGNAL time_out_2                 : Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
               SIGNAL time_out                   : TIME_VECTOR(3 DOWNTO 0);
               SIGNAL time_out_debug             : TIME_VECTOR(3 DOWNTO 0);  -- TODO : debug
               SIGNAL time_reg1                  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL time_reg2                  : STD_LOGIC_VECTOR(47 DOWNTO 0);
               --
               SIGNAL s_empty_almost : STD_LOGIC_VECTOR(3 DOWNTO 0);  --occupancy is lesser than 16 * 32b
               SIGNAL s_empty        : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL s_data_ren     : STD_LOGIC_VECTOR(3 DOWNTO 0);
             --  SIGNAL s_rdata        : STD_LOGIC_VECTOR(31 DOWNTO 0);
               SIGNAL s_rdata_v        : STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
               --
               SIGNAL arbiter_time_out      : STD_LOGIC_VECTOR(47 DOWNTO 0);
               SIGNAL arbiter_time_out_new  : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL fifo_buffer_time : STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
             BEGIN  -- beh
               -----------------------------------------------------------------------------
               lpp_waveform_snapshot_controler_1 : lpp_waveform_snapshot_controler
                 GENERIC MAP (
                   delta_vector_size      => delta_vector_size,
                   delta_vector_size_f0_2 => delta_vector_size_f0_2
                   )
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
                   reg_run            => reg_run,
                   reg_start_date     => reg_start_date,
                   reg_delta_snapshot => reg_delta_snapshot,
                   reg_delta_f0       => reg_delta_f0,
                   reg_delta_f0_2     => reg_delta_f0_2,
                   reg_delta_f1       => reg_delta_f1,
                   reg_delta_f2       => reg_delta_f2,
                   coarse_time        => coarse_time(30 DOWNTO 0),
                   data_f0_valid      => data_f0_in_valid,
                   data_f2_valid      => data_f2_in_valid,
                   start_snapshot_f0  => start_snapshot_f0,
                   start_snapshot_f1  => start_snapshot_f1,
                   start_snapshot_f2  => start_snapshot_f2,
                   wfp_on             => run);
               lpp_waveform_snapshot_f0 : lpp_waveform_snapshot
                 GENERIC MAP (
                   data_size              => data_size,
                   nb_snapshot_param_size => nb_snapshot_param_size)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   enable            => enable_f0,
                   burst_enable      => burst_f0,
                   nb_snapshot_param => nb_snapshot_param,
                   start_snapshot    => start_snapshot_f0,
                   data_in           => data_f0_in,
                   data_in_valid     => data_f0_in_valid,
                   data_out          => data_f0_out,
                   data_out_valid    => data_f0_out_valid);
               nb_snapshot_param_more_one <= ('0' & nb_snapshot_param) ;--+ 1;
               lpp_waveform_snapshot_f1 : lpp_waveform_snapshot
                 GENERIC MAP (
                   data_size              => data_size,
                   nb_snapshot_param_size => nb_snapshot_param_size+1)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   enable            => enable_f1,
                   burst_enable      => burst_f1,
                   nb_snapshot_param => nb_snapshot_param_more_one,
                   start_snapshot    => start_snapshot_f1,
                   data_in           => data_f1_in,
                   data_in_valid     => data_f1_in_valid,
                   data_out          => data_f1_out,
                   data_out_valid    => data_f1_out_valid);
               lpp_waveform_snapshot_f2 : lpp_waveform_snapshot
                 GENERIC MAP (
                   data_size              => data_size,
                   nb_snapshot_param_size => nb_snapshot_param_size+1)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   enable            => enable_f2,
                   burst_enable      => burst_f2,
                   nb_snapshot_param => nb_snapshot_param_more_one,
                   start_snapshot    => start_snapshot_f2,
                   data_in           => data_f2_in,
                   data_in_valid     => data_f2_in_valid,
                   data_out          => data_f2_out,
                   data_out_valid    => data_f2_out_valid);
               lpp_waveform_burst_f3 : lpp_waveform_burst
                 GENERIC MAP (
                   data_size => data_size)
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   run            => run,
                   enable         => enable_f3,
                   data_in        => data_f3_in,
                   data_in_valid  => data_f3_in_valid,
                   data_out       => data_f3_out,
                   data_out_valid => data_f3_out_valid);
               -----------------------------------------------------------------------------
               -- DEBUG -- SNAPSHOT OUT
               --debug_f0_data_valid <= data_f0_out_valid;
               --debug_f0_data       <= data_f0_out;
               --debug_f1_data_valid <= data_f1_out_valid;
               --debug_f1_data       <= data_f1_out;
               --debug_f2_data_valid <= data_f2_out_valid;
               --debug_f2_data       <= data_f2_out;
               --debug_f3_data_valid <= data_f3_out_valid;
               --debug_f3_data       <= data_f3_out;
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   time_reg1 <= (OTHERS => '0');
                   time_reg2 <= (OTHERS => '0');
                 ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                   time_reg1 <= fine_time & coarse_time;
                   time_reg2 <= time_reg1;
                 END IF;
               END PROCESS;
               valid_in <= data_f3_out_valid & data_f2_out_valid & data_f1_out_valid & data_f0_out_valid;
               all_input_valid : FOR i IN 3 DOWNTO 0 GENERATE
                 lpp_waveform_dma_genvalid_I : lpp_waveform_dma_genvalid
                   PORT MAP (
                     HCLK      => clk,
                     HRESETn   => rstn,
                     run       => run,
                     valid_in  => valid_in(I),
                     ack_in    => valid_ack(I),
                     time_in   => time_reg2,         -- Todo
                     valid_out => valid_out(I),
                     time_out  => time_out(I),       -- Todo
                     error     => status_new_err(I));
               END GENERATE all_input_valid;
               data_f0_out_swap <= data_f0_out((16*5)-1 DOWNTO 16*4) &
                                   data_f0_out((16*6)-1 DOWNTO 16*5) &
                                   data_f0_out((16*3)-1 DOWNTO 16*2) &
                                   data_f0_out((16*4)-1 DOWNTO 16*3) &
                                   data_f0_out((16*1)-1 DOWNTO 16*0) &
                                   data_f0_out((16*2)-1 DOWNTO 16*1) ;
               data_f1_out_swap <= data_f1_out((16*5)-1 DOWNTO 16*4) &
                                   data_f1_out((16*6)-1 DOWNTO 16*5) &
                                   data_f1_out((16*3)-1 DOWNTO 16*2) &
                                   data_f1_out((16*4)-1 DOWNTO 16*3) &
                                   data_f1_out((16*1)-1 DOWNTO 16*0) &
                                   data_f1_out((16*2)-1 DOWNTO 16*1) ;
               data_f2_out_swap <= data_f2_out((16*5)-1 DOWNTO 16*4) &
                                   data_f2_out((16*6)-1 DOWNTO 16*5) &
                                   data_f2_out((16*3)-1 DOWNTO 16*2) &
                                   data_f2_out((16*4)-1 DOWNTO 16*3) &
                                   data_f2_out((16*1)-1 DOWNTO 16*0) &
                                   data_f2_out((16*2)-1 DOWNTO 16*1) ;
               data_f3_out_swap <= data_f3_out((16*5)-1 DOWNTO 16*4) &
                                   data_f3_out((16*6)-1 DOWNTO 16*5) &
                                   data_f3_out((16*3)-1 DOWNTO 16*2) &
                                   data_f3_out((16*4)-1 DOWNTO 16*3) &
                                   data_f3_out((16*1)-1 DOWNTO 16*0) &
                                   data_f3_out((16*2)-1 DOWNTO 16*1) ;
               all_bit_of_data_out : FOR I IN 95 DOWNTO 0 GENERATE
                 data_out(0, I) <= data_f0_out_swap(I);
                 data_out(1, I) <= data_f1_out_swap(I);
                 data_out(2, I) <= data_f2_out_swap(I);
                 data_out(3, I) <= data_f3_out_swap(I);
               END GENERATE all_bit_of_data_out;
               -----------------------------------------------------------------------------
               -- TODO : debug
               -----------------------------------------------------------------------------
               all_bit_of_time_out : FOR I IN 47 DOWNTO 0 GENERATE
                 all_sample_of_time_out : FOR J IN 3 DOWNTO 0 GENERATE
                   time_out_2(J, I) <= time_out(J)(I);
                 END GENERATE all_sample_of_time_out;
               END GENERATE all_bit_of_time_out;
               lpp_waveform_fifo_arbiter_1 : lpp_waveform_fifo_arbiter
                 GENERIC MAP (tech                   => tech,
                              nb_data_by_buffer_size => nb_data_by_buffer_size)
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   nb_data_by_buffer => nb_data_by_buffer,
                   data_in_valid     => valid_out,
                   data_in_ack       => valid_ack,
                   data_in           => data_out,
                   time_in           => time_out_2,
                   data_out     => wdata,
                   data_out_wen => data_wen,
                   full_almost  => full_almost,
                   full         => full,
                   time_out          => arbiter_time_out,
                   time_out_new      => arbiter_time_out_new
                   );
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               generate_all_fifo: FOR I IN 0 TO 3 GENERATE
                 lpp_fifo_1: lpp_fifo
                   GENERIC MAP (
                     tech                  => tech,
                     Mem_use               => use_RAM,
                     EMPTY_THRESHOLD_LIMIT => 15,
                     FULL_THRESHOLD_LIMIT  => 3,
                     DataSz                => 32,
                     AddrSz                => 7)
                   PORT MAP (
                     clk             => clk,
                     rstn            => rstn,
                     reUse           => '0',
                     run             => run,
                     ren             => data_ren(I),
                     rdata           => s_rdata_v((I+1)*32-1 downto I*32),
                     wen             => data_wen(I),
                     wdata           => wdata,
                     empty           => empty(I),
                     full            => full(I),
                     full_almost     => OPEN,
                     empty_threshold => empty_almost(I),
                     full_threshold  => full_almost(I) );
               END GENERATE generate_all_fifo;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               all_channel: FOR I IN 3 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN
                   IF rstn = '0' THEN
                     fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
                   ELSIF clk'event AND clk = '1' THEN
                     IF run = '0' THEN
                       fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= (OTHERS => '0');
                     ELSE
                       IF arbiter_time_out_new(I) = '0' THEN
                         fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I) <= arbiter_time_out;
                       END IF;
                     END IF;
                   END IF;
                 END PROCESS;
                 lpp_waveform_fsmdma_I: lpp_waveform_fsmdma
                   PORT MAP (
                     clk                  => clk,
                     rstn                 => rstn,
                     run                  => run,
                     fifo_buffer_time     => fifo_buffer_time(48*(I+1)-1 DOWNTO 48*I),
                     fifo_data            => s_rdata_v(32*(I+1)-1 DOWNTO 32*I),
                     fifo_empty           => empty(I),
                     fifo_empty_threshold => empty_almost(I),
                     fifo_ren             => data_ren(I),
                     dma_fifo_valid_burst => dma_fifo_valid_burst(I),
                     dma_fifo_data        => dma_fifo_data(32*(I+1)-1 DOWNTO 32*I),
                     dma_fifo_ren         => dma_fifo_ren(I),
                     dma_buffer_new       => dma_buffer_new(I),
                     dma_buffer_addr      => dma_buffer_addr(32*(I+1)-1 DOWNTO 32*I),
                     dma_buffer_length    => dma_buffer_length(26*(I+1)-1 DOWNTO 26*I),
                     dma_buffer_full      => dma_buffer_full(I),
                     dma_buffer_full_err  => dma_buffer_full_err(I),
                     status_buffer_ready  => status_buffer_ready(I),                 -- TODO
                     addr_buffer          => addr_buffer(32*(I+1)-1 DOWNTO 32*I),    -- TODO
                     length_buffer        => length_buffer,--(26*(I+1)-1 DOWNTO 26*I),  -- TODO
                     ready_buffer         => ready_buffer(I),                        -- TODO
                     buffer_time          => buffer_time(48*(I+1)-1 DOWNTO 48*I),    -- TODO
                     error_buffer_full    => error_buffer_full(I));                  -- TODO
               END GENERATE all_channel;
             END beh;

lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter.vhd +5 -6

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Jean-christophe PELLION
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.std_logic_1164.ALL;
             USE IEEE.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY lpp_waveform_fifo_arbiter IS
               GENERIC(
                 tech : INTEGER := 0;
                 nb_data_by_buffer_size : INTEGER := 11
                 );
               PORT(
                 clk               : IN  STD_LOGIC;
                 rstn              : IN  STD_LOGIC;
                 ---------------------------------------------------------------------------
                 run               : IN  STD_LOGIC;
                 nb_data_by_buffer : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- SNAPSHOT INTERFACE (INPUT)
                 ---------------------------------------------------------------------------
                 data_in_valid     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 data_in_ack       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 data_in           : IN  Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
                 time_in           : IN  Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- FIFO INTERFACE (OUTPUT)
                 ---------------------------------------------------------------------------
                 data_out     : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                 data_out_wen : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                 full_almost  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 full         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                 ---------------------------------------------------------------------------
                 -- TIME INTERFACE (OUTPUT)
                 ---------------------------------------------------------------------------
                 time_out     : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                 time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
                 );
             END ENTITY;
             ARCHITECTURE ar_lpp_waveform_fifo_arbiter OF lpp_waveform_fifo_arbiter IS
               TYPE state_type_fifo_arbiter IS (IDLE,DATA1,DATA2,DATA3,LAST);
               SIGNAL state : state_type_fifo_arbiter;
               -----------------------------------------------------------------------------
               -- DATA MUX
               -----------------------------------------------------------------------------
               TYPE WORD_VECTOR IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(31 DOWNTO 0);
-              SIGNAL data_0   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_0   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_1   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_1   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_2   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_2   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_3   : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_3   : WORD_VECTOR(2 DOWNTO 0);
-              SIGNAL data_sel : WORD_VECTOR(3 DOWNTO 0);
+              SIGNAL data_sel : WORD_VECTOR(2 DOWNTO 0);
               -----------------------------------------------------------------------------
               -- RR and SELECTION
               -----------------------------------------------------------------------------
               SIGNAL valid_in_rr : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL sel         : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL sel_s         : STD_LOGIC_VECTOR(3 DOWNTO 0);
               SIGNAL sel_reg : STD_LOGIC;
               SIGNAL sel_ack : STD_LOGIC;
               SIGNAL no_sel      : STD_LOGIC;
               -----------------------------------------------------------------------------
               -- REG
               -----------------------------------------------------------------------------
               SIGNAL count_enable : STD_LOGIC;
               SIGNAL count        : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL count_s      : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
               SIGNAL time_sel : STD_LOGIC_VECTOR(47 DOWNTO 0);
             BEGIN
               -----------------------------------------------------------------------------
               -- CONTROL
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                    -- asynchronous reset (active low)
                   count_enable      <= '0';
                   data_in_ack       <= (OTHERS => '0');
                   data_out_wen      <= (OTHERS => '1');
                   sel_ack           <= '0';
                   state             <= IDLE;
                   time_out          <= (OTHERS => '0');
                   time_out_new      <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN    -- rising clock edge
                   count_enable      <= '0';
                   data_in_ack       <= (OTHERS => '0');
                   data_out_wen      <= (OTHERS => '1');
                   sel_ack           <= '0';
                   time_out_new      <= (OTHERS => '0');
                   IF run = '0'  THEN
                     state             <= IDLE;
                     time_out     <= (OTHERS => '0');
                   ELSE
                     CASE state IS
                       WHEN IDLE  =>
                         IF no_sel = '0' THEN
                           state <= DATA1;
                         END IF;
                       WHEN DATA1 =>
                         count_enable <= '1';
                         IF UNSIGNED(count) = 0 THEN
                           time_out     <= time_sel;
                           time_out_new <= sel;
                         END IF;
                         data_out_wen <= NOT sel;
                         data_out     <= data_sel(0);
                         state        <= DATA2;
                       WHEN DATA2 =>
                         data_out_wen <= NOT sel;
                         data_out     <= data_sel(1);
                         state        <= DATA3;
                       WHEN DATA3 =>
                         data_out_wen <= NOT sel;
                         data_out     <= data_sel(2);
                         state        <= LAST;
                         data_in_ack  <= sel;
                       WHEN LAST =>
                         state         <= IDLE;
                         sel_ack       <= '1';
                       WHEN OTHERS => NULL;
                     END CASE;
                   END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -----------------------------------------------------------------------------
               -- DATA MUX
               -----------------------------------------------------------------------------
               all_word: FOR J IN 2 DOWNTO 0 GENERATE
                 all_data_bit: FOR I IN 31 DOWNTO 0 GENERATE
                     data_0(J)(I) <= data_in(0,I+32*J);
                     data_1(J)(I) <= data_in(1,I+32*J);
                     data_2(J)(I) <= data_in(2,I+32*J);
                     data_3(J)(I) <= data_in(3,I+32*J);
                 END GENERATE all_data_bit;
               END GENERATE all_word;
               data_sel <= data_0 WHEN sel(0) = '1' ELSE
                           data_1 WHEN sel(1) = '1' ELSE
                           data_2 WHEN sel(2) = '1' ELSE
                           data_3;
               all_time_bit: FOR I IN 47 DOWNTO 0 GENERATE
                 time_sel(I) <= time_in(0,I) WHEN sel(0) = '1' ELSE
                                time_in(1,I) WHEN sel(1) = '1' ELSE
                                time_in(2,I) WHEN sel(2) = '1' ELSE
                                time_in(3,I);
               END GENERATE all_time_bit;
               -----------------------------------------------------------------------------
               -- RR and SELECTION
               -----------------------------------------------------------------------------
               all_input_rr : FOR I IN 3 DOWNTO 0 GENERATE
                 valid_in_rr(I) <= data_in_valid(I) AND NOT full_almost(I);
               END GENERATE all_input_rr;
               RR_Arbiter_4_1 : RR_Arbiter_4
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   in_valid  => valid_in_rr,
                   out_grant => sel_s);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sel <= "0000";
                   sel_reg <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF run = '0' THEN
                     sel <= "0000";
                     sel_reg <= '0';
                   ELSE
                     IF sel_reg = '0' OR sel_ack = '1' THEN
                       sel <= sel_s;
                       IF sel_s = "0000" THEN
                         sel_reg <= '0';
                       ELSE
                         sel_reg <= '1';
                       END IF;
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               no_sel <= '1' WHEN sel = "0000" ELSE '0';
               -----------------------------------------------------------------------------
               -- REG
               -----------------------------------------------------------------------------
               reg_count_i: lpp_waveform_fifo_arbiter_reg
                 GENERIC MAP (
                   data_size => nb_data_by_buffer_size,
                   data_nb   => 4)
                 PORT MAP (
                   clk       => clk,
                   rstn      => rstn,
                   run       => run,
                   max_count => nb_data_by_buffer,
                   enable    => count_enable,
                   sel       => sel,
                   data      => count,
                   data_s    => count_s);
             END ARCHITECTURE;

lib/lpp/lpp_waveform/lpp_waveform_fifo_arbiter_reg.vhd +1 -2

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             ------------------------------------------------------------------------------
             --                    Author : Jean-christophe PELLION
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             ------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.std_logic_1164.ALL;
             USE IEEE.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.lpp_waveform_pkg.ALL;
             USE lpp.general_purpose.ALL;
             ENTITY lpp_waveform_fifo_arbiter_reg IS
               GENERIC(
                 data_size : INTEGER;
                 data_nb   : INTEGER);
               PORT(
                 clk  : IN STD_LOGIC;
                 rstn : IN STD_LOGIC;
                 ---------------------------------------------------------------------------
                 run  : IN STD_LOGIC;
                 max_count : IN STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
                 enable : IN STD_LOGIC;
                 sel    : IN STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
                 data   : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                 data_s : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0)
                 );
             END ENTITY;
             ARCHITECTURE ar_lpp_waveform_fifo_arbiter_reg OF lpp_waveform_fifo_arbiter_reg IS
               TYPE   Counter_Vector IS ARRAY (NATURAL RANGE <>) OF INTEGER;
               SIGNAL reg : Counter_Vector(data_nb-1 DOWNTO 0);
               SIGNAL reg_sel   : INTEGER := 0;
               SIGNAL reg_sel_s : INTEGER := 0;
             BEGIN
               all_reg : FOR I IN data_nb-1 DOWNTO 0 GENERATE
                 PROCESS (clk, rstn)
                 BEGIN  -- PROCESS
                   IF rstn = '0' THEN                  -- asynchronous reset (active low)
                     reg(I) <= 0;
                   ELSIF clk'EVENT AND clk = '1' THEN  -- rising clock edge
                     IF run = '0' THEN
                       reg(I) <= 0;
                     ELSE
                       IF sel(I) = '1' THEN
                         reg(I) <= reg_sel_s;
                       END IF;
                     END IF;
                   END IF;
                 END PROCESS;
               END GENERATE all_reg;
               reg_sel <= reg(0) WHEN sel(0) = '1' ELSE
                          reg(1) WHEN sel(1) = '1' ELSE
                          reg(2) WHEN sel(2) = '1' ELSE
                          reg(3);
-              reg_sel_s <= reg_sel WHEN enable = '0' ELSE
+              reg_sel_s <= reg_sel     WHEN enable = '0' ELSE
                            reg_sel + 1 WHEN reg_sel < UNSIGNED(max_count) ELSE
 ;
               data   <= STD_LOGIC_VECTOR(to_unsigned(reg_sel , data_size));
               data_s <= STD_LOGIC_VECTOR(to_unsigned(reg_sel_s, data_size));
             END ARCHITECTURE;

lib/lpp/lpp_waveform/lpp_waveform_pkg.vhd +1 -1

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             -- Author : Jean-christophe Pellion
             -- Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --          jean-christophe.pellion@easii-ic.com
             -------------------------------------------------------------------------------
             LIBRARY IEEE;
             USE IEEE.STD_LOGIC_1164.ALL;
             LIBRARY grlib;
             USE grlib.amba.ALL;
             USE grlib.stdlib.ALL;
             USE grlib.devices.ALL;
             USE GRLIB.DMA2AHB_Package.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             PACKAGE lpp_waveform_pkg IS
               TYPE LPP_TYPE_ADDR_FIFO_WAVEFORM IS ARRAY (NATURAL RANGE <>) OF STD_LOGIC_VECTOR(6 DOWNTO 0);
               TYPE Data_Vector IS ARRAY (NATURAL RANGE <>, NATURAL RANGE <>) OF STD_LOGIC;
               -----------------------------------------------------------------------------
               -- SNAPSHOT
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_snapshot
                 GENERIC (
                   data_size              : INTEGER;
                   nb_snapshot_param_size : INTEGER);
                 PORT (
                   clk               : IN  STD_LOGIC;
                   rstn              : IN  STD_LOGIC;
                   run               : IN  STD_LOGIC;
                   enable            : IN  STD_LOGIC;
                   burst_enable      : IN  STD_LOGIC;
                   nb_snapshot_param : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   start_snapshot    : IN  STD_LOGIC;
                   data_in           : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_in_valid     : IN  STD_LOGIC;
                   data_out          : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_out_valid    : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_waveform_burst
                 GENERIC (
                   data_size : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   enable         : IN  STD_LOGIC;
                   data_in        : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_in_valid  : IN  STD_LOGIC;
                   data_out       : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_out_valid : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_waveform_snapshot_controler
                 GENERIC (
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER);
                 PORT (
                   clk                : IN  STD_LOGIC;
                   rstn               : IN  STD_LOGIC;
                   reg_run            : IN  STD_LOGIC;
                   reg_start_date     : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   reg_delta_snapshot : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0       : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0_2     : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f1       : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f2       : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   coarse_time        : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   data_f0_valid      : IN  STD_LOGIC;
                   data_f2_valid      : IN  STD_LOGIC;
                   start_snapshot_f0  : OUT STD_LOGIC;
                   start_snapshot_f1  : OUT STD_LOGIC;
                   start_snapshot_f2  : OUT STD_LOGIC;
                   wfp_on             : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               --
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform
                 GENERIC (
                   tech                   : INTEGER;
                   data_size              : INTEGER;
                   nb_data_by_buffer_size : INTEGER;
                   nb_snapshot_param_size : INTEGER;
                   delta_vector_size      : INTEGER;
                   delta_vector_size_f0_2 : INTEGER);
                 PORT (
                   clk                          : IN  STD_LOGIC;
                   rstn                         : IN  STD_LOGIC;
                   reg_run                      : IN  STD_LOGIC;
                   reg_start_date               : IN  STD_LOGIC_VECTOR(30 DOWNTO 0);
                   reg_delta_snapshot           : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f0_2               : IN  STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0);
                   reg_delta_f1                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   reg_delta_f2                 : IN  STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0);
                   enable_f0                    : IN  STD_LOGIC;
                   enable_f1                    : IN  STD_LOGIC;
                   enable_f2                    : IN  STD_LOGIC;
                   enable_f3                    : IN  STD_LOGIC;
                   burst_f0                     : IN  STD_LOGIC;
                   burst_f1                     : IN  STD_LOGIC;
                   burst_f2                     : IN  STD_LOGIC;
                   nb_data_by_buffer            : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   nb_snapshot_param            : IN  STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0);
                   status_new_err               : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_buffer_ready : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
-                  addr_buffer         : IN STD_LOGIC_VECTOR(32*4 DOWNTO 0);
+                  addr_buffer         : IN STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   length_buffer       : IN STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_buffer        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   buffer_time         : OUT STD_LOGIC_VECTOR(48*4-1 DOWNTO 0);
                   error_buffer_full   : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   coarse_time                  : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fine_time                    : IN  STD_LOGIC_VECTOR(15 DOWNTO 0);
                   data_f0_in_valid             : IN  STD_LOGIC;
                   data_f0_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_f1_in_valid             : IN  STD_LOGIC;
                   data_f1_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_f2_in_valid             : IN  STD_LOGIC;
                   data_f2_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_f3_in_valid             : IN  STD_LOGIC;
                   data_f3_in                   : IN  STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   dma_fifo_valid_burst : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_fifo_data        : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   dma_fifo_ren         : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_buffer_new       : OUT  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_buffer_addr      : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0);
                   dma_buffer_length    : OUT STD_LOGIC_VECTOR(26*4-1 DOWNTO 0);
                   dma_buffer_full      : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   dma_buffer_full_err  : IN  STD_LOGIC_VECTOR(3 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_waveform_dma_genvalid
                 PORT (
                   HCLK      : IN  STD_LOGIC;
                   HRESETn   : IN  STD_LOGIC;
                   run       : IN  STD_LOGIC;
                   valid_in  : IN  STD_LOGIC;
                   ack_in    : IN  STD_LOGIC;
                   time_in   : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   valid_out : OUT STD_LOGIC;
                   time_out  : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   error     : OUT STD_LOGIC);
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- FIFO
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_fifo_ctrl
                 GENERIC (
                   offset : INTEGER;
                   length : INTEGER);
                 PORT (
                   clk          : IN  STD_LOGIC;
                   rstn         : IN  STD_LOGIC;
                   run          : IN  STD_LOGIC;
                   ren          : IN  STD_LOGIC;
                   wen          : IN  STD_LOGIC;
                   mem_re       : OUT STD_LOGIC;
                   mem_we       : OUT STD_LOGIC;
                   mem_addr_ren : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
                   mem_addr_wen : OUT STD_LOGIC_VECTOR(6 DOWNTO 0);
                   empty_almost : OUT STD_LOGIC;
                   empty        : OUT STD_LOGIC;
                   full_almost  : OUT STD_LOGIC;
                   full         : OUT STD_LOGIC);
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_arbiter
                 GENERIC (
                   tech                   : INTEGER;
                   nb_data_by_buffer_size : INTEGER);
                 PORT (
                   clk               : IN  STD_LOGIC;
                   rstn              : IN  STD_LOGIC;
                   run               : IN  STD_LOGIC;
                   nb_data_by_buffer : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size - 1 DOWNTO 0);
                   data_in_valid     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_in_ack       : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_in           : IN  Data_Vector(3 DOWNTO 0, 95 DOWNTO 0);
                   time_in           : IN  Data_Vector(3 DOWNTO 0, 47 DOWNTO 0);
                   data_out          : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_out_wen      : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full_almost       : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full              : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   time_out     : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   time_out_new : OUT STD_LOGIC_VECTOR(3 DOWNTO 0)
                   );
               END COMPONENT;
               COMPONENT lpp_waveform_fifo
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk          : IN  STD_LOGIC;
                   rstn         : IN  STD_LOGIC;
                   run          : IN  STD_LOGIC;
                   empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   rdata        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   full_almost  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full         : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_wen     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_headreg
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk            : IN  STD_LOGIC;
                   rstn           : IN  STD_LOGIC;
                   run            : IN  STD_LOGIC;
                   o_empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   o_empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   o_data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   o_rdata_0      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   o_rdata_1      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   o_rdata_2      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   o_rdata_3      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   i_empty_almost : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   i_empty        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   i_data_ren     : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   i_rdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_latencyCorrection
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk               : IN  STD_LOGIC;
                   rstn              : IN  STD_LOGIC;
                   run               : IN  STD_LOGIC;
                   empty_almost      : OUT STD_LOGIC;
                   empty             : OUT STD_LOGIC;
                   data_ren          : IN  STD_LOGIC;
                   rdata             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   empty_almost_fifo : IN  STD_LOGIC;
                   empty_fifo        : IN  STD_LOGIC;
                   data_ren_fifo     : OUT STD_LOGIC;
                   rdata_fifo        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fifo_withoutLatency
                 GENERIC (
                   tech : INTEGER);
                 PORT (
                   clk          : IN  STD_LOGIC;
                   rstn         : IN  STD_LOGIC;
                   run          : IN  STD_LOGIC;
                   empty_almost : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   empty        : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_ren     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   rdata_0      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   rdata_1      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   rdata_2      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   rdata_3      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   full_almost  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   full         : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_wen     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   wdata        : IN  STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- GEN ADDRESS
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_genaddress
                 GENERIC (
                   nb_data_by_buffer_size : INTEGER);
                 PORT (
                   clk                          : IN  STD_LOGIC;
                   rstn                         : IN  STD_LOGIC;
                   run                          : IN  STD_LOGIC;
                   nb_data_by_buffer            : IN  STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0);
                   addr_data_f0                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f1                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f2                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   addr_data_f3                 : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   empty                        : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   empty_almost                 : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_ren                     : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full                  : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_ack              : IN  STD_LOGIC_VECTOR(3 DOWNTO 0);
                   status_full_err              : OUT STD_LOGIC_VECTOR(3 DOWNTO 0);
                   data_f0_data_out_valid_burst : OUT STD_LOGIC;
                   data_f1_data_out_valid_burst : OUT STD_LOGIC;
                   data_f2_data_out_valid_burst : OUT STD_LOGIC;
                   data_f3_data_out_valid_burst : OUT STD_LOGIC;
                   data_f0_data_out_valid       : OUT STD_LOGIC;
                   data_f1_data_out_valid       : OUT STD_LOGIC;
                   data_f2_data_out_valid       : OUT STD_LOGIC;
                   data_f3_data_out_valid       : OUT STD_LOGIC;
                   data_f0_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f1_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f2_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   data_f3_addr_out             : OUT STD_LOGIC_VECTOR(31 DOWNTO 0));
               END COMPONENT;
               -----------------------------------------------------------------------------
               -- lpp_waveform_fifo_arbiter_reg
               -----------------------------------------------------------------------------
               COMPONENT lpp_waveform_fifo_arbiter_reg
                 GENERIC (
                   data_size : INTEGER;
                   data_nb   : INTEGER);
                 PORT (
                   clk       : IN  STD_LOGIC;
                   rstn      : IN  STD_LOGIC;
                   run       : IN  STD_LOGIC;
                   max_count : IN  STD_LOGIC_VECTOR(data_size -1 DOWNTO 0);
                   enable    : IN  STD_LOGIC;
                   sel       : IN  STD_LOGIC_VECTOR(data_nb-1 DOWNTO 0);
                   data      : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0);
                   data_s    : OUT STD_LOGIC_VECTOR(data_size-1 DOWNTO 0));
               END COMPONENT;
               COMPONENT lpp_waveform_fsmdma
                 PORT (
                   clk                  : IN  STD_ULOGIC;
                   rstn                 : IN  STD_ULOGIC;
                   run                  : IN  STD_LOGIC;
                   fifo_buffer_time     : IN  STD_LOGIC_VECTOR(47 DOWNTO 0);
                   fifo_data            : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   fifo_empty           : IN  STD_LOGIC;
                   fifo_empty_threshold : IN  STD_LOGIC;
                   fifo_ren             : OUT STD_LOGIC;
                   dma_fifo_valid_burst : OUT STD_LOGIC;
                   dma_fifo_data        : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_fifo_ren         : IN  STD_LOGIC;
                   dma_buffer_new       : OUT STD_LOGIC;
                   dma_buffer_addr      : OUT STD_LOGIC_VECTOR(31 DOWNTO 0);
                   dma_buffer_length    : OUT STD_LOGIC_VECTOR(25 DOWNTO 0);
                   dma_buffer_full      : IN  STD_LOGIC;
                   dma_buffer_full_err  : IN  STD_LOGIC;
                   status_buffer_ready  : IN  STD_LOGIC;
                   addr_buffer          : IN  STD_LOGIC_VECTOR(31 DOWNTO 0);
                   length_buffer        : IN  STD_LOGIC_VECTOR(25 DOWNTO 0);
                   ready_buffer         : OUT STD_LOGIC;
                   buffer_time          : OUT STD_LOGIC_VECTOR(47 DOWNTO 0);
                   error_buffer_full    : OUT STD_LOGIC);
               END COMPONENT;
             END lpp_waveform_pkg;

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