##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

[WFP] Register the DMA "send" signal to permit the start of 2 burst consecutively.
pellion -
r302:6b992ec40bf9 WaveFormPicker-0-0-10 (MINI-LFR) JC
parent child
Show More
Show file before | Show file after | Hide comments
@@ -20,4 +20,4 log -r *
20
20
21 do wave_waveform_longsim.do
21 do wave_waveform_longsim.do
22
22
23 run 500 ms
23 run 40 ms
Show file before | Show file after | Hide comments
@@ -19,6 +19,7 USE ieee.std_logic_1164.ALL;
19 LIBRARY grlib;
19 LIBRARY grlib;
20 USE grlib.amba.ALL;
20 USE grlib.amba.ALL;
21 USE grlib.stdlib.ALL;
21 USE grlib.stdlib.ALL;
22 USE grlib.AMBA_TestPackage.ALL;
22 LIBRARY gaisler;
23 LIBRARY gaisler;
23 USE gaisler.memctrl.ALL;
24 USE gaisler.memctrl.ALL;
24 USE gaisler.leon3.ALL;
25 USE gaisler.leon3.ALL;
@@ -224,7 +225,7 ARCHITECTURE behav OF testbench IS
224 -----------------------------------------------------------------------------
225 -----------------------------------------------------------------------------
225
226
226 SIGNAL current_data : INTEGER;
227 SIGNAL current_data : INTEGER;
227 SIGNAL LIMIT_DATA : INTEGER := 194;
228 SIGNAL LIMIT_DATA : INTEGER := 64;
228
229
229 SIGNAL read_buffer_temp : STD_LOGIC;
230 SIGNAL read_buffer_temp : STD_LOGIC;
230 SIGNAL read_buffer_temp_2 : STD_LOGIC;
231 SIGNAL read_buffer_temp_2 : STD_LOGIC;
@@ -367,6 +368,7 BEGIN
367 ADDR_BITS => 20,
368 ADDR_BITS => 20,
368 DATA_BITS => 16,
369 DATA_BITS => 16,
369 depth => 1048576,
370 depth => 1048576,
371 MEM_ARRAY_DEBUG => 194,
370 TimingInfo => TRUE,
372 TimingInfo => TRUE,
371 TimingChecks => '1')
373 TimingChecks => '1')
372 PORT MAP (
374 PORT MAP (
@@ -384,6 +386,7 BEGIN
384 ADDR_BITS => 20,
386 ADDR_BITS => 20,
385 DATA_BITS => 16,
387 DATA_BITS => 16,
386 depth => 1048576,
388 depth => 1048576,
389 MEM_ARRAY_DEBUG => 194,
387 TimingInfo => TRUE,
390 TimingInfo => TRUE,
388 TimingChecks => '1')
391 TimingChecks => '1')
389 PORT MAP (
392 PORT MAP (
@@ -430,16 +433,26 BEGIN
430 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
433 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F2 , X"40040000");
431 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
434 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_ADDRESS_F3 , X"40060000");
432
435
433 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT, X"00000080");--"00000020"
436 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000080");--"00000020"
434 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019"
437 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"00000060");--"00000019"
435 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
438 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
436 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
439 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"00000062");--"00000019"
437 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
440 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
438
439 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
441 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"0000003f"); -- X"00000010"
440 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000040");
441 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
443 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
442 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000c2");
444 APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"000000C2");-- 0xC2 = 64 * 3 + 2
445
446 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTASNAPSHOT , X"00000010");--"00000020"
447 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0 , X"0000000C");--"00000019"
448 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F0_2 , X"00000007");--"00000007"
449 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F1 , X"0000000C");--"00000019"
450 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_DELTA_F2 , X"00000001");--"00000001"
451 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_DATA_IN_BUFFER , X"00000007"); -- X"00000010"
452 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NBSNAPSHOT , X"00000008");
453 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_START_DATE , X"00000001");
454 --APB_WRITE(clk25MHz, INDEX_WAVEFORM_PICKER, apbi, ADDR_WAVEFORM_PICKER_NB_WORD_IN_BUFFER , X"0000001A");-- 0xC2 = 8 * 3 + 2
455
443
456
444
457
445 WAIT UNTIL clk25MHz = '1';
458 WAIT UNTIL clk25MHz = '1';
@@ -525,6 +538,20 BEGIN
525 WAIT UNTIL clk25MHz = '1';
538 WAIT UNTIL clk25MHz = '1';
526 IF read_buffer = '1' THEN
539 IF read_buffer = '1' THEN
527 state_read_buffer_on_going <= '1';
540 state_read_buffer_on_going <= '1';
541
542 --AHBRead(X"40000000",time_mem_f0(31 DOWNTO 0),clk25MHz,
543 --constant Address: in Std_Logic_Vector(31 downto 0);
544 --variable Data: out Std_Logic_Vector(31 downto 0);
545 --signal HCLK: in Std_ULogic;
546
547 --signal AHBIn: out AHB_Slv_In_Type;
548 --signal AHBOut: in AHB_Slv_Out_Type;
549 --variable TP: inout Boolean;
550 --constant InstancePath: in String := "AHBRead";
551 --constant ScreenOutput: in Boolean := False;
552 --constant cBack2Back: in Boolean := False;
553 --constant HINDEX: in Integer := 0;
554 --constant HMBINDEX: in Integer := 0);
528
555
529 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0));
556 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000", time_mem_f0(31 DOWNTO 0));
530 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0));
557 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000", time_mem_f1(31 DOWNTO 0));
@@ -534,44 +561,42 BEGIN
534 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32));
561 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020004", time_mem_f1(63 DOWNTO 32));
535 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32));
562 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040004", time_mem_f2(63 DOWNTO 32));
536
563
537 current_data <= 8;
564 current_data <= 0;
538 ELSE
565 ELSE
539 IF state_read_buffer_on_going = '1' THEN
566 IF state_read_buffer_on_going = '1' THEN
540 -- READ ALL DATA in memory
567 -- READ ALL DATA in memory
541 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
568 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8, data_mem_f0);
542 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
569 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8, data_mem_f1);
543 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
570 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8, data_mem_f2);
544 data_0_f0 <= data_mem_f0(15 DOWNTO 0);
571 data_0_f0 <= data_mem_f0(15 DOWNTO 0);
545 data_1_f0 <= data_mem_f0(31 DOWNTO 16);
572 data_1_f0 <= data_mem_f0(31 DOWNTO 16);
546 data_0_f1 <= data_mem_f1(15 DOWNTO 0);
573 data_0_f1 <= data_mem_f1(15 DOWNTO 0);
547 data_1_f1 <= data_mem_f1(31 DOWNTO 16);
574 data_1_f1 <= data_mem_f1(31 DOWNTO 16);
548 data_0_f2 <= data_mem_f2(15 DOWNTO 0);
575 data_0_f2 <= data_mem_f2(15 DOWNTO 0);
549 data_1_f2 <= data_mem_f2(31 DOWNTO 16);
576 data_1_f2 <= data_mem_f2(31 DOWNTO 16);
550 current_data <= current_data + 4;
551
577
552 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
578 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 4 + 8, data_mem_f0);
553 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
579 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 4 + 8, data_mem_f1);
554 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
580 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 4 + 8, data_mem_f2);
555 data_2_f0 <= data_mem_f0(15 DOWNTO 0);
581 data_2_f0 <= data_mem_f0(15 DOWNTO 0);
556 data_3_f0 <= data_mem_f0(31 DOWNTO 16);
582 data_3_f0 <= data_mem_f0(31 DOWNTO 16);
557 data_2_f1 <= data_mem_f1(15 DOWNTO 0);
583 data_2_f1 <= data_mem_f1(15 DOWNTO 0);
558 data_3_f1 <= data_mem_f1(31 DOWNTO 16);
584 data_3_f1 <= data_mem_f1(31 DOWNTO 16);
559 data_2_f2 <= data_mem_f2(15 DOWNTO 0);
585 data_2_f2 <= data_mem_f2(15 DOWNTO 0);
560 data_3_f2 <= data_mem_f2(31 DOWNTO 16);
586 data_3_f2 <= data_mem_f2(31 DOWNTO 16);
561 current_data <= current_data + 4;
562
587
563 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + current_data, data_mem_f0);
588 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40000000" + (current_data * 12) + 8 + 8, data_mem_f0);
564 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + current_data, data_mem_f1);
589 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40020000" + (current_data * 12) + 8 + 8, data_mem_f1);
565 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + current_data, data_mem_f2);
590 AHB_READ(clk25MHz, hindex, ahbmi, ahbmo(hindex), X"40040000" + (current_data * 12) + 8 + 8, data_mem_f2);
566 data_4_f0 <= data_mem_f0(15 DOWNTO 0);
591 data_4_f0 <= data_mem_f0(15 DOWNTO 0);
567 data_5_f0 <= data_mem_f0(31 DOWNTO 16);
592 data_5_f0 <= data_mem_f0(31 DOWNTO 16);
568 data_4_f1 <= data_mem_f1(15 DOWNTO 0);
593 data_4_f1 <= data_mem_f1(15 DOWNTO 0);
569 data_5_f1 <= data_mem_f1(31 DOWNTO 16);
594 data_5_f1 <= data_mem_f1(31 DOWNTO 16);
570 data_4_f2 <= data_mem_f2(15 DOWNTO 0);
595 data_4_f2 <= data_mem_f2(15 DOWNTO 0);
571 data_5_f2 <= data_mem_f2(31 DOWNTO 16);
596 data_5_f2 <= data_mem_f2(31 DOWNTO 16);
572 current_data <= current_data + 4;
597 current_data <= current_data + 1;
573
598
574 IF current_data > LIMIT_DATA THEN
599 IF current_data >= LIMIT_DATA THEN
575 state_read_buffer_on_going <= '0';
600 state_read_buffer_on_going <= '0';
576 time_mem_f0 <= (OTHERS => '0');
601 time_mem_f0 <= (OTHERS => '0');
577 time_mem_f1 <= (OTHERS => '0');
602 time_mem_f1 <= (OTHERS => '0');
Show file before | Show file after | Hide comments
@@ -1,120 +1,136
1
1
2 LIBRARY ieee;
2 LIBRARY ieee;
3 USE ieee.std_logic_1164.ALL;
3 USE ieee.std_logic_1164.ALL;
4 LIBRARY grlib;
4 LIBRARY grlib;
5 USE grlib.amba.ALL;
5 USE grlib.amba.ALL;
6 USE grlib.stdlib.ALL;
6 USE grlib.stdlib.ALL;
7 --LIBRARY gaisler;
7 --LIBRARY gaisler;
8 --USE gaisler.libdcom.ALL;
8 --USE gaisler.libdcom.ALL;
9 --USE gaisler.sim.ALL;
9 --USE gaisler.sim.ALL;
10 --USE gaisler.jtagtst.ALL;
10 --USE gaisler.jtagtst.ALL;
11 --LIBRARY techmap;
11 --LIBRARY techmap;
12 --USE techmap.gencomp.ALL;
12 --USE techmap.gencomp.ALL;
13
13
14
14
15 PACKAGE testbench_package IS
15 PACKAGE testbench_package IS
16
16
17 PROCEDURE APB_WRITE (
17 PROCEDURE APB_WRITE (
18 SIGNAL clk : IN STD_LOGIC;
18 SIGNAL clk : IN STD_LOGIC;
19 CONSTANT pindex : IN INTEGER;
19 CONSTANT pindex : IN INTEGER;
20 SIGNAL apbi : OUT apb_slv_in_type;
20 SIGNAL apbi : OUT apb_slv_in_type;
21 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
21 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
22 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
23 );
23 );
24
24
25 PROCEDURE APB_READ (
25 PROCEDURE APB_READ (
26 SIGNAL clk : IN STD_LOGIC;
26 SIGNAL clk : IN STD_LOGIC;
27 CONSTANT pindex : IN INTEGER;
27 CONSTANT pindex : IN INTEGER;
28 SIGNAL apbi : OUT apb_slv_in_type;
28 SIGNAL apbi : OUT apb_slv_in_type;
29 SIGNAL apbo : IN apb_slv_out_type;
29 SIGNAL apbo : IN apb_slv_out_type;
30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
30 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
31 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
32 );
32 );
33
33
34 PROCEDURE AHB_READ (
34 PROCEDURE AHB_READ (
35 SIGNAL clk : IN STD_LOGIC;
35 SIGNAL clk : IN STD_LOGIC;
36 CONSTANT hindex : IN INTEGER;
36 CONSTANT hindex : IN INTEGER;
37 SIGNAL ahbmi : IN ahb_mst_in_type;
37 SIGNAL ahbmi : IN ahb_mst_in_type;
38 SIGNAL ahbmo : OUT ahb_mst_out_type;
38 SIGNAL ahbmo : OUT ahb_mst_out_type;
39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
39 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
40 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
41 );
41 );
42
42
43 END testbench_package;
43 END testbench_package;
44
44
45 PACKAGE BODY testbench_package IS
45 PACKAGE BODY testbench_package IS
46
46
47 PROCEDURE APB_WRITE (
47 PROCEDURE APB_WRITE (
48 SIGNAL clk : IN STD_LOGIC;
48 SIGNAL clk : IN STD_LOGIC;
49 CONSTANT pindex : IN INTEGER;
49 CONSTANT pindex : IN INTEGER;
50 SIGNAL apbi : OUT apb_slv_in_type;
50 SIGNAL apbi : OUT apb_slv_in_type;
51 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
51 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
52 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
52 CONSTANT pwdata : IN STD_LOGIC_VECTOR(31 DOWNTO 0)
53 ) IS
53 ) IS
54 BEGIN
54 BEGIN
55 apbi.psel(pindex) <= '1';
55 apbi.psel(pindex) <= '1';
56 apbi.pwrite <= '1';
56 apbi.pwrite <= '1';
57 apbi.penable <= '1';
57 apbi.penable <= '1';
58 apbi.paddr <= paddr;
58 apbi.paddr <= paddr;
59 apbi.pwdata <= pwdata;
59 apbi.pwdata <= pwdata;
60 WAIT UNTIL clk = '1';
60 WAIT UNTIL clk = '0';
61 apbi.psel(pindex) <= '0';
61 WAIT UNTIL clk = '1';
62 apbi.pwrite <= '0';
62 apbi.psel(pindex) <= '0';
63 apbi.penable <= '0';
63 apbi.pwrite <= '0';
64 apbi.paddr <= (OTHERS => '0');
64 apbi.penable <= '0';
65 apbi.pwdata <= (OTHERS => '0');
65 apbi.paddr <= (OTHERS => '0');
66 WAIT UNTIL clk = '1';
66 apbi.pwdata <= (OTHERS => '0');
67
67 WAIT UNTIL clk = '0';
68 END APB_WRITE;
68 WAIT UNTIL clk = '1';
69
69
70 PROCEDURE APB_READ (
70 END APB_WRITE;
71 SIGNAL clk : IN STD_LOGIC;
71
72 CONSTANT pindex : IN INTEGER;
72 PROCEDURE APB_READ (
73 SIGNAL apbi : OUT apb_slv_in_type;
73 SIGNAL clk : IN STD_LOGIC;
74 SIGNAL apbo : IN apb_slv_out_type;
74 CONSTANT pindex : IN INTEGER;
75 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
75 SIGNAL apbi : OUT apb_slv_in_type;
76 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
76 SIGNAL apbo : IN apb_slv_out_type;
77 ) IS
77 CONSTANT paddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
78 BEGIN
78 SIGNAL prdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
79 apbi.psel(pindex) <= '1';
79 ) IS
80 apbi.pwrite <= '0';
80 BEGIN
81 apbi.penable <= '1';
81 apbi.psel(pindex) <= '1';
82 apbi.paddr <= paddr;
82 apbi.pwrite <= '0';
83 WAIT UNTIL clk = '1';
83 apbi.penable <= '1';
84 apbi.psel(pindex) <= '0';
84 apbi.paddr <= paddr;
85 apbi.pwrite <= '0';
85 WAIT UNTIL clk = '0';
86 apbi.penable <= '0';
86 WAIT UNTIL clk = '1';
87 apbi.paddr <= (OTHERS => '0');
87 apbi.psel(pindex) <= '0';
88 WAIT UNTIL clk = '1';
88 apbi.pwrite <= '0';
89 prdata <= apbo.prdata;
89 apbi.penable <= '0';
90 END APB_READ;
90 apbi.paddr <= (OTHERS => '0');
91
91 WAIT UNTIL clk = '0';
92 PROCEDURE AHB_READ (
92 WAIT UNTIL clk = '1';
93 SIGNAL clk : IN STD_LOGIC;
93 prdata <= apbo.prdata;
94 CONSTANT hindex : IN INTEGER;
94 END APB_READ;
95 SIGNAL ahbmi : IN ahb_mst_in_type;
95
96 SIGNAL ahbmo : OUT ahb_mst_out_type;
96 PROCEDURE AHB_READ (
97 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL clk : IN STD_LOGIC;
98 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
98 CONSTANT hindex : IN INTEGER;
99 ) IS
99 SIGNAL ahbmi : IN ahb_mst_in_type;
100 BEGIN
100 SIGNAL ahbmo : OUT ahb_mst_out_type;
101 ahbmo.HADDR <= haddr;
101 CONSTANT haddr : IN STD_LOGIC_VECTOR(31 DOWNTO 0);
102 ahbmo.HPROT <= "0011";
102 SIGNAL hrdata : OUT STD_LOGIC_VECTOR(31 DOWNTO 0)
103 ahbmo.HIRQ <= (OTHERS => '0');
103 ) IS
104 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
104 BEGIN
105 ahbmo.HINDEX <= hindex;
105 WAIT UNTIL clk = '1';
106 ahbmo.HBUSREQ <= '1';
106 ahbmo.HADDR <= haddr;
107 ahbmo.HLOCK <= '1';
107 ahbmo.HPROT <= "0011";
108 ahbmo.HSIZE <= HSIZE_WORD;
108 ahbmo.HIRQ <= (OTHERS => '0');
109 ahbmo.HBURST <= HBURST_SINGLE;
109 ahbmo.HCONFIG <= (0 => (OTHERS => '0'), OTHERS => (OTHERS => '0'));
110 ahbmo.HTRANS <= HTRANS_NONSEQ;
110 ahbmo.HINDEX <= hindex;
111 ahbmo.HWRITE <= '0';
111 ahbmo.HBUSREQ <= '1';
112 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
112 ahbmo.HLOCK <= '1';
113 hrdata <= ahbmi.HRDATA;
113 ahbmo.HSIZE <= HSIZE_WORD;
114 WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
114 ahbmo.HBURST <= HBURST_SINGLE;
115 ahbmo.HTRANS <= HTRANS_IDLE;
115 ahbmo.HTRANS <= HTRANS_NONSEQ;
116 ahbmo.HBUSREQ <= '0';
116 ahbmo.HWRITE <= '0';
117 ahbmo.HLOCK <= '0';
117 WHILE ahbmi.HREADY = '0' LOOP
118 END AHB_READ;
118 WAIT UNTIL clk = '1';
119
119 END LOOP;
120 END testbench_package;
120 WAIT UNTIL clk = '1';
121 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
122 ahbmo.HBUSREQ <= '0';
123 ahbmo.HLOCK <= '0';
124 ahbmo.HTRANS <= HTRANS_IDLE;
125 WHILE ahbmi.HREADY = '0' LOOP
126 WAIT UNTIL clk = '1';
127 END LOOP;
128 WAIT UNTIL clk = '1';
129 hrdata <= ahbmi.HRDATA;
130 --WAIT UNTIL clk = '1' AND ahbmi.HREADY = '1' AND ahbmi.HGRANT(hindex) = '1';
131 ahbmo.HLOCK <= '0';
132 WAIT UNTIL clk = '1';
133
134 END AHB_READ;
135
136 END testbench_package;
Show file before | Show file after | Hide comments
@@ -425,7 +425,7 BEGIN -- beh
425 pirq_ms => 6,
425 pirq_ms => 6,
426 pirq_wfp => 14,
426 pirq_wfp => 14,
427 hindex => 2,
427 hindex => 2,
428 top_lfr_version => X"00000F") -- aa.bb.cc version
428 top_lfr_version => X"000010") -- aa.bb.cc version
429 PORT MAP (
429 PORT MAP (
430 clk => clk_25,
430 clk => clk_25,
431 rstn => reset,
431 rstn => reset,
Show file before | Show file after | Hide comments
@@ -95,6 +95,13 ARCHITECTURE Behavioral OF lpp_dma_singl
95 SIGNAL burst_ren : STD_LOGIC;
95 SIGNAL burst_ren : STD_LOGIC;
96 -----------------------------------------------------------------------------
96 -----------------------------------------------------------------------------
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
97 SIGNAL data_2_halfword : STD_LOGIC_VECTOR(31 DOWNTO 0);
98 -----------------------------------------------------------------------------
99 -- \/ -- 20/02/2014 -- JC Pellion
100 SIGNAL send_reg : STD_LOGIC;
101 SIGNAL send_s : STD_LOGIC;
102 -- /\ --
103
104
98 BEGIN
105 BEGIN
99
106
100 debug_dmaout_okay <= DMAOut.OKAY;
107 debug_dmaout_okay <= DMAOut.OKAY;
@@ -121,14 +128,21 BEGIN
121 -----------------------------------------------------------------------------
128 -----------------------------------------------------------------------------
122
129
123 -----------------------------------------------------------------------------
130 -----------------------------------------------------------------------------
124 -----------------------------------------------------------------------------
131 -- \/ -- 20/02/2014 -- JC Pellion
125 -- LE PROBLEME EST LA !!!!!
132 PROCESS (HCLK, HRESETn)
126 -----------------------------------------------------------------------------
133 BEGIN
127 -----------------------------------------------------------------------------
134 IF HRESETn = '0' THEN
128 -- C'est le signal valid_burst qui n'est pas assez long.
135 send_reg <= '0';
129 -----------------------------------------------------------------------------
136 ELSIF HCLK'event AND HCLK = '1' THEN
130 single_send <= send WHEN valid_burst = '0' ELSE '0';
137 send_reg <= send;
131 burst_send <= send WHEN valid_burst = '1' ELSE '0';
138 END IF;
139 END PROCESS;
140 send_s <= send_reg;
141
142 single_send <= send_s WHEN valid_burst = '0' ELSE '0';
143 burst_send <= send_s WHEN valid_burst = '1' ELSE '0';
144 -- /\ --
145
132 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
146 DMAIn <= single_dmai WHEN valid_burst = '0' ELSE burst_dmai;
133
147
134 -- TODO : verifier
148 -- TODO : verifier
Show file before | Show file after | Hide comments
@@ -29,6 +29,8 ENTITY CY7C1061DV33 IS
29 DATA_BITS : INTEGER := 16;
29 DATA_BITS : INTEGER := 16;
30 depth : INTEGER := 1048576;
30 depth : INTEGER := 1048576;
31
31
32 MEM_ARRAY_DEBUG : INTEGER := 32;
33
32 TimingInfo : BOOLEAN := true;
34 TimingInfo : BOOLEAN := true;
33 TimingChecks : STD_LOGIC := '1'
35 TimingChecks : STD_LOGIC := '1'
34 );
36 );
@@ -68,7 +70,7 ARCHITECTURE behave_arch OF CY7C1061DV33
68 CONSTANT tskew : TIME := 1 ns;
70 CONSTANT tskew : TIME := 1 ns;
69
71
70 -------------------------------------------------------------------------------JC\/
72 -------------------------------------------------------------------------------JC\/
71 TYPE mem_array_type_t IS ARRAY (31 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
73 TYPE mem_array_type_t IS ARRAY (MEM_ARRAY_DEBUG-1 DOWNTO 0) OF STD_LOGIC_VECTOR(DATA_BITS-1 DOWNTO 0);
72 SIGNAL mem_array_0 : mem_array_type_t;
74 SIGNAL mem_array_0 : mem_array_type_t;
73 SIGNAL mem_array_1 : mem_array_type_t;
75 SIGNAL mem_array_1 : mem_array_type_t;
74 SIGNAL mem_array_2 : mem_array_type_t;
76 SIGNAL mem_array_2 : mem_array_type_t;
@@ -236,7 +238,7 BEGIN
236
238
237
239
238 -------------------------------------------------------------------------------JC\/
240 -------------------------------------------------------------------------------JC\/
239 all_mem_array_obs: FOR I IN 0 TO 31 LOOP
241 all_mem_array_obs: FOR I IN 0 TO MEM_ARRAY_DEBUG-1 LOOP
240 IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF;
242 IF I + ((2**15) *0) < depth THEN mem_array_0(I) <= mem_array(I+((2**15) *0)); END IF;
241 IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF;
243 IF I + ((2**15) *1) < depth THEN mem_array_1(I) <= mem_array(I+((2**15) *1)); END IF;
242 IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;
244 IF I + ((2**15) *2) < depth THEN mem_array_2(I) <= mem_array(I+((2**15) *2)); END IF;
General Comments 0
You need to be logged in to leave comments. Login now