@@ -0,0 +1,114 | |||
|
1 | ################################################################################ | |
|
2 | # SDC WRITER VERSION "3.1"; | |
|
3 | # DESIGN "LFR_EQM"; | |
|
4 | # Timing constraints scenario: "Primary"; | |
|
5 | # DATE "Fri Apr 24 16:02:16 2015"; | |
|
6 | # VENDOR "Actel"; | |
|
7 | # PROGRAM "Actel Designer Software Release v9.1 SP5"; | |
|
8 | # VERSION "9.1.5.1" Copyright (C) 1989-2012 Actel Corp. | |
|
9 | ################################################################################ | |
|
10 | ||
|
11 | ||
|
12 | set sdc_version 1.7 | |
|
13 | ||
|
14 | ||
|
15 | ######## Clock Constraints ######## | |
|
16 | ||
|
17 | create_clock -name { clk100MHz } -period 10.000 -waveform { 0.000 5.000 } { clk100MHz } | |
|
18 | ||
|
19 | create_clock -name { clk49_152MHz } -period 20.345 -waveform { 0.000 10.172 } { clk49_152MHz } | |
|
20 | ||
|
21 | create_clock -name { clk_25:Q } -period 40.000 -waveform { 0.000 20.000 } { clk_25:Q } | |
|
22 | ||
|
23 | create_clock -name { clk_24:Q } -period 40.690 -waveform { 0.000 20.345 } { clk_24:Q } | |
|
24 | ||
|
25 | create_clock -name { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.1.spw_phy0/rxclki_RNO:Y } | |
|
26 | ||
|
27 | create_clock -name { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } -period 100.000 -waveform { 0.000 50.000 } { spw_inputloop.0.spw_phy0/rxclki_RNO:Y } | |
|
28 | ||
|
29 | ||
|
30 | ||
|
31 | ######## Generated Clock Constraints ######## | |
|
32 | ||
|
33 | ||
|
34 | ||
|
35 | ######## Clock Source Latency Constraints ######### | |
|
36 | ||
|
37 | ||
|
38 | ||
|
39 | ######## Input Delay Constraints ######## | |
|
40 | ||
|
41 | set_input_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] | |
|
42 | set_max_delay 30.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \ | |
|
43 | data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \ | |
|
44 | data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \ | |
|
45 | data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}] | |
|
46 | set_min_delay 0.000 -from [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] \ | |
|
47 | data[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] \ | |
|
48 | data[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] \ | |
|
49 | data[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] -to [get_clocks {clk_25:Q}] | |
|
50 | ||
|
51 | #set_input_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BUSY }] | |
|
52 | #set_max_delay 10.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |
|
53 | #set_min_delay 0.000 -from [get_ports { nSRAM_BUSY }] -to [get_clocks {clk_25:Q}] | |
|
54 | ||
|
55 | ||
|
56 | ||
|
57 | ######## Output Delay Constraints ######## | |
|
58 | ||
|
59 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] SRAM_DQ[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] SRAM_DQ[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] SRAM_DQ[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] | |
|
60 | set_max_delay 18.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \ | |
|
61 | data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \ | |
|
62 | data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \ | |
|
63 | data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] | |
|
64 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_DQ[0] SRAM_DQ[10] SRAM_DQ[11] \ | |
|
65 | data[12] SRAM_DQ[13] SRAM_DQ[14] SRAM_DQ[15] SRAM_DQ[16] SRAM_DQ[17] SRAM_DQ[18] SRAM_DQ[19] SRAM_DQ[1] SRAM_DQ[20] \ | |
|
66 | data[21] SRAM_DQ[22] SRAM_DQ[23] SRAM_DQ[24] SRAM_DQ[25] SRAM_DQ[26] SRAM_DQ[27] SRAM_DQ[28] SRAM_DQ[29] SRAM_DQ[2] \ | |
|
67 | data[30] SRAM_DQ[31] SRAM_DQ[3] SRAM_DQ[4] SRAM_DQ[5] SRAM_DQ[6] SRAM_DQ[7] SRAM_DQ[8] SRAM_DQ[9] }] | |
|
68 | ||
|
69 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { SRAM_A[0] SRAM_A[10] SRAM_A[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] SRAM_A[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] SRAM_A[7] SRAM_A[8] SRAM_A[9] }] | |
|
70 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \ | |
|
71 | address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \ | |
|
72 | address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \ | |
|
73 | address[7] SRAM_A[8] SRAM_A[9] }] | |
|
74 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { SRAM_A[0] SRAM_A[10] \ | |
|
75 | address[11] SRAM_A[12] SRAM_A[13] SRAM_A[14] SRAM_A[15] SRAM_A[16] SRAM_A[17] \ | |
|
76 | address[18] SRAM_A[19] SRAM_A[1] SRAM_A[2] SRAM_A[3] SRAM_A[4] SRAM_A[5] SRAM_A[6] \ | |
|
77 | address[7] SRAM_A[8] SRAM_A[9] }] | |
|
78 | ||
|
79 | set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }] | |
|
80 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }] | |
|
81 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE[0] nSRAM_BE[1] nSRAM_BE[2] nSRAM_BE[3] nSRAM_WE nSRAM_CE nSRAM_OE }] | |
|
82 | ||
|
83 | ||
|
84 | ######## Delay Constraints ######## | |
|
85 | ||
|
86 | set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks { spw_inputloop.1.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] | |
|
87 | ||
|
88 | set_max_delay 4.000 -from [get_ports { SPW_RED_SIN SPW_RED_DIN SPW_NOM_SIN SPW_NOM_DIN reset }] -to [get_clocks {spw_inputloop.0.spw_phy0/ntstrxclk.rx_clkbuf/pa3e.pae30/buf1.buf_RNO:Y}] | |
|
89 | ||
|
90 | ||
|
91 | ######## Delay Constraints ######## | |
|
92 | ||
|
93 | ||
|
94 | ||
|
95 | ######## Multicycle Constraints ######## | |
|
96 | ||
|
97 | ||
|
98 | ||
|
99 | ######## False Path Constraints ######## | |
|
100 | ||
|
101 | ||
|
102 | ||
|
103 | ######## Output load Constraints ######## | |
|
104 | ||
|
105 | ||
|
106 | ||
|
107 | ######## Disable Timing Constraints ######### | |
|
108 | ||
|
109 | ||
|
110 | ||
|
111 | ######## Clock Uncertainty Constraints ######### | |
|
112 | ||
|
113 | ||
|
114 |
@@ -1,4 +1,4 | |||
|
1 | # Actel Physical design constraints file | |
|
1 | # Actel Physical design constraints file | |
|
2 | 2 | # Generated file |
|
3 | 3 | |
|
4 | 4 | # Version: 9.1 SP3 9.1.3.4 |
@@ -15,12 +15,12 | |||
|
15 | 15 | # I/O constraints |
|
16 | 16 | # |
|
17 | 17 | |
|
18 |
set_io clk |
|
|
18 | set_io clk100MHz \ | |
|
19 | 19 | -pinname F7 \ |
|
20 | 20 | -fixed yes \ |
|
21 | 21 | -DIRECTION Inout |
|
22 | 22 | |
|
23 |
set_io clk |
|
|
23 | set_io clk49_152MHz \ | |
|
24 | 24 | -pinname K14 \ |
|
25 | 25 | -fixed yes \ |
|
26 | 26 | -DIRECTION Inout |
@@ -77,8 +77,8 address[18] address[19] address[1] addre | |||
|
77 | 77 |
address[7] address[8] address[9] }] |
|
78 | 78 | |
|
79 | 79 |
set_output_delay 0.000 -clock { clk_25:Q } [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] |
|
80 |
set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] |
|
|
81 |
set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_E3 nSRAM_WE nSRAM_CE nSRAM_OE }] |
|
|
80 | set_max_delay 20.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] | |
|
81 | set_min_delay 0.000 -from [get_clocks {clk_25:Q}] -to [get_ports { nSRAM_BE0 nSRAM_BE1 nSRAM_BE2 nSRAM_BE3 nSRAM_WE nSRAM_CE nSRAM_OE }] | |
|
82 | 82 | |
|
83 | 83 | |
|
84 | 84 |
######## Delay Constraints ######## |
@@ -48,13 +48,8 USE lpp.lpp_leon3_soc_pkg.ALL; | |||
|
48 | 48 | ENTITY MINI_LFR_top IS |
|
49 | 49 | |
|
50 | 50 | PORT ( |
|
51 | ----------------------------------------------------------------------------- | |
|
52 | -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
|
53 | -- clk_50 frequency is 100 Mhz ! | |
|
54 | clk_50 : IN STD_LOGIC; | |
|
55 | -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! | |
|
56 | ----------------------------------------------------------------------------- | |
|
57 | clk_49 : IN STD_LOGIC; | |
|
51 | clk100MHz : IN STD_LOGIC; | |
|
52 | clk49_152MHz : IN STD_LOGIC; | |
|
58 | 53 | reset : IN STD_LOGIC; |
|
59 | 54 | --BPs |
|
60 | 55 | BP0 : IN STD_LOGIC; |
@@ -227,9 +222,9 BEGIN -- beh | |||
|
227 | 222 | ----------------------------------------------------------------------------- |
|
228 | 223 | -- WARNING !!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!! |
|
229 | 224 | -- clk_50 frequency is 100 Mhz ! |
|
230 |
PROCESS (clk |
|
|
225 | PROCESS (clk100MHz, reset) | |
|
231 | 226 | BEGIN -- PROCESS |
|
232 |
IF clk |
|
|
227 | IF clk100MHz'EVENT AND clk100MHz = '1' THEN -- rising clock edge | |
|
233 | 228 | clk_50_s <= NOT clk_50_s; |
|
234 | 229 | END IF; |
|
235 | 230 | END PROCESS; |
@@ -253,7 +248,7 BEGIN -- beh | |||
|
253 | 248 | END IF; |
|
254 | 249 | END PROCESS; |
|
255 | 250 | |
|
256 |
PROCESS (clk |
|
|
251 | PROCESS (clk49_152MHz, reset) | |
|
257 | 252 | BEGIN -- PROCESS |
|
258 | 253 | IF reset = '0' THEN -- asynchronous reset (active low) |
|
259 | 254 | clk_24 <= '0'; |
@@ -261,7 +256,7 BEGIN -- beh | |||
|
261 | 256 | rstn_24_d2 <= '0'; |
|
262 | 257 | rstn_24_d3 <= '0'; |
|
263 | 258 | rstn_24 <= '0'; |
|
264 |
ELSIF clk |
|
|
259 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge | |
|
265 | 260 | clk_24 <= NOT clk_24; |
|
266 | 261 | rstn_24_d1 <= '1'; |
|
267 | 262 | rstn_24_d2 <= rstn_24_d1; |
@@ -285,11 +280,11 BEGIN -- beh | |||
|
285 | 280 | END IF; |
|
286 | 281 | END PROCESS; |
|
287 | 282 | |
|
288 |
PROCESS (clk |
|
|
283 | PROCESS (clk49_152MHz, rstn_24) | |
|
289 | 284 | BEGIN -- PROCESS |
|
290 | 285 | IF rstn_24 = '0' THEN -- asynchronous reset (active low) |
|
291 | 286 | I00_s <= '0'; |
|
292 |
ELSIF clk |
|
|
287 | ELSIF clk49_152MHz'EVENT AND clk49_152MHz = '1' THEN -- rising clock edge | |
|
293 | 288 | I00_s <= NOT I00_s; |
|
294 | 289 | END IF; |
|
295 | 290 | END PROCESS; |
@@ -298,6 +293,8 BEGIN -- beh | |||
|
298 | 293 | nCTS1 <= '1'; |
|
299 | 294 | nCTS2 <= '1'; |
|
300 | 295 | nDCD2 <= '1'; |
|
296 | -- No AHB UART | |
|
297 | RXD1 <= TXD1; | |
|
301 | 298 | |
|
302 | 299 | -- |
|
303 | 300 |
@@ -13,11 +13,9 SYNPOPT="set_option -pipe 0; set_option | |||
|
13 | 13 | VHDLSYNFILES= MINI_LFR_top.vhd |
|
14 | 14 | VHDLSIMFILES= testbench.vhd |
|
15 | 15 | SIMTOP=testbench |
|
16 |
|
|
|
17 |
|
|
|
18 |
|
|
|
19 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_synthesis.sdc | |
|
20 | SDC=$(VHDLIB)/boards/$(BOARD)/MINI_LFR_place_and_route.sdc | |
|
16 | PDC=$(VHDLIB)/boards/$(BOARD)/default.pdc | |
|
17 | SDCFILE=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc | |
|
18 | SDC=$(VHDLIB)/boards/$(BOARD)/MINI-LFR.sdc | |
|
21 | 19 | BITGEN=$(VHDLIB)/boards/$(BOARD)/default.ut |
|
22 | 20 | CLEAN=soft-clean |
|
23 | 21 |
General Comments 0
You need to be logged in to leave comments.
Login now