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1 | 1 | ------------------------------------------------------------------------------ |
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2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
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3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
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4 | 4 | -- |
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5 | 5 | -- This program is free software; you can redistribute it and/or modify |
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6 | 6 | -- it under the terms of the GNU General Public License as published by |
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7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
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8 | 8 | -- (at your option) any later version. |
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9 | 9 | -- |
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10 | 10 | -- This program is distributed in the hope that it will be useful, |
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11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
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12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
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13 | 13 | -- GNU General Public License for more details. |
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14 | 14 | -- |
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15 | 15 | -- You should have received a copy of the GNU General Public License |
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16 | 16 | -- along with this program; if not, write to the Free Software |
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17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------ |
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19 | -- Author : Martin Morlot | |
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19 | -- Author : Martin Morlot | |
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20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------ |
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22 | 22 | library ieee; |
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23 | 23 | use ieee.std_logic_1164.all; |
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24 | 24 | library grlib; |
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25 | 25 | use grlib.amba.all; |
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26 | 26 | use grlib.stdlib.all; |
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27 | 27 | use grlib.devices.all; |
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28 | 28 | library lpp; |
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29 | 29 | use lpp.lpp_amba.all; |
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30 | 30 | use lpp.apb_devices_list.all; |
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31 | 31 | use lpp.lpp_cna.all; |
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32 | 32 | |
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33 | 33 | --! Driver APB, va faire le lien entre l'IP VHDL du convertisseur et le bus Amba |
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34 | 34 | |
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35 | 35 | entity APB_CNA is |
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36 | 36 | generic ( |
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37 | 37 | pindex : integer := 0; |
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38 | 38 | paddr : integer := 0; |
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39 | 39 | pmask : integer := 16#fff#; |
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40 | 40 | pirq : integer := 0; |
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41 | 41 | abits : integer := 8); |
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42 | 42 | port ( |
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43 | 43 | clk : in std_logic; --! Horloge du composant |
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44 | 44 | rst : in std_logic; --! Reset general du composant |
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45 | 45 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
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46 | 46 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
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47 | 47 | SYNC : out std_logic; --! Signal de synchronisation du convertisseur |
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48 | 48 | SCLK : out std_logic; --! Horloge systeme du convertisseur |
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49 | 49 | DATA : out std_logic --! DonnοΏ½e numοΏ½rique sοΏ½rialisοΏ½ |
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50 | 50 | ); |
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51 | 51 | end APB_CNA; |
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52 | 52 | |
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53 | 53 | --! @details Les deux registres (apbi,apbo) permettent de gοΏ½rer la communication sur le bus |
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54 | 54 | --! et les sorties seront cablοΏ½es vers le convertisseur. |
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55 | 55 | |
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56 | 56 | architecture ar_APB_CNA of APB_CNA is |
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57 | 57 | |
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58 | 58 | constant REVISION : integer := 1; |
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59 | 59 | |
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60 | 60 | constant pconfig : apb_config_type := ( |
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61 | 61 | 0 => ahb_device_reg (VENDOR_LPP, LPP_CNA, 0, REVISION, 0), |
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62 | 62 | 1 => apb_iobar(paddr, pmask)); |
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63 | 63 | |
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64 | 64 | signal enable : std_logic; |
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65 | 65 | signal flag_sd : std_logic; |
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66 | 66 | |
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67 | 67 | type CNA_ctrlr_Reg is record |
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68 | 68 | CNA_Cfg : std_logic_vector(1 downto 0); |
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69 | 69 | CNA_Data : std_logic_vector(15 downto 0); |
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70 | 70 | end record; |
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71 | 71 | |
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72 | 72 | signal Rec : CNA_ctrlr_Reg; |
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73 | 73 | signal Rdata : std_logic_vector(31 downto 0); |
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74 | 74 | |
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75 | 75 | begin |
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76 | 76 | |
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77 | 77 | enable <= Rec.CNA_Cfg(0); |
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78 | 78 | Rec.CNA_Cfg(1) <= flag_sd; |
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79 | 79 | |
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80 | 80 | CONVERTER : entity Work.CNA_TabloC |
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81 | 81 | port map(clk,rst,enable,Rec.CNA_Data,SYNC,SCLK,flag_sd,Data); |
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82 | 82 | |
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83 | 83 | |
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84 | 84 | process(rst,clk) |
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85 | 85 | begin |
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86 | 86 | if(rst='0')then |
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87 | 87 | Rec.CNA_Data <= (others => '0'); |
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88 | 88 | |
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89 | 89 | elsif(clk'event and clk='1')then |
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90 | 90 | |
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91 | 91 | |
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92 | 92 | --APB Write OP |
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93 | 93 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
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94 | 94 | case apbi.paddr(abits-1 downto 2) is |
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95 | 95 | when "000000" => |
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96 | 96 | Rec.CNA_Cfg(0) <= apbi.pwdata(0); |
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97 | 97 | when "000001" => |
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98 | 98 | Rec.CNA_Data <= apbi.pwdata(15 downto 0); |
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99 | 99 | when others => |
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100 | 100 | null; |
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101 | 101 | end case; |
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102 | 102 | end if; |
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103 | 103 | |
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104 | 104 | --APB READ OP |
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105 | 105 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
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106 | 106 | case apbi.paddr(abits-1 downto 2) is |
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107 | 107 | when "000000" => |
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108 | 108 | Rdata(31 downto 2) <= X"ABCDEF5" & "00"; |
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109 | 109 | Rdata(1 downto 0) <= Rec.CNA_Cfg; |
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110 | 110 | when "000001" => |
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111 | 111 | Rdata(31 downto 16) <= X"FD18"; |
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112 | 112 | Rdata(15 downto 0) <= Rec.CNA_Data; |
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113 | 113 | when others => |
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114 | 114 | Rdata <= (others => '0'); |
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115 | 115 | end case; |
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116 | 116 | end if; |
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117 | 117 | |
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118 | 118 | end if; |
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119 | 119 | apbo.pconfig <= pconfig; |
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120 | 120 | end process; |
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121 | 121 | |
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122 | 122 | apbo.prdata <= Rdata when apbi.penable = '1'; |
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123 | 123 | end ar_APB_CNA; |
@@ -1,152 +1,146 | |||
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1 | 1 | ------------------------------------------------------------------------------ |
|
2 | 2 | -- This file is a part of the LPP VHDL IP LIBRARY |
|
3 | 3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS |
|
4 | 4 | -- |
|
5 | 5 | -- This program is free software; you can redistribute it and/or modify |
|
6 | 6 | -- it under the terms of the GNU General Public License as published by |
|
7 | 7 | -- the Free Software Foundation; either version 3 of the License, or |
|
8 | 8 | -- (at your option) any later version. |
|
9 | 9 | -- |
|
10 | 10 | -- This program is distributed in the hope that it will be useful, |
|
11 | 11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of |
|
12 | 12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the |
|
13 | 13 | -- GNU General Public License for more details. |
|
14 | 14 | -- |
|
15 | 15 | -- You should have received a copy of the GNU General Public License |
|
16 | 16 | -- along with this program; if not, write to the Free Software |
|
17 | 17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA |
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18 | 18 | ------------------------------------------------------------------------------ |
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19 | 19 | -- Author : Martin Morlot |
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20 | 20 | -- Mail : martin.morlot@lpp.polytechnique.fr |
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21 | 21 | ------------------------------------------------------------------------------ |
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22 | 22 | library ieee; |
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23 | 23 | use ieee.std_logic_1164.all; |
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24 | 24 | library grlib; |
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25 | 25 | use grlib.amba.all; |
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26 | 26 | use grlib.stdlib.all; |
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27 | 27 | use grlib.devices.all; |
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28 | 28 | library lpp; |
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29 | 29 | use lpp.lpp_amba.all; |
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30 | 30 | use lpp.apb_devices_list.all; |
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31 | 31 | use lpp.lpp_uart.all; |
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32 | 32 | |
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33 | 33 | --! Driver APB, va faire le lien entre l'IP VHDL de l'UART et le bus Amba |
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34 | 34 | |
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35 | 35 | entity APB_UART is |
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36 | 36 | generic ( |
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37 | 37 | pindex : integer := 0; |
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38 | 38 | paddr : integer := 0; |
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39 | 39 | pmask : integer := 16#fff#; |
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40 | 40 | pirq : integer := 0; |
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41 | 41 | abits : integer := 8; |
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42 | 42 | Data_sz : integer := 8); |
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43 | 43 | port ( |
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44 | 44 | clk : in std_logic; --! Horloge du composant |
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45 | 45 | rst : in std_logic; --! Reset general du composant |
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46 | 46 | apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus |
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47 | 47 | apbo : out apb_slv_out_type; --! Registre de gestion des sorties du bus |
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48 | 48 | TXD : out std_logic; --! Transmission sοΏ½rie, cοΏ½tοΏ½ composant |
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49 | 49 | RXD : in std_logic --! Reception sοΏ½rie, cοΏ½tοΏ½ composant |
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50 | 50 | ); |
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51 | 51 | end APB_UART; |
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52 | 52 | |
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53 | 53 | |
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54 | 54 | architecture ar_APB_UART of APB_UART is |
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55 | 55 | |
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56 | 56 | constant REVISION : integer := 1; |
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57 | 57 | |
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58 | 58 | constant pconfig : apb_config_type := ( |
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59 | 59 | 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0), |
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60 | 60 | 1 => apb_iobar(paddr, pmask)); |
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61 | 61 | |
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62 | 62 | signal NwData : std_logic; |
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63 | 63 | signal ACK : std_logic; |
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64 | 64 | signal Capture : std_logic; |
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65 | 65 | signal Send : std_logic; |
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66 | 66 | signal Sended : std_logic; |
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67 | 67 | |
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68 | 68 | type UART_ctrlr_Reg is record |
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69 | 69 | UART_Cfg : std_logic_vector(2 downto 0); |
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70 | 70 | UART_Wdata : std_logic_vector(7 downto 0); |
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71 | 71 | UART_Rdata : std_logic_vector(7 downto 0); |
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72 | 72 | UART_BTrig : std_logic_vector(11 downto 0); |
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73 | 73 | end record; |
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74 | 74 | |
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75 | 75 | signal Rec : UART_ctrlr_Reg; |
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76 | 76 | signal Rdata : std_logic_vector(31 downto 0); |
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77 | 77 | signal temp_ND : std_logic; |
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78 | 78 | |
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79 | 79 | begin |
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80 | 80 | |
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81 | 81 | Capture <= Rec.UART_Cfg(0); |
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82 | --ACK <= Rec.UART_Cfg(1); | |
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83 | --Send <= Rec.UART_Cfg(1); | |
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84 | 82 | Rec.UART_Cfg(1) <= Sended; |
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85 | 83 | Rec.UART_Cfg(2) <= NwData; |
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86 | 84 | |
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87 | 85 | |
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88 | 86 | COM0 : entity work.UART |
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89 | 87 | generic map (Data_sz) |
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90 | 88 | port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata); |
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91 | 89 | |
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92 | 90 | |
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93 | 91 | process(rst,clk) |
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94 | 92 | begin |
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95 | 93 | if(rst='0')then |
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96 | 94 | Rec.UART_Wdata <= (others => '0'); |
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97 | 95 | |
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98 | 96 | |
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99 | 97 | elsif(clk'event and clk='1')then |
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100 | 98 | temp_ND <= NwData; |
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101 | 99 | if(NwData='1' and temp_ND='1')then |
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102 | 100 | ACK <= '1'; |
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103 | 101 | else |
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104 | 102 | ACK <= '0'; |
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105 | 103 | end if; |
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106 | 104 | |
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107 | 105 | --APB Write OP |
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108 | 106 | if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then |
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109 | 107 | case apbi.paddr(7 downto 2) is |
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110 | 108 | when "000000" => |
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111 | 109 | Rec.UART_Cfg(0) <= apbi.pwdata(0); |
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112 | --Rec.UART_Cfg(1) <= apbi.pwdata(4); | |
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113 | 110 | when "000001" => |
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114 | 111 | Rec.UART_Wdata(7 downto 0) <= apbi.pwdata(7 downto 0); |
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115 | 112 | Send <= '1'; |
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116 | 113 | when others => |
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117 | 114 | null; |
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118 | 115 | end case; |
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119 | 116 | else |
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120 | 117 | Send <= '0'; |
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121 | 118 | end if; |
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122 | 119 | |
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123 | 120 | --APB READ OP |
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124 | 121 | if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then |
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125 | 122 | case apbi.paddr(7 downto 2) is |
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126 | 123 | when "000000" => |
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127 | 124 | Rdata(3 downto 0) <= "000" & Rec.UART_Cfg(0); |
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128 | 125 | Rdata(7 downto 4) <= "000" & Rec.UART_Cfg(1); |
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129 | 126 | Rdata(11 downto 8) <= "000" & Rec.UART_Cfg(2); |
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130 | 127 | Rdata(19 downto 12) <= X"EE"; |
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131 | 128 | Rdata(31 downto 20) <= Rec.UART_BTrig; |
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132 | 129 | when "000001" => |
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133 | 130 | Rdata(31 downto 8) <= X"EEEEEE"; |
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134 | 131 | Rdata(7 downto 0) <= Rec.UART_Wdata; |
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135 | 132 | when "000010" => |
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136 | 133 | Rdata(31 downto 8) <= X"EEEEEE"; |
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137 | 134 | Rdata(7 downto 0) <= Rec.UART_Rdata; |
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138 | --Ack <= '1'; | |
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139 | 135 | when others => |
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140 | 136 | Rdata <= (others => '0'); |
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141 | 137 | end case; |
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142 | --else | |
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143 | --Ack <= '0'; | |
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144 | 138 | end if; |
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145 | 139 | |
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146 | 140 | end if; |
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147 | 141 | apbo.pconfig <= pconfig; |
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148 | 142 | end process; |
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149 | 143 | |
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150 | 144 | apbo.prdata <= Rdata when apbi.penable = '1'; |
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151 | 145 | |
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152 | 146 | end ar_APB_UART; |
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