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1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_fifo_Driver -lapb_uart_Driver -lapb_gpio_Driver
25 INPUTFILE=main.c
26 EXEC=BenchFFT+Matrix V2.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
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1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_fifo_Driver.h"
4 #include "apb_uart_Driver.h"
5 #include "apb_fft_Driver.h"
6
7
8 int main()
9 {
10 int i=0;
11 int data1,data2;
12 char temp[256];
13 int Table[256];
14
15 int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE};
16 int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD} ;
17 int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF};
18 int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C};
19 int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E};
20
21 FFT_Device* fft0 = openFFT(0);
22 UART_Device* uart0 = openUART(0);
23 FIFO_Device* fifoIn = openFIFO(0);
24 FIFO_Device* fifoOut = openFIFO(1);
25
26 printf("\nDebut Main\n\n");
27
28 FftInput(TblSinA,fft0,delay); // raie en 3
29 FftInput(TblSinAB,fft0,delay);
30 FftInput(TblSinB,fft0,delay); // raie en 21
31 FftInput(TblSinBC,fft0,delay);
32 FftInput(TblSinC,fft0,delay); // raie en 5
33
34 while(i < 1600){
35
36 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
37
38 data1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
39 data2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
40 i++;
41
42 sprintf(temp,"%d\t%d\n\r",data1,data2);
43 uartputs(uart0,temp);
44 }
45 printf("\nFin Main\n\n");
46 return 0;
47 }
48
49
50
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1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
32 use work.fft_components.all;
33
34 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35
36 entity APB_FFT_half is
37 generic (
38 pindex : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
42 abits : integer := 8;
43 Data_sz : integer := 16
44 );
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 Ren : in std_logic;
49 ready : out std_logic;
50 valid : out std_logic;
51 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
52 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
53 OUTfill : out std_logic;
54 OUTwrite : out std_logic;
55 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 );
58 end entity;
59
60
61 architecture ar_APB_FFT_half of APB_FFT_half is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_FFT, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 signal Wen : std_logic;
70 signal load : std_logic;
71 signal d_valid : std_logic;
72 signal y_valid : std_logic;
73 signal y_rdy : std_logic;
74 signal read_y : std_logic;
75 signal fill : std_logic;
76 signal start : std_logic;
77 signal DataIn_re : std_logic_vector(Data_sz-1 downto 0);
78 signal DataIn_im : std_logic_vector(Data_sz-1 downto 0);
79
80 type FFT_ctrlr_Reg is record
81 FFT_Cfg : std_logic;
82 FFT_Wdata : std_logic_vector((2*Data_sz)-1 downto 0);
83 end record;
84
85 signal Rec : FFT_ctrlr_Reg;
86 signal Rdata : std_logic_vector(31 downto 0);
87
88 begin
89
90 Rec.FFT_Cfg <= fill;
91
92 DataIn_im <= Rec.FFT_Wdata(Data_sz-1 downto 0);
93 DataIn_re <= Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz);
94
95 Actel_FFT : CoreFFT
96 generic map(
97 LOGPTS => gLOGPTS,
98 LOGLOGPTS => gLOGLOGPTS,
99 WSIZE => gWSIZE,
100 TWIDTH => gTWIDTH,
101 DWIDTH => gDWIDTH,
102 TDWIDTH => gTDWIDTH,
103 RND_MODE => gRND_MODE,
104 SCALE_MODE => gSCALE_MODE,
105 PTS => gPTS,
106 HALFPTS => gHALFPTS,
107 inBuf_RWDLY => gInBuf_RWDLY)
108 port map(clk,start,rst,d_valid,read_y,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,y_valid,y_rdy);
109
110 -- Flags : Flag_Extremum
111 -- port map(clk,rst,load,y_rdy,fill,ready);
112
113 process(rst,clk)
114 begin
115 if(rst='0')then
116 Rec.FFT_Wdata <= (others => '0');
117 Wen <= '1';
118
119 elsif(clk'event and clk='1')then
120
121 --APB Write OP
122 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
123 case apbi.paddr(abits-1 downto 2) is
124 when "000001" =>
125 Wen <= '0';
126 Rec.FFT_Wdata(Data_sz-1 downto 0) <= (others => '0');
127 Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz) <= apbi.pwdata(Data_sz-1 downto 0);
128
129 when others =>
130 null;
131 end case;
132 else
133 Wen <= '1';
134 end if;
135
136 --APB Read OP
137 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
138 case apbi.paddr(abits-1 downto 2) is
139 when "000000" =>
140 Rdata(3 downto 0) <= "000" & Rec.FFT_Cfg;
141 Rdata(31 downto 4) <= (others => '0');
142
143 when others =>
144 Rdata <= (others => '0');
145 end case;
146 end if;
147
148 end if;
149 apbo.pconfig <= pconfig;
150 end process;
151
152 apbo.prdata <= Rdata when apbi.penable = '1';
153 d_valid <= not Wen;
154 read_y <= not Ren;
155 fill <= Load;
156 Ready <= y_rdy;
157 valid <= y_valid;
158 start <= not rst;
159
160 OUTfill <= Load;
161 OUTwrite <= not Wen;
162
163 end architecture; No newline at end of file
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@@ -0,0 +1,131
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity Linker_FFT_FIFO is
27 generic(
28 Data_sz : integer range 1 to 32 := 8
29 );
30 port(
31 clk : in std_logic;
32 rstn : in std_logic;
33 Ready : in std_logic;
34 Valid : in std_logic;
35 Full : in std_logic_vector(4 downto 0);
36 Data_re : in std_logic_vector(Data_sz-1 downto 0);
37 Data_im : in std_logic_vector(Data_sz-1 downto 0);
38 Read : out std_logic;
39 Write : out std_logic_vector(4 downto 0);
40 ReUse : out std_logic_vector(4 downto 0);
41 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
42 );
43 end entity;
44
45
46 architecture ar_Linker of Linker_FFT_FIFO is
47
48 type etat is (eX,e0,e1,e2,e3);
49 signal ect : etat;
50
51 signal FifoCpt : integer;
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
53
54 signal sFull : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56 signal sReady : std_logic;
57
58 begin
59
60 process(clk,rstn)
61 begin
62 if(rstn='0')then
63 ect <= e0;
64 Read <= '1';
65 Write <= (others => '1');
66 Reuse <= (others => '0');
67 FifoCpt <= 1;
68 sDATA <= (others => '0');
69
70 elsif(clk'event and clk='1')then
71 sReady <= Ready;
72
73 case ect is
74
75 when e0 =>
76 Write(FifoCpt-1) <= '1';
77 if(sReady='0' and Ready='1' and sfull='0')then
78 Read <= '0';
79 ect <= e1;
80 end if;
81
82 when e1 =>
83 Read <= '1';
84 if(Valid='1' and sfull='0')then
85 DataTmp <= Data_im;
86 sDATA <= Data_re;
87 Write(FifoCpt-1) <= '0';
88 ect <= e2;
89 elsif(sfull='1')then
90 ReUse(FifoCpt-1) <= '1';
91 ect <= eX;
92 end if;
93
94 when e2 =>
95 sDATA <= DataTmp;
96 ect <= e3;
97
98 when e3 =>
99 Write(FifoCpt-1) <= '1';
100 if(Ready='1' and sfull='0')then
101 Read <= '0';
102 ect <= e1;
103 end if;
104
105 when eX =>
106 if(FifoCpt=6)then
107 FifoCpt <= 1;
108 else
109 FifoCpt <= FifoCpt+1;
110 end if;
111 ect <= e0;
112
113 end case;
114 end if;
115 end process;
116
117 DATA <= sData & sData & sData & sData & sData;
118
119 with FifoCpt select
120 sFull <= Full(0) when 1,
121 Full(1) when 2,
122 Full(2) when 3,
123 Full(3) when 4,
124 Full(4) when 5,
125 '1' when others;
126
127 end architecture;
128
129
130
131
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@@ -0,0 +1,103
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity SM_5lppFIFO is
31 generic(
32 tech : integer := apa3;
33 Data_sz : integer range 1 to 32 := 16;
34 Addr_sz : integer range 2 to 12 := 8;
35 Enable_ReUse : std_logic := '0'
36 );
37 port(
38 rst : in std_logic;
39 wclk : in std_logic;
40 rclk : in std_logic;
41 ReUse : in std_logic_vector(4 downto 0);
42 wen : in std_logic_vector(4 downto 0);
43 ren : in std_logic_vector(4 downto 0);
44 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
45 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
46 full : out std_logic_vector(4 downto 0);
47 empty : out std_logic_vector(4 downto 0)
48 );
49 end entity;
50
51
52 architecture ar_SM_5lppFIFO of SM_5lppFIFO is
53
54 begin
55
56 fifoB1 : lpp_fifo
57 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
58 port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
59
60 fifoB2 : lpp_fifo
61 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
63
64 fifoB3 : lpp_fifo
65 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
66 port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
67
68 fifoE1 : lpp_fifo
69 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
70 port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
71
72 fifoE2 : lpp_fifo
73 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
74 port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
75
76
77 end architecture;
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
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@@ -23,15 +23,6
23 #define APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24 #include "apb_delay_Driver.h"
24 #include "apb_delay_Driver.h"
25
25
26 /*! \file apb_fft_Driver.h
27 \brief LPP FFT driver.
28
29 This library is written to work with LPP_APB_FFT VHDL module from LPP's FreeVHDLIB. It calculate a fast fourier transforms,
30 from an input data table.
31
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
34
35 #define FFT_Fill 0x00000001
26 #define FFT_Fill 0x00000001
36 #define FFT_Ready 0x00000010
27 #define FFT_Ready 0x00000010
37 #define Mask 0x0000FFFF
28 #define Mask 0x0000FFFF
@@ -40,9 +31,7
40 /*===================================================
31 /*===================================================
41 T Y P E S D E F
32 T Y P E S D E F
42 ====================================================*/
33 ====================================================*/
43 /*! \struct FFT_Driver
34
44 \brief Sturcture representing the fft registers
45 */
46 struct FFT_Driver
35 struct FFT_Driver
47 {
36 {
48 int ConfigReg;
37 int ConfigReg;
@@ -55,18 +44,11 typedef struct FFT_Driver FFT_Device;
55 /*===================================================
44 /*===================================================
56 F U N C T I O N S
45 F U N C T I O N S
57 ====================================================*/
46 ====================================================*/
58 /*! \fn FFT_Device* openFFT(int count);
59 \brief Return count FFT.
60
47
61 This Function scans APB devices table and returns count FFT.
62
63 \param count The number of the FFT you whant to get. For example if you have 3 FFTS on your SOC you want
64 to use FFT1 so count = 1.
65 \return The pointer to the device.
66 */
67 FFT_Device* openFFT(int count);
48 FFT_Device* openFFT(int count);
68 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
49 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
69 int FftOutput(int Tbl[],FFT_Device*);
50 int FftOutput(int Tbl[],FFT_Device*);
70
51
71
52
53
72 #endif
54 #endif
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@@ -35,21 +35,24 FFT_Device* openFFT(int count)
35
35
36 int FftInput(int * Tbl,FFT_Device* fft,DELAY_Device* delay)
36 int FftInput(int * Tbl,FFT_Device* fft,DELAY_Device* delay)
37 {
37 {
38 //printf("\nFftInput\n\n");
38 int i=0;
39 int i=0;
39
40
40 while((fft->ConfigReg & FFT_Fill) == FFT_Fill) // fill a 1
41 while((fft->ConfigReg & FFT_Fill) == FFT_Fill)// && (i<256)) // fill a 1
41 {
42 {
42 fft->RWDataReg = Tbl[i];
43 fft->RWDataReg = Tbl[i];
43 i++;
44 i++;
44 Delay_us(delay,1);
45 //Delay_us(delay,1);
45 }
46 }
46
47
48 //printf("\nEnd In %d\n\n",i);
47 return 0;
49 return 0;
48 }
50 }
49
51
50
52
51 int FftOutput(int * Tbl, FFT_Device* fft)
53 int FftOutput(int * Tbl, FFT_Device* fft)
52 {
54 {
55 //printf("\nFftOutput\n\n");
53 int i=0;
56 int i=0;
54 int data;
57 int data;
55
58
@@ -61,6 +64,7 int FftOutput(int * Tbl, FFT_Device* fft
61 i = i+2;
64 i = i+2;
62 }
65 }
63
66
67 //printf("\nEnd Out %d\n\n",i);
64 return i;
68 return i;
65 }
69 }
66
70
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@@ -23,15 +23,6
23 #define APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24 #include "apb_delay_Driver.h"
24 #include "apb_delay_Driver.h"
25
25
26 /*! \file apb_fft_Driver.h
27 \brief LPP FFT driver.
28
29 This library is written to work with LPP_APB_FFT VHDL module from LPP's FreeVHDLIB. It calculate a fast fourier transforms,
30 from an input data table.
31
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
34
35 #define FFT_Fill 0x00000001
26 #define FFT_Fill 0x00000001
36 #define FFT_Ready 0x00000010
27 #define FFT_Ready 0x00000010
37 #define Mask 0x0000FFFF
28 #define Mask 0x0000FFFF
@@ -40,9 +31,7
40 /*===================================================
31 /*===================================================
41 T Y P E S D E F
32 T Y P E S D E F
42 ====================================================*/
33 ====================================================*/
43 /*! \struct FFT_Driver
34
44 \brief Sturcture representing the fft registers
45 */
46 struct FFT_Driver
35 struct FFT_Driver
47 {
36 {
48 int ConfigReg;
37 int ConfigReg;
@@ -55,18 +44,11 typedef struct FFT_Driver FFT_Device;
55 /*===================================================
44 /*===================================================
56 F U N C T I O N S
45 F U N C T I O N S
57 ====================================================*/
46 ====================================================*/
58 /*! \fn FFT_Device* openFFT(int count);
59 \brief Return count FFT.
60
47
61 This Function scans APB devices table and returns count FFT.
62
63 \param count The number of the FFT you whant to get. For example if you have 3 FFTS on your SOC you want
64 to use FFT1 so count = 1.
65 \return The pointer to the device.
66 */
67 FFT_Device* openFFT(int count);
48 FFT_Device* openFFT(int count);
68 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
49 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
69 int FftOutput(int Tbl[],FFT_Device*);
50 int FftOutput(int Tbl[],FFT_Device*);
70
51
71
52
53
72 #endif
54 #endif
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@@ -45,8 +45,6 entity APB_FFT is
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 eload : out std_logic;
49 eready :out std_logic;
50 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
49 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
50 );
Show file before | Show file after | Hide comments
@@ -40,19 +40,42 component APB_FFT is
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Data_sz : integer := 32;
43 Data_sz : integer := 16
44 Addr_sz : integer := 8;
44 );
45 addr_max_int : integer := 256);
46 port (
45 port (
47 clk : in std_logic;
46 clk : in std_logic;
48 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
49 eload : out std_logic;
50 eready :out std_logic;
51 apbi : in apb_slv_in_type;
48 apbi : in apb_slv_in_type;
52 apbo : out apb_slv_out_type
49 apbo : out apb_slv_out_type
53 );
50 );
54 end component;
51 end component;
55
52
53
54 component APB_FFT_half is
55 generic (
56 pindex : integer := 0;
57 paddr : integer := 0;
58 pmask : integer := 16#fff#;
59 pirq : integer := 0;
60 abits : integer := 8;
61 Data_sz : integer := 16
62 );
63 port (
64 clk : in std_logic; --! Horloge du composant
65 rst : in std_logic; --! Reset general du composant
66 Ren : in std_logic;
67 ready : out std_logic;
68 valid : out std_logic;
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 OUTfill : out std_logic;
72 OUTwrite : out std_logic;
73 apbi : in apb_slv_in_type; --! Registre de gestion des entr�es du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 );
76 end component;
77
78
56 component Flag_Extremum is
79 component Flag_Extremum is
57 port(
80 port(
58 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
81 clk,raz : in std_logic; --! Horloge et Reset g�n�ral du composant
@@ -63,6 +86,26 component Flag_Extremum is
63 );
86 );
64 end component;
87 end component;
65
88
89
90 component Linker_FFT_FIFO is
91 generic(
92 Data_sz : integer range 1 to 32 := 16
93 );
94 port(
95 clk : in std_logic;
96 rstn : in std_logic;
97 Ready : in std_logic;
98 Valid : in std_logic;
99 Full : in std_logic_vector(4 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 Read : out std_logic;
103 Write : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 );
107 end component;
108
66 --==============================================================|
109 --==============================================================|
67 --================== IP VHDL de la FFT actel ===================|
110 --================== IP VHDL de la FFT actel ===================|
68 --================ non partag� dans la VHD_Lib =================|
111 --================ non partag� dans la VHD_Lib =================|
Show file before | Show file after | Hide comments
@@ -93,6 +93,29 port(
93 );
93 );
94 end component;
94 end component;
95
95
96
97 component SM_5lppFIFO is
98 generic(
99 tech : integer := 0;
100 Data_sz : integer range 1 to 32 := 16;
101 Addr_sz : integer range 2 to 12 := 8;
102 Enable_ReUse : std_logic := '0'
103 );
104 port(
105 rst : in std_logic;
106 wclk : in std_logic;
107 rclk : in std_logic;
108 ReUse : in std_logic_vector(4 downto 0);
109 wen : in std_logic_vector(4 downto 0);
110 ren : in std_logic_vector(4 downto 0);
111 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
112 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
113 full : out std_logic_vector(4 downto 0);
114 empty : out std_logic_vector(4 downto 0)
115 );
116 end component;
117
118
96 component ssram_plugin is
119 component ssram_plugin is
97 generic (tech : integer := 0);
120 generic (tech : integer := 0);
98 port
121 port
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