##// END OF EJS Templates
HG_REPOSITORIES » LPP » INSTRUMENTATION » VHD_Lib
RSS

Clone from https://hephaistos.lpp.polytechnique.fr/rhodecode/HG_REPOSITORIES/LPP/INSTRUMENTATION/USERS/PELLION/VHD_Lib

Data Line second version
martin -
r97:5dd8398817e7 martin
parent child
Show More
Show file before | Show file after | Hide comments
@@ -0,0 +1,44
1 #------------------------------------------------------------------------------
2 #-- This file is a part of the LPP VHDL IP LIBRARY
3 #-- Copyright (C) 2010, Laboratory of Plasmas Physic - CNRS
4 #--
5 #-- This program is free software; you can redistribute it and/or modify
6 #-- it under the terms of the GNU General Public License as published by
7 #-- the Free Software Foundation; either version 3 of the License, or
8 #-- (at your option) any later version.
9 #--
10 #-- This program is distributed in the hope that it will be useful,
11 #-- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 #-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 #-- GNU General Public License for more details.
14 #--
15 #-- You should have received a copy of the GNU General Public License
16 #-- along with this program; if not, write to the Free Software
17 #-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 #------------------------------------------------------------------------------
19
20 include ../../rules.mk
21 LIBDIR = ../../lib
22 INCPATH = ../../includes
23 SCRIPTDIR=../../scripts/
24 LIBS=-lapb_fft_Driver -llpp_apb_functions -lapb_fifo_Driver -lapb_uart_Driver -lapb_gpio_Driver
25 INPUTFILE=main.c
26 EXEC=BenchFFT+Matrix V2.bin
27 OUTBINDIR=bin/
28
29
30 .PHONY:bin
31
32 all:bin
33 @echo $(EXEC)" file created"
34
35 clean:
36 rm -f *.{o,a}
37
38
39
40 help:ruleshelp
41 @echo " all : makes an executable file called "$(EXEC)
42 @echo " in "$(OUTBINDIR)
43 @echo " clean : removes temporary files"
44
Show file before | Show file after | Hide comments
@@ -0,0 +1,50
1 #include <stdio.h>
2 #include "lpp_apb_functions.h"
3 #include "apb_fifo_Driver.h"
4 #include "apb_uart_Driver.h"
5 #include "apb_fft_Driver.h"
6
7
8 int main()
9 {
10 int i=0;
11 int data1,data2;
12 char temp[256];
13 int Table[256];
14
15 int TblSinA[256] = {0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE,0x0000,0x0142,0x0282,0x03C2,0x04FF,0x0638,0x076E,0x08A0,0x09CC,0x0AF2,0x0C11,0x0D29,0x0E39,0x0F40,0x103E,0x1131,0x121A,0x12F8,0x13CA,0x1490,0x1549,0x15F5,0x1694,0x1724,0x17A7,0x181B,0x187F,0x18D5,0x191C,0x1953,0x197A,0x1992,0x199A,0x1992,0x197A,0x1953,0x191C,0x18D5,0x187F,0x181B,0x17A7,0x1724,0x1694,0x15F5,0x1549,0x1490,0x13CA,0x12F8,0x121A,0x1131,0x103E,0x0F40,0x0E39,0x0D29,0x0C11,0x0AF2,0x09CC,0x08A0,0x076E,0x0638,0x04FF,0x03C2,0x0282,0x0142,0x0000,0xFEBE,0xFD7E,0xFC3E,0xFB01,0xF9C8,0xF892,0xF760,0xF634,0xF50E,0xF3EF,0xF2D7,0xF1C7,0xF0C0,0xEFC2,0xEECF,0xEDE6,0xED08,0xEC36,0xEB70,0xEAB7,0xEA0B,0xE96C,0xE8DC,0xE859,0xE7E5,0xE781,0xE72B,0xE6E4,0xE6AD,0xE686,0xE66E,0xE666,0xE66E,0xE686,0xE6AD,0xE6E4,0xE72B,0xE781,0xE7E5,0xE859,0xE8DC,0xE96C,0xEA0B,0xEAB7,0xEB70,0xEC36,0xED08,0xEDE6,0xEECF,0xEFC2,0xF0C0,0xF1C7,0xF2D7,0xF3EF,0xF50E,0xF634,0xF760,0xF892,0xF9C8,0xFB01,0xFC3E,0xFD7E,0xFEBE};
16 int TblSinAB[256] = {0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD,0x0000,0x0D53,0x17CB,0x1D3C,0x1CA5,0x1676,0x0C6D,0x0131,0xF7B2,0xF273,0xF2F6,0xF95F,0x046D,0x11C2,0x1E77,0x27C5,0x2BB4,0x298C,0x2203,0x1712,0x0B7D,0x022B,0xFD78,0xFEA5,0x058D,0x10AC,0x1D7E,0x2913,0x30C2,0x32CD,0x2EC3,0x25A3,0x199A,0x0D80,0x0431,0xFFD9,0x0175,0x0898,0x1381,0x1F89,0x29C1,0x2FA4,0x2FAF,0x29BF,0x1F15,0x120E,0x0591,0xFC64,0xF880,0xFA9D,0x0205,0x0CBE,0x1805,0x20F3,0x252D,0x2371,0x1BE6,0x100E,0x0270,0xF5FB,0xED58,0xEA48,0xED39,0xF530,0x0000,0x0AD0,0x12C7,0x15B8,0x12A8,0x0A05,0xFD90,0xEFF2,0xE41A,0xDC8F,0xDAD3,0xDF0D,0xE7FB,0xF342,0xFDFB,0x0563,0x0780,0x039C,0xFA6F,0xEDF2,0xE0EB,0xD641,0xD051,0xD05C,0xD63F,0xE077,0xEC7F,0xF768,0xFE8B,0x0027,0xFBCF,0xF280,0xE666,0xDA5D,0xD13D,0xCD33,0xCF3E,0xD6ED,0xE282,0xEF54,0xFA73,0x015B,0x0288,0xFDD5,0xF483,0xE8EE,0xDDFD,0xD674,0xD44C,0xD83B,0xE189,0xEE3E,0xFB93,0x06A1,0x0D0A,0x0D8D,0x084E,0xFECF,0xF393,0xE98A,0xE35B,0xE2C4,0xE835,0xF2AD} ;
17 int TblSinB[256] = {0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF,0x0000,0x0C11,0x1549,0x197A,0x17A7,0x103E,0x04FF,0xF892,0xEDE6,0xE781,0xE6E4,0xEC36,0xF634,0x0282,0x0E39,0x1694,0x199A,0x1694,0x0E39,0x0282,0xF634,0xEC36,0xE6E4,0xE781,0xEDE6,0xF892,0x04FF,0x103E,0x17A7,0x197A,0x1549,0x0C11,0x0000,0xF3EF,0xEAB7,0xE686,0xE859,0xEFC2,0xFB01,0x076E,0x121A,0x187F,0x191C,0x13CA,0x09CC,0xFD7E,0xF1C7,0xE96C,0xE666,0xE96C,0xF1C7,0xFD7E,0x09CC,0x13CA,0x191C,0x187F,0x121A,0x076E,0xFB01,0xEFC2,0xE859,0xE686,0xEAB7,0xF3EF};
18 int TblSinBC[256] = {0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C,0x0000,0x0E94,0x1A48,0x20E8,0x2173,0x1C4F,0x1338,0x08CF,0x0000,0xFB4B,0xFC2D,0x02CA,0x0DDB,0x1B02,0x2755,0x300E,0x3333,0x300E,0x2755,0x1B02,0x0DDB,0x02CA,0xFC2D,0xFB4B,0x0000,0x08CF,0x1338,0x1C4F,0x2173,0x20E8,0x1A48,0x0E94,0x0000,0xF16C,0xE5B8,0xDF18,0xDE8D,0xE3B1,0xECC8,0xF731,0x0000,0x04B5,0x03D3,0xFD36,0xF225,0xE4FE,0xD8AB,0xCFF2,0xCCCD,0xCFF2,0xD8AB,0xE4FE,0xF225,0xFD36,0x03D3,0x04B5,0x0000,0xF731,0xECC8,0xE3B1,0xDE8D,0xDF18,0xE5B8,0xF16C};
19 int TblSinC[256] = {0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E,0x0000,0x0282,0x04FF,0x076E,0x09CC,0x0C11,0x0E39,0x103E,0x121A,0x13CA,0x1549,0x1694,0x17A7,0x187F,0x191C,0x197A,0x199A,0x197A,0x191C,0x187F,0x17A7,0x1694,0x1549,0x13CA,0x121A,0x103E,0x0E39,0x0C11,0x09CC,0x076E,0x04FF,0x0282,0x0000,0xFD7E,0xFB01,0xF892,0xF634,0xF3EF,0xF1C7,0xEFC2,0xEDE6,0xEC36,0xEAB7,0xE96C,0xE859,0xE781,0xE6E4,0xE686,0xE666,0xE686,0xE6E4,0xE781,0xE859,0xE96C,0xEAB7,0xEC36,0xEDE6,0xEFC2,0xF1C7,0xF3EF,0xF634,0xF892,0xFB01,0xFD7E};
20
21 FFT_Device* fft0 = openFFT(0);
22 UART_Device* uart0 = openUART(0);
23 FIFO_Device* fifoIn = openFIFO(0);
24 FIFO_Device* fifoOut = openFIFO(1);
25
26 printf("\nDebut Main\n\n");
27
28 FftInput(TblSinA,fft0,delay); // raie en 3
29 FftInput(TblSinAB,fft0,delay);
30 FftInput(TblSinB,fft0,delay); // raie en 21
31 FftInput(TblSinBC,fft0,delay);
32 FftInput(TblSinC,fft0,delay); // raie en 5
33
34 while(i < 1600){
35
36 while((fifoOut->FIFOreg[(2*0)+FIFO_Ctrl] & FIFO_Empty) == FIFO_Empty); // TANT QUE empty a 1 RIEN
37
38 data1 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
39 data2 = fifoOut->FIFOreg[(2*0)+FIFO_RWdata];
40 i++;
41
42 sprintf(temp,"%d\t%d\n\r",data1,data2);
43 uartputs(uart0,temp);
44 }
45 printf("\nFin Main\n\n");
46 return 0;
47 }
48
49
50
Show file before | Show file after | Hide comments
@@ -0,0 +1,163
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library ieee;
23 use ieee.std_logic_1164.all;
24 library grlib;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
28 library lpp;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
32 use work.fft_components.all;
33
34 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35
36 entity APB_FFT_half is
37 generic (
38 pindex : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
42 abits : integer := 8;
43 Data_sz : integer := 16
44 );
45 port (
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
48 Ren : in std_logic;
49 ready : out std_logic;
50 valid : out std_logic;
51 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
52 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
53 OUTfill : out std_logic;
54 OUTwrite : out std_logic;
55 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
56 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
57 );
58 end entity;
59
60
61 architecture ar_APB_FFT_half of APB_FFT_half is
62
63 constant REVISION : integer := 1;
64
65 constant pconfig : apb_config_type := (
66 0 => ahb_device_reg (VENDOR_LPP, LPP_FFT, 0, REVISION, 0),
67 1 => apb_iobar(paddr, pmask));
68
69 signal Wen : std_logic;
70 signal load : std_logic;
71 signal d_valid : std_logic;
72 signal y_valid : std_logic;
73 signal y_rdy : std_logic;
74 signal read_y : std_logic;
75 signal fill : std_logic;
76 signal start : std_logic;
77 signal DataIn_re : std_logic_vector(Data_sz-1 downto 0);
78 signal DataIn_im : std_logic_vector(Data_sz-1 downto 0);
79
80 type FFT_ctrlr_Reg is record
81 FFT_Cfg : std_logic;
82 FFT_Wdata : std_logic_vector((2*Data_sz)-1 downto 0);
83 end record;
84
85 signal Rec : FFT_ctrlr_Reg;
86 signal Rdata : std_logic_vector(31 downto 0);
87
88 begin
89
90 Rec.FFT_Cfg <= fill;
91
92 DataIn_im <= Rec.FFT_Wdata(Data_sz-1 downto 0);
93 DataIn_re <= Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz);
94
95 Actel_FFT : CoreFFT
96 generic map(
97 LOGPTS => gLOGPTS,
98 LOGLOGPTS => gLOGLOGPTS,
99 WSIZE => gWSIZE,
100 TWIDTH => gTWIDTH,
101 DWIDTH => gDWIDTH,
102 TDWIDTH => gTDWIDTH,
103 RND_MODE => gRND_MODE,
104 SCALE_MODE => gSCALE_MODE,
105 PTS => gPTS,
106 HALFPTS => gHALFPTS,
107 inBuf_RWDLY => gInBuf_RWDLY)
108 port map(clk,start,rst,d_valid,read_y,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,y_valid,y_rdy);
109
110 -- Flags : Flag_Extremum
111 -- port map(clk,rst,load,y_rdy,fill,ready);
112
113 process(rst,clk)
114 begin
115 if(rst='0')then
116 Rec.FFT_Wdata <= (others => '0');
117 Wen <= '1';
118
119 elsif(clk'event and clk='1')then
120
121 --APB Write OP
122 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
123 case apbi.paddr(abits-1 downto 2) is
124 when "000001" =>
125 Wen <= '0';
126 Rec.FFT_Wdata(Data_sz-1 downto 0) <= (others => '0');
127 Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz) <= apbi.pwdata(Data_sz-1 downto 0);
128
129 when others =>
130 null;
131 end case;
132 else
133 Wen <= '1';
134 end if;
135
136 --APB Read OP
137 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
138 case apbi.paddr(abits-1 downto 2) is
139 when "000000" =>
140 Rdata(3 downto 0) <= "000" & Rec.FFT_Cfg;
141 Rdata(31 downto 4) <= (others => '0');
142
143 when others =>
144 Rdata <= (others => '0');
145 end case;
146 end if;
147
148 end if;
149 apbo.pconfig <= pconfig;
150 end process;
151
152 apbo.prdata <= Rdata when apbi.penable = '1';
153 d_valid <= not Wen;
154 read_y <= not Ren;
155 fill <= Load;
156 Ready <= y_rdy;
157 valid <= y_valid;
158 start <= not rst;
159
160 OUTfill <= Load;
161 OUTwrite <= not Wen;
162
163 end architecture; No newline at end of file
Show file before | Show file after | Hide comments
@@ -0,0 +1,131
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25
26 entity Linker_FFT_FIFO is
27 generic(
28 Data_sz : integer range 1 to 32 := 8
29 );
30 port(
31 clk : in std_logic;
32 rstn : in std_logic;
33 Ready : in std_logic;
34 Valid : in std_logic;
35 Full : in std_logic_vector(4 downto 0);
36 Data_re : in std_logic_vector(Data_sz-1 downto 0);
37 Data_im : in std_logic_vector(Data_sz-1 downto 0);
38 Read : out std_logic;
39 Write : out std_logic_vector(4 downto 0);
40 ReUse : out std_logic_vector(4 downto 0);
41 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
42 );
43 end entity;
44
45
46 architecture ar_Linker of Linker_FFT_FIFO is
47
48 type etat is (eX,e0,e1,e2,e3);
49 signal ect : etat;
50
51 signal FifoCpt : integer;
52 signal DataTmp : std_logic_vector(Data_sz-1 downto 0);
53
54 signal sFull : std_logic;
55 signal sData : std_logic_vector(Data_sz-1 downto 0);
56 signal sReady : std_logic;
57
58 begin
59
60 process(clk,rstn)
61 begin
62 if(rstn='0')then
63 ect <= e0;
64 Read <= '1';
65 Write <= (others => '1');
66 Reuse <= (others => '0');
67 FifoCpt <= 1;
68 sDATA <= (others => '0');
69
70 elsif(clk'event and clk='1')then
71 sReady <= Ready;
72
73 case ect is
74
75 when e0 =>
76 Write(FifoCpt-1) <= '1';
77 if(sReady='0' and Ready='1' and sfull='0')then
78 Read <= '0';
79 ect <= e1;
80 end if;
81
82 when e1 =>
83 Read <= '1';
84 if(Valid='1' and sfull='0')then
85 DataTmp <= Data_im;
86 sDATA <= Data_re;
87 Write(FifoCpt-1) <= '0';
88 ect <= e2;
89 elsif(sfull='1')then
90 ReUse(FifoCpt-1) <= '1';
91 ect <= eX;
92 end if;
93
94 when e2 =>
95 sDATA <= DataTmp;
96 ect <= e3;
97
98 when e3 =>
99 Write(FifoCpt-1) <= '1';
100 if(Ready='1' and sfull='0')then
101 Read <= '0';
102 ect <= e1;
103 end if;
104
105 when eX =>
106 if(FifoCpt=6)then
107 FifoCpt <= 1;
108 else
109 FifoCpt <= FifoCpt+1;
110 end if;
111 ect <= e0;
112
113 end case;
114 end if;
115 end process;
116
117 DATA <= sData & sData & sData & sData & sData;
118
119 with FifoCpt select
120 sFull <= Full(0) when 1,
121 Full(1) when 2,
122 Full(2) when 3,
123 Full(3) when 4,
124 Full(4) when 5,
125 '1' when others;
126
127 end architecture;
128
129
130
131
Show file before | Show file after | Hide comments
@@ -0,0 +1,103
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2012, Laboratory of Plasmas Physic - CNRS
4 --
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
9 --
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
14 --
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
22 library IEEE;
23 use IEEE.std_logic_1164.all;
24 use IEEE.numeric_std.all;
25 library lpp;
26 use lpp.lpp_memory.all;
27 library techmap;
28 use techmap.gencomp.all;
29
30 entity SM_5lppFIFO is
31 generic(
32 tech : integer := apa3;
33 Data_sz : integer range 1 to 32 := 16;
34 Addr_sz : integer range 2 to 12 := 8;
35 Enable_ReUse : std_logic := '0'
36 );
37 port(
38 rst : in std_logic;
39 wclk : in std_logic;
40 rclk : in std_logic;
41 ReUse : in std_logic_vector(4 downto 0);
42 wen : in std_logic_vector(4 downto 0);
43 ren : in std_logic_vector(4 downto 0);
44 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
45 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
46 full : out std_logic_vector(4 downto 0);
47 empty : out std_logic_vector(4 downto 0)
48 );
49 end entity;
50
51
52 architecture ar_SM_5lppFIFO of SM_5lppFIFO is
53
54 begin
55
56 fifoB1 : lpp_fifo
57 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
58 port map(rst,ReUse(0),rclk,ren(0),rdata(Data_sz-1 downto 0),empty(0),open,wclk,wen(0),wdata(Data_sz-1 downto 0),full(0),open);
59
60 fifoB2 : lpp_fifo
61 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
62 port map(rst,ReUse(1),rclk,ren(1),rdata((2*Data_sz)-1 downto Data_sz),empty(1),open,wclk,wen(1),wdata((2*Data_sz)-1 downto Data_sz),full(1),open);
63
64 fifoB3 : lpp_fifo
65 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
66 port map(rst,ReUse(2),rclk,ren(2),rdata((3*Data_sz)-1 downto 2*Data_sz),empty(2),open,wclk,wen(2),wdata((3*Data_sz)-1 downto 2*Data_sz),full(2),open);
67
68 fifoE1 : lpp_fifo
69 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
70 port map(rst,ReUse(3),rclk,ren(3),rdata((4*Data_sz)-1 downto 3*Data_sz),empty(3),open,wclk,wen(3),wdata((4*Data_sz)-1 downto 3*Data_sz),full(3),open);
71
72 fifoE2 : lpp_fifo
73 generic map (tech,Enable_ReUse,Data_sz,Addr_sz)
74 port map(rst,ReUse(4),rclk,ren(4),rdata((5*Data_sz)-1 downto 4*Data_sz),empty(4),open,wclk,wen(4),wdata((5*Data_sz)-1 downto 4*Data_sz),full(4),open);
75
76
77 end architecture;
78
79
80
81
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
102
103
Show file before | Show file after | Hide comments
@@ -1,72 +1,54
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FFT_DRIVER_H
22 #ifndef APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24 #include "apb_delay_Driver.h"
24 #include "apb_delay_Driver.h"
25
25
26 /*! \file apb_fft_Driver.h
27 \brief LPP FFT driver.
28
29 This library is written to work with LPP_APB_FFT VHDL module from LPP's FreeVHDLIB. It calculate a fast fourier transforms,
30 from an input data table.
31
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
34
35 #define FFT_Fill 0x00000001
26 #define FFT_Fill 0x00000001
36 #define FFT_Ready 0x00000010
27 #define FFT_Ready 0x00000010
37 #define Mask 0x0000FFFF
28 #define Mask 0x0000FFFF
38
29
39
30
40 /*===================================================
31 /*===================================================
41 T Y P E S D E F
32 T Y P E S D E F
42 ====================================================*/
33 ====================================================*/
43 /*! \struct FFT_Driver
34
44 \brief Sturcture representing the fft registers
45 */
46 struct FFT_Driver
35 struct FFT_Driver
47 {
36 {
48 int ConfigReg;
37 int ConfigReg;
49 int RWDataReg;
38 int RWDataReg;
50 };
39 };
51
40
52 typedef struct FFT_Driver FFT_Device;
41 typedef struct FFT_Driver FFT_Device;
53
42
54
43
55 /*===================================================
44 /*===================================================
56 F U N C T I O N S
45 F U N C T I O N S
57 ====================================================*/
46 ====================================================*/
58 /*! \fn FFT_Device* openFFT(int count);
47
59 \brief Return count FFT.
60
61 This Function scans APB devices table and returns count FFT.
62
63 \param count The number of the FFT you whant to get. For example if you have 3 FFTS on your SOC you want
64 to use FFT1 so count = 1.
65 \return The pointer to the device.
66 */
67 FFT_Device* openFFT(int count);
48 FFT_Device* openFFT(int count);
68 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
49 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
69 int FftOutput(int Tbl[],FFT_Device*);
50 int FftOutput(int Tbl[],FFT_Device*);
70
51
71
52
53
72 #endif
54 #endif
Show file before | Show file after | Hide comments
@@ -1,75 +1,79
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #include "apb_fft_Driver.h"
22 #include "apb_fft_Driver.h"
23 #include "lpp_apb_functions.h"
23 #include "lpp_apb_functions.h"
24 #include <stdio.h>
24 #include <stdio.h>
25 #include "apb_delay_Driver.h"
25 #include "apb_delay_Driver.h"
26
26
27
27
28 FFT_Device* openFFT(int count)
28 FFT_Device* openFFT(int count)
29 {
29 {
30 FFT_Device* FFT0;
30 FFT_Device* FFT0;
31 FFT0 = (FFT_Device*) apbgetdevice(LPP_FFT,VENDOR_LPP,count);
31 FFT0 = (FFT_Device*) apbgetdevice(LPP_FFT,VENDOR_LPP,count);
32 return FFT0;
32 return FFT0;
33 }
33 }
34
34
35
35
36 int FftInput(int * Tbl,FFT_Device* fft,DELAY_Device* delay)
36 int FftInput(int * Tbl,FFT_Device* fft,DELAY_Device* delay)
37 {
37 {
38 //printf("\nFftInput\n\n");
38 int i=0;
39 int i=0;
39
40
40 while((fft->ConfigReg & FFT_Fill) == FFT_Fill) // fill a 1
41 while((fft->ConfigReg & FFT_Fill) == FFT_Fill)// && (i<256)) // fill a 1
41 {
42 {
42 fft->RWDataReg = Tbl[i];
43 fft->RWDataReg = Tbl[i];
43 i++;
44 i++;
44 Delay_us(delay,1);
45 //Delay_us(delay,1);
45 }
46 }
46
47
48 //printf("\nEnd In %d\n\n",i);
47 return 0;
49 return 0;
48 }
50 }
49
51
50
52
51 int FftOutput(int * Tbl, FFT_Device* fft)
53 int FftOutput(int * Tbl, FFT_Device* fft)
52 {
54 {
55 //printf("\nFftOutput\n\n");
53 int i=0;
56 int i=0;
54 int data;
57 int data;
55
58
56 while((fft->ConfigReg & FFT_Ready) == FFT_Ready) // ready a 1
59 while((fft->ConfigReg & FFT_Ready) == FFT_Ready) // ready a 1
57 {
60 {
58 data = fft->RWDataReg;
61 data = fft->RWDataReg;
59 Tbl[i] = (data >> 16) & Mask;
62 Tbl[i] = (data >> 16) & Mask;
60 Tbl[i+1] = data & Mask;
63 Tbl[i+1] = data & Mask;
61 i = i+2;
64 i = i+2;
62 }
65 }
63
66
67 //printf("\nEnd Out %d\n\n",i);
64 return i;
68 return i;
65 }
69 }
66
70
67
71
68
72
69
73
70
74
71
75
72
76
73
77
74
78
75
79
Show file before | Show file after | Hide comments
@@ -1,72 +1,54
1 /*------------------------------------------------------------------------------
1 /*------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 -------------------------------------------------------------------------------
18 -------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 -----------------------------------------------------------------------------*/
21 -----------------------------------------------------------------------------*/
22 #ifndef APB_FFT_DRIVER_H
22 #ifndef APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
23 #define APB_FFT_DRIVER_H
24 #include "apb_delay_Driver.h"
24 #include "apb_delay_Driver.h"
25
25
26 /*! \file apb_fft_Driver.h
27 \brief LPP FFT driver.
28
29 This library is written to work with LPP_APB_FFT VHDL module from LPP's FreeVHDLIB. It calculate a fast fourier transforms,
30 from an input data table.
31
32 \author Martin Morlot martin.morlot@lpp.polytechnique.fr
33 */
34
35 #define FFT_Fill 0x00000001
26 #define FFT_Fill 0x00000001
36 #define FFT_Ready 0x00000010
27 #define FFT_Ready 0x00000010
37 #define Mask 0x0000FFFF
28 #define Mask 0x0000FFFF
38
29
39
30
40 /*===================================================
31 /*===================================================
41 T Y P E S D E F
32 T Y P E S D E F
42 ====================================================*/
33 ====================================================*/
43 /*! \struct FFT_Driver
34
44 \brief Sturcture representing the fft registers
45 */
46 struct FFT_Driver
35 struct FFT_Driver
47 {
36 {
48 int ConfigReg;
37 int ConfigReg;
49 int RWDataReg;
38 int RWDataReg;
50 };
39 };
51
40
52 typedef struct FFT_Driver FFT_Device;
41 typedef struct FFT_Driver FFT_Device;
53
42
54
43
55 /*===================================================
44 /*===================================================
56 F U N C T I O N S
45 F U N C T I O N S
57 ====================================================*/
46 ====================================================*/
58 /*! \fn FFT_Device* openFFT(int count);
47
59 \brief Return count FFT.
60
61 This Function scans APB devices table and returns count FFT.
62
63 \param count The number of the FFT you whant to get. For example if you have 3 FFTS on your SOC you want
64 to use FFT1 so count = 1.
65 \return The pointer to the device.
66 */
67 FFT_Device* openFFT(int count);
48 FFT_Device* openFFT(int count);
68 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
49 int FftInput(int Tbl[],FFT_Device*,DELAY_Device*);
69 int FftOutput(int Tbl[],FFT_Device*);
50 int FftOutput(int Tbl[],FFT_Device*);
70
51
71
52
53
72 #endif
54 #endif
Show file before | Show file after | Hide comments
@@ -1,169 +1,167
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use grlib.stdlib.all;
26 use grlib.stdlib.all;
27 use grlib.devices.all;
27 use grlib.devices.all;
28 library lpp;
28 library lpp;
29 use lpp.lpp_amba.all;
29 use lpp.lpp_amba.all;
30 use lpp.apb_devices_list.all;
30 use lpp.apb_devices_list.all;
31 use lpp.lpp_fft.all;
31 use lpp.lpp_fft.all;
32 use work.fft_components.all;
32 use work.fft_components.all;
33
33
34 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
34 --! Driver APB, va faire le lien entre l'IP VHDL de la FFT et le bus Amba
35
35
36 entity APB_FFT is
36 entity APB_FFT is
37 generic (
37 generic (
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Data_sz : integer := 16
43 Data_sz : integer := 16
44 );
44 );
45 port (
45 port (
46 clk : in std_logic; --! Horloge du composant
46 clk : in std_logic; --! Horloge du composant
47 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
48 eload : out std_logic;
49 eready :out std_logic;
50 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
48 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
51 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
49 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
52 );
50 );
53 end APB_FFT;
51 end APB_FFT;
54
52
55
53
56 architecture ar_APB_FFT of APB_FFT is
54 architecture ar_APB_FFT of APB_FFT is
57
55
58 constant REVISION : integer := 1;
56 constant REVISION : integer := 1;
59
57
60 constant pconfig : apb_config_type := (
58 constant pconfig : apb_config_type := (
61 0 => ahb_device_reg (VENDOR_LPP, LPP_FFT, 0, REVISION, 0),
59 0 => ahb_device_reg (VENDOR_LPP, LPP_FFT, 0, REVISION, 0),
62 1 => apb_iobar(paddr, pmask));
60 1 => apb_iobar(paddr, pmask));
63
61
64 signal Ren : std_logic;
62 signal Ren : std_logic;
65 signal Wen : std_logic;
63 signal Wen : std_logic;
66 signal load : std_logic;
64 signal load : std_logic;
67 signal d_valid : std_logic;
65 signal d_valid : std_logic;
68 signal y_rdy : std_logic;
66 signal y_rdy : std_logic;
69 signal read_y : std_logic;
67 signal read_y : std_logic;
70 signal fill : std_logic;
68 signal fill : std_logic;
71 signal ready : std_logic;
69 signal ready : std_logic;
72 signal start : std_logic;
70 signal start : std_logic;
73 signal DataIn_re : std_logic_vector(Data_sz-1 downto 0);
71 signal DataIn_re : std_logic_vector(Data_sz-1 downto 0);
74 signal DataIn_im : std_logic_vector(Data_sz-1 downto 0);
72 signal DataIn_im : std_logic_vector(Data_sz-1 downto 0);
75 signal DataOut_re : std_logic_vector(Data_sz-1 downto 0);
73 signal DataOut_re : std_logic_vector(Data_sz-1 downto 0);
76 signal DataOut_im : std_logic_vector(Data_sz-1 downto 0);
74 signal DataOut_im : std_logic_vector(Data_sz-1 downto 0);
77
75
78 type FFT_ctrlr_Reg is record
76 type FFT_ctrlr_Reg is record
79 FFT_Cfg : std_logic_vector(1 downto 0);
77 FFT_Cfg : std_logic_vector(1 downto 0);
80 FFT_Rdata : std_logic_vector((2*Data_sz)-1 downto 0);
78 FFT_Rdata : std_logic_vector((2*Data_sz)-1 downto 0);
81 FFT_Wdata : std_logic_vector((2*Data_sz)-1 downto 0);
79 FFT_Wdata : std_logic_vector((2*Data_sz)-1 downto 0);
82 end record;
80 end record;
83
81
84 signal Rec : FFT_ctrlr_Reg;
82 signal Rec : FFT_ctrlr_Reg;
85 signal Rdata : std_logic_vector(31 downto 0);
83 signal Rdata : std_logic_vector(31 downto 0);
86
84
87 begin
85 begin
88
86
89 Rec.FFT_Cfg(0) <= fill;
87 Rec.FFT_Cfg(0) <= fill;
90 Rec.FFT_Cfg(1) <= ready;
88 Rec.FFT_Cfg(1) <= ready;
91 eload <= fill;
89 eload <= fill;
92 eready <= ready;
90 eready <= ready;
93
91
94 DataIn_im <= Rec.FFT_Wdata(Data_sz-1 downto 0);
92 DataIn_im <= Rec.FFT_Wdata(Data_sz-1 downto 0);
95 DataIn_re <= Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz);
93 DataIn_re <= Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz);
96 Rec.FFT_Rdata(Data_sz-1 downto 0) <= DataOut_im;
94 Rec.FFT_Rdata(Data_sz-1 downto 0) <= DataOut_im;
97 Rec.FFT_Rdata((2*Data_sz)-1 downto Data_sz) <= DataOut_re;
95 Rec.FFT_Rdata((2*Data_sz)-1 downto Data_sz) <= DataOut_re;
98
96
99 Actel_FFT : CoreFFT
97 Actel_FFT : CoreFFT
100 generic map(
98 generic map(
101 LOGPTS => gLOGPTS,
99 LOGPTS => gLOGPTS,
102 LOGLOGPTS => gLOGLOGPTS,
100 LOGLOGPTS => gLOGLOGPTS,
103 WSIZE => gWSIZE,
101 WSIZE => gWSIZE,
104 TWIDTH => gTWIDTH,
102 TWIDTH => gTWIDTH,
105 DWIDTH => gDWIDTH,
103 DWIDTH => gDWIDTH,
106 TDWIDTH => gTDWIDTH,
104 TDWIDTH => gTDWIDTH,
107 RND_MODE => gRND_MODE,
105 RND_MODE => gRND_MODE,
108 SCALE_MODE => gSCALE_MODE,
106 SCALE_MODE => gSCALE_MODE,
109 PTS => gPTS,
107 PTS => gPTS,
110 HALFPTS => gHALFPTS,
108 HALFPTS => gHALFPTS,
111 inBuf_RWDLY => gInBuf_RWDLY)
109 inBuf_RWDLY => gInBuf_RWDLY)
112 port map(clk,start,rst,d_valid,read_y,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,y_rdy);
110 port map(clk,start,rst,d_valid,read_y,DataIn_im,DataIn_re,load,open,DataOut_im,DataOut_re,open,y_rdy);
113
111
114 Flags : Flag_Extremum
112 Flags : Flag_Extremum
115 port map(clk,rst,load,y_rdy,fill,ready);
113 port map(clk,rst,load,y_rdy,fill,ready);
116
114
117 process(rst,clk)
115 process(rst,clk)
118 begin
116 begin
119 if(rst='0')then
117 if(rst='0')then
120 Rec.FFT_Wdata <= (others => '0');
118 Rec.FFT_Wdata <= (others => '0');
121 Wen <= '1';
119 Wen <= '1';
122 Ren <= '1';
120 Ren <= '1';
123
121
124 elsif(clk'event and clk='1')then
122 elsif(clk'event and clk='1')then
125
123
126 --APB Write OP
124 --APB Write OP
127 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
125 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
128 case apbi.paddr(abits-1 downto 2) is
126 case apbi.paddr(abits-1 downto 2) is
129 when "000001" =>
127 when "000001" =>
130 Wen <= '0';
128 Wen <= '0';
131 Rec.FFT_Wdata(Data_sz-1 downto 0) <= (others => '0');
129 Rec.FFT_Wdata(Data_sz-1 downto 0) <= (others => '0');
132 Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz) <= apbi.pwdata(Data_sz-1 downto 0);
130 Rec.FFT_Wdata((2*Data_sz)-1 downto Data_sz) <= apbi.pwdata(Data_sz-1 downto 0);
133
131
134 when others =>
132 when others =>
135 null;
133 null;
136 end case;
134 end case;
137 else
135 else
138 Wen <= '1';
136 Wen <= '1';
139 end if;
137 end if;
140
138
141 --APB Read OP
139 --APB Read OP
142 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
140 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
143 case apbi.paddr(abits-1 downto 2) is
141 case apbi.paddr(abits-1 downto 2) is
144 when "000000" =>
142 when "000000" =>
145 Rdata(3 downto 0) <= "000" & Rec.FFT_Cfg(0);
143 Rdata(3 downto 0) <= "000" & Rec.FFT_Cfg(0);
146 Rdata(7 downto 4) <= "000" & Rec.FFT_Cfg(1);
144 Rdata(7 downto 4) <= "000" & Rec.FFT_Cfg(1);
147 Rdata(31 downto 8) <= (others => '0');
145 Rdata(31 downto 8) <= (others => '0');
148
146
149 when "000001" =>
147 when "000001" =>
150 Ren <= '0';
148 Ren <= '0';
151 Rdata(31 downto 0) <= Rec.FFT_Rdata((2*Data_sz)-1 downto 0);
149 Rdata(31 downto 0) <= Rec.FFT_Rdata((2*Data_sz)-1 downto 0);
152
150
153 when others =>
151 when others =>
154 Rdata <= (others => '0');
152 Rdata <= (others => '0');
155 end case;
153 end case;
156 else
154 else
157 Ren <= '1';
155 Ren <= '1';
158 end if;
156 end if;
159
157
160 end if;
158 end if;
161 apbo.pconfig <= pconfig;
159 apbo.pconfig <= pconfig;
162 end process;
160 end process;
163
161
164 apbo.prdata <= Rdata when apbi.penable = '1';
162 apbo.prdata <= Rdata when apbi.penable = '1';
165 d_valid <= not Wen;
163 d_valid <= not Wen;
166 read_y <= not Ren;
164 read_y <= not Ren;
167 start <= not rst;
165 start <= not rst;
168
166
169 end ar_APB_FFT; No newline at end of file
167 end ar_APB_FFT;
Show file before | Show file after | Hide comments
@@ -1,144 +1,187
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 use lpp.lpp_memory.all;
29 use lpp.lpp_memory.all;
30 use work.fft_components.all;
30 use work.fft_components.all;
31
31
32 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
32 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
33
33
34 package lpp_fft is
34 package lpp_fft is
35
35
36 component APB_FFT is
36 component APB_FFT is
37 generic (
37 generic (
38 pindex : integer := 0;
38 pindex : integer := 0;
39 paddr : integer := 0;
39 paddr : integer := 0;
40 pmask : integer := 16#fff#;
40 pmask : integer := 16#fff#;
41 pirq : integer := 0;
41 pirq : integer := 0;
42 abits : integer := 8;
42 abits : integer := 8;
43 Data_sz : integer := 32;
43 Data_sz : integer := 16
44 Addr_sz : integer := 8;
44 );
45 addr_max_int : integer := 256);
46 port (
45 port (
47 clk : in std_logic;
46 clk : in std_logic;
48 rst : in std_logic; --! Reset general du composant
47 rst : in std_logic; --! Reset general du composant
49 eload : out std_logic;
50 eready :out std_logic;
51 apbi : in apb_slv_in_type;
48 apbi : in apb_slv_in_type;
52 apbo : out apb_slv_out_type
49 apbo : out apb_slv_out_type
53 );
50 );
54 end component;
51 end component;
55
52
53
54 component APB_FFT_half is
55 generic (
56 pindex : integer := 0;
57 paddr : integer := 0;
58 pmask : integer := 16#fff#;
59 pirq : integer := 0;
60 abits : integer := 8;
61 Data_sz : integer := 16
62 );
63 port (
64 clk : in std_logic; --! Horloge du composant
65 rst : in std_logic; --! Reset general du composant
66 Ren : in std_logic;
67 ready : out std_logic;
68 valid : out std_logic;
69 DataOut_re : out std_logic_vector(Data_sz-1 downto 0);
70 DataOut_im : out std_logic_vector(Data_sz-1 downto 0);
71 OUTfill : out std_logic;
72 OUTwrite : out std_logic;
73 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
74 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
75 );
76 end component;
77
78
56 component Flag_Extremum is
79 component Flag_Extremum is
57 port(
80 port(
58 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
81 clk,raz : in std_logic; --! Horloge et Reset gοΏ½nοΏ½ral du composant
59 load : in std_logic; --! Signal en provenance de CoreFFT
82 load : in std_logic; --! Signal en provenance de CoreFFT
60 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
83 y_rdy : in std_logic; --! Signal en provenance de CoreFFT
61 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
84 fill : out std_logic; --! Flag, Va permettre d'autoriser l'οΏ½criture (Driver C)
62 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
85 ready : out std_logic --! Flag, Va permettre d'autoriser la lecture (Driver C)
63 );
86 );
64 end component;
87 end component;
65
88
89
90 component Linker_FFT_FIFO is
91 generic(
92 Data_sz : integer range 1 to 32 := 16
93 );
94 port(
95 clk : in std_logic;
96 rstn : in std_logic;
97 Ready : in std_logic;
98 Valid : in std_logic;
99 Full : in std_logic_vector(4 downto 0);
100 Data_re : in std_logic_vector(Data_sz-1 downto 0);
101 Data_im : in std_logic_vector(Data_sz-1 downto 0);
102 Read : out std_logic;
103 Write : out std_logic_vector(4 downto 0);
104 ReUse : out std_logic_vector(4 downto 0);
105 DATA : out std_logic_vector((5*Data_sz)-1 downto 0)
106 );
107 end component;
108
66 --==============================================================|
109 --==============================================================|
67 --================== IP VHDL de la FFT actel ===================|
110 --================== IP VHDL de la FFT actel ===================|
68 --================ non partagοΏ½ dans la VHD_Lib =================|
111 --================ non partagοΏ½ dans la VHD_Lib =================|
69 --==============================================================|
112 --==============================================================|
70
113
71 component CoreFFT IS
114 component CoreFFT IS
72 GENERIC (
115 GENERIC (
73 LOGPTS : integer := gLOGPTS;
116 LOGPTS : integer := gLOGPTS;
74 LOGLOGPTS : integer := gLOGLOGPTS;
117 LOGLOGPTS : integer := gLOGLOGPTS;
75 WSIZE : integer := gWSIZE;
118 WSIZE : integer := gWSIZE;
76 TWIDTH : integer := gTWIDTH;
119 TWIDTH : integer := gTWIDTH;
77 DWIDTH : integer := gDWIDTH;
120 DWIDTH : integer := gDWIDTH;
78 TDWIDTH : integer := gTDWIDTH;
121 TDWIDTH : integer := gTDWIDTH;
79 RND_MODE : integer := gRND_MODE;
122 RND_MODE : integer := gRND_MODE;
80 SCALE_MODE : integer := gSCALE_MODE;
123 SCALE_MODE : integer := gSCALE_MODE;
81 PTS : integer := gPTS;
124 PTS : integer := gPTS;
82 HALFPTS : integer := gHALFPTS;
125 HALFPTS : integer := gHALFPTS;
83 inBuf_RWDLY : integer := gInBuf_RWDLY );
126 inBuf_RWDLY : integer := gInBuf_RWDLY );
84 PORT (
127 PORT (
85 clk,ifiStart,ifiNreset : IN std_logic;
128 clk,ifiStart,ifiNreset : IN std_logic;
86 ifiD_valid, ifiRead_y : IN std_logic;
129 ifiD_valid, ifiRead_y : IN std_logic;
87 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
130 ifiD_im, ifiD_re : IN std_logic_vector(WSIZE-1 DOWNTO 0);
88 ifoLoad, ifoPong : OUT std_logic;
131 ifoLoad, ifoPong : OUT std_logic;
89 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
132 ifoY_im, ifoY_re : OUT std_logic_vector(WSIZE-1 DOWNTO 0);
90 ifoY_valid, ifoY_rdy : OUT std_logic);
133 ifoY_valid, ifoY_rdy : OUT std_logic);
91 END component;
134 END component;
92
135
93
136
94 component actar is
137 component actar is
95 port( DataA : in std_logic_vector(15 downto 0); DataB : in
138 port( DataA : in std_logic_vector(15 downto 0); DataB : in
96 std_logic_vector(15 downto 0); Mult : out
139 std_logic_vector(15 downto 0); Mult : out
97 std_logic_vector(31 downto 0);Clock : in std_logic) ;
140 std_logic_vector(31 downto 0);Clock : in std_logic) ;
98 end component;
141 end component;
99
142
100 component actram is
143 component actram is
101 port( DI : in std_logic_vector(31 downto 0); DO : out
144 port( DI : in std_logic_vector(31 downto 0); DO : out
102 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
145 std_logic_vector(31 downto 0);WRB, RDB : in std_logic;
103 WADDR : in std_logic_vector(6 downto 0); RADDR : in
146 WADDR : in std_logic_vector(6 downto 0); RADDR : in
104 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
147 std_logic_vector(6 downto 0);WCLOCK, RCLOCK : in
105 std_logic) ;
148 std_logic) ;
106 end component;
149 end component;
107
150
108 component switch IS
151 component switch IS
109 GENERIC ( DWIDTH : integer := 32 );
152 GENERIC ( DWIDTH : integer := 32 );
110 PORT (
153 PORT (
111 clk, sel, validIn : IN std_logic;
154 clk, sel, validIn : IN std_logic;
112 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
155 inP, inQ : IN std_logic_vector(DWIDTH-1 DOWNTO 0);
113 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
156 outP, outQ : OUT std_logic_vector(DWIDTH-1 DOWNTO 0);
114 validOut : OUT std_logic);
157 validOut : OUT std_logic);
115 END component;
158 END component;
116
159
117 component twid_rA IS
160 component twid_rA IS
118 GENERIC (LOGPTS : integer := 8;
161 GENERIC (LOGPTS : integer := 8;
119 LOGLOGPTS : integer := 3 );
162 LOGLOGPTS : integer := 3 );
120 PORT (clk : IN std_logic;
163 PORT (clk : IN std_logic;
121 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
164 timer : IN std_logic_vector(LOGPTS-2 DOWNTO 0);
122 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
165 stage : IN std_logic_vector(LOGLOGPTS-1 DOWNTO 0);
123 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
166 tA : OUT std_logic_vector(LOGPTS-2 DOWNTO 0));
124 END component;
167 END component;
125
168
126 component counter IS
169 component counter IS
127 GENERIC (
170 GENERIC (
128 WIDTH : integer := 7;
171 WIDTH : integer := 7;
129 TERMCOUNT : integer := 127 );
172 TERMCOUNT : integer := 127 );
130 PORT (
173 PORT (
131 clk, nGrst, rst, cntEn : IN std_logic;
174 clk, nGrst, rst, cntEn : IN std_logic;
132 tc : OUT std_logic;
175 tc : OUT std_logic;
133 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
176 Q : OUT std_logic_vector(WIDTH-1 DOWNTO 0) );
134 END component;
177 END component;
135
178
136
179
137 component twiddle IS
180 component twiddle IS
138 PORT (
181 PORT (
139 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
182 A : IN std_logic_vector(gLOGPTS-2 DOWNTO 0);
140 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
183 T : OUT std_logic_vector(gTDWIDTH-1 DOWNTO 0));
141 END component;
184 END component;
142
185
143
186
144 end; No newline at end of file
187 end;
Show file before | Show file after | Hide comments
@@ -1,121 +1,144
1 ------------------------------------------------------------------------------
1 ------------------------------------------------------------------------------
2 -- This file is a part of the LPP VHDL IP LIBRARY
2 -- This file is a part of the LPP VHDL IP LIBRARY
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 --
4 --
5 -- This program is free software; you can redistribute it and/or modify
5 -- This program is free software; you can redistribute it and/or modify
6 -- it under the terms of the GNU General Public License as published by
6 -- it under the terms of the GNU General Public License as published by
7 -- the Free Software Foundation; either version 3 of the License, or
7 -- the Free Software Foundation; either version 3 of the License, or
8 -- (at your option) any later version.
8 -- (at your option) any later version.
9 --
9 --
10 -- This program is distributed in the hope that it will be useful,
10 -- This program is distributed in the hope that it will be useful,
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 -- GNU General Public License for more details.
13 -- GNU General Public License for more details.
14 --
14 --
15 -- You should have received a copy of the GNU General Public License
15 -- You should have received a copy of the GNU General Public License
16 -- along with this program; if not, write to the Free Software
16 -- along with this program; if not, write to the Free Software
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 ------------------------------------------------------------------------------
18 ------------------------------------------------------------------------------
19 -- Author : Martin Morlot
19 -- Author : Martin Morlot
20 -- Mail : martin.morlot@lpp.polytechnique.fr
20 -- Mail : martin.morlot@lpp.polytechnique.fr
21 ------------------------------------------------------------------------------
21 ------------------------------------------------------------------------------
22 library ieee;
22 library ieee;
23 use ieee.std_logic_1164.all;
23 use ieee.std_logic_1164.all;
24 library grlib;
24 library grlib;
25 use grlib.amba.all;
25 use grlib.amba.all;
26 use std.textio.all;
26 use std.textio.all;
27 library lpp;
27 library lpp;
28 use lpp.lpp_amba.all;
28 use lpp.lpp_amba.all;
29 library gaisler;
29 library gaisler;
30 use gaisler.misc.all;
30 use gaisler.misc.all;
31 use gaisler.memctrl.all;
31 use gaisler.memctrl.all;
32 library techmap;
32 library techmap;
33 use techmap.gencomp.all;
33 use techmap.gencomp.all;
34
34
35 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
35 --! Package contenant tous les programmes qui forment le composant intοΏ½grοΏ½ dans le lοΏ½on
36
36
37 package lpp_memory is
37 package lpp_memory is
38
38
39 component APB_FIFO is
39 component APB_FIFO is
40 generic (
40 generic (
41 tech : integer := apa3;
41 tech : integer := apa3;
42 pindex : integer := 0;
42 pindex : integer := 0;
43 paddr : integer := 0;
43 paddr : integer := 0;
44 pmask : integer := 16#fff#;
44 pmask : integer := 16#fff#;
45 pirq : integer := 0;
45 pirq : integer := 0;
46 abits : integer := 8;
46 abits : integer := 8;
47 FifoCnt : integer := 2;
47 FifoCnt : integer := 2;
48 Data_sz : integer := 16;
48 Data_sz : integer := 16;
49 Addr_sz : integer := 9;
49 Addr_sz : integer := 9;
50 Enable_ReUse : std_logic := '0';
50 Enable_ReUse : std_logic := '0';
51 R : integer := 1;
51 R : integer := 1;
52 W : integer := 1
52 W : integer := 1
53 );
53 );
54 port (
54 port (
55 clk : in std_logic; --! Horloge du composant
55 clk : in std_logic; --! Horloge du composant
56 rst : in std_logic; --! Reset general du composant
56 rst : in std_logic; --! Reset general du composant
57 rclk : in std_logic;
57 rclk : in std_logic;
58 wclk : in std_logic;
58 wclk : in std_logic;
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
59 REN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction de lecture en mοΏ½moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
60 WEN : in std_logic_vector(FifoCnt-1 downto 0); --! Instruction d'οΏ½criture en mοΏ½moire
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
61 Empty : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire vide
62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
62 Full : out std_logic_vector(FifoCnt-1 downto 0); --! Flag, MοΏ½moire pleine
63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
63 RDATA : out std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en entrοΏ½e
64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
64 WDATA : in std_logic_vector((FifoCnt*Data_sz)-1 downto 0); --! Registre de donnοΏ½es en sortie
65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
65 WADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (οΏ½criture)
66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
66 RADDR : out std_logic_vector((FifoCnt*Addr_sz)-1 downto 0); --! Registre d'addresse (lecture)
67 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
67 apbi : in apb_slv_in_type; --! Registre de gestion des entrοΏ½es du bus
68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
68 apbo : out apb_slv_out_type --! Registre de gestion des sorties du bus
69 );
69 );
70 end component;
70 end component;
71
71
72
72
73 component lpp_fifo is
73 component lpp_fifo is
74 generic(
74 generic(
75 tech : integer := 0;
75 tech : integer := 0;
76 Enable_ReUse : std_logic := '0';
76 Enable_ReUse : std_logic := '0';
77 DataSz : integer range 1 to 32 := 8;
77 DataSz : integer range 1 to 32 := 8;
78 abits : integer range 2 to 12 := 8
78 abits : integer range 2 to 12 := 8
79 );
79 );
80 port(
80 port(
81 rstn : in std_logic;
81 rstn : in std_logic;
82 ReUse : in std_logic; --27/01/12
82 ReUse : in std_logic; --27/01/12
83 rclk : in std_logic;
83 rclk : in std_logic;
84 ren : in std_logic;
84 ren : in std_logic;
85 rdata : out std_logic_vector(DataSz-1 downto 0);
85 rdata : out std_logic_vector(DataSz-1 downto 0);
86 empty : out std_logic;
86 empty : out std_logic;
87 raddr : out std_logic_vector(abits-1 downto 0);
87 raddr : out std_logic_vector(abits-1 downto 0);
88 wclk : in std_logic;
88 wclk : in std_logic;
89 wen : in std_logic;
89 wen : in std_logic;
90 wdata : in std_logic_vector(DataSz-1 downto 0);
90 wdata : in std_logic_vector(DataSz-1 downto 0);
91 full : out std_logic;
91 full : out std_logic;
92 waddr : out std_logic_vector(abits-1 downto 0)
92 waddr : out std_logic_vector(abits-1 downto 0)
93 );
93 );
94 end component;
94 end component;
95
95
96
97 component SM_5lppFIFO is
98 generic(
99 tech : integer := 0;
100 Data_sz : integer range 1 to 32 := 16;
101 Addr_sz : integer range 2 to 12 := 8;
102 Enable_ReUse : std_logic := '0'
103 );
104 port(
105 rst : in std_logic;
106 wclk : in std_logic;
107 rclk : in std_logic;
108 ReUse : in std_logic_vector(4 downto 0);
109 wen : in std_logic_vector(4 downto 0);
110 ren : in std_logic_vector(4 downto 0);
111 wdata : in std_logic_vector((5*Data_sz)-1 downto 0);
112 rdata : out std_logic_vector((5*Data_sz)-1 downto 0);
113 full : out std_logic_vector(4 downto 0);
114 empty : out std_logic_vector(4 downto 0)
115 );
116 end component;
117
118
96 component ssram_plugin is
119 component ssram_plugin is
97 generic (tech : integer := 0);
120 generic (tech : integer := 0);
98 port
121 port
99 (
122 (
100 clk : in std_logic;
123 clk : in std_logic;
101 mem_ctrlr_o : in memory_out_type;
124 mem_ctrlr_o : in memory_out_type;
102 SSRAM_CLK : out std_logic;
125 SSRAM_CLK : out std_logic;
103 nBWa : out std_logic;
126 nBWa : out std_logic;
104 nBWb : out std_logic;
127 nBWb : out std_logic;
105 nBWc : out std_logic;
128 nBWc : out std_logic;
106 nBWd : out std_logic;
129 nBWd : out std_logic;
107 nBWE : out std_logic;
130 nBWE : out std_logic;
108 nADSC : out std_logic;
131 nADSC : out std_logic;
109 nADSP : out std_logic;
132 nADSP : out std_logic;
110 nADV : out std_logic;
133 nADV : out std_logic;
111 nGW : out std_logic;
134 nGW : out std_logic;
112 nCE1 : out std_logic;
135 nCE1 : out std_logic;
113 CE2 : out std_logic;
136 CE2 : out std_logic;
114 nCE3 : out std_logic;
137 nCE3 : out std_logic;
115 nOE : out std_logic;
138 nOE : out std_logic;
116 MODE : out std_logic;
139 MODE : out std_logic;
117 ZZ : out std_logic
140 ZZ : out std_logic
118 );
141 );
119 end component;
142 end component;
120
143
121 end;
144 end;
General Comments 0
You need to be logged in to leave comments. Login now