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1 | ----------------------------------------------------------------------------- | |
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2 | -- LEON3 Demonstration design | |
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3 | -- Copyright (C) 2004 Jiri Gaisler, Gaisler Research | |
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4 | -- | |
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5 | -- This program is free software; you can redistribute it and/or modify | |
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6 | -- it under the terms of the GNU General Public License as published by | |
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7 | -- the Free Software Foundation; either version 2 of the License, or | |
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8 | -- (at your option) any later version. | |
|
9 | -- | |
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10 | -- This program is distributed in the hope that it will be useful, | |
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
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13 | -- GNU General Public License for more details. | |
|
14 | -- | |
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15 | -- You should have received a copy of the GNU General Public License | |
|
16 | -- along with this program; if not, write to the Free Software | |
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
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18 | ------------------------------------------------------------------------------ | |
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19 | ||
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20 | ||
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21 | LIBRARY ieee; | |
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22 | USE ieee.std_logic_1164.ALL; | |
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23 | LIBRARY grlib; | |
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24 | USE grlib.amba.ALL; | |
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25 | USE grlib.stdlib.ALL; | |
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26 | LIBRARY techmap; | |
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27 | USE techmap.gencomp.ALL; | |
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28 | LIBRARY gaisler; | |
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29 | USE gaisler.memctrl.ALL; | |
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30 | USE gaisler.leon3.ALL; | |
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31 | USE gaisler.uart.ALL; | |
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32 | USE gaisler.misc.ALL; | |
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33 | USE gaisler.spacewire.ALL; -- PLE | |
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34 | LIBRARY esa; | |
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35 | USE esa.memoryctrl.ALL; | |
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36 | LIBRARY lpp; | |
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37 | USE lpp.lpp_memory.ALL; | |
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38 | USE lpp.lpp_ad_conv.ALL; | |
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39 | USE lpp.lpp_lfr_pkg.ALL; | |
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40 | USE lpp.iir_filter.ALL; | |
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41 | USE lpp.general_purpose.ALL; | |
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42 | USE lpp.lpp_lfr_time_management.ALL; | |
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43 | USE lpp.lpp_leon3_soc_pkg.ALL; | |
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44 | ||
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45 | ENTITY leon3ft_soc IS | |
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46 | GENERIC ( | |
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47 | fabtech : INTEGER := apa3e; | |
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48 | memtech : INTEGER := apa3e; | |
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49 | padtech : INTEGER := inferred; | |
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50 | clktech : INTEGER := inferred; | |
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51 | disas : INTEGER := 0; -- Enable disassembly to console | |
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52 | dbguart : INTEGER := 0; -- Print UART on console | |
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53 | pclow : INTEGER := 2; | |
|
54 | -- | |
|
55 | clk_freq : INTEGER := 25000; --kHz | |
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56 | -- | |
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57 | NB_CPU : INTEGER := 1; | |
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58 | ENABLE_FPU : INTEGER := 1; | |
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59 | FPU_NETLIST : INTEGER := 1; | |
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60 | ENABLE_DSU : INTEGER := 1; | |
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61 | ENABLE_AHB_UART : INTEGER := 1; | |
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62 | ENABLE_APB_UART : INTEGER := 1; | |
|
63 | ENABLE_IRQMP : INTEGER := 1; | |
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64 | ENABLE_GPT : INTEGER := 1; | |
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65 | -- | |
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66 | NB_AHB_MASTER : INTEGER := 11; | |
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67 | NB_AHB_SLAVE : INTEGER := 1; | |
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68 | NB_APB_SLAVE : INTEGER := 2 | |
|
69 | ); | |
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70 | PORT ( | |
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71 | clk : IN STD_ULOGIC; | |
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72 | reset : IN STD_ULOGIC; | |
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73 | ||
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74 | errorn : OUT STD_ULOGIC; | |
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75 | ||
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76 | -- UART AHB --------------------------------------------------------------- | |
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77 | ahbrxd : IN STD_ULOGIC; -- DSU rx data | |
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78 | ahbtxd : OUT STD_ULOGIC; -- DSU tx data | |
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79 | ||
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80 | -- UART APB --------------------------------------------------------------- | |
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81 | urxd1 : IN STD_ULOGIC; -- UART1 rx data | |
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82 | utxd1 : OUT STD_ULOGIC; -- UART1 tx data | |
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83 | ||
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84 | -- RAM -------------------------------------------------------------------- | |
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85 | address : OUT STD_LOGIC_VECTOR(19 DOWNTO 0); | |
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86 | data : INOUT STD_LOGIC_VECTOR(31 DOWNTO 0); | |
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87 | nSRAM_BE0 : OUT STD_LOGIC; | |
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88 | nSRAM_BE1 : OUT STD_LOGIC; | |
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89 | nSRAM_BE2 : OUT STD_LOGIC; | |
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90 | nSRAM_BE3 : OUT STD_LOGIC; | |
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91 | nSRAM_WE : OUT STD_LOGIC; | |
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92 | nSRAM_CE : OUT STD_LOGIC; | |
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93 | nSRAM_OE : OUT STD_LOGIC; | |
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94 | ||
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95 | -- APB -------------------------------------------------------------------- | |
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96 | apbi_ext : OUT apb_slv_in_type; | |
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97 | apbo_ext : IN soc_apb_slv_out_vector(NB_APB_SLAVE-1+5 DOWNTO 5); | |
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98 | -- AHB_Slave -------------------------------------------------------------- | |
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99 | ahbi_s_ext : OUT ahb_slv_in_type; | |
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100 | ahbo_s_ext : IN soc_ahb_slv_out_vector(NB_AHB_SLAVE-1+3 DOWNTO 3); | |
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101 | -- AHB_Master ------------------------------------------------------------- | |
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102 | ahbi_m_ext : OUT AHB_Mst_In_Type; | |
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103 | ahbo_m_ext : IN soc_ahb_mst_out_vector(NB_AHB_MASTER-1+NB_CPU DOWNTO NB_CPU) | |
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104 | ||
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105 | ); | |
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106 | END; | |
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107 | ||
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108 | ARCHITECTURE Behavioral OF leon3ft_soc IS | |
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109 | ||
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110 | ----------------------------------------------------------------------------- | |
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111 | -- CONFIG ------------------------------------------------------------------- | |
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112 | ----------------------------------------------------------------------------- | |
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113 | ||
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114 | -- Clock generator | |
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115 | CONSTANT CFG_CLKMUL : INTEGER := (1); | |
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116 | CONSTANT CFG_CLKDIV : INTEGER := (1); -- divide 50MHz by 2 to get 25MHz | |
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117 | CONSTANT CFG_OCLKDIV : INTEGER := (1); | |
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118 | CONSTANT CFG_CLK_NOFB : INTEGER := 0; | |
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119 | -- LEON3 processor core | |
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120 | CONSTANT CFG_LEON3 : INTEGER := 1; | |
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121 | CONSTANT CFG_NCPU : INTEGER := NB_CPU; | |
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122 | CONSTANT CFG_NWIN : INTEGER := (8); -- to be compatible with BCC and RCC | |
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123 | CONSTANT CFG_V8 : INTEGER := 0; | |
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124 | CONSTANT CFG_MAC : INTEGER := 0; | |
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125 | CONSTANT CFG_SVT : INTEGER := 0; | |
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126 | CONSTANT CFG_RSTADDR : INTEGER := 16#00000#; | |
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127 | CONSTANT CFG_LDDEL : INTEGER := (1); | |
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128 | CONSTANT CFG_NWP : INTEGER := (0); | |
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129 | CONSTANT CFG_PWD : INTEGER := 1*2; | |
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130 | CONSTANT CFG_FPU : INTEGER := ENABLE_FPU *(8 + 16 * FPU_NETLIST); | |
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131 | -- 1*(8 + 16 * 0) => grfpu-light | |
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132 | -- 1*(8 + 16 * 1) => netlist | |
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133 | -- 0*(8 + 16 * 0) => No FPU | |
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134 | -- 0*(8 + 16 * 1) => No FPU; | |
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135 | CONSTANT CFG_ICEN : INTEGER := 1; | |
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136 | CONSTANT CFG_ISETS : INTEGER := 1; | |
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137 | CONSTANT CFG_ISETSZ : INTEGER := 4; | |
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138 | CONSTANT CFG_ILINE : INTEGER := 4; | |
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139 | CONSTANT CFG_IREPL : INTEGER := 0; | |
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140 | CONSTANT CFG_ILOCK : INTEGER := 0; | |
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141 | CONSTANT CFG_ILRAMEN : INTEGER := 0; | |
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142 | CONSTANT CFG_ILRAMADDR : INTEGER := 16#8E#; | |
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143 | CONSTANT CFG_ILRAMSZ : INTEGER := 1; | |
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144 | CONSTANT CFG_DCEN : INTEGER := 1; | |
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145 | CONSTANT CFG_DSETS : INTEGER := 1; | |
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146 | CONSTANT CFG_DSETSZ : INTEGER := 4; | |
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147 | CONSTANT CFG_DLINE : INTEGER := 4; | |
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148 | CONSTANT CFG_DREPL : INTEGER := 0; | |
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149 | CONSTANT CFG_DLOCK : INTEGER := 0; | |
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150 | CONSTANT CFG_DSNOOP : INTEGER := 0 + 0 + 4*0; | |
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151 | CONSTANT CFG_DLRAMEN : INTEGER := 0; | |
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152 | CONSTANT CFG_DLRAMADDR : INTEGER := 16#8F#; | |
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153 | CONSTANT CFG_DLRAMSZ : INTEGER := 1; | |
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154 | CONSTANT CFG_MMUEN : INTEGER := 0; | |
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155 | CONSTANT CFG_ITLBNUM : INTEGER := 2; | |
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156 | CONSTANT CFG_DTLBNUM : INTEGER := 2; | |
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157 | CONSTANT CFG_TLB_TYPE : INTEGER := 1 + 0*2; | |
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158 | CONSTANT CFG_TLB_REP : INTEGER := 1; | |
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159 | ||
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160 | CONSTANT CFG_DSU : INTEGER := ENABLE_DSU; | |
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161 | CONSTANT CFG_ITBSZ : INTEGER := 0; | |
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162 | CONSTANT CFG_ATBSZ : INTEGER := 0; | |
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163 | ||
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164 | -- AMBA settings | |
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165 | CONSTANT CFG_DEFMST : INTEGER := (0); | |
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166 | CONSTANT CFG_RROBIN : INTEGER := 1; | |
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167 | CONSTANT CFG_SPLIT : INTEGER := 0; | |
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168 | CONSTANT CFG_AHBIO : INTEGER := 16#FFF#; | |
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169 | CONSTANT CFG_APBADDR : INTEGER := 16#800#; | |
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170 | ||
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171 | -- DSU UART | |
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172 | CONSTANT CFG_AHB_UART : INTEGER := ENABLE_AHB_UART; | |
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173 | ||
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174 | -- LEON2 memory controller | |
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175 | CONSTANT CFG_MCTRL_SDEN : INTEGER := 0; | |
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176 | ||
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177 | -- UART 1 | |
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178 | CONSTANT CFG_UART1_ENABLE : INTEGER := ENABLE_APB_UART; | |
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179 | CONSTANT CFG_UART1_FIFO : INTEGER := 1; | |
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180 | ||
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181 | -- LEON3 interrupt controller | |
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182 | CONSTANT CFG_IRQ3_ENABLE : INTEGER := ENABLE_IRQMP; | |
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183 | ||
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184 | -- Modular timer | |
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185 | CONSTANT CFG_GPT_ENABLE : INTEGER := ENABLE_GPT; | |
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186 | CONSTANT CFG_GPT_NTIM : INTEGER := (2); | |
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187 | CONSTANT CFG_GPT_SW : INTEGER := (8); | |
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188 | CONSTANT CFG_GPT_TW : INTEGER := (32); | |
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189 | CONSTANT CFG_GPT_IRQ : INTEGER := (8); | |
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190 | CONSTANT CFG_GPT_SEPIRQ : INTEGER := 1; | |
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191 | CONSTANT CFG_GPT_WDOGEN : INTEGER := 0; | |
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192 | CONSTANT CFG_GPT_WDOG : INTEGER := 16#0#; | |
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193 | ----------------------------------------------------------------------------- | |
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194 | ||
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195 | ----------------------------------------------------------------------------- | |
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196 | -- SIGNALs | |
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197 | ----------------------------------------------------------------------------- | |
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198 | CONSTANT maxahbmsp : INTEGER := CFG_NCPU + CFG_AHB_UART + NB_AHB_MASTER; | |
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199 | -- CLK & RST -- | |
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200 | SIGNAL clk2x : STD_ULOGIC; | |
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201 | SIGNAL clkmn : STD_ULOGIC; | |
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202 | SIGNAL clkm : STD_ULOGIC; | |
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203 | SIGNAL rstn : STD_ULOGIC; | |
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204 | SIGNAL rstraw : STD_ULOGIC; | |
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205 | SIGNAL pciclk : STD_ULOGIC; | |
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206 | SIGNAL sdclkl : STD_ULOGIC; | |
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207 | SIGNAL cgi : clkgen_in_type; | |
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208 | SIGNAL cgo : clkgen_out_type; | |
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209 | --- AHB / APB | |
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210 | SIGNAL apbi : apb_slv_in_type; | |
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211 | SIGNAL apbo : apb_slv_out_vector := (OTHERS => apb_none); | |
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212 | SIGNAL ahbsi : ahb_slv_in_type; | |
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213 | SIGNAL ahbso : ahb_slv_out_vector := (OTHERS => ahbs_none); | |
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214 | SIGNAL ahbmi : ahb_mst_in_type; | |
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215 | SIGNAL ahbmo : ahb_mst_out_vector := (OTHERS => ahbm_none); | |
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216 | --UART | |
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217 | SIGNAL ahbuarti : uart_in_type; | |
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218 | SIGNAL ahbuarto : uart_out_type; | |
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219 | SIGNAL apbuarti : uart_in_type; | |
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220 | SIGNAL apbuarto : uart_out_type; | |
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221 | --MEM CTRLR | |
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222 | SIGNAL memi : memory_in_type; | |
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223 | SIGNAL memo : memory_out_type; | |
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224 | SIGNAL wpo : wprot_out_type; | |
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225 | SIGNAL sdo : sdram_out_type; | |
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226 | --IRQ | |
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227 | SIGNAL irqi : irq_in_vector(0 TO CFG_NCPU-1); | |
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228 | SIGNAL irqo : irq_out_vector(0 TO CFG_NCPU-1); | |
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229 | --Timer | |
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230 | SIGNAL gpti : gptimer_in_type; | |
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231 | SIGNAL gpto : gptimer_out_type; | |
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232 | --DSU | |
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233 | SIGNAL dbgi : l3_debug_in_vector(0 TO CFG_NCPU-1); | |
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234 | SIGNAL dbgo : l3_debug_out_vector(0 TO CFG_NCPU-1); | |
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235 | SIGNAL dsui : dsu_in_type; | |
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236 | SIGNAL dsuo : dsu_out_type; | |
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237 | ----------------------------------------------------------------------------- | |
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238 | ||
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239 | SIGNAL nSRAM_CE_s : STD_LOGIC; | |
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240 | BEGIN | |
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241 | ||
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242 | ||
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243 | ---------------------------------------------------------------------- | |
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244 | --- Reset and Clock generation ------------------------------------- | |
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245 | ---------------------------------------------------------------------- | |
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246 | ||
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247 | cgi.pllctrl <= "00"; | |
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248 | cgi.pllrst <= rstraw; | |
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249 | ||
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250 | rst0 : rstgen PORT MAP (reset, clkm, cgo.clklock, rstn, rstraw); | |
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251 | ||
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252 | clkgen0 : clkgen -- clock generator | |
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253 | GENERIC MAP (clktech, CFG_CLKMUL, CFG_CLKDIV, CFG_MCTRL_SDEN, | |
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254 | CFG_CLK_NOFB, 0, 0, 0, clk_freq, 0, 0, CFG_OCLKDIV) | |
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255 | PORT MAP (clk, clk, clkm, clkmn, clk2x, sdclkl, pciclk, cgi, cgo); | |
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256 | ||
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257 | ---------------------------------------------------------------------- | |
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258 | --- LEON3 processor / DSU / IRQ ------------------------------------ | |
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259 | ---------------------------------------------------------------------- | |
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260 | ||
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261 | l3 : IF CFG_LEON3 = 1 GENERATE | |
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262 | cpu : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
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263 | u0 : leon3ft | |
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264 | GENERIC MAP ( | |
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265 | hindex => i, --: integer; | |
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266 | fabtech => fabtech, | |
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267 | memtech => memtech, | |
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268 | nwindows => CFG_NWIN, | |
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269 | dsu => CFG_DSU, | |
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270 | fpu => CFG_FPU, | |
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271 | v8 => CFG_V8, | |
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272 | cp => 0, | |
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273 | mac => CFG_MAC, | |
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274 | pclow => pclow, | |
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275 | notag => 0, | |
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276 | nwp => CFG_NWP, | |
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277 | icen => CFG_ICEN, | |
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278 | irepl => CFG_IREPL, | |
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279 | isets => CFG_ISETS, | |
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280 | ilinesize => CFG_ILINE, | |
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281 | isetsize => CFG_ISETSZ, | |
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282 | isetlock => CFG_ILOCK, | |
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283 | dcen => CFG_DCEN, | |
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284 | drepl => CFG_DREPL, | |
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285 | dsets => CFG_DSETS, | |
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286 | dlinesize => CFG_DLINE, | |
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287 | dsetsize => CFG_DSETSZ, | |
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288 | dsetlock => CFG_DLOCK, | |
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289 | dsnoop => CFG_DSNOOP, | |
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290 | ilram => CFG_ILRAMEN, | |
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291 | ilramsize => CFG_ILRAMSZ, | |
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292 | ilramstart => CFG_ILRAMADDR, | |
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293 | dlram => CFG_DLRAMEN, | |
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294 | dlramsize => CFG_DLRAMSZ, | |
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295 | dlramstart => CFG_DLRAMADDR, | |
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296 | mmuen => CFG_MMUEN, | |
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297 | itlbnum => CFG_ITLBNUM, | |
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298 | dtlbnum => CFG_DTLBNUM, | |
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299 | tlb_type => CFG_TLB_TYPE, | |
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300 | tlb_rep => CFG_TLB_REP, | |
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301 | lddel => CFG_LDDEL, | |
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302 | disas => disas, | |
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303 | tbuf => CFG_ITBSZ, | |
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304 | pwd => CFG_PWD, | |
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305 | svt => CFG_SVT, | |
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306 | rstaddr => CFG_RSTADDR, | |
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307 | smp => CFG_NCPU-1, | |
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308 | iuft => 2, --: integer range 0 to 4; | |
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309 | fpft => 1, --: integer range 0 to 4; | |
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310 | cmft => 1, --: integer range 0 to 1; | |
|
311 | iuinj => 0, --: integer; | |
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312 | ceinj => 0, --: integer range 0 to 3; | |
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313 | cached => 0, --: integer; | |
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314 | netlist => 0, --: integer; | |
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315 | scantest => 0, --: integer; | |
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316 | mmupgsz => 0, --: integer range 0 to 5; | |
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317 | bp => 1) --: integer); | |
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318 | PORT MAP ( | |
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319 | clk => clkm, | |
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320 | rstn => rstn, | |
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321 | ahbi => ahbmi, | |
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322 | ahbo => ahbmo(i), | |
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323 | ahbsi => ahbsi, | |
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324 | ahbso => ahbso, | |
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325 | irqi => irqi(i), | |
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326 | irqo => irqo(i), | |
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327 | dbgi => dbgi(i), | |
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328 | dbgo => dbgo(i), | |
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329 | gclk => clkm | |
|
330 | ); | |
|
331 | ||
|
332 | END GENERATE; | |
|
333 | ||
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334 | ||
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335 | errorn_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (errorn, dbgo(0).error); | |
|
336 | ||
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337 | dsugen : IF CFG_DSU = 1 GENERATE | |
|
338 | dsu0 : dsu3 -- LEON3 Debug Support Unit | |
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339 | GENERIC MAP (hindex => 2, haddr => 16#900#, hmask => 16#F00#, | |
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340 | ncpu => CFG_NCPU, tbits => 30, tech => memtech, irq => 0, kbytes => CFG_ATBSZ) | |
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341 | PORT MAP (rstn, clkm, ahbmi, ahbsi, ahbso(2), dbgo, dbgi, dsui, dsuo); | |
|
342 | dsui.enable <= '1'; | |
|
343 | dsui.break <= '0'; | |
|
344 | END GENERATE; | |
|
345 | END GENERATE; | |
|
346 | ||
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347 | nodsu : IF CFG_DSU = 0 GENERATE | |
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348 | ahbso(2) <= ahbs_none; | |
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349 | dsuo.tstop <= '0'; | |
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350 | dsuo.active <= '0'; | |
|
351 | END GENERATE; | |
|
352 | ||
|
353 | irqctrl : IF CFG_IRQ3_ENABLE /= 0 GENERATE | |
|
354 | irqctrl0 : irqmp -- interrupt controller | |
|
355 | GENERIC MAP (pindex => 2, paddr => 2, ncpu => CFG_NCPU) | |
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356 | PORT MAP (rstn, clkm, apbi, apbo(2), irqo, irqi); | |
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357 | END GENERATE; | |
|
358 | irq3 : IF CFG_IRQ3_ENABLE = 0 GENERATE | |
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359 | x : FOR i IN 0 TO CFG_NCPU-1 GENERATE | |
|
360 | irqi(i).irl <= "0000"; | |
|
361 | END GENERATE; | |
|
362 | apbo(2) <= apb_none; | |
|
363 | END GENERATE; | |
|
364 | ||
|
365 | ---------------------------------------------------------------------- | |
|
366 | --- Memory controllers --------------------------------------------- | |
|
367 | ---------------------------------------------------------------------- | |
|
368 | memctrlr : mctrl GENERIC MAP ( | |
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369 | hindex => 0, | |
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370 | pindex => 0, | |
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371 | paddr => 0, | |
|
372 | srbanks => 1 | |
|
373 | ) | |
|
374 | PORT MAP (rstn, clkm, memi, memo, ahbsi, ahbso(0), apbi, apbo(0), wpo, sdo); | |
|
375 | ||
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376 | memi.brdyn <= '1'; | |
|
377 | memi.bexcn <= '1'; | |
|
378 | memi.writen <= '1'; | |
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379 | memi.wrn <= "1111"; | |
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380 | memi.bwidth <= "10"; | |
|
381 | ||
|
382 | bdr : FOR i IN 0 TO 3 GENERATE | |
|
383 | data_pad : iopadv GENERIC MAP (tech => padtech, width => 8) | |
|
384 | PORT MAP ( | |
|
385 | data(31-i*8 DOWNTO 24-i*8), | |
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386 | memo.data(31-i*8 DOWNTO 24-i*8), | |
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387 | memo.bdrive(i), | |
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388 | memi.data(31-i*8 DOWNTO 24-i*8)); | |
|
389 | END GENERATE; | |
|
390 | ||
|
391 | addr_pad : outpadv GENERIC MAP (width => 20, tech => padtech) | |
|
392 | PORT MAP (address, memo.address(21 DOWNTO 2)); | |
|
393 | nSRAM_CE_s <= NOT(memo.ramsn(0)); | |
|
394 | rams_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_CE, nSRAM_CE_s); | |
|
395 | oen_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_OE, memo.ramoen(0)); | |
|
396 | nBWE_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_WE, memo.writen); | |
|
397 | nBWa_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE0, memo.mben(3)); | |
|
398 | nBWb_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE1, memo.mben(2)); | |
|
399 | nBWc_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE2, memo.mben(1)); | |
|
400 | nBWd_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (nSRAM_BE3, memo.mben(0)); | |
|
401 | ||
|
402 | ---------------------------------------------------------------------- | |
|
403 | --- AHB CONTROLLER ------------------------------------------------- | |
|
404 | ---------------------------------------------------------------------- | |
|
405 | ahb0 : ahbctrl -- AHB arbiter/multiplexer | |
|
406 | GENERIC MAP (defmast => CFG_DEFMST, split => CFG_SPLIT, | |
|
407 | rrobin => CFG_RROBIN, ioaddr => CFG_AHBIO, | |
|
408 | ioen => 0, nahbm => maxahbmsp, nahbs => 8) | |
|
409 | PORT MAP (rstn, clkm, ahbmi, ahbmo, ahbsi, ahbso); | |
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410 | ||
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411 | ---------------------------------------------------------------------- | |
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412 | --- AHB UART ------------------------------------------------------- | |
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413 | ---------------------------------------------------------------------- | |
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414 | dcomgen : IF CFG_AHB_UART = 1 GENERATE | |
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415 | dcom0 : ahbuart | |
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416 | GENERIC MAP (hindex => maxahbmsp-1, pindex => 4, paddr => 4) | |
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417 | PORT MAP (rstn, clkm, ahbuarti, ahbuarto, apbi, apbo(4), ahbmi, ahbmo(maxahbmsp-1)); | |
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418 | dsurx_pad : inpad GENERIC MAP (tech => padtech) PORT MAP (ahbrxd, ahbuarti.rxd); | |
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419 | dsutx_pad : outpad GENERIC MAP (tech => padtech) PORT MAP (ahbtxd, ahbuarto.txd); | |
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420 | END GENERATE; | |
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421 | nouah : IF CFG_AHB_UART = 0 GENERATE apbo(4) <= apb_none; END GENERATE; | |
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422 | ||
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423 | ---------------------------------------------------------------------- | |
|
424 | --- APB Bridge ----------------------------------------------------- | |
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425 | ---------------------------------------------------------------------- | |
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426 | apb0 : apbctrl -- AHB/APB bridge | |
|
427 | GENERIC MAP (hindex => 1, haddr => CFG_APBADDR) | |
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428 | PORT MAP (rstn, clkm, ahbsi, ahbso(1), apbi, apbo); | |
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429 | ||
|
430 | ---------------------------------------------------------------------- | |
|
431 | --- GPT Timer ------------------------------------------------------ | |
|
432 | ---------------------------------------------------------------------- | |
|
433 | gpt : IF CFG_GPT_ENABLE /= 0 GENERATE | |
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434 | timer0 : gptimer -- timer unit | |
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435 | GENERIC MAP (pindex => 3, paddr => 3, pirq => CFG_GPT_IRQ, | |
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436 | sepirq => CFG_GPT_SEPIRQ, sbits => CFG_GPT_SW, ntimers => CFG_GPT_NTIM, | |
|
437 | nbits => CFG_GPT_TW) | |
|
438 | PORT MAP (rstn, clkm, apbi, apbo(3), gpti, gpto); | |
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439 | gpti.dhalt <= dsuo.tstop; | |
|
440 | gpti.extclk <= '0'; | |
|
441 | END GENERATE; | |
|
442 | notim : IF CFG_GPT_ENABLE = 0 GENERATE apbo(3) <= apb_none; END GENERATE; | |
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443 | ||
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444 | ||
|
445 | ---------------------------------------------------------------------- | |
|
446 | --- APB UART ------------------------------------------------------- | |
|
447 | ---------------------------------------------------------------------- | |
|
448 | ua1 : IF CFG_UART1_ENABLE /= 0 GENERATE | |
|
449 | uart1 : apbuart -- UART 1 | |
|
450 | GENERIC MAP (pindex => 1, paddr => 1, pirq => 2, console => dbguart, | |
|
451 | fifosize => CFG_UART1_FIFO) | |
|
452 | PORT MAP (rstn, clkm, apbi, apbo(1), apbuarti, apbuarto); | |
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453 | apbuarti.rxd <= urxd1; | |
|
454 | apbuarti.extclk <= '0'; | |
|
455 | utxd1 <= apbuarto.txd; | |
|
456 | apbuarti.ctsn <= '0'; | |
|
457 | END GENERATE; | |
|
458 | noua0 : IF CFG_UART1_ENABLE = 0 GENERATE apbo(1) <= apb_none; END GENERATE; | |
|
459 | ||
|
460 | ------------------------------------------------------------------------------- | |
|
461 | -- AMBA BUS ------------------------------------------------------------------- | |
|
462 | ------------------------------------------------------------------------------- | |
|
463 | ||
|
464 | -- APB -------------------------------------------------------------------- | |
|
465 | apbi_ext <= apbi; | |
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466 | all_apb : FOR I IN 0 TO NB_APB_SLAVE-1 GENERATE | |
|
467 | max_16_apb : IF I + 5 < 16 GENERATE | |
|
468 | apbo(I+5) <= apbo_ext(I+5); | |
|
469 | END GENERATE max_16_apb; | |
|
470 | END GENERATE all_apb; | |
|
471 | -- AHB_Slave -------------------------------------------------------------- | |
|
472 | ahbi_s_ext <= ahbsi; | |
|
473 | all_ahbs : FOR I IN 0 TO NB_AHB_SLAVE-1 GENERATE | |
|
474 | max_16_ahbs : IF I + 3 < 16 GENERATE | |
|
475 | ahbso(I+3) <= ahbo_s_ext(I+3); | |
|
476 | END GENERATE max_16_ahbs; | |
|
477 | END GENERATE all_ahbs; | |
|
478 | -- AHB_Master ------------------------------------------------------------- | |
|
479 | ahbi_m_ext <= ahbmi; | |
|
480 | all_ahbm : FOR I IN 0 TO NB_AHB_MASTER-1 GENERATE | |
|
481 | max_16_ahbm : IF I + CFG_NCPU + CFG_AHB_UART < 16 GENERATE | |
|
482 | ahbmo(I + CFG_NCPU) <= ahbo_m_ext(I+CFG_NCPU); | |
|
483 | END GENERATE max_16_ahbm; | |
|
484 | END GENERATE all_ahbm; | |
|
485 | ||
|
486 | ||
|
487 | ||
|
488 | END Behavioral; |
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