HG_REPOSITORIES/LPP/INSTRUMENTATION/VHD_Lib Commit - r500:50f24bdc968c

Correction du CIC (probleme d'ecriture des datas des COMB 256)

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r500:50f24bdc968c JC

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r500:50f24bdc968c

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boards/em-LeonLPP-A3PE3kL-v3-core1/em-LeonLPP-A3PE3kL_withHK.pdc created 644 +122 0

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	1	set_io clk49_152MHz -pinname D5 -fixed yes -DIRECTION Inout
	2	set_io clk100MHz -pinname B3 -fixed yes -DIRECTION Inout
	3	set_io reset -pinname N18 -fixed yes -DIRECTION Inout
	4
	5	set_io {address[0]} -pinname H16 -fixed yes -DIRECTION Inout
	6	set_io {address[1]} -pinname J15 -fixed yes -DIRECTION Inout
	7	set_io {address[2]} -pinname B18 -fixed yes -DIRECTION Inout
	8	set_io {address[3]} -pinname C17 -fixed yes -DIRECTION Inout
	9	set_io {address[4]} -pinname C18 -fixed yes -DIRECTION Inout
	10	set_io {address[5]} -pinname U2 -fixed yes -DIRECTION Inout
	11	set_io {address[6]} -pinname U3 -fixed yes -DIRECTION Inout
	12	set_io {address[7]} -pinname R5 -fixed yes -DIRECTION Inout
	13	set_io {address[8]} -pinname N11 -fixed yes -DIRECTION Inout
	14	set_io {address[9]} -pinname R13 -fixed yes -DIRECTION Inout
	15	set_io {address[10]} -pinname V13 -fixed yes -DIRECTION Inout
	16	set_io {address[11]} -pinname U13 -fixed yes -DIRECTION Inout
	17	set_io {address[12]} -pinname V15 -fixed yes -DIRECTION Inout
	18	set_io {address[13]} -pinname V16 -fixed yes -DIRECTION Inout
	19	set_io {address[14]} -pinname V17 -fixed yes -DIRECTION Inout
	20	set_io {address[15]} -pinname N1 -fixed yes -DIRECTION Inout
	21	set_io {address[16]} -pinname R3 -fixed yes -DIRECTION Inout
	22	set_io {address[17]} -pinname P4 -fixed yes -DIRECTION Inout
	23	set_io {address[18]} -pinname N3 -fixed yes -DIRECTION Inout
	24	set_io {address[19]} -pinname M7 -fixed yes -DIRECTION Inout
	25
	26	set_io {data[0]} -pinname P17 -fixed yes -DIRECTION Inout
	27	set_io {data[1]} -pinname R18 -fixed yes -DIRECTION Inout
	28	set_io {data[2]} -pinname T18 -fixed yes -DIRECTION Inout
	29	set_io {data[3]} -pinname J13 -fixed yes -DIRECTION Inout
	30	set_io {data[4]} -pinname T13 -fixed yes -DIRECTION Inout
	31	set_io {data[5]} -pinname T12 -fixed yes -DIRECTION Inout
	32	set_io {data[6]} -pinname R12 -fixed yes -DIRECTION Inout
	33	set_io {data[7]} -pinname T11 -fixed yes -DIRECTION Inout
	34	set_io {data[8]} -pinname N2 -fixed yes -DIRECTION Inout
	35	set_io {data[9]} -pinname P1 -fixed yes -DIRECTION Inout
	36	set_io {data[10]} -pinname R1 -fixed yes -DIRECTION Inout
	37	set_io {data[11]} -pinname T1 -fixed yes -DIRECTION Inout
	38	set_io {data[12]} -pinname M4 -fixed yes -DIRECTION Inout
	39	set_io {data[13]} -pinname K1 -fixed yes -DIRECTION Inout
	40	set_io {data[14]} -pinname J1 -fixed yes -DIRECTION Inout
	41	set_io {data[15]} -pinname H1 -fixed yes -DIRECTION Inout
	42	set_io {data[16]} -pinname H15 -fixed yes -DIRECTION Inout
	43	set_io {data[17]} -pinname G15 -fixed yes -DIRECTION Inout
	44	set_io {data[18]} -pinname H13 -fixed yes -DIRECTION Inout
	45	set_io {data[19]} -pinname G12 -fixed yes -DIRECTION Inout
	46	set_io {data[20]} -pinname V14 -fixed yes -DIRECTION Inout
	47	set_io {data[21]} -pinname N9 -fixed yes -DIRECTION Inout
	48	set_io {data[22]} -pinname M13 -fixed yes -DIRECTION Inout
	49	set_io {data[23]} -pinname M15 -fixed yes -DIRECTION Inout
	50	set_io {data[24]} -pinname J17 -fixed yes -DIRECTION Inout
	51	set_io {data[25]} -pinname K15 -fixed yes -DIRECTION Inout
	52	set_io {data[26]} -pinname J14 -fixed yes -DIRECTION Inout
	53	set_io {data[27]} -pinname U18 -fixed yes -DIRECTION Inout
	54	set_io {data[28]} -pinname H18 -fixed yes -DIRECTION Inout
	55	set_io {data[29]} -pinname J18 -fixed yes -DIRECTION Inout
	56	set_io {data[30]} -pinname G17 -fixed yes -DIRECTION Inout
	57	set_io {data[31]} -pinname F18 -fixed yes -DIRECTION Inout
	58
	59	set_io nSRAM_BE0 -pinname U12 -fixed yes -DIRECTION Inout
	60	set_io nSRAM_BE1 -pinname K18 -fixed yes -DIRECTION Inout
	61	set_io nSRAM_BE2 -pinname K12 -fixed yes -DIRECTION Inout
	62	set_io nSRAM_BE3 -pinname F17 -fixed yes -DIRECTION Inout
	63	set_io nSRAM_WE -pinname D18 -fixed yes -DIRECTION Inout
	64	set_io nSRAM_CE -pinname M6 -fixed yes -DIRECTION Inout
	65	set_io nSRAM_OE -pinname N12 -fixed yes -DIRECTION Inout
	66
	67	set_io spw1_din -pinname D6 -fixed yes -DIRECTION Inout
	68	set_io spw1_sin -pinname C6 -fixed yes -DIRECTION Inout
	69	set_io spw1_dout -pinname C16 -fixed yes -DIRECTION Inout
	70	set_io spw1_sout -pinname C4 -fixed yes -DIRECTION Inout
	71
	72	set_io spw2_din -pinname E6 -fixed yes -DIRECTION Inout
	73	set_io spw2_sin -pinname C15 -fixed yes -DIRECTION Inout
	74	set_io spw2_dout -pinname B7 -fixed yes -DIRECTION Inout
	75	set_io spw2_sout -pinname D7 -fixed yes -DIRECTION Inout
	76
	77	set_io {led[0]} -pinname K17 -fixed yes -DIRECTION Inout
	78	set_io {led[1]} -pinname L18 -fixed yes -DIRECTION Inout
	79	set_io {led[2]} -pinname M17 -fixed yes -DIRECTION Inout
	80
	81	set_io TAG1 -pinname J12 -fixed yes -DIRECTION Inout
	82	set_io TAG2 -pinname K13 -fixed yes -DIRECTION Inout
	83	set_io TAG3 -pinname L16 -fixed yes -DIRECTION Inout
	84	set_io TAG4 -pinname L15 -fixed yes -DIRECTION Inout
	85	#set_io TAG5 -pinname M16 -fixed yes -DIRECTION Inout
	86	#set_io TAG6 -pinname L13 -fixed yes -DIRECTION Inout
	87	#set_io TAG7 -pinname P6 -fixed yes -DIRECTION Inout
	88	set_io TAG8 -pinname R6 -fixed yes -DIRECTION Inout
	89	#set_io TAG9 -pinname T4 -fixed yes -DIRECTION Inout
	90
	91	set_io bias_fail_sw -pinname A3 -fixed yes -DIRECTION Inout
	92
	93	set_io {ADC_OEB_bar_CH[0]} -pinname A13 -fixed yes -DIRECTION Inout
	94	set_io {ADC_OEB_bar_CH[1]} -pinname A14 -fixed yes -DIRECTION Inout
	95	set_io {ADC_OEB_bar_CH[2]} -pinname A10 -fixed yes -DIRECTION Inout
	96	set_io {ADC_OEB_bar_CH[3]} -pinname B10 -fixed yes -DIRECTION Inout
	97	set_io {ADC_OEB_bar_CH[4]} -pinname B13 -fixed yes -DIRECTION Inout
	98	set_io {ADC_OEB_bar_CH[5]} -pinname D13 -fixed yes -DIRECTION Inout
	99	set_io {ADC_OEB_bar_CH[6]} -pinname A11 -fixed yes -DIRECTION Inout
	100	set_io {ADC_OEB_bar_CH[7]} -pinname B12 -fixed yes -DIRECTION Inout
	101
	102	set_io ADC_smpclk -pinname A15 -fixed yes -DIRECTION Inout
	103
	104	set_io HK_smpclk -pinname R11 -fixed yes -DIRECTION Inout
	105	set_io ADC_OEB_bar_HK -pinname D14 -fixed yes -DIRECTION Inout
	106	set_io {HK_SEL[0]} -pinname A2 -fixed yes -DIRECTION Inout
	107	set_io {HK_SEL[1]} -pinname C3 -fixed yes -DIRECTION Inout
	108
	109	set_io {ADC_data[0]} -pinname A16 -fixed yes -DIRECTION Inout
	110	set_io {ADC_data[1]} -pinname B16 -fixed yes -DIRECTION Inout
	111	set_io {ADC_data[2]} -pinname A17 -fixed yes -DIRECTION Inout
	112	set_io {ADC_data[3]} -pinname C12 -fixed yes -DIRECTION Inout
	113	set_io {ADC_data[4]} -pinname B17 -fixed yes -DIRECTION Inout
	114	set_io {ADC_data[5]} -pinname C13 -fixed yes -DIRECTION Inout
	115	set_io {ADC_data[6]} -pinname D15 -fixed yes -DIRECTION Inout
	116	set_io {ADC_data[7]} -pinname E15 -fixed yes -DIRECTION Inout
	117	set_io {ADC_data[8]} -pinname D16 -fixed yes -DIRECTION Inout
	118	set_io {ADC_data[9]} -pinname F16 -fixed yes -DIRECTION Inout
	119	set_io {ADC_data[10]} -pinname F15 -fixed yes -DIRECTION Inout
	120	set_io {ADC_data[11]} -pinname G16 -fixed yes -DIRECTION Inout
	121	set_io {ADC_data[12]} -pinname F13 -fixed yes -DIRECTION Inout
	122	set_io {ADC_data[13]} -pinname G13 -fixed yes -DIRECTION Inout

designs/Validation_CIC_LFR/Makefile created 644 +53 0

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	1	#GRLIB=../..
	2	VHDLIB=../..
	3	SCRIPTSDIR=$(VHDLIB)/scripts/
	4	GRLIB := $(shell sh $(VHDLIB)/scripts/lpp_relpath.sh)
	5	TOP=leon3mp
	6	BOARD=em-LeonLPP-A3PE3kL-v3-core1
	7	include $(GRLIB)/boards/$(BOARD)/Makefile.inc
	8	DEVICE=$(PART)-$(PACKAGE)$(SPEED)
	9	UCF=$(GRLIB)/boards/$(BOARD)/$(TOP).ucf
	10	QSF=$(GRLIB)/boards/$(BOARD)/$(TOP).qsf
	11	EFFORT=high
	12	XSTOPT=
	13	SYNPOPT="set_option -pipe 0; set_option -retiming 0; set_option -write_apr_constraint 0"
	14	#VHDLSYNFILES=config.vhd ahbrom.vhd leon3mp.vhd
	15	VHDLSYNFILES=
	16	VHDLSIMFILES= tb.vhd
	17	SIMTOP=testbench
	18	#SDCFILE=$(GRLIB)/boards/$(BOARD)/synplify.sdc
	19	#SDC=$(GRLIB)/boards/$(BOARD)/leon3mp.sdc
	20	PDC=$(GRLIB)/boards/$(BOARD)/em-LeonLPP-A3PE3kL.pdc
	21	BITGEN=$(GRLIB)/boards/$(BOARD)/default.ut
	22	CLEAN=soft-clean
	23
	24	TECHLIBS = proasic3e
	25
	26	LIBSKIP = core1553bbc core1553brm core1553brt gr1553 corePCIF \
	27	tmtc openchip hynix ihp gleichmann micron usbhc
	28
	29	DIRSKIP = b1553 pcif leon2 leon2ft crypto satcan ddr usb ata i2c \
	30	pci grusbhc haps slink ascs pwm coremp7 spi ac97 \
	31	./amba_lcd_16x2_ctrlr \
	32	./general_purpose/lpp_AMR \
	33	./general_purpose/lpp_balise \
	34	./general_purpose/lpp_delay \
	35	./lpp_bootloader \
	36	./lpp_cna \
	37	./lpp_uart \
	38	./lpp_usb \
	39	./dsp/lpp_fft_rtax \
	40
	41	FILESKIP = i2cmst.vhd \
	42	APB_MULTI_DIODE.vhd \
	43	APB_MULTI_DIODE.vhd \
	44	Top_MatrixSpec.vhd \
	45	APB_FFT.vhd \
	46	lpp_lfr_apbreg.vhd \
	47	CoreFFT.vhd
	48
	49	include $(GRLIB)/bin/Makefile
	50	include $(GRLIB)/software/leon3/Makefile
	51
	52	################## project specific targets ##########################
	53

designs/Validation_CIC_LFR/run.do created 644 +23 0

@@ -0,0 +1,23
	1	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd
	2
	3	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic.vhd
	4	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_integrator.vhd
	5	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_downsampler.vhd
	6	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_comb.vhd
	7
	8
	9	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr.vhd
	10	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_control.vhd
	11	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd
	12	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_address_gen.vhd
	13
	14	vcom -quiet -93 -work work tb.vhd
	15
	16	vsim work.testbench
	17
	18	log -r *
	19
	20	do wave_inout.do
	21
	22	run -all
	23

designs/Validation_CIC_LFR/run_add_sub.do created 644 +12 0

@@ -0,0 +1,12
	1	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_pkg.vhd
	2	vcom -quiet -93 -work lpp ../../lib/lpp/dsp/cic/cic_lfr_add_sub.vhd
	3
	4	vcom -quiet -93 -work work tb_cic_lfr_add_sub.vhd
	5
	6	vsim work.testbench
	7
	8	log -r *
	9
	10	do wave_add_sub.do
	11
	12	run -all

designs/Validation_CIC_LFR/run_calc.do created 644 +10 0

@@ -0,0 +1,10
	1	vcom -quiet -93 -work work tb_calc.vhd
	2
	3	vsim work.testbench
	4
	5	log -r *
	6
	7	do wave_calc.do
	8
	9	run -all
	10

designs/Validation_CIC_LFR/run_calc.vhd created 644 +10 0

@@ -0,0 +1,10
	1	vcom -quiet -93 -work work tb_calc.vhd
	2
	3	vsim work.testbench
	4
	5	log -r *
	6
	7	do wave_calc.do
	8
	9	run -all
	10

designs/Validation_CIC_LFR/tb.vhd created 644 +238 0

@@ -0,0 +1,238
	1
	2	LIBRARY ieee;
	3	USE ieee.std_logic_1164.ALL;
	4	USE IEEE.MATH_REAL.ALL;
	5	USE ieee.numeric_std.ALL;
	6
	7	LIBRARY lpp;
	8	USE lpp.cic_pkg.ALL;
	9	USE lpp.data_type_pkg.ALL;
	10	USE lpp.chirp_pkg.ALL;
	11
	12	ENTITY testbench IS
	13	END;
	14
	15	ARCHITECTURE behav OF testbench IS
	16
	17	SIGNAL clk : STD_LOGIC := '0';
	18	SIGNAL clk_24k : STD_LOGIC := '0';
	19	SIGNAL clk_24k_r : STD_LOGIC := '0';
	20	SIGNAL rstn : STD_LOGIC;
	21	SIGNAL run : STD_LOGIC;
	22	SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
	23	SIGNAL data_gen : STD_LOGIC_VECTOR(15 DOWNTO 0);
	24	SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
	25	SIGNAL data_in_valid : STD_LOGIC;
	26
	27	CONSTANT DATA_VALUE_0 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"7FFF";
	28	CONSTANT DATA_VALUE_1 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"FFFF";
	29	CONSTANT DATA_VALUE_2 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"8000";
	30	CONSTANT DATA_VALUE_3 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0010";
	31	CONSTANT DATA_VALUE_4 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0020";
	32	CONSTANT DATA_VALUE_5 : STD_LOGIC_VECTOR(15 DOWNTO 0) := X"0040";
	33
	34	SIGNAL data_in_0_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
	35
	36	SIGNAL data_in_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	37	SIGNAL data_in_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	38	SIGNAL data_in_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	39	SIGNAL data_in_3 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	40	SIGNAL data_in_4 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	41	SIGNAL data_in_5 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	42
	43	SIGNAL data_in_0_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
	44	SIGNAL data_in_1_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
	45	SIGNAL data_in_2_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
	46	SIGNAL data_in_3_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
	47	SIGNAL data_in_4_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
	48	SIGNAL data_in_5_temp : STD_LOGIC_VECTOR(15 DOWNTO 0);
	49
	50	BEGIN
	51
	52
	53
	54	clk <= NOT clk AFTER 5 ns;
	55	clk_24k <= NOT clk_24k AFTER 20345 ns;
	56
	57	PROCESS (clk, rstn)
	58	BEGIN -- PROCESS
	59	IF rstn = '0' THEN -- asynchronous reset (active low)
	60	data_in_valid <= '0';
	61	clk_24k_r <= '0';
	62	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	63	clk_24k_r <= clk_24k;
	64	IF clk_24k = '1' AND clk_24k_r = '0' THEN
	65	data_in_valid <= '1';
	66	ELSE
	67	data_in_valid <= '0';
	68	END IF;
	69	END IF;
	70	END PROCESS;
	71
	72
	73	PROCESS
	74	BEGIN -- PROCESS
	75	WAIT UNTIL clk = '1';
	76	rstn <= '0';
	77	run <= '0';
	78
	79	WAIT UNTIL clk = '1';
	80	rstn <= '1';
	81	WAIT UNTIL clk = '1';
	82	WAIT UNTIL clk = '1';
	83	run <= '1';
	84	WAIT UNTIL clk = '1';
	85
	86
	87	WAIT FOR 30 ms;
	88	REPORT "* END simulation *" SEVERITY failure;
	89	WAIT;
	90	END PROCESS;
	91	-----------------------------------------------------------------------------
	92	cic_lfr_1: cic_lfr
	93	GENERIC MAP (
	94	tech => 0,
	95	use_RAM_nCEL => 0)
	96	PORT MAP (
	97	clk => clk,
	98	rstn => rstn,
	99	run => run,
	100	data_in => data_in_v,
	101	data_in_valid => data_in_valid,
	102	data_out_16 => OPEN,
	103	data_out_16_valid => OPEN,
	104	data_out_256 => OPEN,
	105	data_out_256_valid => OPEN);
	106	-----------------------------------------------------------------------------
	107	all_bit: FOR J IN 15 DOWNTO 0 GENERATE
	108	data_in_v(0,J) <= data_in_0(J);
	109	data_in_v(1,J) <= data_in_1(J);
	110	data_in_v(2,J) <= data_in_2(J);
	111	data_in_v(3,J) <= data_in_3(J);
	112	data_in_v(4,J) <= data_in_4(J);
	113	data_in_v(5,J) <= data_in_5(J);
	114	END GENERATE all_bit;
	115	-----------------------------------------------------------------------------
	116	--chirp_gen: chirp
	117	-- GENERIC MAP (
	118	-- LOW_FREQUENCY_LIMIT => 0,
	119	-- HIGH_FREQUENCY_LIMIT => 1000,
	120	-- NB_POINT_TO_GEN => 10000,
	121	-- AMPLITUDE => 200,
	122	-- NB_BITS => 16)
	123	-- PORT MAP (
	124	-- clk => clk,
	125	-- rstn => rstn,
	126	-- run => run,
	127	-- data_ack => data_in_valid,
	128	-- data => data_in);
	129
	130	PROCESS (clk, rstn)
	131	BEGIN
	132	IF rstn = '0' THEN
	133	data_in_0_temp <= (OTHERS => '0');
	134	data_in_1_temp <= (OTHERS => '0');
	135	data_in_2_temp <= (OTHERS => '0');
	136	data_in_3_temp <= (OTHERS => '0');
	137	data_in_4_temp <= (OTHERS => '0');
	138	data_in_5_temp <= (OTHERS => '0');
	139	ELSIF clk'event AND clk = '1' THEN
	140	IF data_in_valid = '1' THEN
	141	data_in_0_temp <= DATA_VALUE_0;
	142	data_in_1_temp <= DATA_VALUE_1;
	143	data_in_2_temp <= DATA_VALUE_2;
	144	data_in_3_temp <= DATA_VALUE_3;
	145	data_in_4_temp <= DATA_VALUE_4;
	146	data_in_5_temp <= DATA_VALUE_5;
	147	END IF;
	148	END IF;
	149	END PROCESS;
	150	--data_in_0 <= data_in_0_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_0;
	151	data_in_1 <= data_in_1_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_1;
	152	data_in_2 <= data_in_2_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_2;
	153	data_in_3 <= data_in_3_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_3;
	154	data_in_4 <= data_in_4_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_4;
	155	data_in_5 <= data_in_5_temp WHEN data_in_valid = '0' ELSE DATA_VALUE_5;
	156
	157	-----------------------------------------------------------------------------
	158	chirp_gen: chirp
	159	GENERIC MAP (
	160	LOW_FREQUENCY_LIMIT => 0,
	161	HIGH_FREQUENCY_LIMIT => 1000,
	162	NB_POINT_TO_GEN => 10000,
	163	AMPLITUDE => 200,
	164	NB_BITS => 16)
	165	PORT MAP (
	166	clk => clk,
	167	rstn => rstn,
	168	run => run,
	169	data_ack => data_in_valid,
	170	data => data_in_0_s);
	171
	172	-----------------------------------------------------------------------------
	173
	174	PROCESS (clk, rstn)
	175	BEGIN -- PROCESS
	176	IF rstn = '0' THEN -- asynchronous reset (active low)
	177	data_in_0 <= (OTHERS => '0');
	178	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	179	IF data_in_valid = '1' THEN
	180	data_in_0 <= data_in_0_s;
	181	END IF;
	182	END IF;
	183	END PROCESS;
	184
	185	-----------------------------------------------------------------------------
	186	cic_1: cic
	187	GENERIC MAP (
	188	D_delay_number => 2,
	189	S_stage_number => 3,
	190	R_downsampling_decimation_factor => 16,
	191	b_data_size => 16,
	192	b_grow => 15) --16 #### log2(RD)*S
	193	PORT MAP (
	194	clk => clk,
	195	rstn => rstn,
	196	run => run,
	197	data_in => data_in_0_s,
	198	data_in_valid => data_in_valid,
	199	data_out => OPEN,
	200	data_out_valid => OPEN);
	201
	202	--cic_16: cic
	203	-- GENERIC MAP (
	204	-- D_delay_number => 2,
	205	-- S_stage_number => 3,
	206	-- R_downsampling_decimation_factor => 16,
	207	-- b_data_size => 16,
	208	-- b_grow => 15) --16 #### log2(RD)*S
	209	-- PORT MAP (
	210	-- clk => clk,
	211	-- rstn => rstn,
	212	-- run => run,
	213	-- data_in => data_in_0_s,
	214	-- data_in_valid => data_in_valid,
	215	-- data_out => OPEN,
	216	-- data_out_valid => OPEN);
	217
	218	cic_256: cic
	219	GENERIC MAP (
	220	D_delay_number => 2,
	221	S_stage_number => 3,
	222	R_downsampling_decimation_factor => 256,
	223	b_data_size => 16,
	224	b_grow => 27) --32 #### log2(RD)S = log2(2562)*3
	225	PORT MAP (
	226	clk => clk,
	227	rstn => rstn,
	228	run => run,
	229	data_in => data_in_0_s,
	230	data_in_valid => data_in_valid,
	231	data_out => OPEN,
	232	data_out_valid => OPEN);
	233
	234
	235
	236
	237
	238	END;

designs/Validation_CIC_LFR/tb_calc.vhd created 644 +124 0

@@ -0,0 +1,124
	1	LIBRARY ieee;
	2	USE ieee.std_logic_1164.ALL;
	3	USE ieee.numeric_std.ALL;
	4
	5	LIBRARY lpp;
	6	USE lpp.cic_pkg.ALL;
	7	USE lpp.data_type_pkg.ALL;
	8	USE lpp.chirp_pkg.ALL;
	9
	10	ENTITY testbench IS
	11	END;
	12
	13	ARCHITECTURE behav OF testbench IS
	14
	15	SIGNAL clk : STD_LOGIC := '0';
	16	SIGNAL rstn : STD_LOGIC;
	17
	18	CONSTANT VECTOR_SIZE : INTEGER := 4*2;
	19	SIGNAL VECTOR_1 : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	20	SIGNAL VECTOR_MIN : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	21	SIGNAL VECTOR_MAX : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	22
	23	SIGNAL all_done : STD_LOGIC;
	24	SIGNAL all_ok : STD_LOGIC;
	25	SIGNAL all_ok_E : STD_LOGIC;
	26
	27	SIGNAL A : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	28	SIGNAL B : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	29
	30	SIGNAL C : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	31
	32	SIGNAL D_0 : STD_LOGIC_VECTOR(VECTOR_SIZE/2 DOWNTO 0);
	33	SIGNAL D_1 : STD_LOGIC_VECTOR(VECTOR_SIZE/2-1 DOWNTO 0);
	34	SIGNAL D : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	35
	36	SIGNAL E : STD_LOGIC_VECTOR(VECTOR_SIZE-1 DOWNTO 0);
	37
	38
	39	BEGIN
	40	VECTOR_1(0) <= '1';
	41	VECTOR_1(VECTOR_SIZE-1 DOWNTO 1) <= (OTHERS => '0') ;
	42
	43	VECTOR_MIN(VECTOR_SIZE-1) <= '1';
	44	VECTOR_MIN(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '0') ;
	45	VECTOR_MAX(VECTOR_SIZE-1) <= '0';
	46	VECTOR_MAX(VECTOR_SIZE-2 DOWNTO 0) <= (OTHERS => '1') ;
	47
	48	clk <= NOT clk AFTER 5 ns;
	49
	50	PROCESSD_0(VECTOR_SIZE/2)
	51	BEGIN -- PROCESS
	52	WAIT UNTIL clk = '1';
	53	rstn <= '0';
	54	WAIT UNTIL clk = '1';
	55	rstn <= '1';
	56	WAIT UNTIL clk = '1';
	57
	58
	59	WAIT FOR 2 ms;
	60	REPORT "* END simulation *" SEVERITY failure;
	61	WAIT;
	62	END PROCESS;
	63
	64	PROCESS (clk, rstn)
	65	BEGIN -- PROCESS
	66	IF rstn = '0' THEN -- asynchronous reset (active low)
	67	A <= VECTOR_MIN;
	68	B <= VECTOR_MIN;
	69	all_done <= '0';
	70	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	71	all_done <= '0';
	72	IF A = VECTOR_MAX THEN
	73	A <= VECTOR_MIN;
	74	IF B = VECTOR_MAX THEN
	75	B <= VECTOR_MIN;
	76	all_done <= '1';
	77	ELSE
	78	B <= STD_LOGIC_VECTOR(signed(B) + signed(VECTOR_1));
	79	END IF;
	80	ELSE
	81	A <= STD_LOGIC_VECTOR(signed(A) + signed(VECTOR_1));
	82	END IF;
	83	END IF;
	84	END PROCESS;
	85
	86
	87	C <= STD_LOGIC_VECTOR(SIGNED(A) - SIGNED(B));
	88
	89	E <= STD_LOGIC_VECTOR(UNSIGNED(A) - UNSIGNED(B));
	90
	91
	92
	93
	94	D_0 <= STD_LOGIC_VECTOR(SIGNED('0'&A(VECTOR_SIZE/2-1 DOWNTO 0)) - SIGNED('0' & B(VECTOR_SIZE/2-1 DOWNTO 0)));
	95
	96	D_1 <= STD_LOGIC_VECTOR( SIGNED(A(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2))
	97	- SIGNED(B(VECTOR_SIZE-1 DOWNTO VECTOR_SIZE/2))
	98	- SIGNED(VECTOR_1(VECTOR_SIZE/2-1 DOWNTO 1) & D_0(VECTOR_SIZE/2) ));
	99
	100	D <= D_1(VECTOR_SIZE/2-1 DOWNTO 0) & D_0(VECTOR_SIZE/2-1 DOWNTO 0);
	101
	102
	103	PROCESS (clk, rstn)
	104	BEGIN -- PROCESS
	105	IF rstn = '0' THEN -- asynchronous reset (active low)
	106	all_ok <= '1';
	107	all_ok_E <= '1';
	108	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	109	IF D = C THEN
	110	all_ok <= '1';
	111	ELSE
	112	all_ok <= '0';
	113	END IF;
	114
	115	IF E = C THEN
	116	all_ok_E <= '1';
	117	ELSE
	118	all_ok_E <= '0';
	119	END IF;
	120	END IF;
	121	END PROCESS;
	122
	123	END;
	124

designs/Validation_CIC_LFR/tb_cic_lfr_add_sub.vhd created 644 +173 0

@@ -0,0 +1,173
	1
	2	LIBRARY ieee;
	3	USE ieee.std_logic_1164.ALL;
	4	USE IEEE.MATH_REAL.ALL;
	5	USE ieee.numeric_std.ALL;
	6
	7	LIBRARY lpp;
	8	USE lpp.cic_pkg.ALL;
	9	USE lpp.data_type_pkg.ALL;
	10	USE lpp.chirp_pkg.ALL;
	11
	12	ENTITY testbench IS
	13
	14	END;
	15
	16	ARCHITECTURE behav OF testbench IS
	17
	18	SIGNAL clk : STD_LOGIC := '0';
	19	SIGNAL clk_24k : STD_LOGIC := '0';
	20	SIGNAL clk_24k_r : STD_LOGIC := '0';
	21	SIGNAL rstn : STD_LOGIC;
	22	SIGNAL run : STD_LOGIC;
	23	SIGNAL data_in : STD_LOGIC_VECTOR(15 DOWNTO 0);
	24	SIGNAL data_in_v : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
	25	SIGNAL data_in_valid : STD_LOGIC;
	26	-----------------------------------------------------------------------------
	27	CONSTANT CARRY : STD_LOGIC := '1';
	28	CONSTANT CARRY_NO : STD_LOGIC := '0';
	29	CONSTANT ADD : STD_LOGIC := '0';
	30	CONSTANT SUB : STD_LOGIC := '1';
	31	SIGNAL OP : STD_LOGIC;
	32	SIGNAL OP_0 : STD_LOGIC_VECTOR(1 DOWNTO 0);
	33	SIGNAL OP_1 : STD_LOGIC_VECTOR(1 DOWNTO 0);
	34	SIGNAL data_out_verif : STD_LOGIC_VECTOR(31 DOWNTO 0);
	35	SIGNAL data_out_verif_s : STD_LOGIC_VECTOR(32 DOWNTO 0);
	36	SIGNAL data_in_A_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
	37	SIGNAL data_in_B_reg : STD_LOGIC_VECTOR(31 DOWNTO 0);
	38	SIGNAL data_in_A : STD_LOGIC_VECTOR(31 DOWNTO 0);
	39	SIGNAL data_in_B : STD_LOGIC_VECTOR(31 DOWNTO 0);
	40	SIGNAL data_out_s : STD_LOGIC_VECTOR(15 DOWNTO 0);
	41	SIGNAL data_out : STD_LOGIC_VECTOR(31 DOWNTO 0);
	42	SIGNAL data_out_pre : STD_LOGIC_VECTOR(31 DOWNTO 0);
	43	SIGNAL data_out_diff : STD_LOGIC_VECTOR(31 DOWNTO 0);
	44	SIGNAL data_out_Carry : STD_LOGIC;
	45
	46	SIGNAL COUNTER_A : INTEGER;
	47	SIGNAL COUNTER_B : INTEGER;
	48	CONSTANT COUNTER_MIN : INTEGER := INTEGER'LOW;
	49	CONSTANT COUNTER_MAX : INTEGER := INTEGER'HIGH;
	50	CONSTANT COUNTER_STEP : INTEGER := INTEGER'HIGH/100;
	51
	52	SIGNAL ALL_is_OK : STD_LOGIC;
	53	BEGIN
	54
	55	clk <= NOT clk AFTER 5 ns;
	56
	57	-----------------------------------------------------------------------------
	58	PROCESS
	59	BEGIN -- PROCESS
	60	WAIT UNTIL clk = '1';
	61	rstn <= '0';
	62	run <= '0';
	63	WAIT UNTIL clk = '1';
	64	rstn <= '1';
	65	WAIT UNTIL clk = '1';
	66	WAIT UNTIL clk = '1';
	67	run <= '1';
	68	WAIT UNTIL clk = '1';
	69	OP <= ADD;
	70	WAIT FOR 500 us;
	71	OP <= SUB;
	72	WAIT FOR 500 us;
	73	REPORT "* END simulation *" SEVERITY failure;
	74	WAIT;
	75	END PROCESS;
	76
	77	PROCESS (clk, rstn)
	78	BEGIN -- PROCESS
	79	IF rstn = '0' THEN -- asynchronous reset (active low)
	80	COUNTER_A <= COUNTER_MIN;
	81	COUNTER_B <= COUNTER_MIN;
	82	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	83	IF COUNTER_A < COUNTER_MAX - COUNTER_STEP THEN
	84	COUNTER_A <= COUNTER_A + COUNTER_STEP;
	85	ELSE
	86	COUNTER_A <= COUNTER_MIN;
	87	IF COUNTER_B < COUNTER_MAX - COUNTER_STEP THEN
	88	COUNTER_B <= COUNTER_B + COUNTER_STEP;
	89	ELSE
	90	COUNTER_B <= COUNTER_MIN;
	91	END IF;
	92	END IF;
	93	END IF;
	94	END PROCESS;
	95
	96	data_in_A <= STD_LOGIC_VECTOR(to_signed(COUNTER_A,32));
	97	data_in_B <= STD_LOGIC_VECTOR(to_signed(COUNTER_B,32));
	98
	99	-----------------------------------------------------------------------------
	100	OP_0 <= CARRY_NO & OP;
	101	OP_1 <= CARRY & OP;
	102	cic_lfr_add_sub_1: cic_lfr_add_sub
	103	PORT MAP (
	104	clk => clk,
	105	rstn => rstn,
	106	run => run,
	107	OP => OP_0,
	108	data_in_A => data_in_A(15 DOWNTO 0),
	109	data_in_B => data_in_B(15 DOWNTO 0),
	110	data_in_Carry => '0',
	111	data_out => data_out_s,
	112	data_out_Carry => data_out_Carry);
	113
	114	PROCESS (clk, rstn)
	115	BEGIN -- PROCESS
	116	IF rstn = '0' THEN -- asynchronous reset (active low)
	117	data_in_A_reg <= (OTHERS => '0');
	118	data_in_B_reg <= (OTHERS => '0');
	119	data_out(15 DOWNTO 0) <= (OTHERS => '0');
	120	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	121	data_in_A_reg <= data_in_A;
	122	data_in_B_reg <= data_in_B;
	123	data_out(15 DOWNTO 0) <= data_out_s;
	124	END IF;
	125	END PROCESS;
	126
	127	cic_lfr_add_sub_2: cic_lfr_add_sub
	128	PORT MAP (
	129	clk => clk,
	130	rstn => rstn,
	131	run => run,
	132	OP => OP_1,
	133	data_in_A => data_in_A_reg(31 DOWNTO 16),
	134	data_in_B => data_in_B_reg(31 DOWNTO 16),
	135	data_in_Carry => data_out_Carry,
	136	data_out => data_out(31 DOWNTO 16),
	137	data_out_Carry => OPEN);
	138	-----------------------------------------------------------------------------
	139	data_out_verif_s <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) + to_integer(SIGNED(data_in_B_reg)),33)) WHEN OP = ADD ELSE
	140	STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_in_A_reg)) - to_integer(SIGNED(data_in_B_reg)),33));
	141	PROCESS (clk, rstn)
	142	BEGIN -- PROCESS
	143	IF rstn = '0' THEN -- asynchronous reset (active low)
	144	data_out_verif <= (OTHERS => '0');
	145	ALL_is_OK <= '0';
	146	data_out_pre <= (OTHERS => '0');
	147	data_out_diff <= (OTHERS => '0');
	148	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	149	data_out_verif <= data_out_verif_s(31 DOWNTO 0);
	150	IF data_out_verif = data_out THEN
	151	ALL_is_OK <= '1';
	152	ELSE
	153	ALL_is_OK <= '0';
	154	END IF;
	155	-------------------------------------------------------------------------
	156	data_out_pre <= data_out;
	157	IF OP = ADD THEN
	158	data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32));
	159	ELSE
	160	data_out_diff <= STD_LOGIC_VECTOR(to_signed(to_integer(SIGNED(data_out)) - to_integer(SIGNED(data_out_pre) ),32));
	161	END IF;
	162	END IF;
	163	END PROCESS;
	164	-----------------------------------------------------------------------------
	165
	166
	167
	168
	169
	170
	171
	172
	173	END;

designs/Validation_CIC_LFR/wave.do created 644 +130 0

@@ -0,0 +1,130
	1	onerror {resume}
	2	quietly WaveActivateNextPane {} 0
	3	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group out -radix hexadecimal /testbench/cic_1/data_out_valid
	4	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group out -radix decimal /testbench/cic_1/data_out
	5	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group in -radix decimal /testbench/cic_1/data_in
	6	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group in -radix hexadecimal /testbench/cic_1/data_in_valid
	7	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data
	8	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group int -radix hexadecimal /testbench/cic_1/I_valid
	9	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in
	10	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_in_valid
	11	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal -childformat {{/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) -radix decimal} {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) -radix decimal}} -expand -subitemconfig {/testbench/cic_1/all_C(1)/cic_comb_1/data_reg(2) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(1) {-radix decimal} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg(0) {-radix decimal}} /testbench/cic_1/all_C(1)/cic_comb_1/data_reg
	12	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_out_valid
	13	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group COMB_1 -radix decimal /testbench/cic_1/all_C(1)/cic_comb_1/data_out
	14	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-radix hexadecimal} /testbench/cic_1/C_data(2) {-radix hexadecimal} /testbench/cic_1/C_data(1) {-radix hexadecimal} /testbench/cic_1/C_data(0) {-radix hexadecimal}} /testbench/cic_1/C_data
	15	add wave -noupdate -expand -group TEMP -expand -group CIC -expand -group internal -expand -group comb -radix hexadecimal /testbench/cic_1/C_valid
	16	add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9)
	17	add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12)
	18	add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15)
	19	add wave -noupdate -expand -group C16_REG -group C0 -expand -group C0_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18)
	20	add wave -noupdate -expand -group C16_REG -group C0 -radix hexadecimal /testbench/cic_1/C_data(0)
	21	add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10)
	22	add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13)
	23	add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16)
	24	add wave -noupdate -expand -group C16_REG -group C1 -expand -group C1_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19)
	25	add wave -noupdate -expand -group C16_REG -group C1 -radix hexadecimal /testbench/cic_1/C_data(1)
	26	add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11)
	27	add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14)
	28	add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17)
	29	add wave -noupdate -expand -group C16_REG -group C2 -expand -group C2_1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20)
	30	add wave -noupdate -expand -group C16_REG -group C2 -radix hexadecimal /testbench/cic_1/C_data(2)
	31	add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix decimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s
	32	add wave -noupdate -expand -group C16_REG -expand -group {C3 - OUTPUT} -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(31) -radix hexadecimal} {/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_1/C_data(3)(31) {-radix hexadecimal} /testbench/cic_1/C_data(3)(30) {-radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-radix hexadecimal}} /testbench/cic_1/C_data(3)
	33	add wave -noupdate -group Literal -radix hexadecimal /testbench/cic_1/C_data(0)
	34	add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(1)
	35	add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0)
	36	add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3)
	37	add wave -noupdate -group I_REG -expand -group I0 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6)
	38	add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(2)
	39	add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1)
	40	add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4)
	41	add wave -noupdate -group I_REG -expand -group I1 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7)
	42	add wave -noupdate -group I_REG -radix hexadecimal /testbench/cic_1/I_data(3)
	43	add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2)
	44	add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5)
	45	add wave -noupdate -group I_REG -expand -group I2 -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8)
	46	add wave -noupdate -group OLD -divider DEBUG
	47	add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/current_channel
	48	add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR
	49	add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/OPERATION
	50	add wave -noupdate -group OLD -group CONTROL -radix hexadecimal /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd
	51	add wave -noupdate -group OLD -group INPUT -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in
	52	add wave -noupdate -group OLD -group INPUT -radix hexadecimal /testbench/cic_lfr_1/data_in_valid
	53	add wave -noupdate -group OLD -group SEL_INPUT -radix unsigned -childformat {{/testbench/cic_lfr_1/sel_sample(2) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(1) -radix unsigned} {/testbench/cic_lfr_1/sel_sample(0) -radix unsigned}} -expand -subitemconfig {/testbench/cic_lfr_1/sel_sample(2) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(1) {-height 15 -radix unsigned} /testbench/cic_lfr_1/sel_sample(0) {-height 15 -radix unsigned}} /testbench/cic_lfr_1/sel_sample
	54	add wave -noupdate -group OLD -group SEL_INPUT -radix hexadecimal /testbench/cic_lfr_1/sample
	55	add wave -noupdate -group OLD -group ALU -radix unsigned -radixenum symbolic /testbench/cic_lfr_1/ALU/OP
	56	add wave -noupdate -group OLD -group ALU -expand -group INPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_A
	57	add wave -noupdate -group OLD -group ALU -expand -group INPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_B
	58	add wave -noupdate -group OLD -group ALU -expand -group INPUT /testbench/cic_lfr_1/ALU/data_in_Carry
	59	add wave -noupdate -group OLD -group ALU -expand -group OUTPUT /testbench/cic_lfr_1/ALU/data_out_Carry
	60	add wave -noupdate -group OLD -group ALU -expand -group OUTPUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out
	61	add wave -noupdate -group OLD -group RAM -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray
	62	add wave -noupdate -group OLD -group RAM -expand -group WRITE /testbench/cic_lfr_1/memCEL/RAMblk/WEN
	63	add wave -noupdate -group OLD -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WD
	64	add wave -noupdate -group OLD -group RAM -expand -group WRITE -radix unsigned /testbench/cic_lfr_1/memCEL/RAMblk/WADDR
	65	add wave -noupdate -group OLD -group RAM -expand -group READ /testbench/cic_lfr_1/memCEL/RAMblk/REN
	66	add wave -noupdate -group OLD -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RD
	67	add wave -noupdate -group OLD -group RAM -expand -group READ -radix unsigned /testbench/cic_lfr_1/memCEL/RAMblk/RADDR
	68	add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_base
	69	add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_init
	70	add wave -noupdate -group OLD /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr_add_1
	71	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/cic_lfr_address_gen_1/addr
	72	add wave -noupdate -group OLD -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16
	73	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg256
	74	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_16_valid
	75	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_16
	76	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_256
	77	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/data_out_256_valid
	78	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg256_s
	79	add wave -noupdate -group OLD -radix unsigned /testbench/cic_lfr_1/sample_out_reg16_s
	80	add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/STATE_CIC_LFR
	81	add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_channel
	82	add wave -noupdate -expand -group CIC_LFR -group CONTROL /testbench/cic_lfr_1/cic_lfr_control_1/current_cmd
	83	add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE /testbench/cic_lfr_1/sel_sample
	84	add wave -noupdate -expand -group CIC_LFR -group SEL_SAMPLE -radix hexadecimal /testbench/cic_lfr_1/sample
	85	add wave -noupdate -expand -group CIC_LFR -group SEL_A /testbench/cic_lfr_1/sel_A
	86	add wave -noupdate -expand -group CIC_LFR -group SEL_A -radix hexadecimal /testbench/cic_lfr_1/data_A
	87	add wave -noupdate -expand -group CIC_LFR -group ALU -radix hexadecimal /testbench/cic_lfr_1/ALU/OP
	88	add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_A
	89	add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_B
	90	add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group IN -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_Carry
	91	add wave -noupdate -expand -group CIC_LFR -group ALU /testbench/cic_lfr_1/CARRY_POP
	92	add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group OUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out
	93	add wave -noupdate -expand -group CIC_LFR -group ALU -expand -group OUT -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out_Carry
	94	add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/CARRY_PUSH
	95	add wave -noupdate -expand -group CIC_LFR /testbench/cic_lfr_1/carry_reg
	96	add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/REN
	97	add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/RD
	98	add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group READ -radix decimal /testbench/cic_lfr_1/memCEL/RAMblk/RADDR
	99	add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WEN
	100	add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WD
	101	add wave -noupdate -expand -group CIC_LFR -group RAM -expand -group WRITE -radix hexadecimal /testbench/cic_lfr_1/memCEL/RAMblk/WADDR
	102	add wave -noupdate -group CARRY -radix hexadecimal /testbench/cic_lfr_1/ALU/data_out_Carry
	103	add wave -noupdate -group CARRY /testbench/cic_lfr_1/CARRY_PUSH
	104	add wave -noupdate -group CARRY /testbench/cic_lfr_1/carry_reg
	105	add wave -noupdate -group CARRY -radix hexadecimal /testbench/cic_lfr_1/ALU/data_in_Carry
	106	add wave -noupdate -group CARRY /testbench/cic_lfr_1/CARRY_POP
	107	add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_in
	108	add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_in_valid
	109	add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16
	110	add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid
	111	add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_256
	112	add wave -noupdate -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid
	113	TreeUpdate [SetDefaultTree]
	114	WaveRestoreCursors {{Cursor 1} {6254226873 ps} 0} {{Cursor 2} {10074245984 ps} 0} {{Cursor 3} {36151600 ps} 0}
	115	quietly wave cursor active 1
	116	configure wave -namecolwidth 377
	117	configure wave -valuecolwidth 188
	118	configure wave -justifyvalue left
	119	configure wave -signalnamewidth 0
	120	configure wave -snapdistance 10
	121	configure wave -datasetprefix 0
	122	configure wave -rowmargin 4
	123	configure wave -childrowmargin 2
	124	configure wave -gridoffset 0
	125	configure wave -gridperiod 1
	126	configure wave -griddelta 40
	127	configure wave -timeline 0
	128	configure wave -timelineunits ns
	129	update
	130	WaveRestoreZoom {0 ps} {15750047250 ps}

designs/Validation_CIC_LFR/wave_add_sub.do created 644 +27 0

@@ -0,0 +1,27
	1	onerror {resume}
	2	quietly WaveActivateNextPane {} 0
	3	add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_a
	4	add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_in_b
	5	add wave -noupdate -format Analog-Step -height 74 -max 2147609999.9999995 -min -2104620000.0 -radix decimal /testbench/data_out
	6	add wave -noupdate /testbench/data_out_carry
	7	add wave -noupdate /testbench/all_is_ok
	8	add wave -noupdate -radix hexadecimal /testbench/data_out
	9	add wave -noupdate -radix hexadecimal /testbench/data_out_pre
	10	add wave -noupdate -radix hexadecimal -subitemconfig {/testbench/data_out_diff(31) {-radix hexadecimal} /testbench/data_out_diff(30) {-radix hexadecimal} /testbench/data_out_diff(29) {-radix hexadecimal} /testbench/data_out_diff(28) {-radix hexadecimal} /testbench/data_out_diff(27) {-radix hexadecimal} /testbench/data_out_diff(26) {-radix hexadecimal} /testbench/data_out_diff(25) {-radix hexadecimal} /testbench/data_out_diff(24) {-radix hexadecimal} /testbench/data_out_diff(23) {-radix hexadecimal} /testbench/data_out_diff(22) {-radix hexadecimal} /testbench/data_out_diff(21) {-radix hexadecimal} /testbench/data_out_diff(20) {-radix hexadecimal} /testbench/data_out_diff(19) {-radix hexadecimal} /testbench/data_out_diff(18) {-radix hexadecimal} /testbench/data_out_diff(17) {-radix hexadecimal} /testbench/data_out_diff(16) {-radix hexadecimal} /testbench/data_out_diff(15) {-radix hexadecimal} /testbench/data_out_diff(14) {-radix hexadecimal} /testbench/data_out_diff(13) {-radix hexadecimal} /testbench/data_out_diff(12) {-radix hexadecimal} /testbench/data_out_diff(11) {-radix hexadecimal} /testbench/data_out_diff(10) {-radix hexadecimal} /testbench/data_out_diff(9) {-radix hexadecimal} /testbench/data_out_diff(8) {-radix hexadecimal} /testbench/data_out_diff(7) {-radix hexadecimal} /testbench/data_out_diff(6) {-radix hexadecimal} /testbench/data_out_diff(5) {-radix hexadecimal} /testbench/data_out_diff(4) {-radix hexadecimal} /testbench/data_out_diff(3) {-radix hexadecimal} /testbench/data_out_diff(2) {-radix hexadecimal} /testbench/data_out_diff(1) {-radix hexadecimal} /testbench/data_out_diff(0) {-radix hexadecimal}} /testbench/data_out_diff
	11	TreeUpdate [SetDefaultTree]
	12	WaveRestoreCursors {{Cursor 1} {55000 ps} 0}
	13	configure wave -namecolwidth 182
	14	configure wave -valuecolwidth 97
	15	configure wave -justifyvalue left
	16	configure wave -signalnamewidth 0
	17	configure wave -snapdistance 10
	18	configure wave -datasetprefix 0
	19	configure wave -rowmargin 4
	20	configure wave -childrowmargin 2
	21	configure wave -gridoffset 0
	22	configure wave -gridperiod 1
	23	configure wave -griddelta 40
	24	configure wave -timeline 0
	25	configure wave -timelineunits ns
	26	update
	27	WaveRestoreZoom {0 ps} {424577 ps}

designs/Validation_CIC_LFR/wave_calc.do created 644 +23 0

@@ -0,0 +1,23
	1	onerror {resume}
	2	quietly WaveActivateNextPane {} 0
	3	add wave -noupdate /testbench/a
	4	add wave -noupdate /testbench/b
	5	add wave -noupdate /testbench/c
	6	add wave -noupdate /testbench/all_done
	7	TreeUpdate [SetDefaultTree]
	8	WaveRestoreCursors {{Cursor 1} {631245000 ps} 1} {{Cursor 2} {590125000 ps} 0}
	9	configure wave -namecolwidth 424
	10	configure wave -valuecolwidth 119
	11	configure wave -justifyvalue left
	12	configure wave -signalnamewidth 0
	13	configure wave -snapdistance 10
	14	configure wave -datasetprefix 0
	15	configure wave -rowmargin 4
	16	configure wave -childrowmargin 2
	17	configure wave -gridoffset 0
	18	configure wave -gridperiod 1
	19	configure wave -griddelta 40
	20	configure wave -timeline 0
	21	configure wave -timelineunits ns
	22	update
	23	WaveRestoreZoom {0 ps} {2100026250 ps}

designs/Validation_CIC_LFR/wave_inout.do created 644 +50 0

@@ -0,0 +1,50
	1	onerror {resume}
	2	quietly WaveActivateNextPane {} 0
	3	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in
	4	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_in_valid
	5	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out
	6	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/data_out_valid
	7	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_data
	8	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/I_valid
	9	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_data
	10	add wave -noupdate -group CIC_256 -radix hexadecimal /testbench/cic_256/C_valid
	11	add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in
	12	add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_in_valid
	13	add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out
	14	add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/data_out_valid
	15	add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/I_data(3) -radix hexadecimal} {/testbench/cic_1/I_data(2) -radix hexadecimal} {/testbench/cic_1/I_data(1) -radix hexadecimal} {/testbench/cic_1/I_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/I_data(3) {-radix hexadecimal} /testbench/cic_1/I_data(2) {-radix hexadecimal} /testbench/cic_1/I_data(1) {-radix hexadecimal} /testbench/cic_1/I_data(0) {-radix hexadecimal}} /testbench/cic_1/I_data
	16	add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/I_valid
	17	add wave -noupdate -expand -group CIC_16 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3) -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} {/testbench/cic_1/C_data(2) -radix hexadecimal} {/testbench/cic_1/C_data(1) -radix hexadecimal} {/testbench/cic_1/C_data(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_1/C_data(3) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_1/C_data(3)(30) -radix hexadecimal} {/testbench/cic_1/C_data(3)(29) -radix hexadecimal} {/testbench/cic_1/C_data(3)(28) -radix hexadecimal} {/testbench/cic_1/C_data(3)(27) -radix hexadecimal} {/testbench/cic_1/C_data(3)(26) -radix hexadecimal} {/testbench/cic_1/C_data(3)(25) -radix hexadecimal} {/testbench/cic_1/C_data(3)(24) -radix hexadecimal} {/testbench/cic_1/C_data(3)(23) -radix hexadecimal} {/testbench/cic_1/C_data(3)(22) -radix hexadecimal} {/testbench/cic_1/C_data(3)(21) -radix hexadecimal} {/testbench/cic_1/C_data(3)(20) -radix hexadecimal} {/testbench/cic_1/C_data(3)(19) -radix hexadecimal} {/testbench/cic_1/C_data(3)(18) -radix hexadecimal} {/testbench/cic_1/C_data(3)(17) -radix hexadecimal} {/testbench/cic_1/C_data(3)(16) -radix hexadecimal} {/testbench/cic_1/C_data(3)(15) -radix hexadecimal} {/testbench/cic_1/C_data(3)(14) -radix hexadecimal} {/testbench/cic_1/C_data(3)(13) -radix hexadecimal} {/testbench/cic_1/C_data(3)(12) -radix hexadecimal} {/testbench/cic_1/C_data(3)(11) -radix hexadecimal} {/testbench/cic_1/C_data(3)(10) -radix hexadecimal} {/testbench/cic_1/C_data(3)(9) -radix hexadecimal} {/testbench/cic_1/C_data(3)(8) -radix hexadecimal} {/testbench/cic_1/C_data(3)(7) -radix hexadecimal} {/testbench/cic_1/C_data(3)(6) -radix hexadecimal} {/testbench/cic_1/C_data(3)(5) -radix hexadecimal} {/testbench/cic_1/C_data(3)(4) -radix hexadecimal} {/testbench/cic_1/C_data(3)(3) -radix hexadecimal} {/testbench/cic_1/C_data(3)(2) -radix hexadecimal} {/testbench/cic_1/C_data(3)(1) -radix hexadecimal} {/testbench/cic_1/C_data(3)(0) -radix hexadecimal}}} /testbench/cic_1/C_data(3)(30) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(29) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(28) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(27) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(26) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(25) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(24) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(23) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(22) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(21) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(20) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(19) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(18) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(17) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(16) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(15) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(14) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(13) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(12) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(11) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(10) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(9) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(8) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(7) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(6) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(5) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(4) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(3) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(3)(0) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(2) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(1) {-height 15 -radix hexadecimal} /testbench/cic_1/C_data(0) {-height 15 -radix hexadecimal}} /testbench/cic_1/C_data
	18	add wave -noupdate -expand -group CIC_16 -radix hexadecimal /testbench/cic_1/C_valid
	19	add wave -noupdate -expand -group CIC_LFR -radix decimal -childformat {{/testbench/cic_lfr_1/data_in(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_in(0) -radix hexadecimal}} -expand -subitemconfig {/testbench/cic_lfr_1/data_in(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_in(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_in
	20	add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_in_valid
	21	add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}}} -expand -subitemconfig {/testbench/cic_lfr_1/data_out_16(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/data_out_16(0)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_16
	22	add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_16_valid
	23	add wave -noupdate -expand -group CIC_LFR -radix hexadecimal -childformat {{/testbench/cic_lfr_1/data_out_256(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_256(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_256(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/data_out_256(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/data_out_256
	24	add wave -noupdate -expand -group CIC_LFR -radix hexadecimal /testbench/cic_lfr_1/data_out_256_valid
	25	add wave -noupdate -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0)
	26	add wave -noupdate -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out
	27	add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal -childformat {{/testbench/cic_lfr_1/data_out_16(0)(15) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(14) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(13) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(12) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(11) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(10) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(9) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(8) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(7) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(6) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(5) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(4) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(3) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(2) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(1) -radix hexadecimal} {/testbench/cic_lfr_1/data_out_16(0)(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/data_out_16(0)(15) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(14) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(13) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(12) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(11) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(10) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(9) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(8) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(7) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(6) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(5) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(4) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(3) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(2) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(1) {-radix hexadecimal} /testbench/cic_lfr_1/data_out_16(0)(0) {-radix hexadecimal}} /testbench/cic_lfr_1/data_out_16(0)
	28	add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(4) -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} {/testbench/cic_lfr_1/sample_out_reg16_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg16_s(5) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(5)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(5)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(5)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(5)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4) {-height 15 -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg16_s(4)(31) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(30) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(29) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(28) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(27) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(26) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(25) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(24) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(23) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(22) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(21) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(20) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(19) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(18) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(17) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(16) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(15) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(14) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(13) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(12) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(11) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(10) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(9) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(8) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(7) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(6) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg16_s(4)(0) -radix hexadecimal}}} /testbench/cic_lfr_1/sample_out_reg16_s(4)(31) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(30) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(29) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(28) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(27) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(26) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(25) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(24) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(23) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(22) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(21) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(20) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(19) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(18) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(17) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(16) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(15) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(14) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(13) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(12) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(11) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(10) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(9) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(8) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(7) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(6) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(5) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(4) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(4)(0) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(3) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(2) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(1) {-height 15 -radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg16_s(0) {-height 15 -radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg16_s
	29	add wave -noupdate -group temp -radix hexadecimal -childformat {{/testbench/cic_lfr_1/sample_out_reg256_s(5) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(4) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(3) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(2) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(1) -radix hexadecimal} {/testbench/cic_lfr_1/sample_out_reg256_s(0) -radix hexadecimal}} -subitemconfig {/testbench/cic_lfr_1/sample_out_reg256_s(5) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(4) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(3) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(2) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(1) {-radix hexadecimal} /testbench/cic_lfr_1/sample_out_reg256_s(0) {-radix hexadecimal}} /testbench/cic_lfr_1/sample_out_reg256_s
	30	add wave -noupdate -group temp -format Analog-Step -height 74 -max 6000000.0 -min 6.0000000000000002e-06 -radix decimal /testbench/cic_lfr_1/sample_out_reg16_s(0)
	31	add wave -noupdate -group temp -format Analog-Step -height 200 -max 200.0 -min -200.0 -radix decimal /testbench/cic_1/data_out
	32	add wave -noupdate -radix hexadecimal -childformat {{/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(0) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(1) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(2) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(3) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(4) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(5) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(6) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(7) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(8) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(9) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(10) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(11) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(12) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(13) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(14) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(15) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(16) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(17) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(18) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(19) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(20) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(21) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(22) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(23) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) -radix hexadecimal} {/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) -radix hexadecimal} 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/testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(24) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(25) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(26) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(27) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(28) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(29) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(30) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(31) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(32) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(33) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(34) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(35) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(36) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(37) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(38) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(39) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(40) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(41) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(42) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(43) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(44) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(45) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(46) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(47) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(48) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(49) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(50) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(51) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(52) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(53) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(54) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(55) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(56) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(57) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(58) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(59) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(60) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(61) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(62) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(63) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(64) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(65) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(66) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(67) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(68) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(69) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(70) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(71) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(72) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(73) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(74) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(75) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(76) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(77) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(78) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(79) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(80) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(81) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(82) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(83) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(84) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(85) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(86) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(87) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(88) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(89) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(90) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(91) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(92) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(93) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(94) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(95) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(96) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(97) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(98) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(99) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(100) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(101) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(102) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(103) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(104) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(105) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(106) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(107) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(108) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(109) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(110) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(111) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(112) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(113) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(114) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(115) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(116) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(117) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(118) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(119) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(120) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(121) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(122) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(123) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(124) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(125) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(126) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(127) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(128) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(129) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(130) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(131) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(132) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(133) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(134) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(135) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(136) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(137) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(138) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(139) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(140) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(141) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(142) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(143) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(144) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(145) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(146) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(147) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(148) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(149) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(150) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(151) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(152) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(153) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(154) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(155) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(156) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(157) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(158) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(159) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(160) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(161) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(162) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(163) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(164) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(165) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(166) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(167) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(168) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(169) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(170) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(171) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(172) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(173) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(174) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(175) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(176) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(177) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(178) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(179) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(180) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(181) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(182) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(183) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(184) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(185) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(186) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(187) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(188) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(189) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(190) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(191) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(192) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(193) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(194) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(195) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(196) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(197) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(198) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(199) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(200) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(201) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(202) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(203) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(204) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(205) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(206) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(207) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(208) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(209) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(210) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(211) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(212) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(213) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(214) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(215) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(216) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(217) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(218) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(219) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(220) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(221) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(222) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(223) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(224) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(225) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(226) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(227) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(228) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(229) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(230) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(231) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(232) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(233) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(234) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(235) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(236) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(237) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(238) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(239) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(240) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(241) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(242) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(243) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(244) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(245) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(246) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(247) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(248) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(249) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(250) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(251) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(252) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(253) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(254) {-radix hexadecimal} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray(255) {-radix hexadecimal}} /testbench/cic_lfr_1/memCEL/RAMblk/RAMarray
	33	TreeUpdate [SetDefaultTree]
	34	WaveRestoreCursors {{Cursor 1} {21545643925 ps} 0} {{Cursor 2} {514701877948 ps} 0} {{Cursor 3} {8443215000 ps} 0}
	35	quietly wave cursor active 3
	36	configure wave -namecolwidth 299
	37	configure wave -valuecolwidth 188
	38	configure wave -justifyvalue left
	39	configure wave -signalnamewidth 0
	40	configure wave -snapdistance 10
	41	configure wave -datasetprefix 0
	42	configure wave -rowmargin 4
	43	configure wave -childrowmargin 2
	44	configure wave -gridoffset 0
	45	configure wave -gridperiod 1
	46	configure wave -griddelta 40
	47	configure wave -timeline 0
	48	configure wave -timelineunits ns
	49	update
	50	WaveRestoreZoom {0 ps} {300136435256 ps}

lib/lpp/lpp_ad_Conv/lpp_lfr_hk.vhd created 644 +140 0

@@ -0,0 +1,140
	1	------------------------------------------------------------------------------
	2	-- This file is a part of the LPP VHDL IP LIBRARY
	3	-- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
	4	--
	5	-- This program is free software; you can redistribute it and/or modify
	6	-- it under the terms of the GNU General Public License as published by
	7	-- the Free Software Foundation; either version 3 of the License, or
	8	-- (at your option) any later version.
	9	--
	10	-- This program is distributed in the hope that it will be useful,
	11	-- but WITHOUT ANY WARRANTY; without even the implied warranty of
	12	-- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	13	-- GNU General Public License for more details.
	14	--
	15	-- You should have received a copy of the GNU General Public License
	16	-- along with this program; if not, write to the Free Software
	17	-- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
	18	-------------------------------------------------------------------------------
	19	-- Author : Jean-christophe Pellion
	20	-- Mail : jean-christophe.pellion@lpp.polytechnique.fr
	21	-------------------------------------------------------------------------------
	22	LIBRARY IEEE;
	23	USE IEEE.STD_LOGIC_1164.ALL;
	24	USE IEEE.NUMERIC_STD.ALL;
	25
	26	LIBRARY grlib;
	27	USE grlib.amba.ALL;
	28	USE grlib.stdlib.ALL;
	29	USE grlib.devices.ALL;
	30
	31	LIBRARY lpp;
	32	USE lpp.apb_devices_list.ALL;
	33
	34	ENTITY lpp_lfr_hk IS
	35
	36	GENERIC (
	37	pindex : INTEGER := 0;
	38	paddr : INTEGER := 0;
	39	pmask : INTEGER := 16#fff#); --! MASK field of the APB BAR);
	40
	41	PORT (
	42	clk : IN STD_LOGIC;
	43	rstn : IN STD_LOGIC;
	44
	45	apbi : IN apb_slv_in_type; --! APB slave input signals
	46	apbo : OUT apb_slv_out_type; --! APB slave output signals
	47
	48	sample_val : IN STD_LOGIC;
	49	sample : IN STD_LOGIC_VECTOR(15 DOWNTO 0);
	50
	51	HK_SEL : OUT STD_LOGIC_VECTOR(1 DOWNTO 0)
	52	);
	53
	54	END lpp_lfr_hk;
	55
	56
	57	ARCHITECTURE Behavioral OF lpp_lfr_hk IS
	58
	59	-----------------------------------------------------------------------------
	60	-- APB REG
	61	CONSTANT REVISION : INTEGER := 1;
	62
	63	CONSTANT pconfig : apb_config_type := (
	64	0 => ahb_device_reg (VENDOR_LPP, LPP_LFR_HK_DEVICE, 0, REVISION, 0),
	65	1 => apb_iobar(paddr, pmask)
	66	);
	67
	68	TYPE lpp_lfr_HK_reg IS RECORD
	69	temp_0 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	70	temp_1 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	71	temp_2 : STD_LOGIC_VECTOR(15 DOWNTO 0);
	72	END RECORD;
	73
	74	SIGNAL reg_hk : lpp_lfr_HK_reg;
	75
	76	SIGNAL Rdata : STD_LOGIC_VECTOR(31 DOWNTO 0);
	77	-----------------------------------------------------------------------------
	78	SIGNAL HK_SEL_s :STD_LOGIC_VECTOR(1 DOWNTO 0);
	79
	80	BEGIN
	81
	82	-----------------------------------------------------------------------------
	83	-- APB REG
	84	PROCESS (clk, rstn)
	85	BEGIN -- PROCESS
	86	IF rstn = '0' THEN -- asynchronous reset (active low)
	87
	88	Rdata <= (OTHERS => '0');
	89
	90	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	91	--APB READ OP
	92	IF (apbi.psel(pindex) AND (NOT apbi.pwrite)) = '1' THEN
	93	CASE apbi.paddr(7 DOWNTO 2) IS
	94	WHEN "000000" => Rdata(15 DOWNTO 0) <= reg_hk.temp_0;
	95	WHEN "000001" => Rdata(15 DOWNTO 0) <= reg_hk.temp_1;
	96	WHEN "000010" => Rdata(15 DOWNTO 0) <= reg_hk.temp_2;
	97	WHEN OTHERS => Rdata(31 DOWNTO 0) <= (others => '0');
	98	END CASE;
	99	END IF;
	100
	101	END IF;
	102	END PROCESS;
	103
	104	apbo.pirq <= (OTHERS => '0');
	105	apbo.prdata <= Rdata;
	106	apbo.pconfig <= pconfig;
	107	apbo.pindex <= pindex;
	108	-----------------------------------------------------------------------------
	109
	110	PROCESS (clk, rstn)
	111	BEGIN -- PROCESS
	112	IF rstn = '0' THEN -- asynchronous reset (active low)
	113
	114	reg_hk.temp_0 <= (OTHERS => '0');
	115	reg_hk.temp_1 <= (OTHERS => '0');
	116	reg_hk.temp_2 <= (OTHERS => '0');
	117
	118	HK_SEL_s <= "00";
	119
	120	ELSIF clk'event AND clk = '1' THEN -- rising clock edge
	121
	122	IF sample_val = '1' THEN
	123	CASE HK_SEL_s IS
	124	WHEN "00" => reg_hk.temp_0 <= sample; HK_SEL_s <= "01";
	125	WHEN "01" => reg_hk.temp_1 <= sample; HK_SEL_s <= "10";
	126	WHEN "10" => reg_hk.temp_2 <= sample; HK_SEL_s <= "00";
	127	WHEN OTHERS => NULL;
	128	END CASE;
	129
	130	END IF;
	131
	132	END IF;
	133	END PROCESS;
	134
	135	HK_SEL <= HK_SEL_s;
	136
	137	END Behavioral;
	138
	139
	140

lib/lpp/dsp/cic/cic_lfr.vhd +4 -3

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.all;
             LIBRARY lpp;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             USE lpp.iir_filter.ALL;
             LIBRARY techmap;
             USE techmap.gencomp.ALL;
             ENTITY cic_lfr IS
               GENERIC(
                 tech         : INTEGER := 0;
                 use_RAM_nCEL : INTEGER := 0         -- 1 => RAM(tech) , 0 => RAM_CEL
                 );
               PORT (
                 clk            : IN  STD_LOGIC;
                 rstn           : IN  STD_LOGIC;
                 run            : IN  STD_LOGIC;
                 data_in        : IN  sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_in_valid  : IN  STD_LOGIC;
                 data_out_16        : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_out_16_valid  : OUT STD_LOGIC;
                 data_out_256       : OUT sample_vector(5 DOWNTO 0,15 DOWNTO 0);
                 data_out_256_valid : OUT STD_LOGIC
                 );
             END cic_lfr;
             ARCHITECTURE beh OF cic_lfr IS
               --
               SIGNAL sel_sample  : STD_LOGIC_VECTOR(2 DOWNTO 0);
               SIGNAL sample_temp : sample_vector(5 DOWNTO 0,15 DOWNTO 0);
               SIGNAL sample      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL sel_A  : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL data_A_temp : sample_vector(2 DOWNTO 0,15 DOWNTO 0);
               SIGNAL data_A  : STD_LOGIC_VECTOR(15 DOWNTO 0);
               --
               SIGNAL ALU_OP : STD_LOGIC_VECTOR(1 DOWNTO 0);
               SIGNAL data_B      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_B_reg      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_out      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL data_in_Carry  : STD_LOGIC;
               SIGNAL data_out_Carry : STD_LOGIC;
               --
               CONSTANT S_parameter : INTEGER := 3;
               SIGNAL carry_reg  : STD_LOGIC_VECTOR(S_parameter-1 DOWNTO 0);
               SIGNAL CARRY_PUSH : STD_LOGIC;
               SIGNAL CARRY_POP  : STD_LOGIC;
               --
               SIGNAL OPERATION    : STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OPERATION_reg: STD_LOGIC_VECTOR(15 DOWNTO 0);
               SIGNAL OPERATION_reg2: STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               TYPE ARRAY_OF_ADDR IS ARRAY (5 DOWNTO 0) OF STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL   base_addr_INT   : ARRAY_OF_ADDR;
               CONSTANT base_addr_delta : INTEGER := 40;
               SIGNAL addr_base_sel : STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL addr_gen: STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL addr_read: STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL addr_write: STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL addr_write_mux: STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL addr_write_s: STD_LOGIC_VECTOR(7 DOWNTO 0);
               SIGNAL data_we: STD_LOGIC;
               SIGNAL data_we_s: STD_LOGIC;
               SIGNAL data_wen       : STD_LOGIC;
             --  SIGNAL data_write     : STD_LOGIC_VECTOR(15 DOWNTO 0);
             --  SIGNAL data_read      : STD_LOGIC_VECTOR(15 DOWNTO 0);
             --  SIGNAL data_read_pre      : STD_LOGIC_VECTOR(15 DOWNTO 0);
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16   : sample_vector(6*2-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_out_reg256  : sample_vector(6*3-1 DOWNTO 0, 15 DOWNTO 0);
               SIGNAL sample_valid_reg16 : STD_LOGIC_VECTOR(6*2 DOWNTO 0);
               SIGNAL sample_valid_reg256: STD_LOGIC_VECTOR(6*3 DOWNTO 0);
               SIGNAL  data_out_16_valid_s  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s : STD_LOGIC;
               SIGNAL  data_out_16_valid_s1  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s1 : STD_LOGIC;
               SIGNAL  data_out_16_valid_s2  : STD_LOGIC;
               SIGNAL  data_out_256_valid_s2 : STD_LOGIC;
               -----------------------------------------------------------------------------
               SIGNAL sample_out_reg16_s   : sample_vector(5 DOWNTO 0, 16*2-1 DOWNTO 0);
               SIGNAL sample_out_reg256_s  : sample_vector(5 DOWNTO 0, 16*3-1 DOWNTO 0);
               -----------------------------------------------------------------------------
             BEGIN
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_B_reg <=  (OTHERS => '0');
                   OPERATION_reg <= (OTHERS => '0');
                   OPERATION_reg2 <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   OPERATION_reg <= OPERATION;
                   OPERATION_reg2 <= OPERATION_reg;
                   data_B_reg <= data_B;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- SEL_SAMPLE
               -----------------------------------------------------------------------------
               sel_sample <= OPERATION_reg(2 DOWNTO 0);
               all_bit: FOR I IN 15 DOWNTO 0 GENERATE
                 sample_temp(0,I) <= data_in(0,I)     WHEN sel_sample(0) = '0' ELSE data_in(1,I);
                 sample_temp(1,I) <= data_in(2,I)     WHEN sel_sample(0) = '0' ELSE data_in(3,I);
                 sample_temp(2,I) <= data_in(4,I)     WHEN sel_sample(0) = '0' ELSE data_in(5,I);
                 sample_temp(4,I) <= sample_temp(0,I) WHEN sel_sample(1) = '0' ELSE sample_temp(1,I);
                 sample_temp(5,I) <= sample_temp(2,I) WHEN sel_sample(1) = '0' ELSE '0';
                 sample(I)        <= sample_temp(4,I) WHEN sel_sample(2) = '0' ELSE sample_temp(5,I);
               END GENERATE all_bit;
               -----------------------------------------------------------------------------
               -- SEL_DATA_IN_A
               -----------------------------------------------------------------------------
               sel_A <= OPERATION_reg(4 DOWNTO 3);
               all_data_mux_A: FOR I IN 15 DOWNTO 0 GENERATE
                 data_A_temp(0,I) <= sample(I) WHEN sel_A(0) = '0' ELSE data_out(I);
                 data_A_temp(1,I) <= '0'       WHEN sel_A(0) = '0' ELSE sample(15);
                 data_A_temp(2,I) <= data_A_temp(0,I) WHEN sel_A(1) = '0' ELSE data_A_temp(1,I);
                 data_A(I)        <= data_A_temp(2,I) WHEN OPERATION_reg(14) = '0' ELSE data_B_reg(I);
               END GENERATE all_data_mux_A;
               -----------------------------------------------------------------------------
               -- ALU
               -----------------------------------------------------------------------------
               ALU_OP <= OPERATION_reg(6 DOWNTO 5);
               ALU: cic_lfr_add_sub
                 PORT MAP (
                   clk            => clk,
                   rstn           => rstn,
                   run            => run,
                   OP             => ALU_OP,
                   data_in_A      => data_A,
                   data_in_B      => data_B,
                   data_in_Carry  => data_in_Carry,
                   data_out       => data_out,
                   data_out_Carry => data_out_Carry);
               -----------------------------------------------------------------------------
               -- CARRY_MANAGER
               -----------------------------------------------------------------------------
               data_in_Carry <= carry_reg(S_parameter-2) WHEN OPERATION_reg(7) = '0' ELSE carry_reg(S_parameter-1);
             --  CARRY_PUSH <= OPERATION_reg(7);
             --  CARRY_POP  <= OPERATION_reg(6);
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   carry_reg <= (OTHERS => '0');
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   --IF CARRY_POP = '1' OR CARRY_PUSH = '1' THEN
                     carry_reg(S_parameter-1 DOWNTO 1) <= carry_reg(S_parameter-2 DOWNTO 0);
                     carry_reg(0)                      <= data_out_Carry;
                   --END IF;
                 END IF;
               END PROCESS;
               -----------------------------------------------------------------------------
               -- MEMORY
               -----------------------------------------------------------------------------
               all_channel: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bit: FOR J IN 7 DOWNTO 0 GENERATE
                   base_addr_INT(I)(J) <= '1' WHEN (base_addr_delta * I/(2**J)) MOD 2 = 1 ELSE '0';
                 END GENERATE all_bit;
               END GENERATE all_channel;
               addr_base_sel <= base_addr_INT(to_integer(UNSIGNED(OPERATION(2 DOWNTO 0))));
               cic_lfr_address_gen_1: cic_lfr_address_gen
                 PORT MAP (
                   clk               => clk,
                   rstn              => rstn,
                   run               => run,
                   addr_base         => addr_base_sel,
                   addr_init         => OPERATION(8),
                   addr_add_1        => OPERATION(9),
                   addr              => addr_gen);
               addr_read <= addr_gen                                                               WHEN OPERATION(12 DOWNTO 10) = "000" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+2,8)) WHEN OPERATION(12 DOWNTO 10) = "001" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+5,8)) WHEN OPERATION(12 DOWNTO 10) = "010" ELSE
                            STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_base_sel))+8,8)) WHEN OPERATION(12 DOWNTO 10) = "011" ELSE
-                           STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+6,8));
+                           STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+6,8)) WHEN OPERATION(12 DOWNTO 10) = "100" ELSE
+                           STD_LOGIC_VECTOR(to_unsigned(to_integer(UNSIGNED(addr_gen     ))+15,8));
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   addr_write   <= (OTHERS => '0');
                   data_we      <= '0';
                   addr_write_s <= (OTHERS => '0');
                   data_we_s    <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   addr_write_s <= addr_read;
                   data_we_s    <= OPERATION(13);
                   IF OPERATION_reg(15) = '0' THEN
                     addr_write   <= addr_write_s;
                   ELSE
                     addr_write <= addr_read;
                   END IF;
                   data_we      <= data_we_s;
                 END IF;
               END PROCESS;
               memCEL : IF use_RAM_nCEL = 0 GENERATE
                 data_wen <= NOT data_we;
                 RAMblk : RAM_CEL
                   GENERIC MAP(16, 8)
                   PORT MAP(
                     WD    => data_out,
                     RD    => data_B,
                     WEN   => data_wen,
                     REN   => '0',
                     WADDR => addr_write,
                     RADDR => addr_read,
                     RWCLK => clk,
                     RESET => rstn
                     ) ;
               END GENERATE;
               memRAM : IF use_RAM_nCEL = 1 GENERATE
                 SRAM : syncram_2p
                   GENERIC MAP(tech, 8, 16)
                   PORT MAP(clk, '1', addr_read,  data_B,
                            clk, data_we, addr_write, data_out);
               END GENERATE;
               -----------------------------------------------------------------------------
               -- CONTROL
               -----------------------------------------------------------------------------
               cic_lfr_control_1: cic_lfr_control
                 PORT MAP (
                   clk                => clk,
                   rstn               => rstn,
                   run                => run,
                   data_in_valid      => data_in_valid,
                   data_out_16_valid  => data_out_16_valid_s,
                   data_out_256_valid => data_out_256_valid_s,
                   OPERATION          => OPERATION);
               -----------------------------------------------------------------------------
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   data_out_16_valid_s1 <= '0';
                   data_out_256_valid_s1 <= '0';
                   data_out_16_valid_s2 <= '0';
                   data_out_256_valid_s2 <= '0';
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   data_out_16_valid_s1 <= data_out_16_valid_s;
                   data_out_256_valid_s1 <= data_out_256_valid_s;
                   data_out_16_valid_s2  <= data_out_16_valid_s1;
                   data_out_256_valid_s2 <= data_out_256_valid_s1;
                 END IF;
               END PROCESS;
               PROCESS (clk, rstn)
               BEGIN  -- PROCESS
                 IF rstn = '0' THEN                  -- asynchronous reset (active low)
                   sample_valid_reg16  <= '0' & "000000" & "000001";
                   sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
                 ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                   IF run = '0' THEN
                     sample_valid_reg16  <= '0' & "000000" & "000001";
                     sample_valid_reg256 <= '0' & "000000" & "000000" & "000001";
                   ELSE
                     IF data_out_16_valid_s2 = '1' OR sample_valid_reg16(6*2) = '1' THEN
                       sample_valid_reg16  <= sample_valid_reg16(6*2-1 DOWNTO 0)  & sample_valid_reg16(6*2);
                     END IF;
                     IF data_out_256_valid_s2 = '1' OR sample_valid_reg256(6*3) = '1' THEN
                       sample_valid_reg256 <= sample_valid_reg256(6*3-1 DOWNTO 0) & sample_valid_reg256(6*3);
                     END IF;
                   END IF;
                 END IF;
               END PROCESS;
               data_out_16_valid  <= sample_valid_reg16(6*2);
               data_out_256_valid <= sample_valid_reg256(6*3);
               -----------------------------------------------------------------------------
               all_bits: FOR J IN 15 DOWNTO 0 GENERATE
                 all_channel_out16: FOR I IN 6*2-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN              -- asynchronous reset (active low)
                       sample_out_reg16(I,J)  <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF run = '0' THEN
                         sample_out_reg16(I,J)  <= '0';
                       ELSE
                         IF sample_valid_reg16(I) = '1' AND data_out_16_valid_s2 = '1' THEN
                           sample_out_reg16(I,J) <= data_out(J);
                         END IF;
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_channel_out16;
                 all_channel_out256: FOR I IN 6*3-1 DOWNTO 0 GENERATE
                   PROCESS (clk, rstn)
                   BEGIN  -- PROCESS
                     IF rstn = '0' THEN              -- asynchronous reset (active low)
                       sample_out_reg256(I,J) <= '0';
                     ELSIF clk'event AND clk = '1' THEN  -- rising clock edge
                       IF run = '0' THEN
                         sample_out_reg256(I,J) <= '0';
                       ELSE
                         IF sample_valid_reg256(I) = '1' AND data_out_256_valid_s2 = '1' THEN
                           sample_out_reg256(I,J) <= data_out(J);
                         END IF;
                       END IF;
                     END IF;
                   END PROCESS;
                 END GENERATE all_channel_out256;
               END GENERATE all_bits;
               all_channel_out: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
                   all_reg_16: FOR K IN 1 DOWNTO 0 GENERATE
                     sample_out_reg16_s(I,J+(K*16)) <= sample_out_reg16(2*I+K,J);
                   END GENERATE all_reg_16;
                   all_reg_256: FOR K IN 2 DOWNTO 0 GENERATE
                     sample_out_reg256_s(I,J+(K*16)) <= sample_out_reg256(3*I+K,J);
                   END GENERATE all_reg_256;
                 END GENERATE all_bits;
               END GENERATE all_channel_out;
               all_channel_out_v: FOR I IN 5 DOWNTO 0 GENERATE
                 all_bits: FOR J IN 15 DOWNTO 0 GENERATE
-                  data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-1);
+                  data_out_256(I,J) <= sample_out_reg256_s(I,J+16*2-32+27);
-                  data_out_16(I,J)  <= sample_out_reg16_s (I,J+16  -1);
+                  data_out_16(I,J)  <= sample_out_reg16_s (I,J+16  -16+15);
                 END GENERATE all_bits;
               END GENERATE all_channel_out_v;
             END beh;

lib/lpp/dsp/cic/cic_lfr_control.vhd +19 -12

             ------------------------------------------------------------------------------
             --  This file is a part of the LPP VHDL IP LIBRARY
             --  Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
             --
             --  This program is free software; you can redistribute it and/or modify
             --  it under the terms of the GNU General Public License as published by
             --  the Free Software Foundation; either version 3 of the License, or
             --  (at your option) any later version.
             --
             --  This program is distributed in the hope that it will be useful,
             --  but WITHOUT ANY WARRANTY; without even the implied warranty of
             --  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
             --  GNU General Public License for more details.
             --
             --  You should have received a copy of the GNU General Public License
             --  along with this program; if not, write to the Free Software
             --  Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA  02111-1307  USA
             -------------------------------------------------------------------------------
             --                    Author : Jean-christophe Pellion
             --                    Mail   : jean-christophe.pellion@lpp.polytechnique.fr
             --                             jean-christophe.pellion@easii-ic.com
             ----------------------------------------------------------------------------
             LIBRARY ieee;
             USE ieee.std_logic_1164.ALL;
             USE ieee.numeric_std.ALL;
             LIBRARY lpp;
             USE lpp.cic_pkg.ALL;
             USE lpp.data_type_pkg.ALL;
             ENTITY cic_lfr_control IS
               PORT (
                 clk                : IN  STD_LOGIC;
                 rstn               : IN  STD_LOGIC;
                 run                : IN  STD_LOGIC;
                 --
                 data_in_valid      : IN  STD_LOGIC;
                 data_out_16_valid  : OUT STD_LOGIC;
                 data_out_256_valid : OUT STD_LOGIC;
                 --
                 OPERATION          : OUT STD_LOGIC_VECTOR(15 DOWNTO 0)
                 );
             END cic_lfr_control;
             ARCHITECTURE beh OF cic_lfr_control IS
               TYPE STATE_CIC_LFR_TYPE IS (IDLE,
                                           RUN_PROG_I,
                                           RUN_PROG_C16,
                                           RUN_PROG_C256
                                           );
               SIGNAL STATE_CIC_LFR : STATE_CIC_LFR_TYPE;
               SIGNAL nb_data_receipt : INTEGER := 0;
               SIGNAL current_cmd     : INTEGER := 0;
               SIGNAL current_channel : INTEGER := 0;
               SIGNAL sample_16_odd   : STD_LOGIC;
               SIGNAL sample_256_odd  : STD_LOGIC;
               TYPE     PROGRAM_ARRAY IS ARRAY (INTEGER RANGE <>) OF STD_LOGIC_VECTOR(13 DOWNTO 0);
               --OPERATION( 8 DOWNTO  0) <= PROGRAM_ARRAY( 8 DOWNTO 0) sauf pour PROG_I(0)
               --OPERATION(13 DOWNTO 12) <= PROGRAM_ARRAY(10 DOWNTO 9)
               --OPERATION(11 DOWNTO  9) <= current_channel
               --OPERATION(14)           <= PROGRAM_ARRAY(11) selon sample_X_odd et l'etat
               CONSTANT PROG : PROGRAM_ARRAY(0 TO 28) :=
                 (
                 -- DCBA     98765     43210
                 --PROG I------------------
                   "0001" & "00011" & "00000",                     --0
                   "0101" & "00010" & "00001",                     --1
                   "0101" & "00010" & "00001",                     --2
                   "0001" & "00010" & "01011",                     --3
                   "0101" & "00010" & "01001",                     --4
                   "0101" & "00010" & "01001",                     --5
                   "0001" & "00010" & "01011",                     --6
                   "0101" & "00010" & "01001",                     --7
                   "0101" & "00010" & "01001",                     --8
                 --PROG_C16
                   "1001" & "00100" & "10010",                     --9
                   "1001" & "10010" & "10101",                     --10
                   "1001" & "10010" & "10101",                     --11
                   "1010" & "10010" & "10101",                     --12
                   "1001" & "01000" & "10010",                     --13
                   "1001" & "10010" & "11101",                     --14
                   "1001" & "10010" & "11101",                     --15
                   "1010" & "10010" & "11101",                     --16
                 --PROG_C256
                   "1001" & "00100" & "10010",                     --17
-                  "1001" & "10010" & "10101",                     --18
+                  "1001" & "10110" & "10101",                     --18
-                  "1001" & "10010" & "10101",                     --19
+                  "1001" & "10110" & "10101",                     --19
-                  "1010" & "10010" & "10101",                     --20
+                  "1010" & "10110" & "10101",                     --20
                   "1001" & "01000" & "10010",                     --21
-                  "1001" & "10010" & "11101",                     --22
+                  "1001" & "10110" & "11101",                     --22
-                  "1001" & "10010" & "11101",                     --23
+                  "1001" & "10110" & "11101",                     --23
-                  "1010" & "10010" & "11101",                     --24
+                  "1010" & "10110" & "11101",                     --24
                   "1001" & "01100" & "10010",                     --25
-                  "1001" & "10010" & "11101",                     --26
+                  "1001" & "10110" & "11101",                     --26
-                  "1001" & "10010" & "11101",                     --27
+                  "1001" & "10110" & "11101",                     --27
-                  "1010" & "10010" & "11101"                      --28
+                  "1010" & "10110" & "11101"                      --28
                   );
               CONSTANT PROG_START_I    : INTEGER := 0;
               CONSTANT PROG_END_I      : INTEGER := 8;
               CONSTANT PROG_START_C16  : INTEGER := 9;
               CONSTANT PROG_END_C16    : INTEGER := 16;
               CONSTANT PROG_START_C256 : INTEGER := 17;
               CONSTANT PROG_END_C256   : INTEGER := 28;
             BEGIN
               OPERATION(2 DOWNTO 0)   <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));                                   --SEL_SAMPLE
               OPERATION(4 DOWNTO 3)   <= PROG(current_cmd)(1 DOWNTO 0);                                                       --SEL_DATA_A
               OPERATION(6 DOWNTO 5)   <= "00" WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(3 DOWNTO 2);                                                       --ALU_CMD
               OPERATION(7)            <= '0'  WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(4);                                                                --CARRY_PUSH
               OPERATION(8)            <= PROG(current_cmd)(5);                                                                --@_init
               OPERATION(9)            <= PROG(current_cmd)(6);                                                                --@_add_1
-              OPERATION(11 DOWNTO 10) <= PROG(current_cmd)(8 DOWNTO 7);                                                       --@_sel(1..0)
-              OPERATION(12)           <= PROG(current_cmd)(9) AND sample_16_odd  WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
+              OPERATION(10)           <= PROG(current_cmd)(7) AND PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
-                                         PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0'; --@_sel(2)
+                                         PROG(current_cmd)(7);                        --@_sel(1..0)
+              OPERATION(11)           <= PROG(current_cmd)(8);
+              OPERATION(12)           <= PROG(current_cmd)(9) AND sample_16_odd  WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE
+                                         --PROG(current_cmd)(9) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
+                                         PROG(current_cmd)(9)                    WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE
+                                         '0'; --@_sel(2)
               OPERATION(13)           <= '0' WHEN STATE_CIC_LFR = IDLE ELSE PROG(current_cmd)(10);                            --WE
               OPERATION(14)           <= PROG(current_cmd)(12);  -- SEL_DATA_A = data_b_reg
               OPERATION(15)           <= PROG(current_cmd)(13);  -- WRITE_ADDR_sel
               data_out_16_valid       <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE '0';
               data_out_256_valid      <= PROG(current_cmd)(11) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
               --OPERATION(1 DOWNTO 0) <= PROG(current_cmd)(1 DOWNTO 0);
               --OPERATION(2)          <= '0' WHEN STATE_CIC_LFR = IDLE ELSE
               --                           PROG(current_cmd)(2);
               --OPERATION(5 DOWNTO 3) <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3)) WHEN STATE_CIC_LFR = RUN_PROG_I AND current_cmd = 0 ELSE
               --                           PROG(current_cmd)(5 DOWNTO 3);
               --OPERATION(8 DOWNTO 6) <= "000" WHEN STATE_CIC_LFR = IDLE ELSE
               --                           PROG(current_cmd)(8 DOWNTO 6);
               --OPERATION(11 DOWNTO 9)  <= STD_LOGIC_VECTOR(to_unsigned(current_channel, 3));
               --OPERATION(13 DOWNTO 12) <= PROG(current_cmd)(10 DOWNTO 9);
               --OPERATION(14)           <= PROG(current_cmd)(11) AND sample_16_odd  WHEN STATE_CIC_LFR = RUN_PROG_C16 ELSE
               --                           PROG(current_cmd)(11) AND sample_256_odd WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
               --OPERATION(15)           <= PROG(current_cmd)(12);
               --data_out_16_valid  <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C16  ELSE '0';
               --data_out_256_valid <= PROG(current_cmd)(13) WHEN STATE_CIC_LFR = RUN_PROG_C256 ELSE '0';
               PROCESS (clk, rstn)
               BEGIN
                 IF rstn = '0' THEN
                   STATE_CIC_LFR      <= IDLE;
                   nb_data_receipt    <= 0;
                   current_channel    <= 0;
                   current_cmd        <= 0;
                   sample_16_odd      <= '0';
                   sample_256_odd     <= '0';
                 ELSIF clk'EVENT AND clk = '1' THEN
                   CASE STATE_CIC_LFR IS
                     WHEN IDLE =>
                       IF data_in_valid = '1' THEN
                         STATE_CIC_LFR   <= RUN_PROG_I;
                         current_cmd     <= PROG_START_I;
                         current_channel <= 0;
                         nb_data_receipt <= nb_data_receipt + 1;
                       END IF;
                     WHEN RUN_PROG_I =>
                       IF current_cmd = PROG_END_I THEN
                         IF nb_data_receipt MOD 16 = 15 THEN
                           STATE_CIC_LFR <= RUN_PROG_C16;
                           current_cmd   <= PROG_START_C16;
                           IF current_channel = 0 THEN
                             sample_16_odd <= NOT sample_16_odd;
                           END IF;
                         ELSE
                           IF current_channel = 5 THEN
                             current_channel <= 0;
                             STATE_CIC_LFR   <= IDLE;
                           ELSE
                             current_cmd     <= PROG_START_I;
                             current_channel <= current_channel + 1;
                           END IF;
                         END IF;
                       ELSE
                         current_cmd <= current_cmd +1;
                       END IF;
                     WHEN RUN_PROG_C16 =>
                       IF current_cmd = PROG_END_C16 THEN
                         IF nb_data_receipt MOD 256 = 255 THEN
                           STATE_CIC_LFR <= RUN_PROG_C256;
                           current_cmd   <= PROG_START_C256;
                           IF current_channel = 0 THEN
                             sample_256_odd <= NOT sample_256_odd;
                           END IF;
                         ELSE
                           IF current_channel = 5 THEN
                             current_channel <= 0;
                             STATE_CIC_LFR   <= IDLE;
                           ELSE
                             STATE_CIC_LFR   <= RUN_PROG_I;
                             current_cmd     <= PROG_START_I;
                             current_channel <= current_channel + 1;
                           END IF;
                         END IF;
                       ELSE
                         current_cmd <= current_cmd +1;
                       END IF;
                     WHEN RUN_PROG_C256 =>
                       IF current_cmd = PROG_END_C256 THEN
             --          data_out_256_valid  <= '1';
                         IF current_channel = 5 THEN
                           current_channel <= 0;
                           STATE_CIC_LFR   <= IDLE;
                         ELSE
                           STATE_CIC_LFR   <= RUN_PROG_I;
                           current_cmd     <= PROG_START_I;
                           current_channel <= current_channel + 1;
                         END IF;
                       ELSE
                         current_cmd <= current_cmd +1;
                       END IF;
                     WHEN OTHERS => NULL;
                   END CASE;
                 END IF;
               END PROCESS;
             END beh;

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