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1 | ------------------------------------------------------------------------------ | |||
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2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
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3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
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4 | -- | |||
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5 | -- This program is free software; you can redistribute it and/or modify | |||
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6 | -- it under the terms of the GNU General Public License as published by | |||
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7 | -- the Free Software Foundation; either version 3 of the License, or | |||
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8 | -- (at your option) any later version. | |||
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9 | -- | |||
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10 | -- This program is distributed in the hope that it will be useful, | |||
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11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
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12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
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13 | -- GNU General Public License for more details. | |||
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14 | -- | |||
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15 | -- You should have received a copy of the GNU General Public License | |||
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16 | -- along with this program; if not, write to the Free Software | |||
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17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
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18 | ------------------------------------------------------------------------------- | |||
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19 | -- Author : Jean-christophe PELLION | |||
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20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
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21 | ------------------------------------------------------------------------------- | |||
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22 | ||||
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23 | LIBRARY IEEE; | |||
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24 | USE IEEE.numeric_std.ALL; | |||
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25 | USE IEEE.std_logic_1164.ALL; | |||
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26 | ||||
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27 | LIBRARY techmap; | |||
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28 | USE techmap.gencomp.ALL; | |||
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29 | ||||
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30 | LIBRARY lpp; | |||
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31 | USE lpp.iir_filter.ALL; | |||
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32 | USE lpp.general_purpose.ALL; | |||
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33 | ||||
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34 | ENTITY IIR_CEL_CTRLR_v3 IS | |||
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35 | GENERIC ( | |||
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36 | tech : INTEGER := 0; | |||
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37 | Mem_use : INTEGER := use_RAM; | |||
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38 | Sample_SZ : INTEGER := 18; | |||
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39 | Coef_SZ : INTEGER := 9; | |||
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40 | Coef_Nb : INTEGER := 25; | |||
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41 | Coef_sel_SZ : INTEGER := 5; | |||
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42 | Cels_count : INTEGER := 5; | |||
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43 | ChanelsCount : INTEGER := 8); | |||
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44 | PORT ( | |||
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45 | rstn : IN STD_LOGIC; | |||
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46 | clk : IN STD_LOGIC; | |||
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47 | ||||
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48 | virg_pos : IN INTEGER; | |||
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49 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |||
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50 | ||||
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51 | sample_in1_val : IN STD_LOGIC; | |||
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52 | sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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53 | sample_in2_val : IN STD_LOGIC; | |||
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54 | sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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55 | ||||
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56 | sample_out1_val : OUT STD_LOGIC; | |||
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57 | sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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58 | sample_out2_val : OUT STD_LOGIC; | |||
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59 | sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |||
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60 | END IIR_CEL_CTRLR_v3; | |||
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61 | ||||
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62 | ARCHITECTURE ar_IIR_CEL_CTRLR_v3 OF IIR_CEL_CTRLR_v3 IS | |||
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63 | ||||
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64 | COMPONENT RAM_CTRLR_v2 | |||
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65 | GENERIC ( | |||
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66 | tech : INTEGER; | |||
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67 | Input_SZ_1 : INTEGER; | |||
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68 | Mem_use : INTEGER); | |||
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69 | PORT ( | |||
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70 | rstn : IN STD_LOGIC; | |||
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71 | clk : IN STD_LOGIC; | |||
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72 | ram_write : IN STD_LOGIC; | |||
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73 | ram_read : IN STD_LOGIC; | |||
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74 | raddr_rst : IN STD_LOGIC; | |||
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75 | raddr_add1 : IN STD_LOGIC; | |||
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76 | waddr_previous : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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77 | sample_in : IN STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0); | |||
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78 | sample_out : OUT STD_LOGIC_VECTOR(Input_SZ_1-1 DOWNTO 0)); | |||
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79 | END COMPONENT; | |||
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80 | ||||
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81 | COMPONENT IIR_CEL_CTRLR_v3_DATAFLOW | |||
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82 | GENERIC ( | |||
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83 | Sample_SZ : INTEGER; | |||
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84 | Coef_SZ : INTEGER; | |||
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85 | Coef_Nb : INTEGER; | |||
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86 | Coef_sel_SZ : INTEGER); | |||
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87 | PORT ( | |||
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88 | rstn : IN STD_LOGIC; | |||
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89 | clk : IN STD_LOGIC; | |||
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90 | virg_pos : IN INTEGER; | |||
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91 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |||
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92 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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93 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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94 | ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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95 | ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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96 | alu_sel_input : IN STD_LOGIC; | |||
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97 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |||
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98 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
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99 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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100 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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101 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0)); | |||
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102 | END COMPONENT; | |||
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103 | ||||
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104 | COMPONENT IIR_CEL_CTRLR_v2_CONTROL | |||
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105 | GENERIC ( | |||
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106 | Coef_sel_SZ : INTEGER; | |||
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107 | Cels_count : INTEGER; | |||
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108 | ChanelsCount : INTEGER); | |||
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109 | PORT ( | |||
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110 | rstn : IN STD_LOGIC; | |||
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111 | clk : IN STD_LOGIC; | |||
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112 | sample_in_val : IN STD_LOGIC; | |||
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113 | sample_in_rot : OUT STD_LOGIC; | |||
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114 | sample_out_val : OUT STD_LOGIC; | |||
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115 | sample_out_rot : OUT STD_LOGIC; | |||
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116 | in_sel_src : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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117 | ram_sel_Wdata : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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118 | ram_write : OUT STD_LOGIC; | |||
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119 | ram_read : OUT STD_LOGIC; | |||
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120 | raddr_rst : OUT STD_LOGIC; | |||
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121 | raddr_add1 : OUT STD_LOGIC; | |||
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122 | waddr_previous : OUT STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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123 | alu_sel_input : OUT STD_LOGIC; | |||
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124 | alu_sel_coeff : OUT STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |||
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125 | alu_ctrl : OUT STD_LOGIC_VECTOR(2 DOWNTO 0)); | |||
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126 | END COMPONENT; | |||
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127 | ||||
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128 | SIGNAL in_sel_src : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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129 | SIGNAL ram_sel_Wdata : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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130 | SIGNAL ram_write : STD_LOGIC; | |||
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131 | SIGNAL ram_read : STD_LOGIC; | |||
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132 | SIGNAL raddr_rst : STD_LOGIC; | |||
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133 | SIGNAL raddr_add1 : STD_LOGIC; | |||
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134 | SIGNAL waddr_previous : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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135 | SIGNAL alu_sel_input : STD_LOGIC; | |||
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136 | SIGNAL alu_sel_coeff : STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |||
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137 | SIGNAL alu_ctrl : STD_LOGIC_VECTOR(2 DOWNTO 0); | |||
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138 | ||||
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139 | SIGNAL sample_in_buf : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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140 | SIGNAL sample_in_rotate : STD_LOGIC; | |||
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141 | SIGNAL sample_in_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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142 | SIGNAL sample_out_val_s : STD_LOGIC; | |||
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143 | SIGNAL sample_out_val_s2 : STD_LOGIC; | |||
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144 | SIGNAL sample_out_rot_s : STD_LOGIC; | |||
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145 | SIGNAL sample_out_s : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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146 | ||||
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147 | SIGNAL sample_out_s2 : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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148 | ||||
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149 | SIGNAL ram_input : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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150 | SIGNAL ram_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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151 | -- | |||
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152 | SIGNAL sample_in_val : STD_LOGIC; | |||
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153 | SIGNAL sample_in : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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154 | SIGNAL sample_out_val : STD_LOGIC; | |||
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155 | SIGNAL sample_out : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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156 | ||||
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157 | ----------------------------------------------------------------------------- | |||
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158 | -- | |||
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159 | ----------------------------------------------------------------------------- | |||
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160 | SIGNAL CHANNEL_SEL : STD_LOGIC; | |||
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161 | ||||
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162 | SIGNAL ram_output_1 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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163 | SIGNAL ram_output_2 : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
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164 | ||||
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165 | SIGNAL ram_write_1 : STD_LOGIC; | |||
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166 | SIGNAL ram_read_1 : STD_LOGIC; | |||
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167 | SIGNAL raddr_rst_1 : STD_LOGIC; | |||
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168 | SIGNAL raddr_add1_1 : STD_LOGIC; | |||
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169 | SIGNAL waddr_previous_1 : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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170 | ||||
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171 | SIGNAL ram_write_2 : STD_LOGIC; | |||
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172 | SIGNAL ram_read_2 : STD_LOGIC; | |||
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173 | SIGNAL raddr_rst_2 : STD_LOGIC; | |||
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174 | SIGNAL raddr_add1_2 : STD_LOGIC; | |||
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175 | SIGNAL waddr_previous_2 : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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176 | ----------------------------------------------------------------------------- | |||
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177 | SIGNAL channel_ready : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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178 | SIGNAL channel_val : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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179 | SIGNAL channel_done : STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
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180 | ----------------------------------------------------------------------------- | |||
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181 | TYPE FSM_CHANNEL_SELECTION IS (IDLE, ONGOING_1, ONGOING_2, WAIT_STATE); | |||
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182 | SIGNAL state_channel_selection : FSM_CHANNEL_SELECTION; | |||
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183 | ||||
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184 | SIGNAL sample_out_zero : samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
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185 | ||||
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186 | BEGIN | |||
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187 | ||||
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188 | ----------------------------------------------------------------------------- | |||
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189 | channel_val(0) <= sample_in1_val; | |||
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190 | channel_val(1) <= sample_in2_val; | |||
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191 | all_channel_input_valid: FOR I IN 1 DOWNTO 0 GENERATE | |||
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192 | PROCESS (clk, rstn) | |||
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193 | BEGIN -- PROCESS | |||
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194 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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195 | channel_ready(I) <= '0'; | |||
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196 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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197 | IF channel_val(I) = '1' THEN | |||
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198 | channel_ready(I) <= '1'; | |||
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199 | ELSIF channel_done(I) = '1' THEN | |||
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200 | channel_ready(I) <= '0'; | |||
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201 | END IF; | |||
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202 | END IF; | |||
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203 | END PROCESS; | |||
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204 | END GENERATE all_channel_input_valid; | |||
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205 | ----------------------------------------------------------------------------- | |||
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206 | all_channel_sample_out: FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE | |||
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207 | all_bit: FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE | |||
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208 | sample_out_zero(I,J) <= '0'; | |||
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209 | END GENERATE all_bit; | |||
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210 | END GENERATE all_channel_sample_out; | |||
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211 | ||||
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212 | PROCESS (clk, rstn) | |||
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213 | BEGIN -- PROCESS | |||
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214 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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215 | state_channel_selection <= IDLE; | |||
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216 | CHANNEL_SEL <= '0'; | |||
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217 | sample_in_val <= '0'; | |||
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218 | sample_out1_val <= '0'; | |||
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219 | sample_out2_val <= '0'; | |||
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220 | sample_out1 <= sample_out_zero; | |||
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221 | sample_out2 <= sample_out_zero; | |||
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222 | channel_done <= "00"; | |||
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223 | ||||
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224 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
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225 | CASE state_channel_selection IS | |||
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226 | WHEN IDLE => | |||
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227 | CHANNEL_SEL <= '0'; | |||
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228 | sample_in_val <= '0'; | |||
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229 | sample_out1_val <= '0'; | |||
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230 | sample_out2_val <= '0'; | |||
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231 | channel_done <= "00"; | |||
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232 | IF channel_ready(0) = '1' THEN | |||
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233 | state_channel_selection <= ONGOING_1; | |||
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234 | CHANNEL_SEL <= '0'; | |||
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235 | sample_in_val <= '1'; | |||
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236 | ELSIF channel_ready(1) = '1' THEN | |||
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237 | state_channel_selection <= ONGOING_2; | |||
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238 | CHANNEL_SEL <= '1'; | |||
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239 | sample_in_val <= '1'; | |||
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240 | END IF; | |||
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241 | WHEN ONGOING_1 => | |||
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242 | sample_in_val <= '0'; | |||
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243 | IF sample_out_val = '1' THEN | |||
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244 | state_channel_selection <= WAIT_STATE; | |||
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245 | sample_out1 <= sample_out; | |||
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246 | sample_out1_val <= '1'; | |||
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247 | channel_done(0) <= '1'; | |||
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248 | END IF; | |||
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249 | WHEN ONGOING_2 => | |||
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250 | sample_in_val <= '0'; | |||
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251 | IF sample_out_val = '1' THEN | |||
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252 | state_channel_selection <= WAIT_STATE; | |||
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253 | sample_out2 <= sample_out; | |||
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254 | sample_out2_val <= '1'; | |||
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255 | channel_done(1) <= '1'; | |||
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256 | END IF; | |||
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257 | WHEN WAIT_STATE => | |||
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258 | state_channel_selection <= IDLE; | |||
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259 | CHANNEL_SEL <= '0'; | |||
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260 | sample_in_val <= '0'; | |||
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261 | sample_out1_val <= '0'; | |||
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262 | sample_out2_val <= '0'; | |||
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263 | channel_done <= "00"; | |||
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264 | ||||
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265 | WHEN OTHERS => NULL; | |||
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266 | END CASE; | |||
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267 | ||||
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268 | END IF; | |||
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269 | END PROCESS; | |||
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270 | ||||
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271 | sample_in <= sample_in1 WHEN CHANNEL_SEL = '0' ELSE sample_in2; | |||
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272 | ----------------------------------------------------------------------------- | |||
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273 | ram_output <= ram_output_1 WHEN CHANNEL_SEL = '0' ELSE | |||
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274 | ram_output_2; | |||
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275 | ||||
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276 | ram_write_1 <= ram_write WHEN CHANNEL_SEL = '0' ELSE '0'; | |||
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277 | ram_read_1 <= ram_read WHEN CHANNEL_SEL = '0' ELSE '0'; | |||
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278 | raddr_rst_1 <= raddr_rst WHEN CHANNEL_SEL = '0' ELSE '1'; | |||
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279 | raddr_add1_1 <= raddr_add1 WHEN CHANNEL_SEL = '0' ELSE '0'; | |||
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280 | waddr_previous_1 <= waddr_previous WHEN CHANNEL_SEL = '0' ELSE "00"; | |||
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281 | ||||
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282 | ram_write_2 <= ram_write WHEN CHANNEL_SEL = '1' ELSE '0'; | |||
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283 | ram_read_2 <= ram_read WHEN CHANNEL_SEL = '1' ELSE '0'; | |||
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284 | raddr_rst_2 <= raddr_rst WHEN CHANNEL_SEL = '1' ELSE '1'; | |||
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285 | raddr_add1_2 <= raddr_add1 WHEN CHANNEL_SEL = '1' ELSE '0'; | |||
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286 | waddr_previous_2 <= waddr_previous WHEN CHANNEL_SEL = '1' ELSE "00"; | |||
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287 | ||||
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288 | RAM_CTRLR_v2_1: RAM_CTRLR_v2 | |||
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289 | GENERIC MAP ( | |||
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290 | tech => tech, | |||
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291 | Input_SZ_1 => Sample_SZ, | |||
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292 | Mem_use => Mem_use) | |||
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293 | PORT MAP ( | |||
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294 | clk => clk, | |||
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295 | rstn => rstn, | |||
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296 | ram_write => ram_write_1, | |||
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297 | ram_read => ram_read_1, | |||
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298 | raddr_rst => raddr_rst_1, | |||
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299 | raddr_add1 => raddr_add1_1, | |||
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300 | waddr_previous => waddr_previous_1, | |||
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301 | sample_in => ram_input, | |||
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302 | sample_out => ram_output_1); | |||
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303 | ||||
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304 | RAM_CTRLR_v2_2: RAM_CTRLR_v2 | |||
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305 | GENERIC MAP ( | |||
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306 | tech => tech, | |||
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307 | Input_SZ_1 => Sample_SZ, | |||
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308 | Mem_use => Mem_use) | |||
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309 | PORT MAP ( | |||
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310 | clk => clk, | |||
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311 | rstn => rstn, | |||
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312 | ram_write => ram_write_2, | |||
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313 | ram_read => ram_read_2, | |||
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314 | raddr_rst => raddr_rst_2, | |||
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315 | raddr_add1 => raddr_add1_2, | |||
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316 | waddr_previous => waddr_previous_2, | |||
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317 | sample_in => ram_input, | |||
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318 | sample_out => ram_output_2); | |||
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319 | ----------------------------------------------------------------------------- | |||
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320 | ||||
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321 | IIR_CEL_CTRLR_v3_DATAFLOW_1 : IIR_CEL_CTRLR_v3_DATAFLOW | |||
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322 | GENERIC MAP ( | |||
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323 | Sample_SZ => Sample_SZ, | |||
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324 | Coef_SZ => Coef_SZ, | |||
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325 | Coef_Nb => Coef_Nb, | |||
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326 | Coef_sel_SZ => Coef_sel_SZ) | |||
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327 | PORT MAP ( | |||
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328 | rstn => rstn, | |||
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329 | clk => clk, | |||
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330 | virg_pos => virg_pos, | |||
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331 | coefs => coefs, | |||
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332 | --CTRL | |||
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333 | in_sel_src => in_sel_src, | |||
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334 | ram_sel_Wdata => ram_sel_Wdata, | |||
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335 | -- | |||
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336 | ram_input => ram_input, | |||
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337 | ram_output => ram_output, | |||
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338 | -- | |||
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339 | alu_sel_input => alu_sel_input, | |||
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340 | alu_sel_coeff => alu_sel_coeff, | |||
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341 | alu_ctrl => alu_ctrl, | |||
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342 | alu_comp => "00", | |||
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343 | --DATA | |||
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344 | sample_in => sample_in_s, | |||
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345 | sample_out => sample_out_s); | |||
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346 | ----------------------------------------------------------------------------- | |||
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347 | ||||
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348 | ||||
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349 | IIR_CEL_CTRLR_v3_CONTROL_1 : IIR_CEL_CTRLR_v2_CONTROL | |||
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350 | GENERIC MAP ( | |||
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351 | Coef_sel_SZ => Coef_sel_SZ, | |||
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352 | Cels_count => Cels_count, | |||
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353 | ChanelsCount => ChanelsCount) | |||
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354 | PORT MAP ( | |||
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355 | rstn => rstn, | |||
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356 | clk => clk, | |||
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357 | sample_in_val => sample_in_val, | |||
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358 | sample_in_rot => sample_in_rotate, | |||
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359 | sample_out_val => sample_out_val_s, | |||
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360 | sample_out_rot => sample_out_rot_s, | |||
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361 | ||||
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362 | in_sel_src => in_sel_src, | |||
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363 | ram_sel_Wdata => ram_sel_Wdata, | |||
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364 | ram_write => ram_write, | |||
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365 | ram_read => ram_read, | |||
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366 | raddr_rst => raddr_rst, | |||
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367 | raddr_add1 => raddr_add1, | |||
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368 | waddr_previous => waddr_previous, | |||
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369 | alu_sel_input => alu_sel_input, | |||
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370 | alu_sel_coeff => alu_sel_coeff, | |||
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371 | alu_ctrl => alu_ctrl); | |||
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372 | ||||
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373 | ----------------------------------------------------------------------------- | |||
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374 | -- SAMPLE IN | |||
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375 | ----------------------------------------------------------------------------- | |||
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376 | loop_all_sample : FOR J IN Sample_SZ-1 DOWNTO 0 GENERATE | |||
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377 | ||||
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378 | loop_all_chanel : FOR I IN ChanelsCount-1 DOWNTO 0 GENERATE | |||
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379 | PROCESS (clk, rstn) | |||
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380 | BEGIN -- PROCESS | |||
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381 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
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382 | sample_in_buf(I, J) <= '0'; | |||
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383 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
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384 | IF sample_in_val = '1' THEN | |||
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385 | sample_in_buf(I, J) <= sample_in(I, J); | |||
|
386 | ELSIF sample_in_rotate = '1' THEN | |||
|
387 | sample_in_buf(I, J) <= sample_in_buf((I+1) MOD ChanelsCount, J); | |||
|
388 | END IF; | |||
|
389 | END IF; | |||
|
390 | END PROCESS; | |||
|
391 | END GENERATE loop_all_chanel; | |||
|
392 | ||||
|
393 | sample_in_s(J) <= sample_in(0, J) WHEN sample_in_val = '1' ELSE sample_in_buf(0, J); | |||
|
394 | ||||
|
395 | END GENERATE loop_all_sample; | |||
|
396 | ||||
|
397 | ----------------------------------------------------------------------------- | |||
|
398 | -- SAMPLE OUT | |||
|
399 | ----------------------------------------------------------------------------- | |||
|
400 | PROCESS (clk, rstn) | |||
|
401 | BEGIN -- PROCESS | |||
|
402 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
403 | sample_out_val <= '0'; | |||
|
404 | sample_out_val_s2 <= '0'; | |||
|
405 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
406 | sample_out_val <= sample_out_val_s2; | |||
|
407 | sample_out_val_s2 <= sample_out_val_s; | |||
|
408 | END IF; | |||
|
409 | END PROCESS; | |||
|
410 | ||||
|
411 | chanel_HIGH : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE | |||
|
412 | PROCESS (clk, rstn) | |||
|
413 | BEGIN -- PROCESS | |||
|
414 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
415 | sample_out_s2(ChanelsCount-1, I) <= '0'; | |||
|
416 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
417 | IF sample_out_rot_s = '1' THEN | |||
|
418 | sample_out_s2(ChanelsCount-1, I) <= sample_out_s(I); | |||
|
419 | END IF; | |||
|
420 | END IF; | |||
|
421 | END PROCESS; | |||
|
422 | END GENERATE chanel_HIGH; | |||
|
423 | ||||
|
424 | chanel_more : IF ChanelsCount > 1 GENERATE | |||
|
425 | all_chanel : FOR J IN ChanelsCount-1 DOWNTO 1 GENERATE | |||
|
426 | all_bit : FOR I IN Sample_SZ-1 DOWNTO 0 GENERATE | |||
|
427 | PROCESS (clk, rstn) | |||
|
428 | BEGIN -- PROCESS | |||
|
429 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
430 | sample_out_s2(J-1, I) <= '0'; | |||
|
431 | ELSIF clk'EVENT AND clk = '1' THEN -- rising clock edge | |||
|
432 | IF sample_out_rot_s = '1' THEN | |||
|
433 | sample_out_s2(J-1, I) <= sample_out_s2(J, I); | |||
|
434 | END IF; | |||
|
435 | END IF; | |||
|
436 | END PROCESS; | |||
|
437 | END GENERATE all_bit; | |||
|
438 | END GENERATE all_chanel; | |||
|
439 | END GENERATE chanel_more; | |||
|
440 | ||||
|
441 | sample_out <= sample_out_s2; | |||
|
442 | END ar_IIR_CEL_CTRLR_v3; |
@@ -0,0 +1,213 | |||||
|
1 | ------------------------------------------------------------------------------ | |||
|
2 | -- This file is a part of the LPP VHDL IP LIBRARY | |||
|
3 | -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS | |||
|
4 | -- | |||
|
5 | -- This program is free software; you can redistribute it and/or modify | |||
|
6 | -- it under the terms of the GNU General Public License as published by | |||
|
7 | -- the Free Software Foundation; either version 3 of the License, or | |||
|
8 | -- (at your option) any later version. | |||
|
9 | -- | |||
|
10 | -- This program is distributed in the hope that it will be useful, | |||
|
11 | -- but WITHOUT ANY WARRANTY; without even the implied warranty of | |||
|
12 | -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |||
|
13 | -- GNU General Public License for more details. | |||
|
14 | -- | |||
|
15 | -- You should have received a copy of the GNU General Public License | |||
|
16 | -- along with this program; if not, write to the Free Software | |||
|
17 | -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |||
|
18 | ------------------------------------------------------------------------------- | |||
|
19 | -- Author : Jean-christophe PELLION | |||
|
20 | -- Mail : jean-christophe.pellion@lpp.polytechnique.fr | |||
|
21 | ------------------------------------------------------------------------------- | |||
|
22 | LIBRARY IEEE; | |||
|
23 | USE IEEE.numeric_std.ALL; | |||
|
24 | USE IEEE.std_logic_1164.ALL; | |||
|
25 | LIBRARY lpp; | |||
|
26 | USE lpp.iir_filter.ALL; | |||
|
27 | USE lpp.general_purpose.ALL; | |||
|
28 | ||||
|
29 | ||||
|
30 | ||||
|
31 | ENTITY IIR_CEL_CTRLR_v3_DATAFLOW IS | |||
|
32 | GENERIC( | |||
|
33 | Sample_SZ : INTEGER := 16; | |||
|
34 | Coef_SZ : INTEGER := 9; | |||
|
35 | Coef_Nb : INTEGER := 30; | |||
|
36 | Coef_sel_SZ : INTEGER := 5 | |||
|
37 | ); | |||
|
38 | PORT( | |||
|
39 | rstn : IN STD_LOGIC; | |||
|
40 | clk : IN STD_LOGIC; | |||
|
41 | -- PARAMETER | |||
|
42 | virg_pos : IN INTEGER; | |||
|
43 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |||
|
44 | -- CONTROL | |||
|
45 | in_sel_src : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
46 | -- | |||
|
47 | ram_sel_Wdata : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
48 | -- | |||
|
49 | ram_input : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
|
50 | ram_output : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
|
51 | ||||
|
52 | -- | |||
|
53 | alu_sel_input : IN STD_LOGIC; | |||
|
54 | alu_sel_coeff : IN STD_LOGIC_VECTOR(Coef_sel_SZ-1 DOWNTO 0); | |||
|
55 | alu_ctrl : IN STD_LOGIC_VECTOR(2 DOWNTO 0);--(MAC_op, MULT_with_clear_ADD, IDLE) | |||
|
56 | alu_comp : IN STD_LOGIC_VECTOR(1 DOWNTO 0); | |||
|
57 | -- DATA | |||
|
58 | sample_in : IN STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
|
59 | sample_out : OUT STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0) | |||
|
60 | ); | |||
|
61 | END IIR_CEL_CTRLR_v3_DATAFLOW; | |||
|
62 | ||||
|
63 | ARCHITECTURE ar_IIR_CEL_CTRLR_v3_DATAFLOW OF IIR_CEL_CTRLR_v3_DATAFLOW IS | |||
|
64 | ||||
|
65 | SIGNAL reg_sample_in : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
|
66 | SIGNAL alu_output : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
|
67 | SIGNAL alu_sample : STD_LOGIC_VECTOR(Sample_SZ-1 DOWNTO 0); | |||
|
68 | SIGNAL alu_output_s : STD_LOGIC_VECTOR(Sample_SZ+Coef_SZ-1 DOWNTO 0); | |||
|
69 | ||||
|
70 | SIGNAL arrayCoeff : MUX_INPUT_TYPE(0 TO (2**Coef_sel_SZ)-1,Coef_SZ-1 DOWNTO 0); | |||
|
71 | SIGNAL alu_coef_s : MUX_OUTPUT_TYPE(Coef_SZ-1 DOWNTO 0); | |||
|
72 | ||||
|
73 | SIGNAL alu_coef : STD_LOGIC_VECTOR(Coef_SZ-1 DOWNTO 0); | |||
|
74 | ||||
|
75 | BEGIN | |||
|
76 | ||||
|
77 | ----------------------------------------------------------------------------- | |||
|
78 | -- INPUT | |||
|
79 | ----------------------------------------------------------------------------- | |||
|
80 | PROCESS (clk, rstn) | |||
|
81 | BEGIN -- PROCESS | |||
|
82 | IF rstn = '0' THEN -- asynchronous reset (active low) | |||
|
83 | reg_sample_in <= (OTHERS => '0'); | |||
|
84 | ELSIF clk'event AND clk = '1' THEN -- rising clock edge | |||
|
85 | CASE in_sel_src IS | |||
|
86 | WHEN "00" => reg_sample_in <= reg_sample_in; | |||
|
87 | WHEN "01" => reg_sample_in <= sample_in; | |||
|
88 | WHEN "10" => reg_sample_in <= ram_output; | |||
|
89 | WHEN "11" => reg_sample_in <= alu_output; | |||
|
90 | WHEN OTHERS => NULL; | |||
|
91 | END CASE; | |||
|
92 | END IF; | |||
|
93 | END PROCESS; | |||
|
94 | ||||
|
95 | ||||
|
96 | ----------------------------------------------------------------------------- | |||
|
97 | -- RAM + CTRL | |||
|
98 | ----------------------------------------------------------------------------- | |||
|
99 | ||||
|
100 | ram_input <= reg_sample_in WHEN ram_sel_Wdata = "00" ELSE | |||
|
101 | alu_output WHEN ram_sel_Wdata = "01" ELSE | |||
|
102 | ram_output; | |||
|
103 | ||||
|
104 | ----------------------------------------------------------------------------- | |||
|
105 | -- MAC_ACC | |||
|
106 | ----------------------------------------------------------------------------- | |||
|
107 | -- Control : mac_ctrl (MAC_op, MULT_with_clear_ADD, IDLE) | |||
|
108 | -- Data In : mac_sample, mac_coef | |||
|
109 | -- Data Out: mac_output | |||
|
110 | ||||
|
111 | alu_sample <= reg_sample_in WHEN alu_sel_input = '0' ELSE ram_output; | |||
|
112 | ||||
|
113 | coefftable: FOR I IN 0 TO (2**Coef_sel_SZ)-1 GENERATE | |||
|
114 | coeff_in: IF I < Coef_Nb GENERATE | |||
|
115 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |||
|
116 | arrayCoeff(I,J) <= coefs(Coef_SZ*I+J); | |||
|
117 | END GENERATE all_bit; | |||
|
118 | END GENERATE coeff_in; | |||
|
119 | coeff_null: IF I > (Coef_Nb -1) GENERATE | |||
|
120 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |||
|
121 | arrayCoeff(I,J) <= '0'; | |||
|
122 | END GENERATE all_bit; | |||
|
123 | END GENERATE coeff_null; | |||
|
124 | END GENERATE coefftable; | |||
|
125 | ||||
|
126 | Coeff_Mux : MUXN | |||
|
127 | GENERIC MAP ( | |||
|
128 | Input_SZ => Coef_SZ, | |||
|
129 | NbStage => Coef_sel_SZ) | |||
|
130 | PORT MAP ( | |||
|
131 | sel => alu_sel_coeff, | |||
|
132 | INPUT => arrayCoeff, | |||
|
133 | RES => alu_coef_s); | |||
|
134 | ||||
|
135 | ||||
|
136 | all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 GENERATE | |||
|
137 | alu_coef(J) <= alu_coef_s(J); | |||
|
138 | END GENERATE all_bit; | |||
|
139 | ||||
|
140 | ----------------------------------------------------------------------------- | |||
|
141 | -- TODO : just for Synthesis test | |||
|
142 | ||||
|
143 | --PROCESS (clk, rstn) | |||
|
144 | --BEGIN | |||
|
145 | -- IF rstn = '0' THEN | |||
|
146 | -- alu_coef <= (OTHERS => '0'); | |||
|
147 | -- ELSIF clk'event AND clk = '1' THEN | |||
|
148 | -- all_bit: FOR J IN Coef_SZ-1 DOWNTO 0 LOOP | |||
|
149 | -- alu_coef(J) <= alu_coef_s(J); | |||
|
150 | -- END LOOP all_bit; | |||
|
151 | -- END IF; | |||
|
152 | --END PROCESS; | |||
|
153 | ||||
|
154 | ----------------------------------------------------------------------------- | |||
|
155 | ||||
|
156 | ||||
|
157 | ALU_1: ALU | |||
|
158 | GENERIC MAP ( | |||
|
159 | Arith_en => 1, | |||
|
160 | Input_SZ_1 => Sample_SZ, | |||
|
161 | Input_SZ_2 => Coef_SZ, | |||
|
162 | COMP_EN => 1) | |||
|
163 | PORT MAP ( | |||
|
164 | clk => clk, | |||
|
165 | reset => rstn, | |||
|
166 | ctrl => alu_ctrl, | |||
|
167 | comp => alu_comp, | |||
|
168 | OP1 => alu_sample, | |||
|
169 | OP2 => alu_coef, | |||
|
170 | RES => alu_output_s); | |||
|
171 | ||||
|
172 | alu_output <= alu_output_s(Sample_SZ+virg_pos-1 DOWNTO virg_pos); | |||
|
173 | ||||
|
174 | sample_out <= alu_output; | |||
|
175 | ||||
|
176 | END ar_IIR_CEL_CTRLR_v3_DATAFLOW; | |||
|
177 | ||||
|
178 | ||||
|
179 | ||||
|
180 | ||||
|
181 | ||||
|
182 | ||||
|
183 | ||||
|
184 | ||||
|
185 | ||||
|
186 | ||||
|
187 | ||||
|
188 | ||||
|
189 | ||||
|
190 | ||||
|
191 | ||||
|
192 | ||||
|
193 | ||||
|
194 | ||||
|
195 | ||||
|
196 | ||||
|
197 | ||||
|
198 | ||||
|
199 | ||||
|
200 | ||||
|
201 | ||||
|
202 | ||||
|
203 | ||||
|
204 | ||||
|
205 | ||||
|
206 | ||||
|
207 | ||||
|
208 | ||||
|
209 | ||||
|
210 | ||||
|
211 | ||||
|
212 | ||||
|
213 |
@@ -379,7 +379,7 BEGIN -- beh | |||||
379 | pirq_ms => 6, |
|
379 | pirq_ms => 6, | |
380 | pirq_wfp => 14, |
|
380 | pirq_wfp => 14, | |
381 | hindex => 2, |
|
381 | hindex => 2, | |
382 |
top_lfr_version => X"01013 |
|
382 | top_lfr_version => X"010135") -- aa.bb.cc version | |
383 | -- AA : BOARD NUMBER |
|
383 | -- AA : BOARD NUMBER | |
384 | -- 0 => MINI_LFR |
|
384 | -- 0 => MINI_LFR | |
385 | -- 1 => EM |
|
385 | -- 1 => EM |
@@ -582,8 +582,8 BEGIN -- beh | |||||
582 | ADC_SDO_sig <= ADC_SDO; |
|
582 | ADC_SDO_sig <= ADC_SDO; | |
583 |
|
583 | |||
584 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE |
|
584 | sample_hk <= "0001000100010001" WHEN HK_SEL = "00" ELSE | |
585 |
"0010001000100010" WHEN HK_SEL = " |
|
585 | "0010001000100010" WHEN HK_SEL = "01" ELSE | |
586 |
"0100010001000100" WHEN HK_SEL = "1 |
|
586 | "0100010001000100" WHEN HK_SEL = "10" ELSE | |
587 | (OTHERS => '0'); |
|
587 | (OTHERS => '0'); | |
588 |
|
588 | |||
589 |
|
589 |
@@ -139,8 +139,35 PACKAGE iir_filter IS | |||||
139 | sample_out_val : OUT STD_LOGIC; |
|
139 | sample_out_val : OUT STD_LOGIC; | |
140 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); |
|
140 | sample_out : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |
141 | END COMPONENT; |
|
141 | END COMPONENT; | |
|
142 | ||||
|
143 | COMPONENT IIR_CEL_CTRLR_v3 | |||
|
144 | GENERIC ( | |||
|
145 | tech : INTEGER; | |||
|
146 | Mem_use : INTEGER; | |||
|
147 | Sample_SZ : INTEGER; | |||
|
148 | Coef_SZ : INTEGER; | |||
|
149 | Coef_Nb : INTEGER; | |||
|
150 | Coef_sel_SZ : INTEGER; | |||
|
151 | Cels_count : INTEGER; | |||
|
152 | ChanelsCount : INTEGER); | |||
|
153 | PORT ( | |||
|
154 | rstn : IN STD_LOGIC; | |||
|
155 | clk : IN STD_LOGIC; | |||
|
156 | virg_pos : IN INTEGER; | |||
|
157 | coefs : IN STD_LOGIC_VECTOR((Coef_SZ*Coef_Nb)-1 DOWNTO 0); | |||
|
158 | sample_in1_val : IN STD_LOGIC; | |||
|
159 | sample_in1 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
|
160 | sample_in2_val : IN STD_LOGIC; | |||
|
161 | sample_in2 : IN samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
|
162 | sample_out1_val : OUT STD_LOGIC; | |||
|
163 | sample_out1 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0); | |||
|
164 | sample_out2_val : OUT STD_LOGIC; | |||
|
165 | sample_out2 : OUT samplT(ChanelsCount-1 DOWNTO 0, Sample_SZ-1 DOWNTO 0)); | |||
|
166 | END COMPONENT; | |||
142 |
|
167 | |||
143 |
|
168 | |||
|
169 | ||||
|
170 | ||||
144 | --component FilterCTRLR is |
|
171 | --component FilterCTRLR is | |
145 | --port( |
|
172 | --port( | |
146 | -- reset : in std_logic; |
|
173 | -- reset : in std_logic; |
@@ -6,3 +6,5 RAM_CTRLR_v2.vhd | |||||
6 | IIR_CEL_CTRLR_v2_CONTROL.vhd |
|
6 | IIR_CEL_CTRLR_v2_CONTROL.vhd | |
7 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd |
|
7 | IIR_CEL_CTRLR_v2_DATAFLOW.vhd | |
8 | IIR_CEL_CTRLR_v2.vhd |
|
8 | IIR_CEL_CTRLR_v2.vhd | |
|
9 | IIR_CEL_CTRLR_v3_DATAFLOW.vhd | |||
|
10 | IIR_CEL_CTRLR_v3.vhd |
@@ -69,8 +69,8 ENTITY lpp_lfr_apbreg IS | |||||
69 | ready_matrix_f2 : IN STD_LOGIC; |
|
69 | ready_matrix_f2 : IN STD_LOGIC; | |
70 |
|
70 | |||
71 | -- error_bad_component_error : IN STD_LOGIC; |
|
71 | -- error_bad_component_error : IN STD_LOGIC; | |
72 |
error_buffer_full |
|
72 | error_buffer_full : IN STD_LOGIC; -- TODO | |
73 |
error_input_fifo_write |
|
73 | error_input_fifo_write : IN STD_LOGIC_VECTOR(2 DOWNTO 0); -- TODO | |
74 |
|
74 | |||
75 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
75 | -- debug_reg : IN STD_LOGIC_VECTOR(31 DOWNTO 0); | |
76 |
|
76 | |||
@@ -100,8 +100,8 ENTITY lpp_lfr_apbreg IS | |||||
100 | --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
100 | --status_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
101 | --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
101 | --status_full_ack : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
102 | --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
102 | --status_full_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
103 |
status_new_err |
|
103 | status_new_err : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
104 |
|
104 | |||
105 | -- OUT |
|
105 | -- OUT | |
106 | data_shaping_BW : OUT STD_LOGIC; |
|
106 | data_shaping_BW : OUT STD_LOGIC; | |
107 | data_shaping_SP0 : OUT STD_LOGIC; |
|
107 | data_shaping_SP0 : OUT STD_LOGIC; | |
@@ -130,22 +130,22 ENTITY lpp_lfr_apbreg IS | |||||
130 |
|
130 | |||
131 | run : OUT STD_LOGIC; |
|
131 | run : OUT STD_LOGIC; | |
132 |
|
132 | |||
133 |
start_date |
|
133 | start_date : OUT STD_LOGIC_VECTOR(30 DOWNTO 0); | |
134 |
|
134 | |||
135 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
135 | wfp_status_buffer_ready : OUT STD_LOGIC_VECTOR(3 DOWNTO 0); | |
136 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); |
|
136 | wfp_addr_buffer : OUT STD_LOGIC_VECTOR(32*4-1 DOWNTO 0); | |
137 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
137 | wfp_length_buffer : OUT STD_LOGIC_VECTOR(25 DOWNTO 0); | |
138 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
138 | wfp_ready_buffer : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); |
|
139 | wfp_buffer_time : IN STD_LOGIC_VECTOR(48*4-1 DOWNTO 0); | |
140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
140 | wfp_error_buffer_full : IN STD_LOGIC_VECTOR(3 DOWNTO 0); | |
141 | --------------------------------------------------------------------------- |
|
141 | --------------------------------------------------------------------------- | |
142 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
142 | sample_f3_v : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
143 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
143 | sample_f3_e1 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
144 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); |
|
144 | sample_f3_e2 : IN STD_LOGIC_VECTOR(15 DOWNTO 0); | |
145 |
sample_f3_valid : IN STD_LOGIC; |
|
145 | sample_f3_valid : IN STD_LOGIC; | |
146 | --------------------------------------------------------------------------- |
|
146 | --------------------------------------------------------------------------- | |
147 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) |
|
147 | debug_vector : OUT STD_LOGIC_VECTOR(11 DOWNTO 0) | |
148 |
|
148 | |||
149 | ); |
|
149 | ); | |
150 |
|
150 | |||
151 | END lpp_lfr_apbreg; |
|
151 | END lpp_lfr_apbreg; | |
@@ -197,35 +197,35 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
197 | TYPE lpp_WaveformPicker_regs IS RECORD |
|
197 | TYPE lpp_WaveformPicker_regs IS RECORD | |
198 | -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
198 | -- status_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
199 | -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
199 | -- status_full_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
200 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); |
|
200 | status_new_err : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
201 | data_shaping_BW : STD_LOGIC; |
|
201 | data_shaping_BW : STD_LOGIC; | |
202 | data_shaping_SP0 : STD_LOGIC; |
|
202 | data_shaping_SP0 : STD_LOGIC; | |
203 | data_shaping_SP1 : STD_LOGIC; |
|
203 | data_shaping_SP1 : STD_LOGIC; | |
204 | data_shaping_R0 : STD_LOGIC; |
|
204 | data_shaping_R0 : STD_LOGIC; | |
205 | data_shaping_R1 : STD_LOGIC; |
|
205 | data_shaping_R1 : STD_LOGIC; | |
206 | data_shaping_R2 : STD_LOGIC; |
|
206 | data_shaping_R2 : STD_LOGIC; | |
207 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
207 | delta_snapshot : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
208 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
208 | delta_f0 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
209 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); |
|
209 | delta_f0_2 : STD_LOGIC_VECTOR(delta_vector_size_f0_2-1 DOWNTO 0); | |
210 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
210 | delta_f1 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
211 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); |
|
211 | delta_f2 : STD_LOGIC_VECTOR(delta_vector_size-1 DOWNTO 0); | |
212 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); |
|
212 | nb_data_by_buffer : STD_LOGIC_VECTOR(nb_data_by_buffer_size-1 DOWNTO 0); | |
213 | -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); |
|
213 | -- nb_word_by_buffer : STD_LOGIC_VECTOR(nb_word_by_buffer_size-1 DOWNTO 0); | |
214 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); |
|
214 | nb_snapshot_param : STD_LOGIC_VECTOR(nb_snapshot_param_size-1 DOWNTO 0); | |
215 | enable_f0 : STD_LOGIC; |
|
215 | enable_f0 : STD_LOGIC; | |
216 | enable_f1 : STD_LOGIC; |
|
216 | enable_f1 : STD_LOGIC; | |
217 | enable_f2 : STD_LOGIC; |
|
217 | enable_f2 : STD_LOGIC; | |
218 | enable_f3 : STD_LOGIC; |
|
218 | enable_f3 : STD_LOGIC; | |
219 | burst_f0 : STD_LOGIC; |
|
219 | burst_f0 : STD_LOGIC; | |
220 | burst_f1 : STD_LOGIC; |
|
220 | burst_f1 : STD_LOGIC; | |
221 | burst_f2 : STD_LOGIC; |
|
221 | burst_f2 : STD_LOGIC; | |
222 | run : STD_LOGIC; |
|
222 | run : STD_LOGIC; | |
223 |
status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); |
|
223 | status_ready_buffer_f : STD_LOGIC_VECTOR(4*2-1 DOWNTO 0); | |
224 |
addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); |
|
224 | addr_buffer_f : STD_LOGIC_VECTOR(4*2*32-1 DOWNTO 0); | |
225 |
time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); |
|
225 | time_buffer_f : STD_LOGIC_VECTOR(4*2*48-1 DOWNTO 0); | |
226 | length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); |
|
226 | length_buffer : STD_LOGIC_VECTOR(25 DOWNTO 0); | |
227 |
error_buffer_full : |
|
227 | error_buffer_full : STD_LOGIC_VECTOR(3 DOWNTO 0); | |
228 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); |
|
228 | start_date : STD_LOGIC_VECTOR(30 DOWNTO 0); | |
229 | END RECORD; |
|
229 | END RECORD; | |
230 | SIGNAL reg_wp : lpp_WaveformPicker_regs; |
|
230 | SIGNAL reg_wp : lpp_WaveformPicker_regs; | |
231 |
|
231 | |||
@@ -267,16 +267,16 ARCHITECTURE beh OF lpp_lfr_apbreg IS | |||||
267 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; |
|
267 | SIGNAL reg1_ready_matrix_f2 : STD_LOGIC; | |
268 | -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); |
|
268 | -- SIGNAL reg1_addr_matrix_f2 : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
269 | -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); |
|
269 | -- SIGNAL reg1_matrix_time_f2 : STD_LOGIC_VECTOR(47 DOWNTO 0); | |
270 | SIGNAL apbo_irq_ms : STD_LOGIC; |
|
270 | SIGNAL apbo_irq_ms : STD_LOGIC; | |
271 | SIGNAL apbo_irq_wfp : STD_LOGIC; |
|
271 | SIGNAL apbo_irq_wfp : STD_LOGIC; | |
272 | ----------------------------------------------------------------------------- |
|
272 | ----------------------------------------------------------------------------- | |
273 |
SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR( |
|
273 | SIGNAL reg_ready_buffer_f : STD_LOGIC_VECTOR(2*4-1 DOWNTO 0); | |
274 |
|
274 | |||
275 |
SIGNAL pirq_temp |
|
275 | SIGNAL pirq_temp : STD_LOGIC_VECTOR(31 DOWNTO 0); | |
276 |
|
276 | |||
277 |
SIGNAL |
|
277 | SIGNAL sample_f3_v_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
278 |
SIGNAL |
|
278 | SIGNAL sample_f3_e1_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
279 |
SIGNAL |
|
279 | SIGNAL sample_f3_e2_reg : STD_LOGIC_VECTOR(15 DOWNTO 0); | |
280 |
|
280 | |||
281 | BEGIN -- beh |
|
281 | BEGIN -- beh | |
282 |
|
282 | |||
@@ -288,7 +288,7 BEGIN -- beh | |||||
288 | debug_vector(9) <= reg0_ready_matrix_f2; |
|
288 | debug_vector(9) <= reg0_ready_matrix_f2; | |
289 | debug_vector(10) <= reg1_ready_matrix_f2; |
|
289 | debug_vector(10) <= reg1_ready_matrix_f2; | |
290 | debug_vector(11) <= HRESETn; |
|
290 | debug_vector(11) <= HRESETn; | |
291 |
|
291 | |||
292 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; |
|
292 | -- status_ready_matrix_f0 <= reg_sp.status_ready_matrix_f0; | |
293 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; |
|
293 | -- status_ready_matrix_f1 <= reg_sp.status_ready_matrix_f1; | |
294 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; |
|
294 | -- status_ready_matrix_f2 <= reg_sp.status_ready_matrix_f2; | |
@@ -335,20 +335,20 BEGIN -- beh | |||||
335 |
|
335 | |||
336 | start_date <= reg_wp.start_date; |
|
336 | start_date <= reg_wp.start_date; | |
337 |
|
337 | |||
338 | length_matrix_f0 <= reg_sp.length_matrix; |
|
338 | length_matrix_f0 <= reg_sp.length_matrix; | |
339 | length_matrix_f1 <= reg_sp.length_matrix; |
|
339 | length_matrix_f1 <= reg_sp.length_matrix; | |
340 | length_matrix_f2 <= reg_sp.length_matrix; |
|
340 | length_matrix_f2 <= reg_sp.length_matrix; | |
341 | wfp_length_buffer <= reg_wp.length_buffer; |
|
341 | wfp_length_buffer <= reg_wp.length_buffer; | |
342 |
|
342 | |||
343 |
|
343 | |||
344 |
|
344 | |||
345 | PROCESS (HCLK, HRESETn) |
|
345 | PROCESS (HCLK, HRESETn) | |
346 | BEGIN -- PROCESS |
|
346 | BEGIN -- PROCESS | |
347 | IF HRESETn = '0' THEN -- asynchronous reset (active low) |
|
347 | IF HRESETn = '0' THEN -- asynchronous reset (active low) | |
348 | sample_f3_v_reg <= (OTHERS => '0'); |
|
348 | sample_f3_v_reg <= (OTHERS => '0'); | |
349 | sample_f3_e1_reg <= (OTHERS => '0'); |
|
349 | sample_f3_e1_reg <= (OTHERS => '0'); | |
350 | sample_f3_e2_reg <= (OTHERS => '0'); |
|
350 | sample_f3_e2_reg <= (OTHERS => '0'); | |
351 |
ELSIF HCLK' |
|
351 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
352 | IF sample_f3_valid = '1' THEN |
|
352 | IF sample_f3_valid = '1' THEN | |
353 | sample_f3_v_reg <= sample_f3_v; |
|
353 | sample_f3_v_reg <= sample_f3_v; | |
354 | sample_f3_e1_reg <= sample_f3_e1; |
|
354 | sample_f3_e1_reg <= sample_f3_e1; | |
@@ -356,7 +356,7 BEGIN -- beh | |||||
356 | END IF; |
|
356 | END IF; | |
357 | END IF; |
|
357 | END IF; | |
358 | END PROCESS; |
|
358 | END PROCESS; | |
359 |
|
359 | |||
360 |
|
360 | |||
361 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) |
|
361 | lpp_lfr_apbreg : PROCESS (HCLK, HRESETn) | |
362 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); |
|
362 | VARIABLE paddr : STD_LOGIC_VECTOR(7 DOWNTO 2); | |
@@ -383,7 +383,7 BEGIN -- beh | |||||
383 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); |
|
383 | reg_sp.addr_matrix_f2_1 <= (OTHERS => '0'); | |
384 |
|
384 | |||
385 | reg_sp.length_matrix <= (OTHERS => '0'); |
|
385 | reg_sp.length_matrix <= (OTHERS => '0'); | |
386 |
|
386 | |||
387 | -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok |
|
387 | -- reg_sp.time_matrix_f0_0 <= (OTHERS => '0'); -- ok | |
388 | -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok |
|
388 | -- reg_sp.time_matrix_f1_0 <= (OTHERS => '0'); -- ok | |
389 | -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok |
|
389 | -- reg_sp.time_matrix_f2_0 <= (OTHERS => '0'); -- ok | |
@@ -394,10 +394,10 BEGIN -- beh | |||||
394 |
|
394 | |||
395 | prdata <= (OTHERS => '0'); |
|
395 | prdata <= (OTHERS => '0'); | |
396 |
|
396 | |||
397 |
|
397 | |||
398 | apbo_irq_ms <= '0'; |
|
398 | apbo_irq_ms <= '0'; | |
399 | apbo_irq_wfp <= '0'; |
|
399 | apbo_irq_wfp <= '0'; | |
400 |
|
400 | |||
401 |
|
401 | |||
402 | -- status_full_ack <= (OTHERS => '0'); |
|
402 | -- status_full_ack <= (OTHERS => '0'); | |
403 |
|
403 | |||
@@ -427,14 +427,14 BEGIN -- beh | |||||
427 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); |
|
427 | reg_wp.nb_data_by_buffer <= (OTHERS => '0'); | |
428 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); |
|
428 | reg_wp.nb_snapshot_param <= (OTHERS => '0'); | |
429 | reg_wp.start_date <= (OTHERS => '1'); |
|
429 | reg_wp.start_date <= (OTHERS => '1'); | |
430 |
|
430 | |||
431 | reg_wp.status_ready_buffer_f <= (OTHERS => '0'); |
|
431 | reg_wp.status_ready_buffer_f <= (OTHERS => '0'); | |
432 | reg_wp.length_buffer <= (OTHERS => '0'); |
|
432 | reg_wp.length_buffer <= (OTHERS => '0'); | |
433 |
|
433 | |||
434 | pirq_temp <= (OTHERS => '0'); |
|
434 | pirq_temp <= (OTHERS => '0'); | |
435 |
|
435 | |||
436 | reg_wp.addr_buffer_f <= (OTHERS => '0'); |
|
436 | reg_wp.addr_buffer_f <= (OTHERS => '0'); | |
437 |
|
437 | |||
438 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge |
|
438 | ELSIF HCLK'EVENT AND HCLK = '1' THEN -- rising clock edge | |
439 |
|
439 | |||
440 | -- status_full_ack <= (OTHERS => '0'); |
|
440 | -- status_full_ack <= (OTHERS => '0'); | |
@@ -447,7 +447,7 BEGIN -- beh | |||||
447 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; |
|
447 | reg_sp.status_ready_matrix_f1_1 <= reg_sp.status_ready_matrix_f1_1 OR reg1_ready_matrix_f1; | |
448 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; |
|
448 | reg_sp.status_ready_matrix_f2_1 <= reg_sp.status_ready_matrix_f2_1 OR reg1_ready_matrix_f2; | |
449 |
|
449 | |||
450 | all_status_ready_buffer_bit: FOR I IN 4*2-1 DOWNTO 0 LOOP |
|
450 | all_status_ready_buffer_bit : FOR I IN 4*2-1 DOWNTO 0 LOOP | |
451 | reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); |
|
451 | reg_wp.status_ready_buffer_f(I) <= reg_wp.status_ready_buffer_f(I) OR reg_ready_buffer_f(I); | |
452 | END LOOP all_status_ready_buffer_bit; |
|
452 | END LOOP all_status_ready_buffer_bit; | |
453 |
|
453 | |||
@@ -460,8 +460,8 BEGIN -- beh | |||||
460 |
|
460 | |||
461 |
|
461 | |||
462 | all_status : FOR I IN 3 DOWNTO 0 LOOP |
|
462 | all_status : FOR I IN 3 DOWNTO 0 LOOP | |
463 |
reg_wp.error_buffer_full(I) <= |
|
463 | reg_wp.error_buffer_full(I) <= reg_wp.error_buffer_full(I) OR wfp_error_buffer_full(I); | |
464 |
reg_wp.status_new_err(I) <= |
|
464 | reg_wp.status_new_err(I) <= reg_wp.status_new_err(I) OR status_new_err(I); | |
465 | END LOOP all_status; |
|
465 | END LOOP all_status; | |
466 |
|
466 | |||
467 | paddr := "000000"; |
|
467 | paddr := "000000"; | |
@@ -477,7 +477,7 BEGIN -- beh | |||||
477 | prdata(2) <= reg_sp.config_ms_run; |
|
477 | prdata(2) <= reg_sp.config_ms_run; | |
478 |
|
478 | |||
479 | WHEN ADDR_LFR_SM_STATUS => |
|
479 | WHEN ADDR_LFR_SM_STATUS => | |
480 | prdata(0) <= reg_sp.status_ready_matrix_f0_0; |
|
480 | prdata(0) <= reg_sp.status_ready_matrix_f0_0; | |
481 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; |
|
481 | prdata(1) <= reg_sp.status_ready_matrix_f0_1; | |
482 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; |
|
482 | prdata(2) <= reg_sp.status_ready_matrix_f1_0; | |
483 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; |
|
483 | prdata(3) <= reg_sp.status_ready_matrix_f1_1; | |
@@ -508,8 +508,8 BEGIN -- beh | |||||
508 | WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); |
|
508 | WHEN ADDR_LFR_SM_F2_1_TIME_COARSE => prdata <= reg_sp.time_matrix_f2_1(47 DOWNTO 16); | |
509 | WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); |
|
509 | WHEN ADDR_LFR_SM_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_sp.time_matrix_f2_1(15 DOWNTO 0); | |
510 | WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; |
|
510 | WHEN ADDR_LFR_SM_LENGTH => prdata(25 DOWNTO 0) <= reg_sp.length_matrix; | |
511 | --------------------------------------------------------------------- |
|
511 | --------------------------------------------------------------------- | |
512 | WHEN ADDR_LFR_WP_DATASHAPING => |
|
512 | WHEN ADDR_LFR_WP_DATASHAPING => | |
513 | prdata(0) <= reg_wp.data_shaping_BW; |
|
513 | prdata(0) <= reg_wp.data_shaping_BW; | |
514 | prdata(1) <= reg_wp.data_shaping_SP0; |
|
514 | prdata(1) <= reg_wp.data_shaping_SP0; | |
515 | prdata(2) <= reg_wp.data_shaping_SP1; |
|
515 | prdata(2) <= reg_wp.data_shaping_SP1; | |
@@ -525,60 +525,60 BEGIN -- beh | |||||
525 | prdata(5) <= reg_wp.burst_f1; |
|
525 | prdata(5) <= reg_wp.burst_f1; | |
526 | prdata(6) <= reg_wp.burst_f2; |
|
526 | prdata(6) <= reg_wp.burst_f2; | |
527 | prdata(7) <= reg_wp.run; |
|
527 | prdata(7) <= reg_wp.run; | |
528 |
WHEN ADDR_LFR_WP_F0_0_ADDR => prdata |
|
528 | WHEN ADDR_LFR_WP_F0_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*1-1 DOWNTO 32*0); --0 | |
529 |
WHEN ADDR_LFR_WP_F0_1_ADDR => prdata |
|
529 | WHEN ADDR_LFR_WP_F0_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*2-1 DOWNTO 32*1); | |
530 |
WHEN ADDR_LFR_WP_F1_0_ADDR => prdata |
|
530 | WHEN ADDR_LFR_WP_F1_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*3-1 DOWNTO 32*2); --1 | |
531 |
WHEN ADDR_LFR_WP_F1_1_ADDR => prdata |
|
531 | WHEN ADDR_LFR_WP_F1_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*4-1 DOWNTO 32*3); | |
532 |
WHEN ADDR_LFR_WP_F2_0_ADDR => prdata |
|
532 | WHEN ADDR_LFR_WP_F2_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*5-1 DOWNTO 32*4); --2 | |
533 |
WHEN ADDR_LFR_WP_F2_1_ADDR => prdata |
|
533 | WHEN ADDR_LFR_WP_F2_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5); | |
534 |
WHEN ADDR_LFR_WP_F3_0_ADDR => prdata |
|
534 | WHEN ADDR_LFR_WP_F3_0_ADDR => prdata <= reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6); --3 | |
535 |
WHEN ADDR_LFR_WP_F3_1_ADDR => prdata |
|
535 | WHEN ADDR_LFR_WP_F3_1_ADDR => prdata <= reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7); | |
536 |
|
536 | |||
537 | WHEN ADDR_LFR_WP_STATUS => |
|
537 | WHEN ADDR_LFR_WP_STATUS => | |
538 |
prdata(7 |
|
538 | prdata(7 DOWNTO 0) <= reg_wp.status_ready_buffer_f; | |
539 |
prdata(11 DOWNTO |
|
539 | prdata(11 DOWNTO 8) <= reg_wp.error_buffer_full; | |
540 | prdata(15 DOWNTO 12) <= reg_wp.status_new_err; |
|
540 | prdata(15 DOWNTO 12) <= reg_wp.status_new_err; | |
541 |
|
541 | |||
542 | WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; |
|
542 | WHEN ADDR_LFR_WP_DELTASNAPSHOT => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_snapshot; | |
543 | WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; |
|
543 | WHEN ADDR_LFR_WP_DELTA_F0 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f0; | |
544 | WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; |
|
544 | WHEN ADDR_LFR_WP_DELTA_F0_2 => prdata(delta_vector_size_f0_2-1 DOWNTO 0) <= reg_wp.delta_f0_2; | |
545 | WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; |
|
545 | WHEN ADDR_LFR_WP_DELTA_F1 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f1; | |
546 | WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; |
|
546 | WHEN ADDR_LFR_WP_DELTA_F2 => prdata(delta_vector_size-1 DOWNTO 0) <= reg_wp.delta_f2; | |
547 | WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; |
|
547 | WHEN ADDR_LFR_WP_DATA_IN_BUFFER => prdata(nb_data_by_buffer_size-1 DOWNTO 0) <= reg_wp.nb_data_by_buffer; | |
548 | WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; |
|
548 | WHEN ADDR_LFR_WP_NBSNAPSHOT => prdata(nb_snapshot_param_size-1 DOWNTO 0) <= reg_wp.nb_snapshot_param; | |
549 | WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date; |
|
549 | WHEN ADDR_LFR_WP_START_DATE => prdata(30 DOWNTO 0) <= reg_wp.start_date; | |
550 |
|
550 | |||
551 |
WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); |
|
551 | WHEN ADDR_LFR_WP_F0_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 31 DOWNTO 48*0); | |
552 | WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); |
|
552 | WHEN ADDR_LFR_WP_F0_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*0 + 47 DOWNTO 48*0 + 32); | |
553 | WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1); |
|
553 | WHEN ADDR_LFR_WP_F0_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 31 DOWNTO 48*1); | |
554 | WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32); |
|
554 | WHEN ADDR_LFR_WP_F0_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*1 + 47 DOWNTO 48*1 + 32); | |
555 |
|
555 | |||
556 | WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2); |
|
556 | WHEN ADDR_LFR_WP_F1_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 31 DOWNTO 48*2); | |
557 | WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32); |
|
557 | WHEN ADDR_LFR_WP_F1_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*2 + 47 DOWNTO 48*2 + 32); | |
558 | WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3); |
|
558 | WHEN ADDR_LFR_WP_F1_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 31 DOWNTO 48*3); | |
559 | WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32); |
|
559 | WHEN ADDR_LFR_WP_F1_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*3 + 47 DOWNTO 48*3 + 32); | |
560 |
|
560 | |||
561 | WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4); |
|
561 | WHEN ADDR_LFR_WP_F2_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 31 DOWNTO 48*4); | |
562 | WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32); |
|
562 | WHEN ADDR_LFR_WP_F2_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*4 + 47 DOWNTO 48*4 + 32); | |
563 | WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5); |
|
563 | WHEN ADDR_LFR_WP_F2_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 31 DOWNTO 48*5); | |
564 | WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32); |
|
564 | WHEN ADDR_LFR_WP_F2_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*5 + 47 DOWNTO 48*5 + 32); | |
565 |
|
565 | |||
566 | WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6); |
|
566 | WHEN ADDR_LFR_WP_F3_0_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 31 DOWNTO 48*6); | |
567 | WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32); |
|
567 | WHEN ADDR_LFR_WP_F3_0_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*6 + 47 DOWNTO 48*6 + 32); | |
568 | WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); |
|
568 | WHEN ADDR_LFR_WP_F3_1_TIME_COARSE => prdata(31 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 31 DOWNTO 48*7); | |
569 | WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); |
|
569 | WHEN ADDR_LFR_WP_F3_1_TIME_FINE => prdata(15 DOWNTO 0) <= reg_wp.time_buffer_f(48*7 + 47 DOWNTO 48*7 + 32); | |
570 |
|
570 | |||
571 | WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; |
|
571 | WHEN ADDR_LFR_WP_LENGTH => prdata(25 DOWNTO 0) <= reg_wp.length_buffer; | |
572 |
|
572 | |||
573 |
WHEN ADDR_LFR_WP_F3_V |
|
573 | WHEN ADDR_LFR_WP_F3_V => prdata(15 DOWNTO 0) <= sample_f3_v_reg; | |
574 |
prdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
574 | prdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
575 |
WHEN ADDR_LFR_WP_F3_E1 |
|
575 | WHEN ADDR_LFR_WP_F3_E1 => prdata(15 DOWNTO 0) <= sample_f3_e1_reg; | |
576 |
prdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
576 | prdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
577 |
WHEN ADDR_LFR_WP_F3_E2 |
|
577 | WHEN ADDR_LFR_WP_F3_E2 => prdata(15 DOWNTO 0) <= sample_f3_e2_reg; | |
578 |
prdata(31 DOWNTO 16) <= (OTHERS => '0'); |
|
578 | prdata(31 DOWNTO 16) <= (OTHERS => '0'); | |
579 | --------------------------------------------------------------------- |
|
579 | --------------------------------------------------------------------- | |
580 |
WHEN ADDR_LFR_VERSION |
|
580 | WHEN ADDR_LFR_VERSION => prdata(23 DOWNTO 0) <= top_lfr_version(23 DOWNTO 0); | |
581 | WHEN OTHERS => NULL; |
|
581 | WHEN OTHERS => NULL; | |
582 |
|
582 | |||
583 | END CASE; |
|
583 | END CASE; | |
584 | IF (apbi.pwrite AND apbi.penable) = '1' THEN |
|
584 | IF (apbi.pwrite AND apbi.penable) = '1' THEN | |
@@ -589,17 +589,17 BEGIN -- beh | |||||
589 | reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); |
|
589 | reg_sp.config_active_interruption_onNewMatrix <= apbi.pwdata(0); | |
590 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); |
|
590 | reg_sp.config_active_interruption_onError <= apbi.pwdata(1); | |
591 | reg_sp.config_ms_run <= apbi.pwdata(2); |
|
591 | reg_sp.config_ms_run <= apbi.pwdata(2); | |
592 |
|
|
592 | ||
593 | WHEN ADDR_LFR_SM_STATUS => |
|
593 | WHEN ADDR_LFR_SM_STATUS => | |
594 |
reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0) |
|
594 | reg_sp.status_ready_matrix_f0_0 <= ((NOT apbi.pwdata(0)) AND reg_sp.status_ready_matrix_f0_0) OR reg0_ready_matrix_f0; | |
595 |
reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1) |
|
595 | reg_sp.status_ready_matrix_f0_1 <= ((NOT apbi.pwdata(1)) AND reg_sp.status_ready_matrix_f0_1) OR reg1_ready_matrix_f0; | |
596 |
reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2) |
|
596 | reg_sp.status_ready_matrix_f1_0 <= ((NOT apbi.pwdata(2)) AND reg_sp.status_ready_matrix_f1_0) OR reg0_ready_matrix_f1; | |
597 |
reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3) |
|
597 | reg_sp.status_ready_matrix_f1_1 <= ((NOT apbi.pwdata(3)) AND reg_sp.status_ready_matrix_f1_1) OR reg1_ready_matrix_f1; | |
598 |
reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4) |
|
598 | reg_sp.status_ready_matrix_f2_0 <= ((NOT apbi.pwdata(4)) AND reg_sp.status_ready_matrix_f2_0) OR reg0_ready_matrix_f2; | |
599 |
reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5) |
|
599 | reg_sp.status_ready_matrix_f2_1 <= ((NOT apbi.pwdata(5)) AND reg_sp.status_ready_matrix_f2_1) OR reg1_ready_matrix_f2; | |
600 |
reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7) |
|
600 | reg_sp.status_error_buffer_full <= ((NOT apbi.pwdata(7)) AND reg_sp.status_error_buffer_full) OR error_buffer_full; | |
601 |
reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8) |
|
601 | reg_sp.status_error_input_fifo_write(0) <= ((NOT apbi.pwdata(8)) AND reg_sp.status_error_input_fifo_write(0)) OR error_input_fifo_write(0); | |
602 |
reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9) |
|
602 | reg_sp.status_error_input_fifo_write(1) <= ((NOT apbi.pwdata(9)) AND reg_sp.status_error_input_fifo_write(1)) OR error_input_fifo_write(1); | |
603 | reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2); |
|
603 | reg_sp.status_error_input_fifo_write(2) <= ((NOT apbi.pwdata(10)) AND reg_sp.status_error_input_fifo_write(2)) OR error_input_fifo_write(2); | |
604 | WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; |
|
604 | WHEN ADDR_LFR_SM_F0_0_ADDR => reg_sp.addr_matrix_f0_0 <= apbi.pwdata; | |
605 | WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; |
|
605 | WHEN ADDR_LFR_SM_F0_1_ADDR => reg_sp.addr_matrix_f0_1 <= apbi.pwdata; | |
@@ -608,8 +608,8 BEGIN -- beh | |||||
608 | WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; |
|
608 | WHEN ADDR_LFR_SM_F2_0_ADDR => reg_sp.addr_matrix_f2_0 <= apbi.pwdata; | |
609 | WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; |
|
609 | WHEN ADDR_LFR_SM_F2_1_ADDR => reg_sp.addr_matrix_f2_1 <= apbi.pwdata; | |
610 |
|
610 | |||
611 |
WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= |
|
611 | WHEN ADDR_LFR_SM_LENGTH => reg_sp.length_matrix <= apbi.pwdata(25 DOWNTO 0); | |
612 | --------------------------------------------------------------------- |
|
612 | --------------------------------------------------------------------- | |
613 | WHEN ADDR_LFR_WP_DATASHAPING => |
|
613 | WHEN ADDR_LFR_WP_DATASHAPING => | |
614 | reg_wp.data_shaping_BW <= apbi.pwdata(0); |
|
614 | reg_wp.data_shaping_BW <= apbi.pwdata(0); | |
615 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); |
|
615 | reg_wp.data_shaping_SP0 <= apbi.pwdata(1); | |
@@ -617,7 +617,7 BEGIN -- beh | |||||
617 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); |
|
617 | reg_wp.data_shaping_R0 <= apbi.pwdata(3); | |
618 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); |
|
618 | reg_wp.data_shaping_R1 <= apbi.pwdata(4); | |
619 | reg_wp.data_shaping_R2 <= apbi.pwdata(5); |
|
619 | reg_wp.data_shaping_R2 <= apbi.pwdata(5); | |
620 |
WHEN |
|
620 | WHEN ADDR_LFR_WP_CONTROL => | |
621 | reg_wp.enable_f0 <= apbi.pwdata(0); |
|
621 | reg_wp.enable_f0 <= apbi.pwdata(0); | |
622 | reg_wp.enable_f1 <= apbi.pwdata(1); |
|
622 | reg_wp.enable_f1 <= apbi.pwdata(1); | |
623 | reg_wp.enable_f2 <= apbi.pwdata(2); |
|
623 | reg_wp.enable_f2 <= apbi.pwdata(2); | |
@@ -634,12 +634,12 BEGIN -- beh | |||||
634 | WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; |
|
634 | WHEN ADDR_LFR_WP_F2_1_ADDR => reg_wp.addr_buffer_f(32*6-1 DOWNTO 32*5) <= apbi.pwdata; | |
635 | WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; |
|
635 | WHEN ADDR_LFR_WP_F3_0_ADDR => reg_wp.addr_buffer_f(32*7-1 DOWNTO 32*6) <= apbi.pwdata; | |
636 | WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; |
|
636 | WHEN ADDR_LFR_WP_F3_1_ADDR => reg_wp.addr_buffer_f(32*8-1 DOWNTO 32*7) <= apbi.pwdata; | |
637 | WHEN ADDR_LFR_WP_STATUS => |
|
637 | WHEN ADDR_LFR_WP_STATUS => | |
638 | all_reg_wp_status_bit: FOR I IN 3 DOWNTO 0 LOOP |
|
638 | all_reg_wp_status_bit : FOR I IN 3 DOWNTO 0 LOOP | |
639 |
reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2) |
|
639 | reg_wp.status_ready_buffer_f(I*2) <= ((NOT apbi.pwdata(I*2)) AND reg_wp.status_ready_buffer_f(I*2)) OR reg_ready_buffer_f(I*2); | |
640 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); |
|
640 | reg_wp.status_ready_buffer_f(I*2+1) <= ((NOT apbi.pwdata(I*2+1)) AND reg_wp.status_ready_buffer_f(I*2+1)) OR reg_ready_buffer_f(I*2+1); | |
641 |
reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8) |
|
641 | reg_wp.error_buffer_full(I) <= ((NOT apbi.pwdata(I+8)) AND reg_wp.error_buffer_full(I)) OR wfp_error_buffer_full(I); | |
642 |
reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12) |
|
642 | reg_wp.status_new_err(I) <= ((NOT apbi.pwdata(I+12)) AND reg_wp.status_new_err(I)) OR status_new_err(I); | |
643 | END LOOP all_reg_wp_status_bit; |
|
643 | END LOOP all_reg_wp_status_bit; | |
644 |
|
644 | |||
645 | WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); |
|
645 | WHEN ADDR_LFR_WP_DELTASNAPSHOT => reg_wp.delta_snapshot <= apbi.pwdata(delta_vector_size-1 DOWNTO 0); | |
@@ -650,37 +650,37 BEGIN -- beh | |||||
650 | WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); |
|
650 | WHEN ADDR_LFR_WP_DATA_IN_BUFFER => reg_wp.nb_data_by_buffer <= apbi.pwdata(nb_data_by_buffer_size-1 DOWNTO 0); | |
651 | WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); |
|
651 | WHEN ADDR_LFR_WP_NBSNAPSHOT => reg_wp.nb_snapshot_param <= apbi.pwdata(nb_snapshot_param_size-1 DOWNTO 0); | |
652 | WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); |
|
652 | WHEN ADDR_LFR_WP_START_DATE => reg_wp.start_date <= apbi.pwdata(30 DOWNTO 0); | |
653 |
|
||||
654 | WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); |
|
|||
655 |
|
653 | |||
656 | WHEN OTHERS => NULL; |
|
654 | WHEN ADDR_LFR_WP_LENGTH => reg_wp.length_buffer <= apbi.pwdata(25 DOWNTO 0); | |
|
655 | ||||
|
656 | WHEN OTHERS => NULL; | |||
657 | END CASE; |
|
657 | END CASE; | |
658 | END IF; |
|
658 | END IF; | |
659 | END IF; |
|
659 | END IF; | |
660 | --apbo.pirq(pirq_ms) <= |
|
660 | --apbo.pirq(pirq_ms) <= | |
661 |
pirq_temp( |
|
661 | pirq_temp(pirq_ms) <= apbo_irq_ms; | |
662 | pirq_temp(pirq_wfp) <= apbo_irq_wfp; |
|
662 | pirq_temp(pirq_wfp) <= apbo_irq_wfp; | |
663 | apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR |
|
663 | apbo_irq_ms <= ((reg_sp.config_active_interruption_onNewMatrix AND (ready_matrix_f0 OR | |
664 |
|
|
664 | ready_matrix_f1 OR | |
665 |
|
|
665 | ready_matrix_f2) | |
666 |
|
|
666 | ) | |
667 |
|
|
667 | OR | |
668 |
|
|
668 | (reg_sp.config_active_interruption_onError AND ( | |
669 | -- error_bad_component_error OR |
|
669 | -- error_bad_component_error OR | |
670 |
|
|
670 | error_buffer_full | |
671 |
|
|
671 | OR error_input_fifo_write(0) | |
672 |
|
|
672 | OR error_input_fifo_write(1) | |
673 |
|
|
673 | OR error_input_fifo_write(2)) | |
674 |
|
|
674 | )); | |
675 | -- apbo.pirq(pirq_wfp) |
|
675 | -- apbo.pirq(pirq_wfp) | |
676 | apbo_irq_wfp<= ored_irq_wfp; |
|
676 | apbo_irq_wfp <= ored_irq_wfp; | |
677 |
|
677 | |||
678 | END IF; |
|
678 | END IF; | |
679 | END PROCESS lpp_lfr_apbreg; |
|
679 | END PROCESS lpp_lfr_apbreg; | |
680 |
|
680 | |||
681 | apbo.pirq <= pirq_temp; |
|
681 | apbo.pirq <= pirq_temp; | |
682 |
|
682 | |||
683 |
|
683 | |||
684 | --all_irq: FOR I IN 31 DOWNTO 0 GENERATE |
|
684 | --all_irq: FOR I IN 31 DOWNTO 0 GENERATE | |
685 | -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE |
|
685 | -- IRQ_is_PIRQ_MS: IF I = pirq_ms GENERATE | |
686 | -- apbo.pirq(I) <= apbo_irq_ms; |
|
686 | -- apbo.pirq(I) <= apbo_irq_ms; | |
@@ -691,11 +691,11 BEGIN -- beh | |||||
691 | -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE |
|
691 | -- IRQ_OTHERS: IF I /= pirq_ms AND pirq_wfp /= pirq_wfp GENERATE | |
692 | -- apbo.pirq(I) <= '0'; |
|
692 | -- apbo.pirq(I) <= '0'; | |
693 | -- END GENERATE IRQ_OTHERS; |
|
693 | -- END GENERATE IRQ_OTHERS; | |
694 |
|
694 | |||
695 | --END GENERATE all_irq; |
|
695 | --END GENERATE all_irq; | |
696 |
|
696 | |||
697 |
|
697 | |||
698 |
|
698 | |||
699 | apbo.pindex <= pindex; |
|
699 | apbo.pindex <= pindex; | |
700 | apbo.pconfig <= pconfig; |
|
700 | apbo.pconfig <= pconfig; | |
701 | apbo.prdata <= prdata; |
|
701 | apbo.prdata <= prdata; | |
@@ -731,8 +731,8 BEGIN -- beh | |||||
731 | clk => HCLK, |
|
731 | clk => HCLK, | |
732 | rstn => HRESETn, |
|
732 | rstn => HRESETn, | |
733 |
|
733 | |||
734 |
run |
|
734 | run => '1', --reg_sp.config_ms_run, | |
735 |
|
735 | |||
736 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, |
|
736 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f0_0, | |
737 | reg0_ready_matrix => reg0_ready_matrix_f0, |
|
737 | reg0_ready_matrix => reg0_ready_matrix_f0, | |
738 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, |
|
738 | reg0_addr_matrix => reg_sp.addr_matrix_f0_0, --reg0_addr_matrix_f0, | |
@@ -753,7 +753,7 BEGIN -- beh | |||||
753 | clk => HCLK, |
|
753 | clk => HCLK, | |
754 | rstn => HRESETn, |
|
754 | rstn => HRESETn, | |
755 |
|
755 | |||
756 |
run |
|
756 | run => '1', --reg_sp.config_ms_run, | |
757 |
|
757 | |||
758 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, |
|
758 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f1_0, | |
759 | reg0_ready_matrix => reg0_ready_matrix_f1, |
|
759 | reg0_ready_matrix => reg0_ready_matrix_f1, | |
@@ -775,7 +775,7 BEGIN -- beh | |||||
775 | clk => HCLK, |
|
775 | clk => HCLK, | |
776 | rstn => HRESETn, |
|
776 | rstn => HRESETn, | |
777 |
|
777 | |||
778 |
run |
|
778 | run => '1', --reg_sp.config_ms_run, | |
779 |
|
779 | |||
780 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, |
|
780 | reg0_status_ready_matrix => reg_sp.status_ready_matrix_f2_0, | |
781 | reg0_ready_matrix => reg0_ready_matrix_f2, |
|
781 | reg0_ready_matrix => reg0_ready_matrix_f2, | |
@@ -793,33 +793,33 BEGIN -- beh | |||||
793 | matrix_time => matrix_time_f2); |
|
793 | matrix_time => matrix_time_f2); | |
794 |
|
794 | |||
795 | ----------------------------------------------------------------------------- |
|
795 | ----------------------------------------------------------------------------- | |
796 | all_wfp_pointer: FOR I IN 3 DOWNTO 0 GENERATE |
|
796 | all_wfp_pointer : FOR I IN 3 DOWNTO 0 GENERATE | |
797 | lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer |
|
797 | lpp_apbreg_wfp_pointer_fi : lpp_apbreg_ms_pointer | |
798 | PORT MAP ( |
|
798 | PORT MAP ( | |
799 | clk => HCLK, |
|
799 | clk => HCLK, | |
800 | rstn => HRESETn, |
|
800 | rstn => HRESETn, | |
801 |
|
801 | |||
802 |
run |
|
802 | run => '1', --reg_wp.run, | |
803 |
|
803 | |||
804 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), |
|
804 | reg0_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I), | |
805 | reg0_ready_matrix => reg_ready_buffer_f(2*I), |
|
805 | reg0_ready_matrix => reg_ready_buffer_f(2*I), | |
806 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), |
|
806 | reg0_addr_matrix => reg_wp.addr_buffer_f((2*I+1)*32-1 DOWNTO (2*I)*32), | |
807 |
reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), |
|
807 | reg0_matrix_time => reg_wp.time_buffer_f((2*I+1)*48-1 DOWNTO (2*I)*48), | |
808 |
|
808 | |||
809 | reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), |
|
809 | reg1_status_ready_matrix => reg_wp.status_ready_buffer_f(2*I+1), | |
810 | reg1_ready_matrix => reg_ready_buffer_f(2*I+1), |
|
810 | reg1_ready_matrix => reg_ready_buffer_f(2*I+1), | |
811 | reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), |
|
811 | reg1_addr_matrix => reg_wp.addr_buffer_f((2*I+2)*32-1 DOWNTO (2*I+1)*32), | |
812 |
reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), |
|
812 | reg1_matrix_time => reg_wp.time_buffer_f((2*I+2)*48-1 DOWNTO (2*I+1)*48), | |
813 |
|
813 | |||
814 | ready_matrix => wfp_ready_buffer(I), |
|
814 | ready_matrix => wfp_ready_buffer(I), | |
815 | status_ready_matrix => wfp_status_buffer_ready(I), |
|
815 | status_ready_matrix => wfp_status_buffer_ready(I), | |
816 | addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), |
|
816 | addr_matrix => wfp_addr_buffer((I+1)*32-1 DOWNTO I*32), | |
817 | matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) |
|
817 | matrix_time => wfp_buffer_time((I+1)*48-1 DOWNTO I*48) | |
818 | ); |
|
818 | ); | |
819 |
|
819 | |||
820 |
END GENERATE all_wfp_pointer; |
|
820 | END GENERATE all_wfp_pointer; | |
821 | ----------------------------------------------------------------------------- |
|
821 | ----------------------------------------------------------------------------- | |
822 |
|
822 | |||
823 | END beh; |
|
823 | END beh; | |
824 |
|
824 | |||
825 | ------------------------------------------------------------------------------ |
|
825 | ------------------------------------------------------------------------------ |
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