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1 -- Systeme_Clock.vhd
2 library IEEE;
3 use IEEE.std_logic_1164.all;
4 use IEEE.numeric_std.all;
5
6 --! Programme qui va permetre de g�n�rer l'horloge systeme (sclk)
7
8 entity Systeme_Clock is
9 generic(N :integer := 695); --! G�n�rique contenant le r�sultat de la division clk/sclk
10 port(
11 clk, raz : in std_logic; --! Horloge et Reset globale
12 sclk : out std_logic --! Horloge Systeme g�n�r�e
13 );
14 end Systeme_Clock;
15
16 --! @details Fonctionne a base d'un compteur (countint) qui va permetre de diviser l'horloge N fois
17 architecture ar_Systeme_Clock of Systeme_Clock is
18
19 signal clockint : std_logic;
20 signal countint : integer range 0 to N/2-1;
21
22 begin
23 process (clk,raz)
24 begin
25 if(raz = '0') then
26 countint <= 0;
27 clockint <= '0';
28 elsif (clk' event and clk='1') then
29 if (countint = N/2-1) then
30 countint <= 0;
31 clockint <= not clockint;
32 else
33 countint <= countint+1;
34 end if;
35 end if;
36 end process;
37
38 sclk <= clockint;
39
40 end ar_Systeme_Clock; No newline at end of file
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@@ -1,8 +1,7
1 1 ./amba_lcd_16x2_ctrlr
2 2 ./dsp/iir_filter
3 3 ./general_purpose
4 4 ./lpp_ad_Conv
5 5 ./lpp_amba
6 6 ./lpp_cna
7 ./lpp_CNA_amba
8 7 ./lpp_uart
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@@ -1,104 +1,105
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 library ieee;
20 20 use ieee.std_logic_1164.all;
21 21 --use ieee.numeric_std.all;
22 22 library grlib;
23 23 use grlib.amba.all;
24 24 use grlib.stdlib.all;
25 25 use grlib.devices.all;
26 26 library lpp;
27 27 use lpp.lpp_amba.all;
28 28
29 29
30 30 entity APB_MULTI_DIODE is
31 31 generic (
32 32 pindex : integer := 0;
33 33 paddr : integer := 0;
34 34 pmask : integer := 16#fff#;
35 35 pirq : integer := 0;
36 36 abits : integer := 8);
37 37 port (
38 38 rst : in std_ulogic;
39 39 clk : in std_ulogic;
40 40 apbi : in apb_slv_in_type;
41 41 apbo : out apb_slv_out_type;
42 42 LED : out std_logic_vector(2 downto 0)
43 43 );
44 44 end;
45 45
46 46
47 47 architecture AR_APB_MULTI_DIODE of APB_MULTI_DIODE is
48 48
49 49 constant REVISION : integer := 1;
50 50
51 51 constant pconfig : apb_config_type := (
52 52 0 => ahb_device_reg (VENDOR_LPP, LPP_MULTI_DIODE, 0, REVISION, 0),
53 53 1 => apb_iobar(paddr, pmask));
54 54
55 55
56 56
57 57 type LEDregs is record
58 58 DATAin : std_logic_vector(31 downto 0);
59 59 DATAout : std_logic_vector(31 downto 0);
60 60 end record;
61 61
62 62 signal r : LEDregs;
63 signal Rdata : std_logic_vector(31 downto 0);
63 64
64 65
65 66 begin
66 67
67 68 r.DATAout <= r.DATAin xor X"FFFFFFFF";
68 69
69 70 process(rst,clk)
70 71 begin
71 72 if rst = '0' then
72 73 LED <= "000";
73 74 r.DATAin <= (others => '0');
74 apbo.prdata <= (others => '0');
75
75 76 elsif clk'event and clk = '1' then
76 77
77 78 LED <= r.DATAin(2 downto 0);
78 79
79 80 --APB Write OP
80 81 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
81 82 case apbi.paddr(abits-1 downto 2) is
82 83 when "000000" =>
83 84 r.DATAin <= apbi.pwdata;
84 85 when others =>
85 86 null;
86 87 end case;
87 88 end if;
88 89
89 90 --APB READ OP
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
91 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 92 case apbi.paddr(abits-1 downto 2) is
92 93 when "000000" =>
93 apbo.prdata <= r.DATAin;
94 Rdata <= r.DATAin;
94 95 when others =>
95 apbo.prdata <= r.DATAout;
96 Rdata <= r.DATAout;
96 97 end case;
97 98 end if;
98 99
99 100 end if;
100 101 apbo.pconfig <= pconfig;
101 102 end process;
102 103
103
104 apbo.prdata <= Rdata when apbi.penable = '1';
104 105 end ar_APB_MULTI_DIODE;
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@@ -1,127 +1,127
1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 library ieee;
20 20 use ieee.std_logic_1164.all;
21 21 --use ieee.numeric_std.all;
22 22 library grlib;
23 23 use grlib.amba.all;
24 24 use grlib.stdlib.all;
25 25 use grlib.devices.all;
26 26 library lpp;
27 27 use lpp.lpp_amba.all;
28 28
29 29
30 30 entity APB_SIMPLE_DIODE is
31 31 generic (
32 32 pindex : integer := 0;
33 33 paddr : integer := 0;
34 34 pmask : integer := 16#fff#;
35 35 pirq : integer := 0;
36 36 abits : integer := 8);
37 37 port (
38 38 rst : in std_ulogic;
39 39 clk : in std_ulogic;
40 40 apbi : in apb_slv_in_type;
41 41 apbo : out apb_slv_out_type;
42 42 LED : out std_ulogic
43 43 );
44 44 end;
45 45
46 46
47 47 architecture AR_APB_SIMPLE_DIODE of APB_SIMPLE_DIODE is
48 48
49 49 constant REVISION : integer := 1;
50 50
51 51 constant pconfig : apb_config_type := (
52 52 0 => ahb_device_reg (VENDOR_LPP, LPP_SIMPLE_DIODE, 0, REVISION, 0),
53 53 1 => apb_iobar(paddr, pmask));
54 54
55 55
56 56
57 57 type LEDregs is record
58 58 DATAin : std_logic_vector(31 downto 0);
59 59 DATAout : std_logic_vector(31 downto 0);
60 60 end record;
61 61
62 62 signal r : LEDregs;
63
63 signal Rdata : std_logic_vector(31 downto 0);
64 64
65 65 begin
66 66
67 67 r.DATAout <= r.DATAin xor X"FFFFFFFF";
68 68
69 69 process(rst,clk)
70 70 begin
71 71 if rst = '0' then
72 72 LED <= '0';
73 73 r.DATAin <= (others => '0');
74 apbo.prdata <= (others => '0');
74
75 75 elsif clk'event and clk = '1' then
76 76
77 77 LED <= r.DATAin(0);
78 78
79 79 --APB Write OP
80 80 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
81 81 case apbi.paddr(abits-1 downto 2) is
82 82 when "000000" =>
83 83 r.DATAin <= apbi.pwdata;
84 84 when others =>
85 85 null;
86 86 end case;
87 87 end if;
88 88
89 89 --APB READ OP
90 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
90 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
91 91 case apbi.paddr(abits-1 downto 2) is
92 92 when "000000" =>
93 apbo.prdata <= r.DATAin;
93 Rdata <= r.DATAin;
94 94 when others =>
95 apbo.prdata <= r.DATAout;
95 Rdata <= r.DATAout;
96 96 end case;
97 97 end if;
98 98
99 99 end if;
100 100 apbo.pconfig <= pconfig;
101 101 end process;
102 102
103
103 apbo.prdata <= Rdata when apbi.penable = '1';
104 104
105 105 -- pragma translate_off
106 106 -- bootmsg : report_version
107 107 -- generic map ("apbuart" & tost(pindex) &
108 108 -- ": Generic UART rev " & tost(REVISION) & ", fifo " & tost(fifosize) &
109 109 -- ", irq " & tost(pirq));
110 110 -- pragma translate_on
111 111
112 112
113 113
114 114 end ar_APB_SIMPLE_DIODE;
115 115
116 116
117 117
118 118
119 119
120 120
121 121
122 122
123 123
124 124
125 125
126 126
127 127
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@@ -1,67 +1,67
1 1 -- CNA_TabloC.vhd
2 2 library IEEE;
3 3 use IEEE.std_logic_1164.all;
4 4 use IEEE.numeric_std.all;
5 5 use work.Convertisseur_config.all;
6 6
7 7 entity CNA_TabloC is
8 8 port(
9 9 clock : in std_logic;
10 10 rst : in std_logic;
11 11 enable : in std_logic;
12 12 --bp : in std_logic;
13 13 Data_C : in std_logic_vector(15 downto 0);
14 14 SYNC : out std_logic;
15 15 SCLK : out std_logic;
16 16 --Rz : out std_logic;
17 17 flag_sd : out std_logic;
18 18 Data : out std_logic
19 19 );
20 20 end CNA_TabloC;
21 21
22 22
23 23 architecture ar_CNA_TabloC of CNA_TabloC is
24 24
25 25 component CLKINT
26 26 port( A : in std_logic := 'U';
27 27 Y : out std_logic);
28 28 end component;
29 29
30 30 signal clk : std_logic;
31 31
32 32 signal raz : std_logic;
33 33 signal s_SCLK : std_logic;
34 34 signal OKAI_send : std_logic;
35 35 --signal Data_int : std_logic_vector(15 downto 0);
36 36
37 37 begin
38 38
39 39
40 40 CLKINT_0 : CLKINT
41 41 port map(A => clock, Y => clk);
42 42
43 43 CLKINT_1 : CLKINT
44 44 port map(A => rst, Y => raz);
45 45
46 46
47 SystemCLK : entity work.Clock_Serie
47 SystemCLK : entity work.Systeme_Clock
48 48 generic map (nb_serial)
49 49 port map (clk,raz,s_SCLK);
50 50
51 51
52 52 Signal_sync : entity work.Gene_SYNC
53 53 port map (s_SCLK,raz,enable,OKAI_send,SYNC);
54 54
55 55
56 56 Serial : entity work.serialize
57 57 port map (clk,raz,s_SCLK,Data_C,OKAI_send,flag_sd,Data);
58 58
59 59
60 60 --Rz <= raz;
61 61 SCLK <= s_SCLK;
62 62
63 63 --with bp select
64 64 -- Data_int <= X"9555" when '1',
65 65 -- Data_C when others;
66 66
67 67 end ar_CNA_TabloC; No newline at end of file
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@@ -1,77 +1,77
1 1 library ieee;
2 2 use ieee.std_logic_1164.all;
3 3 library grlib;
4 4 use grlib.amba.all;
5 5 -- pragma translate_off
6 6 use std.textio.all;
7 7 -- pragma translate_on
8 8 library lpp;
9 9 use lpp.lpp_amba.all;
10 10
11 11
12 12 package lpp_cna is
13 13
14 14 component APB_CNA is
15 15 generic (
16 16 pindex : integer := 0;
17 17 paddr : integer := 0;
18 18 pmask : integer := 16#fff#;
19 19 pirq : integer := 0;
20 20 abits : integer := 8);
21 21 port (
22 22 clk : in std_logic;
23 23 rst : in std_logic;
24 24 apbi : in apb_slv_in_type;
25 25 apbo : out apb_slv_out_type;
26 26 SYNC : out std_logic;
27 27 SCLK : out std_logic;
28 28 DATA : out std_logic
29 29 );
30 30 end component;
31 31
32 32
33 33 component CNA_TabloC is
34 34 port(
35 35 clock : in std_logic;
36 36 rst : in std_logic;
37 37 flag_nw : in std_logic;
38 38 bp : in std_logic;
39 39 Data_C : in std_logic_vector(15 downto 0);
40 40 SYNC : out std_logic;
41 41 SCLK : out std_logic;
42 42 Rz : out std_logic;
43 43 flag_sd : out std_logic;
44 44 Data : out std_logic
45 45 );
46 46 end component;
47 47
48 48
49 component Clock_Serie is
49 component Systeme_Clock is
50 50 generic(N :integer := 695);
51 51 port(
52 52 clk, raz : in std_logic ;
53 53 clock : out std_logic);
54 54 end component;
55 55
56 56
57 57 component Gene_SYNC is
58 58 port(
59 59 clk,raz : in std_logic;
60 60 send : in std_logic;
61 61 Sysclk : in std_logic;
62 62 OKAI_send : out std_logic;
63 63 SYNC : out std_logic);
64 64 end component;
65 65
66 66
67 67 component Serialize is
68 68 port(
69 69 clk,raz : in std_logic;
70 70 sclk : in std_logic;
71 71 vectin : in std_logic_vector(15 downto 0);
72 72 send : in std_logic;
73 73 sended : out std_logic;
74 74 Data : out std_logic);
75 75 end component;
76 76
77 77 end;
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1 1 ------------------------------------------------------------------------------
2 2 -- This file is a part of the LPP VHDL IP LIBRARY
3 3 -- Copyright (C) 2009 - 2010, Laboratory of Plasmas Physic - CNRS
4 4 --
5 5 -- This program is free software; you can redistribute it and/or modify
6 6 -- it under the terms of the GNU General Public License as published by
7 7 -- the Free Software Foundation; either version 3 of the License, or
8 8 -- (at your option) any later version.
9 9 --
10 10 -- This program is distributed in the hope that it will be useful,
11 11 -- but WITHOUT ANY WARRANTY; without even the implied warranty of
12 12 -- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
13 13 -- GNU General Public License for more details.
14 14 --
15 15 -- You should have received a copy of the GNU General Public License
16 16 -- along with this program; if not, write to the Free Software
17 17 -- Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
18 18 -------------------------------------------------------------------------------
19 19 library ieee;
20 20 use ieee.std_logic_1164.all;
21 21 library grlib;
22 22 use grlib.amba.all;
23 23 use grlib.stdlib.all;
24 24 use grlib.devices.all;
25 25 library lpp;
26 26 use lpp.lpp_amba.all;
27 27 use lpp.lpp_uart.all;
28 28
29 29 entity APB_UART is
30 30 generic (
31 31 pindex : integer := 0;
32 32 paddr : integer := 0;
33 33 pmask : integer := 16#fff#;
34 34 pirq : integer := 0;
35 35 abits : integer := 8;
36 36 Data_sz : integer := 8);
37 37 port (
38 38 clk : in std_logic;
39 39 rst : in std_logic;
40 40 apbi : in apb_slv_in_type;
41 41 apbo : out apb_slv_out_type;
42 42 TXD : out std_logic;
43 43 RXD : in std_logic
44 44 );
45 45 end APB_UART;
46 46
47 47
48 48 architecture ar_APB_UART of APB_UART is
49 49
50 50 constant REVISION : integer := 1;
51 51
52 52 constant pconfig : apb_config_type := (
53 53 0 => ahb_device_reg (VENDOR_LPP, LPP_UART, 0, REVISION, 0),
54 54 1 => apb_iobar(paddr, pmask));
55 55
56 56 signal NwData : std_logic;
57 57 signal ACK : std_logic;
58 58 signal Capture : std_logic;
59 59 signal Send : std_logic;
60 60 signal Sended : std_logic;
61 61
62 62 type UART_ctrlr_Reg is record
63 63 UART_Cfg : std_logic_vector(4 downto 0);
64 64 UART_Wdata : std_logic_vector(7 downto 0);
65 65 UART_Rdata : std_logic_vector(7 downto 0);
66 66 UART_BTrig : std_logic_vector(11 downto 0);
67 67 end record;
68 68
69 69 signal Rec : UART_ctrlr_Reg;
70 signal Rdata : std_logic_vector(31 downto 0);
70 71
71 72 begin
72 73
73 74 Capture <= Rec.UART_Cfg(0);
74 75 ACK <= Rec.UART_Cfg(1);
75 76 Send <= Rec.UART_Cfg(2);
76 77 Rec.UART_Cfg(3) <= Sended;
77 78 Rec.UART_Cfg(4) <= NwData;
78 79
79 80
80 81 COM0 : entity work.UART
81 82 generic map (Data_sz)
82 83 port map (clk,rst,TXD,RXD,Capture,NwData,ACK,Send,Sended,Rec.UART_BTrig,Rec.UART_Rdata,Rec.UART_Wdata);
83 84
84 85
85 86 process(rst,clk)
86 87 begin
87 88 if(rst='0')then
88 89 Rec.UART_Wdata <= (others => '0');
89 apbo.prdata <= (others => '0');
90
90 91
91 92 elsif(clk'event and clk='1')then
92 93
93 94
94 95 --APB Write OP
95 96 if (apbi.psel(pindex) and apbi.penable and apbi.pwrite) = '1' then
96 97 case apbi.paddr(abits-1 downto 2) is
97 98 when "000000" =>
98 99 Rec.UART_Cfg(2 downto 0) <= apbi.pwdata(2 downto 0);
99 100 when "000001" =>
100 101 Rec.UART_Wdata <= apbi.pwdata(7 downto 0);
101 102 when others =>
102 103 null;
103 104 end case;
104 105 end if;
105 106
106 107 --APB READ OP
107 if (apbi.psel(pindex) and apbi.penable and (not apbi.pwrite)) = '1' then
108 if (apbi.psel(pindex) and (not apbi.pwrite)) = '1' then
108 109 case apbi.paddr(abits-1 downto 2) is
109 110 when "000000" =>
110 apbo.prdata(31 downto 27) <= Rec.UART_Cfg;
111 apbo.prdata(26 downto 12) <= (others => '0');
112 apbo.prdata(11 downto 0) <= Rec.UART_BTrig;
111 Rdata(31 downto 27) <= Rec.UART_Cfg;
112 Rdata(26 downto 12) <= (others => '0');
113 Rdata(11 downto 0) <= Rec.UART_BTrig;
113 114 when "000001" =>
114 apbo.prdata(7 downto 0) <= Rec.UART_Wdata;
115 Rdata(7 downto 0) <= Rec.UART_Wdata;
115 116 when "000010" =>
116 apbo.prdata(7 downto 0) <= Rec.UART_Rdata;
117 Rdata(7 downto 0) <= Rec.UART_Rdata;
117 118 when others =>
118 apbo.prdata <= (others => '0');
119 Rdata <= (others => '0');
119 120 end case;
120 121 end if;
121 122
122 123 end if;
123 124 apbo.pconfig <= pconfig;
124 125 end process;
125 126
127 apbo.prdata <= Rdata when apbi.penable = '1';
128
126 129 end ar_APB_UART;
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